A memory chip testing method and device

Abstract

The application relates to the chip technical field and discloses a memory chip testing method and device, which are used for improving the reliability of the value of the determined initialization parameter. The method comprises the following steps: a first binary sequence and a second binary sequence are used to test the value of the initialization parameter of a memory chip, the second binary sequence has H same direction jumps and I reverse jumps relative to the first binary sequence, one data signal line in N data signal lines of the memory chip transmits the first binary sequence, at least one data signal line in N-1 data signal lines transmits the second binary sequence, and the H and the I are integers greater than or equal to 1; a reference value of the initialization parameter is determined according to a value range of the initialization parameter obtained through the test; and data transmission is performed between the reference value and the memory chip.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a testing method and apparatus for memory chips. Background Technology

[0002] Most modern electronic devices integrate processors and memory chips. The memory chip is fundamental for the processor's computation, temporarily storing the data processed by the processor. After the electronic device is powered on, the memory chip undergoes an initialization process. This involves testing the memory chip to obtain optimal reference values ​​for its initialization parameters before high-speed data transmission can proceed normally. For example, obtaining a reference level to determine whether the data signal transmitted between the processor and the memory chip is high or low, and thus whether the transmitted data signal carries a "1" or a "0", is essential for normal high-speed data transmission.

[0003] The binary sequence selected during testing directly affects the reference values ​​of the initialization parameters. The more effectively the selected binary sequence stimulates crosstalk and inter-symbol interference (ISI) in the data signal, the better the results. Simultaneously, a shorter binary sequence reduces the testing time for the memory chip, resulting in a more user-friendly boot experience. The memory chip testing process utilizes two binary sequences: one as the victim line pattern and the other as the aggressor line pattern. Of the N data signal lines on the memory chip, one line transmits the data signal carrying the victim line pattern, while the other N-1 lines transmit the data signal carrying the aggressor line pattern. ISI is primarily determined by the victim line pattern, while crosstalk is mainly determined by the aggressor line patterns surrounding the victim line pattern. However, simple binary sequences (such as 0101, 0011, etc.) cannot effectively stimulate ISI and crosstalk in the data signal.

[0004] To induce ISI and crosstalk in data signals, pseudo-random binary sequences (PRBS) have been widely used in the testing of memory chips. One PRBS serves as the victim line pattern, and another as the intruder line pattern. A key characteristic of PRBS is that an N-order PRBS can traverse 2^N 1 ... N-1 encoding combinations can produce up to N consecutive 1s and N-1 consecutive 0s, with rich frequency components, effectively stimulating ISI and crosstalk in the data signal. However, using two different PRBS, one as the victim line code pattern and the other as the aggressor line code pattern, cannot effectively stimulate crosstalk in the data signal, affecting the reliability of the reference values ​​of the obtained initialization parameters. Summary of the Invention

[0005] This application provides a testing method and apparatus for memory chips to improve the reliability of the reference values ​​of determined initialization parameters.

[0006] Firstly, embodiments of this application provide a testing method for a memory chip. This method can be executed by electronic devices such as smartphones, tablets, smart cameras, autonomous vehicles, and personal computers. The method includes: testing the values ​​of initialization parameters of the memory chip using a first binary sequence and a second binary sequence, wherein the second binary sequence has H unidirectional transitions relative to the first binary sequence and I inverse transitions relative to the first binary sequence; one of the N data signal lines of the memory chip transmits the first binary sequence, and at least one of the other N-1 data signal lines transmits the second binary sequence, where N is an integer greater than or equal to 2, and H and I are integers greater than or equal to 1; determining a reference value for the initialization parameters based on the range of values ​​obtained from the test; and transmitting data with the memory chip according to the reference value. That is, one or more of the N data signal lines of the memory chip transmit the first binary sequence, and one or more of the remaining N data signal lines (excluding the data line used to transmit the first binary sequence) transmit the second binary sequence. Of the N data signal lines in a memory chip, two or more data signal lines are used to transmit a first binary sequence, and at least one of the remaining data signal lines is used to transmit a second binary sequence.

[0007] In the embodiments of this application, a jump is a transformation of the values ​​of two adjacent bits in a binary sequence, such as the change of the values ​​of two adjacent bits (e.g., the first bit and the second bit) from 0 to 1 or from 1 to 0. Same-direction jumps and opposite-direction jumps compare whether the directions of two jumps from the same bit position in the first binary sequence and the second binary sequence are the same or opposite. Same-direction jumps mean that both jumps are either from 1 to 0 or both are from 0 to 1; opposite-direction jumps mean that one of the jumps is from 0 to 1 and the other is from 1 to 0.

[0008] Due to the coupling effect between data signals, a level change in one data signal can cause a similar level change in another data signal, introducing crosstalk and affecting the transmission of the other data signal. In the embodiments of this application, during the testing of the memory chip, since the second binary sequence has abundant in-direction and out-of-direction transitions relative to the first binary sequence, the data signal carrying the second binary sequence transmitted in the data signal line has multiple in-direction level changes at the same transmission time (e.g., at a certain transmission time, all data signals change from high level (carrying "1") to low level (carrying "0")) and multiple out-of-direction level changes at the same transmission time (e.g., at a certain transmission time, one data signal changes from high level (carrying "1") to low level (carrying "0"), and another data signal changes from low level (carrying "0") to high level (carrying "1")), which will cause interference from in-direction and out-of-direction level changes to the data signal carrying the second binary sequence, thereby introducing strong crosstalk to the data signal carrying the second binary sequence, thus improving the reliability of the determined reference values ​​of the initialization parameters.

[0009] In one possible design, the initialization parameters include one or more of the following: reference level, data strobe signal (DQS) phase adjustment amplitude, etc.

[0010] The reference level is the level at which the memory chip or processor identifies the data signal level during data transmission. Specifically, when identifying the data signal level, if the data signal level is greater than or equal to the reference level, it is a high level; if the data signal level is less than the reference level, it is a low level. The DQS phase adjustment amplitude represents the transmission delay of DQS, while DQS is the signal that triggers the memory chip or processor to identify the data signal level during data transmission. By changing the value of the DQS phase adjustment amplitude, the timing at which DQS triggers the memory chip or processor to identify the data signal level can be adjusted.

[0011] In one possible design, the first binary sequence is a pseudo-random binary sequence with a variable tag ratio.

[0012] The more random the level of a data signal, the stronger the interference between different levels and the stronger the inter-symbol interference. A variable-mark-ratio pseudo-random binary sequence, generated by ANDing an invariant-mark-ratio pseudo-random binary sequence, is more random than the invariant-mark-ratio pseudo-random binary sequence, allowing for a greater number of consecutive bits with the same value "0 or 1". In the above design, using a variable-mark-ratio pseudo-random binary sequence as the first binary sequence makes the levels of the data signal carrying this sequence (high levels carrying "1" and low levels carrying "0") more random, leading to stronger inter-symbol interference and thus improving the reliability of the reference values ​​for the determined initialization parameters. Simultaneously, while ensuring the reliability of the reference values ​​for the determined initialization parameters, the length of the first binary sequence can be shortened, thereby improving the testing efficiency of the memory chip and enhancing the user's boot experience.

[0013] In one possible design, the second binary sequence is determined by reversing one or more transitions in the first binary sequence to determine the second binary sequence.

[0014] In the above design, the second binary sequence can be quickly obtained by reversing one or more transitions in the first binary sequence, such as changing two adjacent bits of 10 to 01, or changing two adjacent bits of 01 to 10, which is beneficial to improving the testing efficiency of memory chips.

[0015] In one possible design, the second binary sequence is determined as follows: the first binary sequence is divided into units of M bits each; multiple coding units are determined within the first binary sequence, wherein there are no duplicate bits between any two coding units, and M is an integer greater than or equal to 2; coding units carrying a target coding combination are marked as target coding units, wherein the target coding combination is the 2^32 bits corresponding to the coding unit. M One or more of the following encoding combinations; reverse the transitions in the target encoding unit of the first binary sequence to determine the second binary sequence.

[0016] In the above design, encoding can be performed using every M bits in the first binary sequence as the encoding unit, and the corresponding 2 bits of the encoding unit can be used as the encoding unit. M One or more of the following encoding combinations are used as the target encoding combination. The transitions in the target encoding unit carrying the target encoding combination are reversed to determine the second binary sequence. This method can quickly obtain the second binary sequence and improve the testing efficiency of memory chips.

[0017] In one possible design, the 2 M Half of the possible coding combinations constitutes the target coding combination.

[0018] In the above design, 2 M Using half of the coding combinations as the target coding combination helps to balance the number of unidirectional and inverse transitions of the second binary sequence relative to the first binary sequence, fully stimulates the crosstalk caused by unidirectional and inverse transitions to the data signal carrying the first binary sequence, and improves the reliability of the reference values ​​of the determined initialization parameters.

[0019] Secondly, embodiments of this application provide an initialization device for a memory chip. This device has the function of implementing the first aspect or any possible design method described in the first aspect. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units (modules) corresponding to the above functions, such as an initialization test unit, a determination unit, and a transmission unit.

[0020] Thirdly, embodiments of this application provide an electronic device, which includes a processor, a memory, and a memory chip. When the processor executes a computer program stored in the memory, the memory chip executes the method described in the first aspect or any possible design of the first aspect.

[0021] Fourthly, embodiments of this application provide a chip system comprising: a processor and an interface, wherein the processor is configured to call and execute a computer program from the interface, and when the processor executes the computer program, it can implement the method described in the first aspect or any possible design of the first aspect.

[0022] Fifthly, embodiments of this application provide a computer-readable storage medium having a computer program for performing the method described in the first aspect or any possible design of the first aspect.

[0023] Sixthly, embodiments of this application also provide a computer program product, including a computer program that, when executed, can implement the method described in the first aspect or any possible design of the first aspect.

[0024] The technical effects achievable by the second to sixth aspects mentioned above are similar to those achievable by the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0025] Figure 1This is a schematic diagram showing the connection between the processor and memory chip in an electronic device provided in an embodiment of this application;

[0026] Figure 2 A schematic diagram of the DQ provided for an embodiment of this application;

[0027] Figure 3 This is one of the relative timing diagrams of DQ and DQS provided in the embodiments of this application;

[0028] Figure 4 This is the second relative timing diagram of DQ and DQS provided in the embodiments of this application;

[0029] Figure 5 A conceptual diagram of an automatically rotating victim-aggressor pattern provided in the embodiments of this application;

[0030] Figure 6 This application provides a schematic diagram of the memory chip test code pattern stimulus method for its embodiments;

[0031] Figure 7 This is one of the schematic diagrams of an electronic device structure provided in the embodiments of this application;

[0032] Figure 8 This is a second schematic diagram of the electronic device structure provided in the embodiments of this application;

[0033] Figure 9 A schematic diagram of a testing method for a memory chip provided in an embodiment of this application;

[0034] Figure 10 This is a schematic diagram illustrating the level change of DQ under interference, provided in an embodiment of this application.

[0035] Figure 11 A schematic diagram of the first binary sequence and the second binary sequence provided in the embodiments of this application;

[0036] Figure 12 This is a schematic diagram of transition processing in the encoding unit provided in an embodiment of this application;

[0037] Figure 13 A schematic diagram illustrating the generation of PRBS 7 provided for an embodiment of this application;

[0038] Figure 14 A schematic diagram illustrating the generation of VMRQ-PRBS provided for embodiments of this application;

[0039] Figure 15 A schematic diagram illustrating the determination of the range of values ​​for the DQS phase adjustment amplitude provided in this application embodiment;

[0040] Figure 16 A schematic diagram of the memory training algorithm provided in the embodiments of this application;

[0041] Figure 17 This is one of the simulation result diagrams provided in the embodiments of this application;

[0042] Figure 18 The second schematic diagram of the simulation results provided for the embodiments of this application;

[0043] Figure 19 The third schematic diagram of the simulation results provided for the embodiments of this application;

[0044] Figure 20 This is a schematic diagram of a memory chip initialization device provided in an embodiment of this application. Detailed Implementation

[0045] Most current electronic devices (such as smartphones, tablets, smart cameras, autonomous vehicles, and personal computers (PCs)) integrate processors and memory chips. The memory chip is fundamental for the processor's computation, temporarily storing the data processed by the processor. The processor and memory chip are connected via a memory bus. This memory bus can include data signal lines and timing signal lines. The data signal lines transmit data signals, referred to as DQ in this application. DQ stands for Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), also known as the DDR protocol, and is an abbreviation for the data signal defined within it. The timing signal lines transmit data strobe signals, referred to as DQS in this application. DQS is an abbreviation for the data strobe signal defined in the DDR protocol. Both DQ and DQS are periodic signals, generally having the same period length.

[0046] like Figure 1 The diagram shown is a schematic of the connection between a processor and a memory chip in an electronic device provided in this application embodiment, wherein the memory bus may include N data signal lines and M timing signal lines, where N and M are integers greater than or equal to 2. In this application embodiment, the memory bus includes 8 data signal lines (DQ0-DQ7) and 2 timing signal lines (DQS0-DQS1) as an example for illustration.

[0047] Before introducing the embodiments of this application, some terms used in the embodiments of this application will be explained to facilitate understanding by those skilled in the art.

[0048] 1) Transition: In this embodiment, a transition refers to the change in the value of two adjacent bits in a binary sequence, such as a change from 0 to 1 or from 1 to 0. The comparison between same-direction transitions and opposite-direction transitions is whether the directions of two transitions originating from the same bit position in two binary sequences are the same or opposite. Same-direction transitions mean that both transitions are either from 0 to 1 or both are from 1 to 0. Opposite-direction transitions mean that one transition is from 0 to 1 and the other is from 1 to 0. For example, if the value of the first bit and the second bit in the first binary sequence is "10", and the value of the first bit and the second bit in the second binary sequence is also "10", then the transition "10" between the first and second bits in the first binary sequence and the transition "10" between the first and second bits in the second binary sequence are same-direction transitions. For example, if the value of the 5th and 6th bits in the first binary sequence is "10", and the value of the 5th and 6th bits in the second binary sequence is "01", then the transition "10" between the 5th and 6th bits in the first binary sequence and the transition "01" between the 5th and 6th bits in the second binary sequence are opposite transitions. Furthermore, in data signals carrying binary sequences, a high level typically carries "1" and a low level carries "0". A transition can also refer to a change (or conversion) in the level (i.e., voltage) of a data signal, including a change from a high level (carrying "1") to a low level (carrying "0"), and a change from a low level (carrying "0") to a high level (carrying "1").

[0049] 2) Inter-symbol interference (ISI) refers to the interference caused by the overlapping of multiple paths propagating the same signal at the receiver. It is also known as inter-symbol interference. It is usually caused by signal transmission multipath, fading, and distortion.

[0050] 3) Crosstalk: Crosstalk is noise caused by coupling between two data signal lines, as well as by mutual inductance and capacitance between them. It is an unwanted energy level generated by one data signal coupling to another, which may lead to data loss and transmission errors.

[0051] 4) Binary sequence pressure, also known as code pattern pressure, in this embodiment, can be understood as the ability of a binary sequence to induce crosstalk and / or inter-symbol interference in the data signals transmitted between the processor and the memory chip when testing the memory chip using a binary sequence. The greater the binary sequence pressure, the stronger the ability to induce crosstalk and / or inter-symbol interference. The ability to induce inter-symbol interference is mainly related to the length of the maximum number of consecutive identical digits (CID) that can appear in the binary sequence carried by the data signal, that is, the maximum length of consecutive 1s and consecutive 0s that can appear. The larger the CID length, the stronger the ability to induce inter-symbol interference. The ability to induce crosstalk is mainly related to the number of in-direction and out-of-direction transitions between the binary sequences carried by adjacent data signals. The more in-direction and out-of-direction transitions between binary sequences, the more interference is generated between the data signals, and the stronger the ability to induce crosstalk.

[0052] Processors in electronic devices can both read data from and write data to memory chips. Taking writing data to a memory chip as an example... Figure 1 As shown, the processor can send DQ to the memory chip via data signal lines DQ0-DQ7, and DQS to the memory chip via timing signal lines DQS0 and DQS1. DQ can carry the data that the processor wants to write to the memory chip, and DQS can trigger the memory chip to recognize the level state of DQ, and then write the data carried in DQ to the memory chip.

[0053] Specifically, data signal lines DQ0-DQ7 can transmit eight DQ signals in parallel. For example, data signal line DQ0 can transmit DQ0, data signal line DQ1 can transmit DQ1, ..., data signal line DQ7 can transmit DQ7. Timing signal line DQS0 can transmit DQS0, and timing signal line DQS1 can transmit DQS1. DQ0-DQ7 can be periodic signals; different data can be carried by controlling the level within the period, thus achieving data transmission. Figure 2 As shown, a DQ (which can be any DQ from DQ0 to DQ7) can transmit 1 bit of data in one cycle. If DQ is high in one cycle, it transmits 1 bit of data "1", and if DQ is low in one cycle, it transmits 1 bit of data "0". As an example, a DQ carrying 1010001 has a voltage level of high, low, high, low, low, low, high in seven cycles to transmit 7 bits of data "1010001".

[0054] DQS (which can be any of DQS0-DQS1) is typically a data strobe pulse signal with the same period length as DQ, used to trigger the memory chip to recognize the level state of DQ, and then write the data carried in DQ into the memory chip. For example... Figure 3 As shown, timing signal line DQS0 can transmit DQS0, and timing signal line DQS1 can transmit DQS1. DQS0 and DQS1 are inverted signals (i.e., within the same cycle, one DQS0 is high and the other is low). The intersection point between DQS0 and DQS1 (i.e., the point where DQS0 and DQS1 levels are equal) can serve as a trigger point for the memory chip to recognize the level state of DQ. In other words, when the memory chip determines that the received DQS0 and DQS1 are at an intersection point, that is, at the moment when DQS0 and DQS1 levels are equal, the memory chip can recognize the current level state of DQ, and thus write the data carried by DQ into the memory chip. For ease of description, this embodiment will hereinafter refer to DQS0 and DQS1 as DQS.

[0055] Furthermore, during data transmission, the memory chip identifies whether the DQ level is high or low relative to a reference level. This reference level is configured by the processor to identify the DQ level. Specifically, if the DQ level is greater than or equal to the reference level at the trigger point for identifying the DQ level, the memory chip determines the DQ level to be high; if the DQ level is less than the reference level at the trigger point, the memory chip determines the DQ level to be low. Figure 4 As shown, the accuracy of memory chip recognition in identifying the DQ level is closely related to the relative timing (relative delay) between DQS and DQ and the value of the reference level. An unreasonable reference level value and / or an unreasonable relative timing setting between DQS and DQ can cause the memory chip to misinterpret a high level of DQ as a low level at the trigger point for identifying the DQ level, resulting in the memory chip misinterpreting a "1" carried by DQ as a "0". Conversely, it can also cause the memory chip to misinterpret a low level of DQ as a high level at the trigger point for identifying the DQ level, resulting in the memory chip misinterpreting a "0" carried by DQ as a "1". The relative delay between DQS and DQ can be adjusted by the DQS phase adjustment amplitude (i.e., the DQS transmission delay). By adjusting the DQS phase adjustment amplitude, the timing (i.e., the delay) of DQS relative to DQ can be changed.

[0056] Therefore, after an electronic device starts up, the processor typically needs to test the memory chip, such as performing write / read tests, to obtain the optimal reference values ​​for initialization parameters (such as DQS phase adjustment amplitude and / or reference voltage) before high-speed data transmission with the memory chip can occur. During testing, the initialization parameter values ​​are usually continuously adjusted to test whether the data signals in the data signal lines can be transmitted accurately under different values. This determines the range of initialization parameter values ​​that ensure accurate data signal transmission, and based on this range, an optimal value is selected as a reference value for data transmission between the processor and the memory chip.

[0057] Currently, the main methods for writing / reading memory chips include the following:

[0058] Option 1: Victim-Aggressor Algorithm. The victim-aggressor algorithm has two main characteristics: (1) It uses two different pseudo-random binary sequences (PRBS), one PRBS as the victim line code pattern used by the victim, and the other PRBS as the aggressor line code pattern used by the aggressor. The two PRBS are completely random. (2) It provides an automatic rotation function for the victim-aggressor pattern, where multiple data signal lines alternately switch between the victim role and the aggressor role. For example... Figure 5 As shown, there are 17 parallel data signal lines. Each square represents the role of the data signal line, such as the victim role or the aggressor role. The role of different data signal lines changes over time. For example, data signal line 1 will successively play the roles of aggressor, aggressor, aggressor, and victim. Specifically, during read / write tests on memory chips, the data signal line being tested between the processor and the memory chip acts as the victim, transmitting data signals carrying the victim line code pattern. The other data signal lines act as aggressor, transmitting data signals carrying the aggressor line code pattern, attempting to introduce stronger ISI and crosstalk. However, the existing victim-aggressor algorithm uses two completely random PRBS patterns for the victim and aggressor line codes, which cannot introduce sufficient crosstalk to the data signal carrying the victim line code pattern.

[0059] Option 2: Option 2 is similar to part of the above options, except that it uses two PRBS15s (i.e., PRBSs of order 15) as the victim line code pattern and the aggressor line code pattern, respectively. Taking the PRBS15 used for the aggressor line code pattern as the first PRBS15 and the PRBS15 used for the victim line code pattern as the second PRBS15 as an example, the first PRBS15 can be a completely random PRBS15, and the second PRBS15 is the inverted first PRBS15. Inverting the first PRBS15 means inverting the value of either "1" or "0" in the first PRBS15, where "1" and "0" are opposite values. For example, if the first PRBS15 is "010……10", then the inverted first PRBS15 is "101……01".

[0060] Taking an electronic device with eight data signal lines (data signal lines DQ0-DQ7) between its processor and memory chip as an example, such as... Figure 6 As shown, each rectangle represents one data signal transmission of a data signal line. Rectangles filled with black represent data signals carrying the first PRBS15, while rectangles without black filling represent data signals carrying the second PRBS15. Specifically, during read / write tests of memory chips, the data signal line being tested between the processor and the memory chip transmits the data signal carrying the second PRBS15, while other data signal lines transmit the data signal carrying the first PRBS15 (as in examples from groups 2-9). Alternatively, all eight data signal lines can transmit the data signal carrying the first PRBS15 to test the accuracy of the data signals in the additional test data signal lines. However, this scheme, using two completely opposite PRBS15s, cannot guarantee sufficient crosstalk to the data signal carrying the victim line pattern (i.e., the second PRBS15). Furthermore, the long length of the PRBS15 reduces the testing efficiency of the memory chip, leading to longer boot times and impacting the user's boot experience.

[0061] This application aims to provide a testing scheme for memory chips. By employing a second binary sequence having H unidirectional transitions relative to a first binary sequence and I inverse transitions relative to the first binary sequence, the scheme leverages the rich unidirectional and inverse transitions of the second binary sequence relative to the first binary sequence to fully stimulate the crosstalk caused by the second binary sequence (i.e., the transmitted data signal carrying the second binary sequence) transmitted on at least one data signal line of the memory chip to the first binary sequence (i.e., the transmitted data signal carrying the first binary sequence) transmitted on a certain data signal line of the memory chip, thereby improving the reliability of the reference values ​​of the determined initialization parameters.

[0062] Figure 7 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Figure 7 yes Figure 1 The electronic device shown is logically divided into software and hardware layers. Figure 7 Electronic devices can include a hardware layer and a software layer. The software layer can include one or more applications and an operating system, while the hardware layer can include a processor, memory chips, and memory. The operating system is system software used to manage hardware and software resources. Figure 7 The processor and memory chips in it can be Figure 1 The processor and memory chips in it.

[0063] The processor is the control center of an electronic device, connecting various components via interfaces and buses. For example, it connects to memory chips via a memory bus. For details on how a processor connects to memory chips via the memory bus, please refer to [link to relevant documentation]. Figure 1 As shown, further details will not be repeated. In some embodiments, the processor may include one or more processing units, or physical cores, such as... Figure 7 The processor includes core 0 and core 1. The processor may also include registers, which can be used to store reference values ​​for memory chip initialization parameters, etc. The processor can be a central processing unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0064] Memory chips (also called memory) can be DDR SDRAM, such as 4th generation DDR (DDR4) SDRAM, 5th generation DDR (DDR5) SDRAM, etc., or low-power double data rate synchronous dynamic random access memory (LPDDR), etc., which can be used to temporarily store data processed by the processor. In addition, memory chips may also include registers, which can be used to store reference values ​​of the memory chip's initialization parameters.

[0065] The memory can store the operating system and applications, as well as data generated by the operating system and applications during operation.

[0066] like Figure 7 As shown, electronic devices may also include firmware. Since firmware is software embedded in hardware and includes computer instructions, it can be logically classified as part of the software layer. The Basic Input / Output System (BIOS) is a common type of firmware that performs hardware initialization during the power-on boot phase and provides runtime services to the operating system. In this embodiment, the BIOS of the electronic device can be used to execute computer instructions for testing the memory chip. After the electronic device is powered on, the BIOS executes the memory chip testing method to test the memory chip. After the test is completed, the reference values ​​of the obtained initialization parameters are written into the processor's registers and / or the memory chip's registers. Based on the reference values ​​of the initialization parameters in the processor's registers and / or the memory chip's registers, the processor and the memory chip can achieve high-speed data transmission. Typically, the processor's registers contain the reference values ​​of the initialization parameters obtained from the read (processor reads data from memory chip) test, and the memory chip's registers contain the reference values ​​of the initialization parameters obtained from the write (processor writes data to memory chip) test.

[0067] The computer instructions in the BIOS can be stored on the motherboard of the electronic device, specifically in a read-only memory (ROM) chip on the motherboard. Alternatively, the BIOS can be stored in other formats. Figure 7 The memory in the illustrated electronic device includes, but is not limited to, flash memory, hard disk, optical disk, and universal serial bus (USB) disk. In one implementation, the memory and the memory chip can be the same storage medium, that is, the memory chip stores computer instructions for implementing memory testing methods. When the processor of the electronic device calls the BIOS to perform hardware initialization, these computer instructions are invoked to execute the memory testing methods provided in the various embodiments of this application, thereby completing the testing of the memory chip.

[0068] Taking the BIOS being stored in memory as an example, the physical structure diagram of an electronic device can be shown as follows: Figure 8 As shown, it includes a memory, a processor, and a memory chip. The processor, memory chip, and memory can be... Figure 7 The implementation details of the processor, memory chips, and memory, including both parts and all, can be found in [reference]. Figure 7 The corresponding description in the text.

[0069] Additionally, it should be understood that in this application, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. In the textual description of this application, the character " / " generally indicates that the preceding and following related objects have an "or" relationship. Furthermore, unless otherwise stated, the ordinal numbers such as "first" and "second" mentioned in the embodiments of this application are used to distinguish multiple objects, not to limit the order, sequence, priority, or importance of multiple objects, and the descriptions of "first" and "second" do not necessarily imply that the objects are different. The various numerical designations used in this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application. The sequence numbers of the above processes do not imply the order of execution; the execution order of each process should be determined by its function and internal logic. In this application, terms such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design scheme described as "exemplary" or "for example" should not be construed as being more preferred or advantageous than other embodiments or design schemes. The use of terms such as "exemplary" or "for example" is intended to present related concepts in a concrete manner for ease of understanding. The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0070] Figure 9 This is a schematic diagram of a testing method for a memory chip provided in an embodiment of this application. The method includes:

[0071] S901: The processor uses the first binary sequence and the second binary sequence to test the values ​​of the initialization parameters of the memory chip.

[0072] In this configuration, one of the N data signal lines of the memory chip transmits the first binary sequence (i.e., transmits the data signal carrying the first binary sequence), and at least one of the other N-1 data signal lines transmits the second binary sequence (i.e., transmits the data signal carrying the second binary sequence).

[0073] Whether the first binary sequence can be correctly written to the memory chip depends on the interference received by the data signal carrying the first binary sequence sent by the processor to the memory chip through the data signal line, such as... Figure 10As shown, when a data signal is subjected to crosstalk and / or inter-symbol interference, the level of the data signal will change, which may cause the first binary sequence carried by the data signal to fail to be correctly written to the memory chip. Crosstalk is mainly related to the same-direction transitions and opposite-direction transitions between binary sequences carried by adjacent data signals. In order to maximize the excitation of crosstalk on the data signal carrying the first binary sequence, in this embodiment of the application, when testing the memory chip, the second binary sequence used has H same-direction transitions and I opposite-direction transitions relative to the first binary sequence, where H and I are integers greater than or equal to 1; and one of the N data signal lines of the memory chip can transmit the first binary sequence, while the other N-1 data signal lines can transmit the second binary sequence.

[0074] In this context, "same-direction transition" and "opposite-direction transition" compare whether two transitions from the same bit position in the first binary sequence and the second binary sequence are in the same direction or opposite directions. Same-direction transitions mean both transitions are either from 0 to 1 or both are from 1 to 0. Opposite-direction transitions mean one transition is from 0 to 1 and the other is from 1 to 0. For example... Figure 11 As shown, taking the first binary sequence as 101000111001010 and the second binary sequence as 011000110110010 as an example, the second binary sequence has 3 same-direction transitions relative to the first binary sequence and 3 opposite-direction transitions relative to the first binary sequence.

[0075] In this embodiment, the first binary sequence can be a completely random PRBS, such as a completely random PRBS of order 7. A PRBS of order 7 means that the initial code (composed of 0s and / or 1s) generating PRBS 7 has 7 bits or a size of 7. That is, the PRBS is obtained by performing an XOR operation on several bits of the initial code and cyclically shifting the output. The second binary sequence can be determined based on the first binary sequence. In some implementations, the processor can reverse one or more transitions in the first binary sequence to determine the second binary sequence.

[0076] Taking the first binary sequence as 10111011001110000110 (only a part is shown) as an example, the processor can randomly select one or more transitions in the first binary sequence that do not have repeated bits and reverse them to obtain the second binary sequence. For example, the processor can select the "10" in the first and second bits, and the "10" in the fifth and sixth bits of the first binary sequence. There are no duplicate bits between the "10" transitions corresponding to the first and second bits and the "10" transitions corresponding to the fifth and sixth bits. The decoding circuit converts the "10" in the first and second bits to "01" and the "10" in the fifth and sixth bits to "01", thus reversing the processing of the "10" in the first and second bits, and the "10" in the fifth and sixth bits of the first binary sequence, to obtain the second binary sequence "01110111001110000110 (partially shown)". The decoding circuit can be integrated into the processor or set up separately in the electronic device and connected to the processor; this application does not impose any limitations.

[0077] As another example, the processor can also divide the first binary sequence into units of 2 bits each, resulting in multiple coding units where no two coding units have repeated bits, such as 10, 11, 10, 11, 00, 11, 10, 00, 01, 10, etc. The processor then reverses the coding units corresponding to specific transitions via a decoding circuit, for example, converting the coding unit corresponding to the transition "10" to "01". The second binary sequence obtained after processing by the decoding circuit is "01 11 01 11 00 11 01 00 01 01 (only a portion is shown)".

[0078] In some implementations, the processor can further divide the first binary sequence into units of M bits, identify multiple coding units in the first binary sequence where no two coding units have repeated bits, mark the coding units carrying the target coding combination among the multiple coding units as target coding units, and reverse the transitions in the target coding units in the first binary sequence to determine the second binary sequence. Here, M is an integer greater than or equal to 2.

[0079] Specifically, the 2 corresponding to the encoding unit can be... M Some coding combinations from a given coding combination can be used as the target coding combination, or 2 can be used as the target coding combination. M All encoding combinations are used as the target encoding combination; this application does not impose any limitations. Furthermore, to ensure that the obtained second binary sequence has sufficient and opposite-direction transitions and same-direction transitions relative to the first binary sequence, thus achieving the best crosstalk effect, the 2... MHalf of the possible coding combinations is used as the target coding combination.

[0080] Taking M=3 as an example, the encoding unit consisting of M bits corresponds to 8 encoding combinations, namely 000, 001, 010, 011, 100, 101, 110, and 111. 100, 101, 110, and 111 can be used as target encoding combinations. The encoding units carrying 100, 101, 110, and 111 are marked as target encoding units, and the transitions in the target encoding units are reversed.

[0081] As an example, such as Figure 12 As shown, the processor can reverse the transitions in the target encoding units carrying 100, 101, 110, and 111 through the decoding circuit. The output of 100 after decoding can be 01X, 101 can be 010, 110 can be X01, and 111 can be XXX, where X can be 0 or 1. The processor can also maintain the transitions in non-target encoding units carrying 000, 001, 010, and 011 unchanged. The output of 000 after decoding can be XXX, 001 can be X01, 010 can be 010, and 011 can be 01X, where X can be 0 or 1.

[0082] In some implementations, the coded combination containing X can be set as a high-frequency coded combination (such as 010, 101, 011, etc.) to increase the crosstalk capability of the determined second binary sequence to the first binary sequence. For example... Figure 12 As shown, the decoding circuit can be configured to output 010 for input 000, 101 for input 001, 010 for input 010, 011 for input 011, 100 for input 101, 010 for input 110, 001 for input 111, and 101 for input 111.

[0083] It should be understood that the above example illustrates that non-target coding units carrying 000, 001, 010, and 011 are also processed through a decoding circuit. In some implementations, non-target coding units carrying 000, 001, 010, and 011 may not be processed through a decoding circuit, and the values ​​of each bit in the non-target coding unit remain unchanged.

[0084] Additionally, it's important to understand that the first binary sequence may contain bits that cannot be divided by M. For bits in the first binary sequence that cannot be divided by M, these bits can be left unprocessed. Still assuming M is 3, the decoding circuit uses... Figure 12 Taking the processing method shown as an example, assuming the first binary sequence is 101 110 110 011 100 001 10, the resulting second binary sequence is 010 001 001 011 011 101 10. The last 2 bits of the second binary sequence are the same as the last 2 bits of the first binary sequence. When determining the second binary sequence, the last 2 bits of the first binary sequence were not processed.

[0085] In PRBS, the ratio of "0" to "1" bits is equal; that is, the number of bits with a value of 0 is the same as the number of bits with a value of 1. For example... Figure 13 The diagram shows the generation of PRBS 7 (i.e., PRBS of order 7). PRBS is generated by a linear feedback shift register (LFSR). By performing an XOR operation on a set of initial codes (7 bits for PRBS7, consisting of 0 and / or 1) and cyclically shifting the output, a pseudo-random binary sequence in which the proportion of "0" and "1" is equal can be obtained.

[0086] In order to further stimulate the inter-symbol interference of the data signal carrying the first binary sequence and make the reference values ​​of the obtained initialization parameters suitable for the actual service transmission between the processor and the memory chip, in this embodiment of the application, the first binary sequence may also adopt a variable mark ratio quasi-PRBS (VMRQ-PRBS), that is, a 0 / 1 ratio variable pseudo-random binary sequence.

[0087] VMRQ-PRBS is a PRBS with a variable ratio of "0" and "1" to its constituent parts. It is generated by performing a bitwise AND operation on certain bits of an N-order PRBS. Common ratios include 1 / 8, 1 / 4, 3 / 4, and 7 / 8. For example... Figure 14As shown, performing a bitwise AND operation on 2 bits of the PRBS output from the standard PRBS7 pattern generator yields a pseudo-random binary sequence where the number of bits with a value of 1 is 1 / 4 of the total PRBS bits, i.e., a VMRQ-PRBS with a 1 / 4 ratio. Performing a bitwise AND operation on 3 bits of the output PRBS yields a pseudo-random binary sequence where the number of bits with a value of 1 is 1 / 8 of the total PRBS bits, i.e., a VMRQ-PRBS with a 1 / 8 ratio. Inverting the VMRQ-PRBS with 1 / 4 and 1 / 8 ratios of 1 yields the VMRQ-PRBS with 0 ratios of 1 / 4 and 1 / 8, respectively.

[0088] Table 1 shows the longest consecutive 1s and longest consecutive 0s for VMRQ-PRBS7 with a 1 / 4 ratio and a 1-bit shift (i.e., VMRQ-PRBS7 with a 1 / 4 ratio) and PRBS7. The ability of a binary sequence to induce inter-symbol interference (ISI) is mainly related to the maximum CID length that the binary sequence can exhibit. By using VMRQ-PRBS as the first binary sequence, ISI can be effectively induced in the data signal carrying the first binary sequence, making the reference values ​​of the obtained initialization parameters suitable for the actual business transmission between the processor and the memory chip. It also helps to shorten the length of the first binary sequence while ensuring the reliability of the obtained reference values ​​of the initialization parameters, thereby improving the testing efficiency of the memory chip.

[0089] PRB7 7 6 1 / 4ratio1 bit shift VMRQ-PRBS7 12 12

[0090] Table 1

[0091] The following example demonstrates how to test the initialization parameters of a memory chip using the first and second binary sequences.

[0092] The processor can send DQ0 carrying the first binary sequence to the memory chip via data signal line DQ0, send DQ1-DQ7 carrying the second binary sequence to the memory chip via data signal lines DQ1-DQ7, and send DQS to the memory chip via timing signal lines DQS0 and DQS1. For example... Figure 15As shown in Figure A, under the default reference level and default DQS phase adjustment amplitude (i.e., under the default values ​​of the reference level and the default DQS phase adjustment amplitude), the processor gradually reduces the value of the DQS phase adjustment amplitude until the first binary sequence carried by DQ0 cannot be correctly written to the memory chip. At this point, the relative timing position between the trigger point for identifying the DQ level state determined by DQS and DQ0 can be determined as follows: Figure 15 As shown in B in the diagram.

[0093] After the processor fails to correctly write the first binary sequence carried by DQ0 to the memory chip, it gradually increases the value of the DQS phase adjustment amplitude until the first binary sequence carried by DQ0 fails to be correctly written to the memory chip again. At this point, the relative timing position between the trigger point for identifying the level state of DQ, determined by DQS, and DQ0 can be determined as follows: Figure 15 As shown in C. Assume Figure 15 In B, the value of the DQS phase adjustment amplitude is P1. Figure 15 If the value of the DQS phase adjustment amplitude in C is P2, then the processor can obtain the range of the DQS phase adjustment amplitude from P1 to P2.

[0094] Similarly, for reference level testing, under the default reference level and default DQS phase adjustment amplitude, the processor can gradually reduce the value of the reference level until the first binary sequence carried by DQ0 cannot be correctly written to the memory chip. At this point, assume the reference level value is Q1.

[0095] After the processor fails to correctly write the first binary sequence carried by DQ0 to the memory chip, it gradually increases the value of the reference level until the first binary sequence carried by DQ0 fails to be correctly written to the memory chip again. At this point, assuming the value of the reference level is Q2, the processor obtains a reference level ranging from Q1 to Q2.

[0096] S402: The processor determines a reference value for the initialization parameter based on the range of values ​​of the initialization parameter obtained from the test.

[0097] In practical applications, due to factors such as noise, the trigger point for recognizing the DQ state determined by the memory chip based on DQS may deviate from the ideal trigger point. For example, the trigger point for recognizing the DQ state may be earlier or later than the ideal trigger point in time. The DQ level recognized by the memory chip may also deviate from the ideal DQ level. For example, the DQ level recognized by the memory chip may be higher or lower than the DQ level sent by the processor.

[0098] To ensure that the reference value of the determined DQS phase adjustment amplitude has more redundancy to cope with the influence of factors such as noise, in some embodiments, taking the range of DQS phase adjustment amplitude as P1 to P2 as an example, the reference value of DQS phase adjustment amplitude can be (P1+P2) / 2, which is the median of the range of DQS phase adjustment amplitude, so as to have more redundancy to cope with the influence of factors such as noise.

[0099] In addition, if the processor also obtains multiple sets of DQS phase adjustment amplitude values ​​based on data signal lines DQ1-DQ7, i.e. multiple sets of P1 and P2, the processor can also use the set of P1 and P2 with the largest difference among the multiple sets of P1 and P2 corresponding to data signal lines DQ0-DQ7 to determine the reference value of DQS phase adjustment amplitude.

[0100] To ensure that the reference value of the determined reference level has more redundancy to cope with the influence of factors such as noise, in some embodiments, taking the reference level range as Q1 to Q2 as an example, the reference value of the reference level can be (Q1+Q2) / 2, which is the median of the reference level range.

[0101] In addition, if the processor also obtains multiple sets of reference level values ​​based on data signal lines DQ1-DQ7, i.e. multiple sets of Q1 and Q2, the processor can also use the set of Q1 and Q2 with the largest difference among the multiple sets of Q1 and Q2 corresponding to data signal lines DQ0-DQ7 to determine the reference value of the reference level.

[0102] In some implementations, to improve the accuracy of memory chip testing, the processor can first determine a reference value for the DQS phase adjustment amplitude, and then test the reference level based on the reference value of the DQS phase adjustment amplitude and the default reference level, thereby determining the range of the reference level value, and then determining the reference value of the reference level; or first determine the reference value of the reference level, and then test the DQS phase adjustment amplitude based on the default DQS phase adjustment amplitude and the reference value of the reference level, thereby determining the range of the DQS phase adjustment amplitude value, and then determining the reference value of the DQS phase adjustment amplitude.

[0103] S403: The processor transmits data with the memory chip according to the reference value.

[0104] After obtaining the reference value of the DQS phase adjustment amplitude and / or the reference value of the reference level by performing a write test on the memory chip, the processor writes the obtained reference values ​​of the DQS phase adjustment amplitude and / or the reference level into the register of the memory chip. The memory chip can then identify the level of the data signal sent by the processor based on the reference values ​​of the DQS phase adjustment amplitude and / or the reference level stored in the register, and thus identify the data carried by the data signal, thereby enabling the processor to write data to the memory chip.

[0105] The above mainly describes how to determine the reference values ​​for the DQS phase adjustment amplitude and the reference level during write testing of memory chips. During read testing, the memory chip can send DQ to the processor via data signal lines DQ0 to DQ7, and DQS to the processor via timing signal lines DQS0 and DQS1. DQ carries the data the processor wants to read. For details on how to determine the reference values ​​for the DQS phase adjustment amplitude and the reference level during read testing, please refer to the section on how to determine the reference values ​​for the DQS phase adjustment amplitude and the reference level during write testing; further details will not be provided here.

[0106] After obtaining the reference value of the DQS phase adjustment amplitude and / or the reference value of the reference level by performing a read test on the memory chip, the processor writes the obtained reference value of the DQS phase adjustment amplitude and / or the reference value of the reference level into the processor's register. Based on the reference value of the DQS phase adjustment amplitude and / or the reference value of the reference level stored in the register, the processor can identify the level of the data signal sent by the memory chip, and then identify the data carried by the data signal, thereby enabling the processor to read data from the memory chip.

[0107] It should be understood that the memory chip testing method of this application can be used in memory chip training or testing scenarios. The main principle is to first stimulate a DQ victim line eye diagram using the victim line code pattern (first binary sequence) and the infringer line code pattern (second binary sequence). Then, using a certain algorithm, the center point of the inner contour of the DQ victim line eye diagram is found, which is the reference value for the initialization parameters of the memory chip. Figure 16As shown, taking the testing of a memory chip using a memory chip training algorithm (such as the DDR training algorithm) with a first binary sequence (victim line code pattern) and a second binary sequence (infringer line code pattern) as an example, the main steps include: using the default reference level (default-VREF) as a reference, finding the left and right boundaries of the inner contour of the DQ victim line eye diagram (i.e., the value range of the DQS phase adjustment amplitude), averaging the left and right boundaries to determine the reference value of the DQS phase adjustment amplitude; using the reference value of the DQS phase adjustment amplitude as a reference, finding the upper and lower boundaries of the inner contour of the DQ victim line eye diagram (i.e., the value range of the reference voltage), averaging the upper and lower boundaries to determine the reference value of the reference voltage.

[0108] As shown in Table 2, for a set of 8 DQs, the victim line code pattern (first binary sequence) of this application adopts VMRQ-PRBS11 (i.e., VMRQ-PRBS of order 11). The first and second schemes mentioned above both use PRBS15 (i.e., PRBS of order 15) as an example. The code pattern length required by the second scheme is 9*32767 bits; the code pattern length required by this application is 8*4094 bits (8 DQs are needed to transmit the victim line code pattern respectively); the code pattern length of this application is 1 / 9 of that of the second scheme.

[0109] We analyzed the stress on the verification code through simulation. Taking a 1-bit signal simulation as an example, the simulation results at different transmission rates are as follows: Figure 17 , Figure 18 , Figure 19 As shown, the affected line code pattern in this application is short in length, but it causes the greatest inter-symbol interference and crosstalk. Therefore, the reference values ​​for the initialization parameters with the highest reliability can be determined. Here, EH represents eye height, and EW represents eye width.

[0110]

[0111]

[0112] Table 2

[0113] The foregoing mainly introduced the solution provided by this application from the perspective of method and process. The following will elaborate on the technical solutions of the embodiments of this application from the perspective of hardware or logical module division. It is understood that, in order to achieve the above functions, the apparatus may include hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, based on the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed by hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0114] When using integrated units, Figure 20 This illustration shows a possible exemplary block diagram of a memory chip initialization apparatus according to an embodiment of this application. The memory chip initialization apparatus 2000 may exist in the form of a software module or a hardware module. The memory chip initialization apparatus 2000 may include: an initialization test unit 2001, a determination unit 2002, and a transmission unit 2002.

[0115] In one example, the device can exist as a software module, such as Figure 7 The firmware of the illustrated electronic device includes software instructions for implementing this module. These instructions can be stored in a storage medium, such as... Figure 7 The memory or Figure 7 The memory chip is located within the internal storage space of the electronic device. When the electronic device is powered on, its processor calls the firmware (such as the BIOS) to perform hardware initialization. In this process, the processor calls the stored computer instructions used to implement the functions of the various software modules of the device, uses a first binary sequence and a second binary sequence to test the memory chip, and finally obtains reference values ​​for the initialization parameters of the memory chip. The processor can then configure the registers in the memory chip or the registers in the processor based on the obtained reference values, thereby achieving more reliable testing of the memory chip and making the direct data transmission between the processor and the memory chip more reliable.

[0116] Specifically, in one embodiment, the initialization test unit 2001 is used to test the values ​​of the initialization parameters of the memory chip using a first binary sequence and a second binary sequence, wherein the second binary sequence has H unidirectional transitions relative to the first binary sequence and I inverse transitions relative to the first binary sequence, one of the N data signal lines of the memory chip transmits the first binary sequence, and at least one of the other N-1 data signal lines transmits the second binary sequence, wherein the transition is a change in the value of two adjacent bits in a binary sequence, N is an integer greater than or equal to 2, and H and I are integers greater than or equal to 1;

[0117] The determining unit 2002 is used to determine a reference value for the initialization parameter based on the value range of the initialization parameter obtained from the test.

[0118] The transmission unit 2003 is used to transmit data with the memory chip according to the reference value.

[0119] In one possible design, the first binary sequence is a pseudo-random binary sequence with a variable tag ratio.

[0120] In one possible design, the determining unit 2002 is further configured to reverse one or more transitions in the first binary sequence to determine the second binary sequence.

[0121] In one possible design, the determining unit 2002 is further configured to divide the first binary sequence into units of M bits, determine multiple coding units in the first binary sequence, wherein there are no duplicate bits between any two coding units, and M is an integer greater than or equal to 2; and mark the coding unit carrying the target coding combination among the multiple coding units as the target coding unit, wherein the target coding combination is the 2^32 bits corresponding to the coding unit. M One or more of the following encoding combinations; reverse the transitions in the target encoding unit of the first binary sequence to determine the second binary sequence.

[0122] In one possible design, the 2 M Half of the possible coding combinations constitutes the target coding combination.

[0123] In one possible design, the initialization parameters include at least one of the following: reference level, and the phase adjustment amplitude of the data strobe pulse signal DQS.

[0124] As another form of this embodiment, a computer-readable storage medium is provided, on which a computer program (or instructions) is stored. When the computer program is run on an electronic device, it enables the electronic device to execute the memory chip testing method described in the above method embodiments. As an example, such as... Figure 8 As shown, the computer-readable storage medium can be a memory in an electronic device. The BIOS stored in the memory contains a computer program for implementing a test method for a memory chip. The processor in the electronic device can schedule and run the computer program to implement the test method for a memory chip in the above method embodiment.

[0125] As another form of this embodiment, a computer program product is provided, which includes a computer program for implementing a testing method for a memory chip. When the computer program is executed, it can implement the testing method for the memory chip in the above-described method embodiment. As an example: Figure 8 As shown, the computer program product can be written into the memory (or BIOS) of an electronic device, and the processor in the electronic device can schedule and run the computer program included in the computer program product to implement the memory chip testing method in the above method embodiment.

[0126] As another embodiment, a chip system is provided, comprising: a processor and an interface. The processor is configured to call and execute a computer program from the interface for implementing a testing method for a memory chip. When the processor executes the computer program, it implements the testing method for the memory chip described in the above method embodiment. As an example, the interface may be an interface circuit, such as... Figure 8 As shown, the processor can call and execute a computer program stored in the memory to implement the memory chip testing method in the above method embodiment through the interface circuit connecting the processor and the memory.

[0127] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0128] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0129] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0130] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0131] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0132] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. A method for testing a memory chip, characterized in that, include: The initialization parameters of the memory chip are tested using a first binary sequence and a second binary sequence. The second binary sequence has H unidirectional transitions relative to the first binary sequence and I inverse transitions relative to the first binary sequence. One of the N data signal lines of the memory chip transmits the first binary sequence, and one or more of the other N-1 data signal lines transmit the second binary sequence. The transition is a change in the value of two adjacent bits in a binary sequence, N is an integer greater than or equal to 2, and H and I are integers greater than or equal to 1. Based on the range of values ​​of the initialization parameters obtained from the test, determine the reference value of the initialization parameters; Data is transmitted to the memory chip based on the reference value.

2. The method as described in claim 1, characterized in that, The first binary sequence is a pseudo-random binary sequence with a variable tag ratio.

3. The method as described in claim 1 or 2, characterized in that, The second binary sequence is determined in the following manner: The second binary sequence is determined by reversing one or more transitions in the first binary sequence.

4. The method as described in claim 1 or 2, characterized in that, The second binary sequence is determined in the following manner: The first binary sequence is divided into units of M bits, and multiple coding units are determined in the first binary sequence, wherein there are no duplicate bits between any two coding units, and M is an integer greater than or equal to 2. The coding unit carrying the target coding combination among the plurality of coding units is marked as the target coding unit, wherein the target coding combination is the 2 corresponding to the coding unit. M One or more of the following encoding combinations; The transitions in the target coding unit of the first binary sequence are reversed to determine the second binary sequence.

5. The method as described in claim 4, characterized in that, The 2 M Half of the possible coding combinations constitutes the target coding combination.

6. The method as described in claim 1 or 2, characterized in that, The initialization parameters include at least one of the following: The reference level and the amplitude of the data strobe pulse signal DQS phase adjustment.

7. An initialization device for a memory chip, characterized in that, include: Initialize the test unit, determination unit, and transmission unit; The initialization test unit is used to test the values ​​of the initialization parameters of the memory chip using a first binary sequence and a second binary sequence. The second binary sequence has H unidirectional transitions relative to the first binary sequence and I inverse transitions relative to the first binary sequence. One of the N data signal lines of the memory chip transmits the first binary sequence, and one or more of the other N-1 data signal lines transmit the second binary sequence. The transition is a change in the value of two adjacent bits in a binary sequence. N is an integer greater than or equal to 2, and H and I are integers greater than or equal to 1. The determining unit is used to determine a reference value for the initialization parameter based on the value range of the initialization parameter obtained from the test. The transmission unit is used to transmit data with the memory chip according to the reference value.

8. The apparatus as claimed in claim 7, characterized in that, The first binary sequence is a pseudo-random binary sequence with a variable tag ratio.

9. The apparatus as claimed in claim 7 or 8, characterized in that, The determining unit is further configured to reverse one or more transitions in the first binary sequence to determine the second binary sequence.

10. The apparatus as claimed in claim 7 or 8, characterized in that, The determining unit is further configured to divide the first binary sequence into units of M bits, determine multiple coding units in the first binary sequence, wherein there are no duplicate bits between any two coding units, and M is an integer greater than or equal to 2; and mark the coding unit carrying the target coding combination among the multiple coding units as the target coding unit, wherein the target coding combination is the 2^32 bits corresponding to the coding unit. M One or more of the following encoding combinations; reverse the transitions in the target encoding unit of the first binary sequence to determine the second binary sequence.

11. The apparatus as claimed in claim 10, characterized in that, The 2 M Half of the possible coding combinations constitutes the target coding combination.

12. The apparatus as claimed in claim 7 or 8, characterized in that, The initialization parameters include at least one of the following: The reference level and the amplitude of the data strobe pulse signal DQS phase adjustment.

13. An electronic device, characterized in that, This includes processors, memory, and memory chips; The memory is used to store program instructions; The processor is configured to execute the method as described in any one of claims 1-6 via the memory chip by invoking program instructions stored in the memory.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store a computer program that, when run on an electronic device, causes the electronic device to perform the method as described in any one of claims 1-6.

15. A chip system, characterized in that, The chip system includes: A processor and an interface, the processor being configured to call and execute a computer program from the interface, wherein when the processor executes the computer program, it implements the method as described in any one of claims 1-6.

16. A computer program product, characterized in that, The computer program product includes a computer program that, when executed, implements the method as described in any one of claims 1-6.

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