Semiconductor structure and method of fabricating the same

Abstract

This disclosure relates to the semiconductor field, providing a semiconductor structure and a method for fabricating the same. The method includes: providing a substrate on which a first transistor array including a plurality of first semiconductor pillars is disposed; forming a plurality of first contact structures on the top surface of the first semiconductor pillars; forming a first capacitor, the first capacitor including: a first electrode correspondingly connected to the first contact structures; a first dielectric layer covering the top and sidewalls of the first electrode; a second electrode covering and filling the gaps between the first dielectric layers; forming a second capacitor, the second capacitor sharing a second electrode with the first capacitor, the second capacitor further including: a second dielectric layer with its bottom and sidewalls located within the second electrode; a third electrode filling the gaps between the second dielectric layers; forming a plurality of second contact structures on the top surface of the third electrode, and forming a second transistor array including a plurality of second semiconductor pillars, the bottom of the second semiconductor pillars correspondingly connected to the second contact structures, thereby improving the integration density of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for fabricating the same. Background Technology

[0002] As various electronic products trend toward miniaturization, the design of Dynamic Random Access Memory (DRAM) cells must also meet the requirements of high integration and high density.

[0003] A DRAM memory cell consists of a storage transistor and a capacitor connected in series. In order to improve cell performance and reduce cell area, it is necessary to fabricate a capacitor with a large capacitance value per unit area. However, capacitors usually require a large space to achieve good charge storage efficiency.

[0004] Therefore, how to improve the integration density of semiconductor structures, obtain greater charge storage capacity, and reduce process difficulty has become an important technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] This disclosure provides a semiconductor structure and a method for fabricating the same, to improve the integration density of the semiconductor structure.

[0006] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate on which a first transistor array is disposed, the first transistor array including a plurality of first semiconductor pillars; forming a plurality of first contact structures, the first contact structures being located on the top surface of the first semiconductor pillars; forming a first capacitor, the first capacitor including: a first electrode, correspondingly connected to the first contact structure; a first dielectric layer, covering the top and sidewalls of the first electrode; a second electrode, covering and filling the gaps between the first dielectric layers; forming a second capacitor, the second capacitor sharing a second electrode with the first capacitor, the second capacitor further including: a second dielectric layer, the bottom and sidewalls being located within the second electrode; a third electrode, filling the gaps between the second dielectric layers; forming a plurality of second contact structures and a second transistor array, the second contact structures being located on the top surface of the third electrode, the second transistor array including a plurality of second semiconductor pillars, the bottoms of the second semiconductor pillars being correspondingly connected to the second contact structures.

[0007] In some embodiments, forming a first electrode includes: forming an insulating layer that covers and fills the gap between first contact structures; forming a plurality of first electrode holes in the insulating layer that expose the top surface of the first contact structures; and filling the first electrode holes with a conductive material to form a first electrode.

[0008] In some embodiments, forming a first electrode includes: forming an insulating layer that covers and fills the gap between first contact structures; forming a plurality of first electrode holes in the insulating layer that expose the top surface of the first contact structures; and forming a first electrode that covers the sidewalls of the first electrode holes and the top surface of the first contact structures.

[0009] In some embodiments, forming a first dielectric layer includes: removing a portion of an insulating layer, wherein the top surface of the remaining insulating layer is flush with the top surface of the first contact structure; forming a first dielectric layer on the top and sidewalls of the first electrode, wherein the first dielectric layer further covers the top of the insulating layer.

[0010] In some embodiments, forming a first dielectric layer includes: removing an insulating layer; forming a first dielectric layer on the top and sidewalls of a first electrode, the first dielectric layer further covering the sidewalls of a first contact structure and the top of a first transistor array.

[0011] In some embodiments, forming a second electrode and a second dielectric layer includes: forming an initial first electrode layer that covers and fills the gaps between first dielectric layers; forming a sacrificial layer that covers the top surface of the initial first electrode layer; forming a plurality of dielectric holes in the sacrificial layer that expose the top surface of the initial first electrode layer, with the projections of the dielectric holes onto the substrate located between the projections of the first electrodes onto the substrate; filling the dielectric holes with a conductive material to form an initial second electrode layer; removing the sacrificial layer and forming a second dielectric layer that covers the top and sidewalls of the initial second electrode layer and the exposed top of the initial first electrode layer, wherein the initial first electrode layer and the initial second electrode layer together constitute a second electrode.

[0012] In some embodiments, forming a second dielectric layer includes: forming a plurality of second electrode holes in a second electrode, the second electrode holes corresponding to a first electrode; and forming a second dielectric layer at the bottom and sidewalls of the second electrode holes.

[0013] In some embodiments, the first transistor array further includes: a plurality of first bit lines extending along a first direction and a plurality of first word lines extending along a second direction; a first semiconductor pillar extending along a third direction; the bottom of the first semiconductor pillar being connected to the first bit line; and the bottom of a plurality of first semiconductor pillars being connected to the same first bit line along the first direction; the first word lines surrounding the first semiconductor pillars; and the same first word line surrounding a plurality of first semiconductor pillars along the second direction.

[0014] In some embodiments, the second semiconductor pillar extending along a third direction to form a second transistor array further includes: forming a plurality of second word lines extending along a fourth direction, the second word lines surrounding the second semiconductor pillars, and the same second word line surrounding a plurality of second semiconductor pillars along the fourth direction; forming a plurality of second bit lines extending along a fifth direction, the tops of the second semiconductor pillars being connected to the second bit lines, and the tops of a plurality of second semiconductor pillars being connected to the same second bit line along the fifth direction.

[0015] In some embodiments, the angle between the first direction and the fifth direction is 0° to 30°, and the angle between the second direction and the fourth direction is 0° to 30°. In some embodiments, forming the second transistor array further includes forming a plurality of bit line control buses extending along a third direction, one end of the bit line control bus being connected to the first bit line, and the other end being connected to the second bit line.

[0016] According to some embodiments of this disclosure, another aspect of this disclosure provides a semiconductor structure, including: a substrate, on which a first transistor array is disposed, the first transistor array including a plurality of first semiconductor pillars; a plurality of first contact structures located on the top surface of the first semiconductor pillars; a first capacitor, the first capacitor including: a first electrode correspondingly connected to the first contact structures; a first dielectric layer covering the top and sidewalls of the first electrode; a second electrode covering and filling the gaps between the first dielectric layers; a second capacitor, the second capacitor sharing a second electrode with the first capacitor, the second capacitor further including: a second dielectric layer, the bottom and sidewalls of which are located within the second electrode; a third electrode filling the gaps between the second dielectric layers; a plurality of second contact structures located on the top surface of the third electrode; and a second transistor array including a plurality of second semiconductor pillars, the bottoms of the second semiconductor pillars correspondingly connected to the second contact structures.

[0017] In some embodiments, the first electrode has at least one U-shaped cross-section or at least one rectangular cross-section, and the third electrode has at least one U-shaped cross-section or at least one rectangular cross-section.

[0018] In some embodiments, the cross-sectional shape of the first electrode is the same as that of the third electrode.

[0019] In some embodiments, the projection of the first electrode onto the substrate coincides with the projection of the third electrode onto the substrate.

[0020] In some embodiments, the semiconductor structure further includes a support structure located between adjacent first electrodes and also between adjacent third electrodes.

[0021] The technical solution provided by the embodiments of this disclosure has at least the following advantages: by forming a first contact structure on the top of the first semiconductor pillar in the first transistor array and connecting a first capacitor corresponding to the first contact structure, the transistor structure in the first transistor array is correspondingly connected to the first capacitor; by continuing to form a second capacitor on the first capacitor and a second contact structure and a second transistor array corresponding to the second capacitor, the transistor structure in the second transistor array is correspondingly connected to the second capacitor; by stacking the transistor structure and the corresponding capacitor structure, the space utilization of the semiconductor structure can be improved and the integration density of the semiconductor structure can be increased; wherein, the second capacitor and the first capacitor share the second electrode, that is, the first capacitor and the second capacitor share the upper electrode, which can reduce the capacitor manufacturing process in the semiconductor structure and improve the manufacturing efficiency of the semiconductor structure. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figures 1 to 12 This is a schematic diagram of the various steps corresponding to a method for fabricating a semiconductor structure according to an embodiment of the present disclosure. Detailed Implementation

[0024] As can be seen from the background art, how to improve the integration density of semiconductor structures, obtain a large charge storage capacity, and reduce the process difficulty has become an important technical problem that needs to be solved by those skilled in the art.

[0025] Analysis revealed that a DRAM memory cell consists of a storage transistor and a capacitor connected in series. To improve cell performance and reduce cell area, a capacitor with a large capacitance value needs to be fabricated per unit area. However, capacitors typically require a large space to achieve good charge storage efficiency. To ensure the capacitor's storage capacity, electrodes need to be extended in the direction perpendicular to the substrate, for example, by setting a columnar lower electrode. Reducing the size of the transistor structure on a unit area substrate can increase the semiconductor structure integration density; however, the smaller the transistor structure, the more difficult it is to fabricate, and consequently, the more complex the capacitor structure process becomes.

[0026] According to some embodiments of this disclosure, one aspect of this disclosure is to provide a method for fabricating a semiconductor structure, thereby improving the integration density of the semiconductor structure.

[0027] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0028] Figures 1 to 12 This is a schematic diagram of the various steps corresponding to a method for fabricating a semiconductor structure according to an embodiment of the present disclosure, wherein... Figures 2 to 12 for Figure 1 A cross-sectional view along the AA1 direction is shown below. The fabrication method of the semiconductor structure provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0029] refer to Figure 1 A substrate 101 is provided, on which a first transistor array 100 is disposed. The first transistor array 100 includes a plurality of first semiconductor pillars 203. The first semiconductor pillars 203 extend along a third direction Z and also include a plurality of first bit lines 201 extending along a first direction X and a plurality of first word lines 202 extending along a second direction Y. The bottom of the first semiconductor pillars 203 is connected to the first bit lines 201. The bottom of the plurality of first semiconductor pillars 203 along the first direction X is connected to the same first bit line 201. The first word lines 202 surround the first semiconductor pillars 203. Along the second direction Y, the same first word line 202 surrounds the plurality of first semiconductor pillars 203.

[0030] It should be noted that in this embodiment, the angle between the first direction X and the second direction Y is 90°, and the plane containing the first direction X and the second direction Y is parallel to the surface of the substrate 101, while the third direction Z is perpendicular to the surface of the substrate 101. That is, the angle between the plane containing the first direction and the second direction and the third direction is 90°. In other embodiments, the angle between the first direction X and the second direction Y can be 30°, 45°, or 60°, and the angle between the plane containing the first direction and the second direction and the surface of the substrate can be 30°, 45°, or 90°. In this embodiment, the angle between the third direction and the surface of the substrate can be 30°, 45°, or 60°, and the angle between the plane containing the first direction and the second direction and the third direction can be 30°, 45°, or 60°. This embodiment does not constitute a limitation on the angle between the first direction, the second direction, and the third direction.

[0031] For the substrate, the material forming the substrate can be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. Elemental semiconductor materials can be silicon or germanium; crystalline inorganic compound semiconductor materials can be silicon carbide, silicon germanide, gallium arsenide, or indium gallium, etc.

[0032] For the first semiconductor pillar 203, the material forming the first semiconductor pillar 203 includes at least one of IGZO (indium gallium zinc oxide), IWO (indium tungsten oxide), or ITO (indium tin oxide). When the first semiconductor pillar is composed of the above materials, it is beneficial to improve the carrier mobility of the first semiconductor pillar, thereby facilitating more efficient transmission of electrical signals. For example, when the material of the first semiconductor pillar is IGZO, the carrier mobility of IGZO is 20 to 50 times that of polycrystalline silicon, which is beneficial to improving the carrier mobility in the first semiconductor pillar, thereby reducing the leakage current during semiconductor structure operation, thus reducing the power consumption of the semiconductor structure and improving its operating efficiency. Furthermore, the retention time of a memory cell configured with a gate-all-around transistor formed by IGZO-formed first semiconductor pillars can exceed 400 seconds, which is beneficial to reducing the refresh rate and power consumption of the memory.

[0033] In this embodiment, the first semiconductor pillar 203 is cylindrical; in other embodiments, the first semiconductor pillar may be elliptical or polygonal. It is understood that when the first semiconductor pillar is cylindrical or elliptical, its smooth surface prevents tip discharge or leakage during operation. When it is a polygonal prism, the corners can be chamfered to create a smooth transition in angles, also preventing leakage.

[0034] For the first line 201, the material forming the first line 201 includes at least one of metal silicide, copper, or tungsten. In some embodiments, the material forming the first line can be a single metal, a metal compound, or an alloy. The single metal can be copper, aluminum, tungsten, gold, or silver, etc.; the metal compound can be tantalum nitride or titanium nitride; the alloy can be an alloy material composed of at least two of copper, aluminum, tungsten, gold, or silver. Setting the material of the first line to a metallic material can give the first line a lower resistivity, which is beneficial to the resistance of the first line, increasing the transmission rate of electrical signals in the first line, reducing the parasitic capacitance of the first line, and reducing heat loss to reduce power consumption.

[0035] In some embodiments, forming the first word line includes: forming a first gate dielectric layer covering the surface of a first semiconductor pillar; and forming a first gate conductive layer covering the surface of the first gate dielectric layer and surrounding the first semiconductor pillar. The first gate dielectric layer covering the surface of the first semiconductor pillar prevents the first gate conductive layer from reacting with the first semiconductor pillar during subsequent processes, thus avoiding damage to the semiconductor structure.

[0036] For the first gate dielectric layer, the material forming the first gate dielectric layer includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0037] The material forming the first gate conductive layer includes at least one of polycrystalline silicon, titanium nitride, titanium aluminide, tantalum nitride, tantalum, copper, aluminum, lanthanum, copper, or tungsten.

[0038] Furthermore, the first transistor array 100 also includes a first isolation structure 204. The first isolation structure 204 covers the surfaces of the substrate 101 and the first bit line 201, fills the gaps between the first semiconductor pillars 203, and is also located between adjacent first word lines 202. The first isolation structure 204 can isolate adjacent first semiconductor pillars, first word lines, or first bit lines, preventing interconnection between different first semiconductor pillars, first word lines, or first bit lines that could damage the semiconductor structure and improving the stability of the semiconductor structure.

[0039] For the first isolation structure 204, the material forming the first isolation structure 204 includes silicon oxide, silicon nitride, silicon oxynitride, etc.

[0040] refer to Figure 2 and Figure 3 Multiple first contact structures 205 are formed, and the first contact structures 205 are located on the top surface of the first semiconductor pillar 203.

[0041] For the first contact structure 205, the material forming the first contact structure 205 includes copper, titanium, titanium nitride or tungsten, etc.

[0042] refer to Figure 2 In some embodiments, the step of forming the first contact structure 205 includes: forming a first contact layer covering the surface of the first transistor array 100; and patterning the first contact layer to form the first contact structure 205.

[0043] refer to Figure 3 In other embodiments, the step of forming the first contact structure 205 includes: removing a portion of the height of the first semiconductor pillar 203; and forming the first contact structure 205 on the surface of the first semiconductor pillar 203.

[0044] refer to Figure 4A first capacitor 110 is formed, comprising: a first electrode 211, which is correspondingly connected to a first contact structure 205; a first dielectric layer 212, which covers the top and sidewalls of the first electrode 211; and a second electrode 213, which covers and fills the gaps between the first dielectric layers 212.

[0045] For the first electrode 211, the material forming the first electrode 211 includes at least one of platinum nickel, titanium, tantalum, cobalt, polycrystalline silicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium.

[0046] For the second electrode 213, the material forming the second electrode 213 includes at least one of platinum nickel, titanium, tantalum, cobalt, polycrystalline silicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium.

[0047] In some embodiments, the first electrode 211 and the second electrode 213 are made of the same material; in other embodiments, the materials of the first electrode and the second electrode may be different.

[0048] For the first dielectric layer, the materials forming the first dielectric layer include high dielectric constant materials such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate.

[0049] In some embodiments, forming the first electrode 211 includes: a reference Figure 5 An insulating layer 220 is formed, which covers and fills the gaps between the first contact structures 205. Multiple first electrode holes are formed within the insulating layer, exposing the top surface of the first contact structures 205. Conductive material is filled into the first electrode holes to form first electrodes 211. This forms a columnar first electrode 211, whose top surface and sidewalls form the lower electrode of the first capacitor. The columnar first electrode 211 has a simple fabrication process, which is beneficial for improving the fabrication efficiency of semiconductor structures.

[0050] In other embodiments, forming the first electrode 211 includes: a reference Figure 6 An insulating layer 220 is formed, covering and filling the gaps between the first contact structures 205. Multiple first electrode holes are formed within the insulating layer 220, exposing the top surface of the first contact structures 205. A first electrode 211 is formed, covering the sidewalls of the first electrode holes and the top surface of the first contact structures 205. This forms a cup-shaped first electrode 211. The outer and inner sidewalls of the cup-shaped first electrode 211, as well as the bottom surface connected to the inner sidewall, form the lower electrode plate of the first capacitor, thereby increasing the area of ​​the lower electrode plate, improving the charge storage capacity of the first capacitor, and ultimately improving the performance of the semiconductor structure.

[0051] For insulating layer 220, the material forming the insulating layer includes silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0052] Further, refer to Figure 7 In some embodiments, forming a first dielectric layer 212 includes: removing a portion of the insulating layer 220, with the top surface of the remaining insulating layer 220 flush with the top surface of the first contact structure 205; forming the first dielectric layer 212 on the top and sidewalls of the first electrode 211, the first dielectric layer 212 also covering the top of the insulating layer 220. By filling the gaps between different first contact structures 205 with the insulating layer 220, damage to the semiconductor structure caused by interconnection between adjacent first contact structures 205 is avoided, thereby improving the stability of the semiconductor structure.

[0053] In other embodiments, reference is made to Figure 8 The process of forming a first dielectric layer 212 includes: removing the insulating layer 220; forming the first dielectric layer 212 on the top and sidewalls of the first electrode 211, the first dielectric layer 212 also covering the sidewalls of the first contact structure 205 and the top of the first transistor array. The first dielectric layer 212 also covering the sidewalls of the first contact structure 205 allows the first capacitor formed by the first electrode to surround the first contact structure 205, thereby increasing the capacitance of the first capacitor.

[0054] In this embodiment, the first dielectric layer is a single-layer structure; in other embodiments, the first dielectric layer can be a multi-layer structure. For example, the first dielectric layer can be formed by stacking titanium oxide / zirconia / titanium oxide. The multi-layer structure of the first dielectric layer can prevent the leakage current from increasing and causing device failure.

[0055] In some embodiments, the first dielectric layer may be doped with at least one of silicon nitride and silicon oxynitride. The doped silicon nitride or silicon oxynitride occupies only a portion of the vacancies in the first dielectric layer and does not constitute a complete thin film. Doping with silicon nitride or silicon oxynitride can further reduce leakage current in the first dielectric layer.

[0056] refer to Figure 9 A second capacitor 120 is formed, which shares a second electrode 213 with the first capacitor 110. The second capacitor 120 also includes: a second dielectric layer 222, the bottom and sidewalls of which are located within the second electrode 213; and a third electrode 221, which fills the gaps between the second dielectric layers 222.

[0057] For the third electrode 221, the material forming the third electrode 221 includes at least one of platinum nickel, titanium, tantalum, cobalt, polycrystalline silicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium.

[0058] In some embodiments, the material of the third electrode may be the same as that of the second electrode; in other embodiments, the material of the third electrode may be different from that of the second electrode. In some embodiments, the material of the third electrode may be the same as that of the first electrode; in other embodiments, the material of the third electrode may be different from that of the first electrode.

[0059] For the second dielectric layer, the materials forming the second dielectric layer include high dielectric constant materials such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate.

[0060] In some embodiments, forming a second electrode 213 and a second dielectric layer 222 includes: a reference Figure 10 An initial first electrode layer 313 is formed, which covers and fills the gaps between the first dielectric layers 212; a sacrificial layer 301 is formed, which covers the top surface of the initial first electrode layer 313; a plurality of dielectric holes are formed within the sacrificial layer 301, the dielectric holes exposing the top surface of the initial first electrode layer 313, and the projections of the dielectric holes onto the substrate 101 are located between the projections of the first electrodes 211 onto the substrate 101; a conductive material is filled into the dielectric holes to form an initial second electrode layer 323; Reference Figure 11 The sacrificial layer 301 is removed, and a second dielectric layer 222 is formed to cover the top and sidewalls of the initial second electrode layer 323 and the exposed top of the initial first electrode layer 313. The initial first electrode layer 313 and the initial second electrode layer 323 together constitute the second electrode 213.

[0061] For the sacrificial layer 301, the materials forming the sacrificial layer 301 include silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0062] In some embodiments, forming a second dielectric layer includes: forming a plurality of second electrode holes within a second electrode, the second electrode holes corresponding to the first electrode; and forming a second dielectric layer at the bottom and sidewalls of the second electrode holes. That is, when the second electrode located above the first electrode is relatively high, the second electrode holes can be directly formed within the second electrode, and the second dielectric layer and the second electrode can be formed within the second electrode holes. This reduces the number of steps in the semiconductor structure fabrication process and improves the fabrication efficiency of the semiconductor structure.

[0063] In this embodiment, the second dielectric layer is a single-layer structure; in other embodiments, the second dielectric layer can be a multi-layer structure. For example, the second dielectric layer can be formed by stacking titanium oxide / zirconia / titanium oxide. The multi-layer structure of the second dielectric layer can prevent the leakage current from increasing and causing device failure.

[0064] In some embodiments, the second dielectric layer may also be doped with at least one of silicon nitride and silicon oxynitride. The doped silicon nitride or silicon oxynitride occupies only a portion of the vacancies in the second dielectric layer and does not constitute a complete thin film. Doping with silicon nitride or silicon oxynitride can further reduce leakage current in the second dielectric layer.

[0065] It should be noted that in this embodiment, the first electrode is a columnar structure, and the third electrode has the same shape as the first electrode, being a columnar structure; in other embodiments, the first electrode may also be a cup-shaped structure, and the shape of the third electrode may be different from that of the first electrode. This embodiment does not constitute a limitation on the shape of the first electrode and the shape of the third electrode.

[0066] refer to Figure 12 Multiple second contact structures 206 and a second transistor array 200 are formed. The second contact structures 206 are located on the top surface of the third electrode 221. The second transistor array 200 includes multiple second semiconductor pillars 303 extending along the third direction Z. The bottom of the second semiconductor pillars 303 is correspondingly connected to the second contact structures 206.

[0067] Furthermore, in some embodiments, forming the second transistor array 200 further includes: forming a plurality of second word lines 302 extending along a fourth direction, the second word lines 302 surrounding the second semiconductor pillars 303, and the same second word line 302 surrounding the plurality of second semiconductor pillars 303 along the fourth direction; forming a plurality of second bit lines 305 extending along a fifth direction, the tops of the second semiconductor pillars 303 being connected to the second bit lines 305, and the tops of the plurality of second semiconductor pillars 303 being connected to the same second bit line 305 along the fifth direction.

[0068] In some embodiments, the angle between the first direction and the fifth direction is 0° to 30°. Specifically, the angle between the first direction and the fifth direction can be 0°, 20°, or 30°. The angle between the second direction and the fourth direction is 0° to 30°. Specifically, the angle between the second direction and the fourth direction can be 0°, 20°, or 30°. It is understood that the second transistor array is controlled to conduct through a second word line and a second bit line. When the extension directions of the second word line and the second bit line are different, the transistors in the second transistor array can be positioned and selected. The second word line can be parallel to the first word line or have a certain angle with the first word line; the second bit line can be parallel to the first bit line or have a certain angle with the first bit line.

[0069] In some embodiments, the second transistor array 200 further includes a second isolation structure 304. The second isolation structure 304 covers the surface of the second dielectric layer 222, fills the gaps between the second semiconductor pillars 303, and is also located between adjacent second word lines 302. The second isolation structure 304 can isolate adjacent second semiconductor pillars and second word lines, preventing damage to the semiconductor structure caused by interconnection between different second semiconductor pillars or second word lines, and improving the stability of the semiconductor structure.

[0070] For the second isolation structure 304, the materials forming the second isolation structure 304 include silicon oxide, silicon nitride, silicon oxynitride, etc.

[0071] For the second semiconductor pillar 303, the material forming the second semiconductor pillar 303 includes at least one of IGZO (indium gallium zinc oxide), IWO (indium tungsten oxide), or ITO (indium tin oxide).

[0072] In this embodiment, the material of the second semiconductor pillar is the same as that of the first semiconductor pillar and is represented by the same characteristics; in other embodiments, the material of the second semiconductor pillar may be different from that of the first semiconductor pillar.

[0073] For the second word line, in some embodiments, the step of forming the second word line includes: forming a second gate dielectric layer covering the surface of the second semiconductor pillar; and forming a second gate conductive layer covering the surface of the second gate dielectric layer and surrounding the second semiconductor pillar. The second gate dielectric layer covering the surface of the second semiconductor pillar can prevent the second gate conductive layer from reacting with the second semiconductor pillar during subsequent processes, thus avoiding damage to the semiconductor structure.

[0074] For the second gate dielectric layer, the material forming the second gate dielectric layer includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0075] For the second gate conductive layer, the material forming the second gate conductive layer includes at least one of polycrystalline silicon, titanium nitride, titanium aluminide, tantalum nitride, tantalum, copper, aluminum, lanthanum, copper, or tungsten.

[0076] In this embodiment, the material of the second character line is the same as that of the first character line, and they are represented by the same features; in other embodiments, the material of the second character line may be different from that of the first character line.

[0077] For the second bit line, the material forming the second bit line includes at least one of metal silicide, copper, or tungsten. In some embodiments, the material forming the second bit line can be a single metal, a metal compound, or a metal silicide. The single metal can be copper, aluminum, tungsten, gold, or silver, etc.; the metal compound can be tantalum nitride or titanium nitride; the alloy can be an alloy material composed of at least two of copper, aluminum, tungsten, gold, or silver. Setting the material of the second bit line to a metallic material can give the second bit line a lower resistivity, which is beneficial to the resistance of the second bit line, increasing the transmission rate of electrical signals in the second bit line, reducing the parasitic capacitance of the second bit line, and reducing heat loss to reduce power consumption.

[0078] In this embodiment, the material of the second bit line is the same as that of the first bit line and is represented by the same features; in other embodiments, the material of the second bit line may be different from that of the first bit line.

[0079] Furthermore, in some embodiments, after forming the second transistor array, a third transistor array, a third capacitor, a fourth transistor array, and a fourth capacitor can be stacked on top of the second transistor array. The third transistor array has the same structure as the first transistor array and shares a second bit line with the second transistor array. The third capacitor has the same structure as the first capacitor, the fourth capacitor has the same structure as the second capacitor, and the third and fourth capacitors share an upper electrode. The fourth transistor array also has the same structure as the second transistor array. This allows for the formation of repeatedly stacked transistor and capacitor structures on the substrate, with adjacent transistor structures sharing an upper electrode, thereby improving the space utilization of the semiconductor structure, increasing its integration density, and enhancing its performance.

[0080] In some embodiments, the projection of the semiconductor pillars in the third transistor array onto the substrate coincides with the projection of the first semiconductor pillars in the first transistor array onto the substrate, or the projection of the semiconductor pillars in the third transistor array onto the substrate coincides with the projection of the second semiconductor pillars in the second transistor array onto the substrate. In other embodiments, the projection of the semiconductor pillars in the third transistor array onto the substrate does not coincide with the projection of the first semiconductor pillars in the first transistor array, i.e., the transistor structures in the third transistor array are misaligned with the transistor structures in the first transistor array; or, the projection of the semiconductor pillars in the third transistor array onto the substrate does not coincide with the projection of the second semiconductor pillars in the second transistor array, i.e., the transistor structures in the third transistor array are misaligned with the transistor structures in the second transistor array. Similarly, the transistor structures in the fourth transistor array may correspond to the transistor structures in the first transistor array or the second transistor array, or the transistor structures in the fourth transistor array may be misaligned with the transistor structures in the first transistor array or the second transistor array. In some embodiments, after forming the second transistor array, the method further includes: forming multiple bit line control buses extending along a third direction, one end of each bit line control bus being connected to a first bit line and the other end being connected to a second bit line. Connecting the first bit line of the first transistor array to the second bit line of the second transistor array via a bit line control bus allows the first bit line and the second bit line to share the same control port, improving the control capability of the semiconductor structure.

[0081] The semiconductor structure fabrication method provided in this disclosure involves forming a first contact structure on the top of a first semiconductor pillar in a first transistor array and connecting a first capacitor to the first contact structure, thereby connecting the transistor structures in the first transistor array to the first capacitor. A second capacitor, a second contact structure, and a second transistor array are then formed on the first capacitor, connecting the transistor structures in the second transistor array to the second capacitor. By stacking the transistor structures and their corresponding capacitor structures, the space utilization of the semiconductor structure can be improved, and the integration density of the semiconductor structure can be increased. Furthermore, the second capacitor shares a second electrode with the first capacitor, i.e., the first capacitor and the second capacitor share an upper electrode, which can reduce the capacitor fabrication process in the semiconductor structure and improve the fabrication efficiency of the semiconductor structure.

[0082] According to some embodiments of this disclosure, another aspect of this disclosure also provides a semiconductor structure formed using the semiconductor structure fabrication method provided in the above embodiments, for increasing the integration density of the semiconductor structure. It should be noted that the parts that are the same as or corresponding to the above embodiments can be referred to the corresponding descriptions of the foregoing embodiments, and will not be described in detail below.

[0083] Continue to refer to Figure 12 The semiconductor structure provided in this embodiment includes: a substrate 101, on which a first transistor array 100 is disposed, the first transistor array 100 including a plurality of first semiconductor pillars 203; a plurality of first contact structures 205 located on the top surface of the first semiconductor pillars 203; a first capacitor 12, the first capacitor 12 including: a first electrode 211, correspondingly connected to the first contact structure 205; a first dielectric layer 212 covering the top and sidewalls of the first electrode 211; a second electrode 213 covering and filling the gaps between the first dielectric layers 212; a second capacitor 120, the second capacitor 120 sharing the second electrode 213 with the first capacitor 110, the second capacitor 120 further including: a second dielectric layer 222, the bottom and sidewalls of which are located within the second electrode 213; a third electrode 221 filling the gaps between the second dielectric layers 222; a plurality of second contact structures 206 located on the top surface of the third electrode 221; and a second transistor array 200 including a plurality of second semiconductor pillars 303, the bottom of the second semiconductor pillars 303 correspondingly connected to the second contact structures 206.

[0084] In the first transistor array, the top of the first semiconductor pillar is connected to the first capacitor via a first contact structure, and in the second transistor array, the bottom of the second semiconductor pillar is connected to the second capacitor via a second contact structure. By stacking, the space utilization of the transistor structure and the corresponding capacitor structure is improved, and the integration density of the semiconductor structure is increased. The second capacitor and the first capacitor share the second electrode, that is, the first capacitor and the second capacitor share the upper electrode, which can improve the utilization of the upper electrode of the capacitor in the semiconductor structure, reduce the capacitor manufacturing process in the semiconductor structure, and improve the manufacturing efficiency of the semiconductor structure.

[0085] In some embodiments, the first electrode has at least one U-shaped cross-section or at least one rectangular cross-section, and the third electrode has at least one U-shaped cross-section or at least one rectangular cross-section. That is, the first electrode can be a cup-shaped structure or a columnar structure, and the third electrode can be a cup-shaped structure or a columnar structure. It is understood that the top and sidewalls of the columnar first electrode form the lower electrode of the first capacitor, and the bottom and sidewalls of the columnar third electrode form the lower electrode of the second capacitor. The columnar capacitor structure is simple and facilitates semiconductor fabrication, thus improving the fabrication efficiency of semiconductor structures. The cup-shaped first electrode has inner and outer sidewalls and a bottom surface connected to the inner sidewall to form the lower electrode of the first capacitor, and the cup-shaped third electrode has inner and outer sidewalls and a top surface connected to the inner sidewall to form the lower electrode of the second capacitor. The cup-shaped capacitor can increase the relative area of ​​the upper and lower electrodes, thereby improving the capacitor's storage capacity.

[0086] It should be noted that in this embodiment, the cross-sectional shape of the first electrode is the same as that of the third electrode, meaning the first and third electrodes have the same structure. In other embodiments, the cross-sectional shapes of the first and third electrodes may be different. In this embodiment, the projection of the first electrode onto the substrate coincides with the projection of the third electrode onto the substrate, meaning the first and third electrodes are directly opposite each other, and the corresponding first and second capacitors are directly opposite each other. In other embodiments, the projections of the first and third electrodes onto the substrate may not coincide, meaning the first and third electrodes are misaligned, and the corresponding first and second capacitors are misaligned.

[0087] In some embodiments, the semiconductor structure further includes a support structure located between adjacent first electrodes and also between adjacent third electrodes. It is understood that when the capacitor height is high, to prevent the capacitor's shape from tilting due to the high aspect ratio, the support structure is located between adjacent first electrodes and adjacent third electrodes. This can improve the stability of the first and third electrodes, prevent deformation of the first and third electrodes, and improve the reliability of the semiconductor structure.

[0088] The semiconductor structure provided in this embodiment has the following characteristics: in the first transistor array, the top of the first semiconductor pillar is connected to the first capacitor via a first contact structure; in the second transistor array, the bottom of the second semiconductor pillar is connected to the second capacitor via a second contact structure. By stacking the first transistor array with the corresponding first capacitor and the second transistor array with the second capacitor, the space utilization of the transistor structure and the corresponding capacitor structure can be improved, and the integration density of the semiconductor structure can be increased. Furthermore, the second capacitor shares a second electrode with the first capacitor, i.e., the first capacitor and the second capacitor share an upper electrode plate, which can improve the utilization rate of the upper electrode plate of the capacitor in the semiconductor structure and reduce the capacitor manufacturing process in the semiconductor structure, thereby improving the manufacturing efficiency of the semiconductor structure.

[0089] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, on which a first transistor array is disposed, the first transistor array comprising a plurality of first semiconductor pillars; Multiple first contact structures are formed, and the first contact structures are located on the top surface of the first semiconductor pillar; A first capacitor is formed, the first capacitor comprising: a first electrode, correspondingly connected to the first contact structure; a first dielectric layer, covering the top and sidewalls of the first electrode; and a second electrode, covering and filling the gaps between the first dielectric layers; A second capacitor is formed, which shares the second electrode with the first capacitor. The second capacitor further includes: a second dielectric layer with its bottom and sidewalls located within the second electrode; and a third electrode that fills the gaps between the second dielectric layers. Multiple second contact structures and a second transistor array are formed. The second contact structures are located on the top surface of the third electrode. The second transistor array includes multiple second semiconductor pillars, and the bottom of the second semiconductor pillars is connected to the second contact structures.

2. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, Forming the first electrode includes: An insulating layer is formed, which covers and fills the gap between the first contact structures; A plurality of first electrode holes are formed within the insulating layer, the first electrode holes exposing the top surface of the first contact structure; The first electrode is formed by filling the first electrode hole with conductive material.

3. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, Forming the first electrode includes: An insulating layer is formed, which covers and fills the gap between the first contact structures; A plurality of first electrode holes are formed within the insulating layer, the first electrode holes exposing the top surface of the first contact structure; The first electrode is formed, and the first electrode covers the sidewall of the first electrode hole and the top surface of the first contact structure.

4. The method for fabricating a semiconductor structure as described in claim 2 or 3, characterized in that, Forming the first dielectric layer includes: A portion of the insulating layer is removed, leaving the top surface of the remaining insulating layer flush with the top surface of the first contact structure; a first dielectric layer is formed on the top and sidewalls of the first electrode, the first dielectric layer also covering the top of the insulating layer.

5. The method for fabricating a semiconductor structure as described in claim 2 or 3, characterized in that, Forming the first dielectric layer includes: Remove the insulating layer; The first dielectric layer is formed on the top and sidewalls of the first electrode, and the first dielectric layer also covers the sidewalls of the first contact structure and the top of the first transistor array.

6. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, Forming the second electrode and the second dielectric layer includes: An initial first electrode layer is formed, which covers and fills the gaps between the first dielectric layers; A sacrificial layer is formed, which covers the top surface of the initial first electrode layer; A plurality of dielectric holes are formed within the sacrificial layer, the dielectric holes exposing the top surface of the initial first electrode layer, and the projection of the dielectric holes on the substrate is located between the projections of the first electrode on the substrate; An initial second electrode layer is formed by filling the dielectric pores with conductive material. The sacrificial layer is removed, and a second dielectric layer is formed to cover the top and sidewalls of the initial second electrode layer and the exposed top of the initial first electrode layer, the initial first electrode layer and the initial second electrode layer together constituting the second electrode.

7. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, Forming the second dielectric layer includes: A plurality of second electrode holes are formed in the second electrode, and the second electrode holes correspond to the first electrode. The second dielectric layer is formed at the bottom and sidewall of the second electrode hole.

8. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The first transistor array further includes: a plurality of first bit lines extending along a first direction and a plurality of first word lines extending along a second direction; the first semiconductor pillars extend along a third direction; the bottom of the first semiconductor pillars is connected to the first bit lines; and the bottom of a plurality of first semiconductor pillars along the first direction is connected to the same first bit line; the first word lines surround the first semiconductor pillars; and the same first word line surrounds a plurality of first semiconductor pillars along the second direction.

9. The method for fabricating a semiconductor structure as described in claim 8, characterized in that, The second semiconductor pillar extends along the third direction to form the second transistor array, further comprising: Multiple second word lines are formed extending along the fourth direction, the second word lines surround the second semiconductor pillars, and the same second word line surrounds multiple second semiconductor pillars along the fourth direction; Multiple second bit lines are formed extending along a fifth direction, the top of the second semiconductor pillar is connected to the second bit line, and the tops of multiple second semiconductor pillars along the fifth direction are connected to the same second bit line.

10. The method for fabricating a semiconductor structure as described in claim 9, characterized in that, The angle between the first direction and the fifth direction is 0° to 30°, and the angle between the second direction and the fourth direction is 0° to 30°.

11. The method for fabricating a semiconductor structure as described in claim 9, characterized in that, Forming the second transistor array further includes: forming a plurality of bit line control buses extending along the third direction, one end of the bit line control bus being connected to the first bit line and the other end being connected to the second bit line.

12. A semiconductor structure, characterized in that, include: A substrate on which a first transistor array is disposed, the first transistor array comprising a plurality of first semiconductor pillars; Multiple first contact structures are located on the top surface of the first semiconductor pillar; The first capacitor includes: a first electrode connected to the first contact structure; a first dielectric layer covering the top and sidewalls of the first electrode; and a second electrode covering and filling the gaps between the first dielectric layers. The second capacitor shares the second electrode with the first capacitor. The second capacitor further includes: a second dielectric layer with its bottom and sidewalls located within the second electrode; and a third electrode filling the gaps between the second dielectric layers. Multiple second contact structures are located on the top surface of the third electrode; The second transistor array includes a plurality of second semiconductor pillars, the bottom of which is connected to the second contact structure.

13. The semiconductor structure as described in claim 12, characterized in that, The first electrode has at least one U-shaped cross-section or at least one rectangular cross-section, and the third electrode has at least one U-shaped cross-section or at least one rectangular cross-section.

14. The semiconductor structure as described in claim 13, characterized in that, The cross-sectional shape of the first electrode is the same as that of the third electrode.

15. The semiconductor structure as described in claim 12, characterized in that, The projection of the first electrode on the substrate coincides with the projection of the third electrode on the substrate.

16. The semiconductor structure as claimed in claim 12, characterized in that, Also includes: A support structure is located between adjacent first electrodes and also between adjacent third electrodes.

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