Semiconductor structure

Abstract

This disclosure relates to the semiconductor field and provides a semiconductor structure, including: a substrate and an array structure located on the substrate; the array structure includes a first transistor array and a second transistor array, the first transistor array including a plurality of first semiconductor pillars, and the second transistor array including a plurality of second semiconductor pillars; a memory structure located between the first transistor array and the second transistor array; the memory structure includes a plurality of first capacitors and a plurality of second capacitors, the first capacitors including a first electrode electrically contacting the top surface of the first semiconductor pillars, the second capacitors including a second electrode electrically contacting the bottom surface of the second semiconductor pillars, and a common electrode provided between the first capacitors and the second capacitors; a lead structure, the lead structure including at least one electrode lead, the electrode lead being electrically contacting the common electrode, and the orthographic projection of the electrode lead on the substrate surface not coinciding with the orthographic projection of the array structure on the substrate surface, thereby improving the integration density of the semiconductor structure and reducing the difficulty of capacitor lead connection.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure. Background Technology

[0002] As various electronic products trend toward miniaturization, the design of Dynamic Random Access Memory (DRAM) cells must also meet the requirements of high integration and high density.

[0003] A DRAM memory cell consists of a storage transistor and a capacitor connected in series. In order to improve cell performance and reduce cell area, it is necessary to fabricate a capacitor with a large capacitance value per unit area. However, capacitors usually require a large space to achieve good charge storage efficiency.

[0004] Therefore, how to improve the integration density of semiconductor structures, obtain greater charge storage capacity, and reduce the difficulty of capacitor leads has become an important technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] This disclosure provides a semiconductor structure to improve the integration density of the semiconductor structure and reduce the difficulty of capacitor lead wires.

[0006] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including: a substrate; an array structure located on the substrate; the array structure including a first transistor array and a second transistor array, the first transistor array including a plurality of first semiconductor pillars, and the second transistor array including a plurality of second semiconductor pillars; a memory structure located between the first transistor array and the second transistor array; the memory structure including a plurality of first capacitors and a plurality of second capacitors, the first capacitors including a first electrode electrically contacting the top surface of the first semiconductor pillars, the second capacitors including a second electrode electrically contacting the bottom surface of the second semiconductor pillars, and a common electrode provided between the first capacitors and the second capacitors; and a lead structure including at least one electrode lead, the electrode lead being electrically contacting the common electrode, and the orthographic projection of the electrode lead on the substrate surface not coinciding with the orthographic projection of the array structure on the substrate surface.

[0007] In some embodiments, the common electrode includes: a first part and a second part, the second part being located around the first part, the orthographic projection of the first part on the substrate surface coinciding with the orthographic projection of the array structure on the substrate surface, and the electrode leads being electrically connected to the second part.

[0008] In some embodiments, the bottom of the electrode lead is located within the common electrode in a direction perpendicular to the substrate surface.

[0009] In some embodiments, electrode leads pass through a common electrode in a direction perpendicular to the substrate surface.

[0010] In some embodiments, the second part includes a plurality of corner regions, and a common electrode in each corner region is connected to at least one electrode lead.

[0011] In some embodiments, the electrode lead includes: an extension extending in a direction parallel to the substrate surface, one end of the extension being in electrical contact with the side of a common electrode; and a body extending in a direction perpendicular to the substrate surface, one end of the body being in electrical contact with the other end of the extension.

[0012] In some embodiments, the common electrode has multiple sides, and each side is in electrical contact with at least one electrode lead.

[0013] In some embodiments, each side is electrically contacted with a plurality of electrode leads, and among the plurality of electrode leads electrically contacting the same side, the orthographic projections of the extensions of different electrode leads on the substrate surface overlap each other, and the orthographic projections of the main bodies of different electrode leads on the substrate surface are staggered.

[0014] In some embodiments, each side is electrically contacted with a plurality of electrode leads, and among the plurality of electrode leads electrically contacting the same side, the orthographic projections of the extensions of different electrode leads on the substrate surface are staggered from each other, and the orthographic projections of the main bodies of different electrode leads on the substrate surface are staggered from each other.

[0015] In some embodiments, the semiconductor structure further includes word line leads and bit line leads; each extension is electrically contacted with a plurality of body portions, and the spacing between different body portions electrically contacting the same extension is a first spacing, which is greater than the spacing between adjacent bit line leads or the spacing between adjacent word line leads.

[0016] In some embodiments, the semiconductor structure includes: a plurality of array units stacked along a direction perpendicular to the substrate surface, each array unit including a first transistor array, a first capacitor, a second capacitor and a second transistor array stacked sequentially, and the plurality of array units sharing a lead structure.

[0017] In some embodiments, the semiconductor structure includes a first array unit and a second array unit, the second array unit being located above the first array unit, an electrode lead passing through a common electrode of the second array unit, and the bottom of the electrode lead being located within the common electrode of the first array unit.

[0018] In some embodiments, the semiconductor structure includes a first array unit and a second array unit, the second array unit being located above the first array unit. The side of the first array unit is electrically connected to a first electrode lead, the first electrode lead including a first extension and a first body portion electrically connected. The side of the second array unit is electrically connected to a second electrode lead, the second electrode lead including a second extension and a second body portion electrically connected. The first extension is electrically connected to the side of the first array unit, the second extension is electrically connected to the side of the second array unit, and the first body portion is electrically connected to the second body portion.

[0019] In some embodiments, the first array unit includes a first transistor array and a second transistor array, the second array unit includes a third transistor array and a fourth transistor array, and the second transistor array and the third transistor array are provided with a shared bit line structure.

[0020] In some embodiments, the orthographic projection of the second transistor array onto the substrate surface is offset from the orthographic projection of the third transistor array onto the substrate surface.

[0021] The technical solution provided by the embodiments of this disclosure has at least the following advantages: In the first transistor array, the top of the first semiconductor pillar is connected to the first electrode, and in the second transistor array, the bottom of the second semiconductor pillar is connected to the second electrode. By stacking the first transistor array with the corresponding first capacitor and the second transistor array with the second capacitor, the space utilization of the transistor structure and the corresponding capacitor structure can be improved, and the integration density of the semiconductor structure can be increased. Among them, a common electrode is provided between the first capacitor and the second capacitor, that is, the first capacitor and the second capacitor share the same upper plate, which can improve the utilization of the upper plate of the capacitor in the semiconductor structure and reduce the capacitor manufacturing process in the semiconductor structure, thereby improving the manufacturing efficiency of the semiconductor structure. The electrode leads in the lead structure are electrically contacted with the common capacitor, and the orthographic projection of the electrode leads on the substrate surface does not coincide with the orthographic projection of the array structure on the substrate surface, so that the common electrode in the stacked array structure and the memory structure is connected to the external device through the electrode leads, reducing the difficulty of the electrode leads of the capacitor in the stacked structure. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figures 1 to 7 This is a schematic diagram of various semiconductor structures provided in one embodiment of the present disclosure. Detailed Implementation

[0024] As can be seen from the background art, how to improve the integration density of semiconductor structures, obtain a large charge storage capacity, and reduce the difficulty of capacitor leads has become an important technical problem that needs to be solved by those skilled in the art.

[0025] Analysis revealed that a DRAM memory cell consists of a storage transistor and a capacitor connected in series. To improve cell performance and reduce cell area, a capacitor with a large capacitance value needs to be fabricated per unit area. However, capacitors typically require a large space to achieve good charge storage efficiency. To ensure the capacitor's storage capacity, electrodes usually need to be extended in the direction perpendicular to the substrate, for example, by setting a columnar lower electrode. Reducing the size of the transistor structure on a unit area substrate can increase the semiconductor structure integration density. However, the smaller the transistor structure, the more difficult it is to fabricate, and the more complex the capacitor structure process becomes. Furthermore, the difficulty of electrode lead fabrication increases in stacked semiconductor structures.

[0026] This disclosure provides a semiconductor structure to improve the integration density of the semiconductor structure and reduce the difficulty of capacitor lead wires.

[0027] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0028] Figures 1 to 7 This is a schematic diagram of various semiconductor structures provided in an embodiment of the present disclosure, wherein, Figure 2 and Figure 3 This is a top view of the semiconductor structure. Figure 4 and Figure 5 The diagram below illustrates the positional relationship between the common electrode and the electrode leads. The semiconductor structure provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0029] refer to Figure 1The semiconductor structure includes: a substrate 101; an array structure located on the substrate 101; the array structure includes a first transistor array 100 and a second transistor array 200, the first transistor array 100 including a plurality of first semiconductor pillars 203, and the second transistor array 200 including a plurality of second semiconductor pillars 303; a memory structure located between the first transistor array 100 and the second transistor array 200; the memory structure includes a plurality of first capacitors 110 and a plurality of second capacitors 120, the first capacitors 110 including a first electrode 211 electrically contacting the top surface of the first semiconductor pillars 203, the second capacitors 120 including a second electrode 221 electrically contacting the bottom surface of the second semiconductor pillars 303, and a common electrode 213 provided between the first capacitors 110 and the second capacitors 120; and a lead structure including at least one electrode lead 102, the electrode lead 102 being electrically contacting the common electrode 213, and the orthographic projection of the electrode lead 102 on the surface of the substrate 101 not coinciding with the orthographic projection of the array structure on the surface of the substrate 101.

[0030] In the first transistor array 100, the top of the first semiconductor pillar 203 is connected to the first electrode 211. In the second transistor array 200, the bottom of the second semiconductor pillar 303 is connected to the second electrode 221. By stacking the first transistor array 100 with the corresponding first capacitor 110 and the second transistor array 200 with the second capacitor 120, the space utilization of the transistor structure and the corresponding capacitor structure can be improved, and the integration density of the semiconductor structure can be increased. A common electrode 213 is provided between the first capacitor 110 and the second capacitor 120. The shared upper plate of capacitor 10 and second capacitor 120 can improve the utilization rate of the upper plate of capacitor in semiconductor structure and reduce the capacitor manufacturing process in semiconductor structure, thereby improving the manufacturing efficiency of semiconductor structure. The electrode lead 102 in the lead structure is electrically contacted with the shared electrode 213, and the orthographic projection of electrode lead 102 on the surface of substrate 101 does not coincide with the orthographic projection of array structure on the surface of substrate 101. This allows the shared electrode 213 in the stacked array structure and memory structure to be connected to external devices through electrode lead 102, reducing the difficulty of electrode lead of capacitor in stacked structure.

[0031] For the substrate, the material forming the substrate can be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. Elemental semiconductor materials can be silicon or germanium; crystalline inorganic compound semiconductor materials can be silicon carbide, silicon germanide, gallium arsenide, or indium gallium, etc.

[0032] The array structure includes a first transistor array 100 and a second transistor array 200.

[0033] For the first transistor array 100, the first transistor array 100 includes a plurality of first semiconductor pillars 203, the first semiconductor pillars 203 extending along a third direction Z, and also includes a plurality of first bit lines 201 extending along a first direction X and a plurality of first word lines 202 extending along a second direction Y. The bottom of the first semiconductor pillars 203 is connected to the first bit lines 201, the bottom of the plurality of first semiconductor pillars 203 along the first direction X is connected to the same first bit line 201, the first word lines 202 surround the first semiconductor pillars 203, and the same first word line 202 along the second direction Y surrounds the plurality of first semiconductor pillars 203. An isolation layer 204 is provided between adjacent transistor structures.

[0034] For the second transistor array 200, the second transistor array 200 includes a plurality of second semiconductor pillars 303, the second semiconductor pillars 303 extend along a third direction Z, and also include a plurality of second bit lines 301 extending along a first direction X and a plurality of second word lines 302 extending along a second direction Y. The top of the second semiconductor pillars 303 is connected to the second bit lines 301, the bottom of the plurality of second semiconductor pillars 303 along the first direction X is connected to the same second bit line 301, the second word lines 302 surround the second semiconductor pillars 303, and the same second word line 302 surrounds the plurality of second semiconductor pillars 303 along the second direction Y. An isolation layer 304 is provided between adjacent transistor structures.

[0035] It should be noted that, in this embodiment, the angle between the first direction X and the second direction Y is 90°, and the plane containing the first direction X and the second direction Y is parallel to the surface of the substrate 101, while the third direction Z is perpendicular to the surface of the substrate 101. That is, the angle between the plane containing the first direction X and the second direction Y and the third direction Z is 90°. In other embodiments, the angle between the first direction and the second direction can be 30°, 45°, or 60°, and the angle between the plane containing the first direction and the second direction and the surface of the substrate can be 30°, 45°, or 60°. In this embodiment, the angle between the third direction and the surface of the substrate can be 30°, 45°, or 60°, and the angle between the plane containing the first direction and the second direction and the third direction can be 30°, 45°, or 60°. This embodiment does not constitute a limitation on the angle between the first direction, the second direction, and the third direction.

[0036] For the first semiconductor pillar 203 and the second semiconductor pillar 303, the materials of both the first semiconductor pillar 203 and the second semiconductor pillar 303 include at least one of IGZO (Indium Gallium Zinc Oxide), IWO (Indium Tungsten Oxide), or ITO (Indium Tin Oxide).

[0037] For both the first line 201 and the second line 301, the material of both the first line 201 and the second line 301 includes at least one of metal silicide, titanium nitride, or tungsten. In some embodiments, the material forming the first line can be a single metal, a metal compound, or an alloy. The single metal can be titanium, aluminum, tungsten, gold, or silver, etc.; the metal compound can be tantalum nitride or titanium nitride; and the alloy can be an alloy material composed of at least two of titanium, aluminum, tungsten, gold, or silver.

[0038] For the first letter 202 and the second letter 302, the materials of both the first letter 202 and the second letter 302 include at least one of polycrystalline silicon, titanium nitride, titanium aluminide, tantalum nitride, tantalum, titanium, aluminum, lanthanum, platinum or tungsten.

[0039] In this embodiment, the first transistor array and the second transistor array are arranged facing each other, and the first semiconductor pillar and the second semiconductor pillar are arranged facing each other; in other embodiments, the first transistor array and the second transistor array may be staggered, and the first semiconductor pillar and the second semiconductor pillar may be staggered. In this embodiment, the first word line and the second word line extend in the same direction, and the first bit line and the second bit line extend in the same direction; in other embodiments, the first word line and the second word line may extend in different directions, and the first bit line and the second bit line may extend in different directions.

[0040] The storage structure includes multiple first capacitors 110 and multiple second capacitors 120.

[0041] The first capacitor 110 includes a first electrode 211, a first dielectric layer 212, and a common electrode 213. In this embodiment, the first electrode 211 is a columnar electrode, with its bottom correspondingly connected to the first semiconductor pillar 203; the first dielectric layer 212 covers the top and sidewalls of the first electrode 211; and the common electrode 213 covers and fills the gaps between the first dielectric layers 212. In other embodiments, the first electrode may be a hollow cylindrical electrode, with its bottom correspondingly connected to the first semiconductor pillar; the first dielectric layer covers the top, inner sidewalls, and outer sidewalls of the first electrode; and the common electrode covers and fills the gaps between the first dielectric layers.

[0042] The material of the first electrode includes at least one of platinum nickel, titanium, tantalum, cobalt, polycrystalline silicon, tungsten, tantalum nitride, titanium nitride, or ruthenium.

[0043] For the common electrode, the material of the common electrode includes at least one of platinum nickel, titanium, tantalum, cobalt, polycrystalline silicon, tungsten, tantalum nitride, titanium nitride, or ruthenium.

[0044] In some embodiments, the material of the first electrode is the same as the material of the common electrode; in other embodiments, the material of the first electrode may be different from the material of the common electrode.

[0045] For the first dielectric layer, the material of the first dielectric layer includes high dielectric constant materials such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate.

[0046] The second capacitor 120 shares a common electrode 213 with the first capacitor 110. The second capacitor 120 further includes a second dielectric layer 222 and a second electrode 221. In this embodiment, the second electrode 221 is a columnar electrode, the second dielectric layer covers the bottom and sidewalls of the second electrode 221, and the second electrode is located within the common electrode 213. In other embodiments, the second electrode may be a hollow cylindrical electrode, the second dielectric layer covers the bottom, inner sidewalls, and outer sidewalls of the second electrode, and the second electrode is located within the common electrode.

[0047] For the second electrode, the material of the second electrode includes at least one of platinum nickel, titanium, tantalum, cobalt, polycrystalline silicon, tungsten, tantalum nitride, titanium nitride, or ruthenium.

[0048] In some embodiments, the material of the second electrode is the same as that of the common electrode; in other embodiments, the material of the second electrode may be different from that of the common electrode.

[0049] For the second dielectric layer, the material of the second dielectric layer includes high dielectric constant materials such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate.

[0050] It should be noted that in this embodiment, the first electrode and the second electrode are directly opposite each other, and the corresponding first capacitor and the second capacitor are directly opposite each other; in other embodiments, the first electrode and the second electrode may be misaligned, and the corresponding first capacitor and the second capacitor may be misaligned.

[0051] In other embodiments, the first electrode can be either a columnar electrode or a hollow cylindrical electrode, and the second electrode can be either a columnar electrode or a hollow cylindrical electrode. The columnar electrode is located inside the hollow cylindrical electrode, and the common electrode is located in the region between the first and second electrodes, or it can be located on the side of the first electrode and the side of the second electrode. By placing the columnar electrode inside the hollow cylindrical electrode, the space occupied by the capacitor structure can be further reduced when the first capacitor and the second capacitor share the same common electrode, thereby improving the space utilization of the semiconductor structure and increasing the integration density of the semiconductor structure.

[0052] For the lead structure, the lead structure includes at least one electrode lead 102, which is in electrical contact with the common electrode 213, and the orthographic projection of the electrode lead 102 on the surface of the substrate 101 does not coincide with the orthographic projection of the array structure on the surface of the substrate 101.

[0053] In this embodiment, the electrode lead 102 is made of the same material as the common electrode 213; in other embodiments, the electrode lead may be made of a different material than the common electrode. It is understood that using the same material for the electrode lead as the common electrode can reduce contact resistance.

[0054] In some embodiments, the common electrode 213 includes a first portion 313 and a second portion 323, the second portion 323 being located around the first portion 313. The orthographic projection of the first portion 313 onto the surface of the substrate 101 coincides with the orthographic projection of the array structure onto the substrate surface. The electrode lead 102 is electrically connected to the second portion 323. Electrical connection between the electrode lead and the second portion avoids interference between the electrode lead and the device structure in the array structure or memory structure, thereby improving the stability of the semiconductor structure.

[0055] In some embodiments, the bottom of the electrode lead 102 is located within the common electrode 213 in a direction perpendicular to the surface of the substrate 101; in other embodiments, the electrode lead penetrates the common electrode in a direction perpendicular to the surface of the substrate. It is understood that when the bottom of the electrode lead is located within the common electrode, the common electrode can be electrically connected to the electrode lead, thereby reducing the fabrication difficulty of the electrode lead; when the electrode lead penetrates the common electrode, the contact area between the electrode lead and the common electrode can be increased, even with a relatively high common electrode, thus improving the transmission capability of the electrode lead.

[0056] refer to Figure 2 Furthermore, in some embodiments, the second portion 323 may include multiple corner regions 333, with a common electrode 213 of each corner region 333 connected to at least one electrode lead 102. It is understood that by providing electrode leads in multiple corner regions of the second portion, multiple electrode leads can be connected in parallel, thereby reducing the resistance of the electrode leads and improving their transmission efficiency.

[0057] Return to reference Figure 1In some embodiments, the electrode lead 102 includes: an extension 103 extending in a direction parallel to the surface of the substrate 101, one end of which is electrically in contact with the side of the common electrode 213; and a main body 104 extending in a direction perpendicular to the surface of the substrate 101, one end of which is electrically in contact with the other end of the extension 103. The extension allows the electrode lead to be electrically in contact with the side of the common electrode, and the extension extends in a direction away from the side of the common electrode. The other end of the extension is electrically in contact with one end of the main body, and the other end of the main body extends in a direction perpendicular to the substrate surface. This increases the distance between the electrode lead and the common electrode, preventing the electrode lead from affecting the memory structure or array structure.

[0058] It should be noted that in the accompanying drawings provided in this embodiment, the main body 104 extends in a direction away from the surface of the substrate 101; in other embodiments, the main body may also extend in a direction pointing towards the surface of the substrate.

[0059] refer to Figure 3 Furthermore, in some embodiments, the common electrode 213 has multiple sides, each of which is in electrical contact with at least one electrode lead 102. It is understood that by connecting the electrode leads to the multiple sides of the common electrode respectively, the electrode leads can be connected in parallel, thereby reducing resistance and improving the transmission efficiency of the electrode leads.

[0060] In some embodiments, the semiconductor structure further includes word line leads 105 and bit line leads 106; each extension 103 corresponds to an electrical contact with a plurality of main body portions 104, and the spacing between different main body portions 104 electrically contacting the same extension 103 is a first spacing, which is greater than the spacing between adjacent bit line leads 106 or the spacing between adjacent word line leads 105. Setting the first spacing to be greater than the spacing between adjacent bit line leads 106 or adjacent word line leads 105 can reduce the process difficulty of electrical contact between the same extension 103 and multiple main body portions 104, and increasing the spacing between multiple main body portions 104 connected to the same extension 103 can avoid mutual interference between the main body portions 104.

[0061] For the word line leads 105, along the first direction X, the word line leads 105 are staggered at both ends of the first word line and also staggered at both ends of the second word line. One end of the word line lead 105 is electrically in contact with either the first or second word line, and the other end extends along the third direction Z. Thus, compared to a scheme where the word line leads 105 are located at the same end of multiple adjacent first word lines, the staggered arrangement avoids signal interference between adjacent word line leads 105 and improves the allowable error in the manufacturing process of the word line leads 105.

[0062] For the bit line leads 106, along the second direction Y, the bit line leads 106 are staggered at both ends of the first bit line and also staggered at both ends of the second bit line. One end of the bit line lead 106 is electrically in contact with either the first or second bit line, and the other end extends along the third direction Z. Thus, compared to a scheme where the bit line leads 106 are located at the same end of multiple adjacent first bit lines, the staggered arrangement avoids signal interference between adjacent bit line leads 106 and improves the allowable process error during the manufacturing of the bit line leads 106.

[0063] refer to Figure 4 In some embodiments, each side of the common electrode 213 is in electrical contact with a plurality of electrode leads 102, and among the plurality of electrode leads 102 in electrical contact with the same side, the orthographic projections of the extensions 103 of different electrode leads 102 on the surface of the substrate 101 overlap with each other, and the orthographic projections of the main body portions 104 of different electrode leads 102 on the surface of the substrate 101 are staggered.

[0064] refer to Figure 5 In some embodiments, each side of the common electrode 213 is in electrical contact with a plurality of electrode leads 102, and among the plurality of electrode leads 102 in electrical contact with the same side, the orthographic projections of the extensions 103 of different electrode leads 102 on the surface of the substrate 101 are staggered from each other, and the orthographic projections of the main body portions 104 of different electrode leads 102 on the surface of the substrate 101 are staggered from each other.

[0065] It is understandable that when each side of the common electrode 213 is in electrical contact with multiple electrode leads 102, the different electrode leads can be arranged according to the actual situation to avoid mutual interference between different electrode leads or interference between electrode leads and other devices in the semiconductor structure.

[0066] It should be noted that the electrode lead configuration schemes provided in the above embodiments can be arbitrarily combined without conflict to achieve new embodiments; the multiple electrode lead configuration schemes provided in this embodiment do not constitute a limitation on the electrode lead configuration scheme.

[0067] In some embodiments, the semiconductor structure includes: a plurality of array units stacked along a direction perpendicular to the substrate surface, each array unit including a first transistor array, a first capacitor, a second capacitor and a second transistor array stacked sequentially, and the plurality of array units sharing a lead structure.

[0068] Specifically, refer to Figure 6In some embodiments, the semiconductor structure includes a first array unit 10 and a second array unit 11, the second array unit 11 being located above the first array unit 10, and the first array unit 10 and the second array unit 11 sharing a bit line 305; an electrode lead 102 passing through the common electrode 413 of the second array unit 11, and the bottom of the electrode lead 102 being located within the common electrode 213 of the first array unit 10.

[0069] Specifically, refer to Figure 7 In some embodiments, the semiconductor structure includes a first array unit 10 and a second array unit 11, the second array unit 11 being located above the first array unit 10. The side of the first array unit 10 is electrically connected to a first electrode lead 107, the first electrode lead 107 including an electrically connected first extension 117 and a first body portion 127. The side of the second array unit 11 is electrically connected to a second electrode lead 108, the second electrode lead 108 including an electrically connected second extension 118 and a second body portion 128. The first extension 117 is electrically connected to the side of the first array unit 10, the second extension 118 is electrically connected to the side of the second array unit 11, and the first body portion 127 is electrically connected to the second body portion 128.

[0070] By connecting the common electrode of the first array unit and the common electrode of the second array unit to the same electrode lead, the control terminals of the electrode lead can be reduced when multiple array units are stacked, thereby improving the utilization efficiency of the electrode lead.

[0071] In this embodiment, the first array unit and the second array unit have the same structure; in other embodiments, the first array unit and the second array unit may have different structures.

[0072] In some embodiments, the first array unit includes a first transistor array and a second transistor array, and the second array unit includes a third transistor array and a fourth transistor array. A shared bit line structure is provided between the second transistor array and the third transistor array. By providing a shared bit line structure between the second transistor array and the third transistor array, the control capability of the bit line structure can be improved, the fabrication process of the bit line structure can be reduced, and the fabrication efficiency of the semiconductor structure can be improved.

[0073] In some embodiments, the orthographic projection of the second transistor array onto the substrate surface coincides with the orthographic projection of the third transistor array onto the substrate surface; in other embodiments, the orthographic projection of the second transistor array onto the substrate surface is offset from the orthographic projection of the third transistor array onto the substrate surface.

[0074] The semiconductor structure provided in this disclosure has the following characteristics: in the first transistor array, the top of the first semiconductor pillar is connected to the first electrode; in the second transistor array, the bottom of the second semiconductor pillar is connected to the second electrode. By stacking the first transistor array with the corresponding first capacitor and the second transistor array with the second capacitor, the space utilization of the transistor structure and the corresponding capacitor structure can be improved, and the integration density of the semiconductor structure can be increased. A common electrode is provided between the first capacitor and the second capacitor, meaning the first capacitor and the second capacitor share an upper electrode plate. This improves the utilization rate of the upper electrode plate of the capacitor in the semiconductor structure and reduces the capacitor fabrication process, thus improving the fabrication efficiency of the semiconductor structure. The electrode leads in the lead structure are electrically contacted with the common capacitor, and the orthographic projection of the electrode leads on the substrate surface does not coincide with the orthographic projection of the array structure on the substrate surface. This allows the common electrode in the stacked array structure and the memory structure to be connected to external devices through the electrode leads, reducing the difficulty of electrode lead fabrication for the capacitors in the stacked structure.

[0075] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; An array structure is located on the substrate; the array structure includes a first transistor array and a second transistor array, the first transistor array including a plurality of first semiconductor pillars, and the second transistor array including a plurality of second semiconductor pillars; A storage structure is located between the first transistor array and the second transistor array; the storage structure includes a plurality of first capacitors and a plurality of second capacitors, the first capacitors include a first electrode that is electrically in contact with the top surface of the first semiconductor pillar, the second capacitors include a second electrode that is electrically in contact with the bottom surface of the second semiconductor pillar, and a common electrode is provided between the first capacitors and the second capacitors; The lead structure includes at least one electrode lead, which is in electrical contact with the common electrode, and the orthographic projection of the electrode lead on the substrate surface does not coincide with the orthographic projection of the array structure on the substrate surface.

2. The semiconductor structure as described in claim 1, characterized in that, The common electrode includes a first part and a second part, the second part being located around the first part, the orthographic projection of the first part on the substrate surface coinciding with the orthographic projection of the array structure on the substrate surface, and the electrode lead being electrically connected to the second part.

3. The semiconductor structure as described in claim 1, characterized in that, In a direction perpendicular to the substrate surface, the bottom of the electrode lead is located within the common electrode.

4. The semiconductor structure as described in claim 1, characterized in that, The electrode leads pass through the common electrode in a direction perpendicular to the surface of the substrate.

5. The semiconductor structure as described in claim 2, characterized in that, The second part includes multiple corner areas, and the common electrode of each corner area is connected to at least one electrode lead.

6. The semiconductor structure as described in claim 1, characterized in that, The electrode leads include: An extension extends in a direction parallel to the surface of the substrate, and one end of the extension is in electrical contact with the side of the common electrode. The main body extends in a direction perpendicular to the surface of the substrate, and one end of the main body is in electrical contact with the other end of the extension.

7. The semiconductor structure as described in claim 6, characterized in that, The common electrode has multiple sides, and each side is in electrical contact with at least one of the electrode leads.

8. The semiconductor structure as described in claim 7, characterized in that, Each of the said side surfaces is in electrical contact with a plurality of said electrode leads, and among the plurality of said electrode leads in electrical contact with the same said side surface, the orthographic projections of the extension portions of different said electrode leads on the substrate surface coincide with each other, and the orthographic projections of the main body portions of different said electrode leads on the substrate surface are staggered with each other.

9. The semiconductor structure as described in claim 7, characterized in that, Each of the said side surfaces is in electrical contact with a plurality of said electrode leads, and among the plurality of said electrode leads in electrical contact with the same said side surface, the orthographic projections of the extension portions of different said electrode leads on the substrate surface are staggered from each other, and the orthographic projections of the main body portions of different said electrode leads on the substrate surface are staggered from each other.

10. The semiconductor structure as described in claim 6, characterized in that, The semiconductor structure further includes word lines and bit lines; each extension is electrically contacted with a plurality of main bodies, and the spacing between different main bodies electrically contacting the same extension is a first spacing, which is greater than the spacing between adjacent bit lines or adjacent word lines.

11. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure includes a plurality of array units stacked along a direction perpendicular to the surface of the substrate. Each array unit includes a first transistor array, a first capacitor, a second capacitor, and a second transistor array stacked sequentially. The plurality of array units share the lead structure.

12. The semiconductor structure as claimed in claim 11, characterized in that, The semiconductor structure includes a first array unit and a second array unit, the second array unit being located above the first array unit, the electrode lead passing through the common electrode of the second array unit, and the bottom of the electrode lead being located within the common electrode of the first array unit.

13. The semiconductor structure as described in claim 11, characterized in that, The semiconductor structure includes a first array unit and a second array unit, the second array unit being located above the first array unit. The side of the first array unit is electrically connected to a first electrode lead, the first electrode lead including a first extension and a first main body portion electrically connected. The side of the second array unit is electrically connected to a second electrode lead, the second electrode lead including a second extension and a second main body portion electrically connected. The first extension is electrically connected to the side of the first array unit, the second extension is electrically connected to the side of the second array unit, and the first main body portion is electrically connected to the second main body portion.

14. The semiconductor structure as described in claim 12 or 13, characterized in that, The first array unit includes a first transistor array and a second transistor array, the second array unit includes a third transistor array and a fourth transistor array, and the second transistor array and the third transistor array are provided with a shared bit line structure.

15. The semiconductor structure as described in claim 14, characterized in that, The orthographic projection of the second transistor array on the substrate surface at least partially overlaps with or offsets the orthographic projection of the third transistor array on the substrate surface.

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