Semiconductor memory device and method for manufacturing semiconductor memory device

Abstract

A semiconductor memory device and a method for manufacturing the semiconductor memory device are provided. The semiconductor memory device includes a gate stack structure having a cell array region and a contact region having a step shape, wherein the roughness of a first sidewall of the cell array region is greater than the roughness of a second sidewall of the contact region.

Description

Technical Field

[0001] Various embodiments of the present disclosure generally relate to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a three-dimensional semiconductor memory device and a method of manufacturing the same. Background Art

[0002] A three-dimensional semiconductor memory device including a plurality of three-dimensionally arranged memory cells has been proposed to increase integration density.

[0003] As the number of memory cells stacked over a substrate increases, the integration density of a three-dimensional semiconductor memory device may increase. However, as the number of stacked memory cells increases, process stability may deteriorate. Summary of the invention

[0004] According to an embodiment, a semiconductor memory device may include: a source structure; and a gate stack structure arranged above the source structure, the gate stack structure having a cell array region and a contact region having a stepped shape, wherein the roughness of a first side wall of the cell array region of the gate stack structure is higher than the roughness of a second side wall of the contact region of the gate stack structure.

[0005] According to an embodiment, a semiconductor memory device may include: a first gate stack structure and a second gate stack structure spaced apart from each other; a vertical structure between the first gate stack structure and the second gate stack structure, the vertical structure including a first portion and a second portion; and a plurality of cell plugs passing through the first gate stack structure and the second gate stack structure to be adjacent to both sides of the first portion of the vertical structure, wherein the first portion of the vertical structure includes a recess and a protrusion facing the plurality of cell plugs, and wherein the second portion of the vertical structure is formed into a straight shape.

[0006] According to an embodiment, a method for manufacturing a semiconductor memory device may include the following steps: forming a stacking structure having a cell array region and a contact region; forming a hole group having a plurality of channel holes and a plurality of auxiliary holes, wherein the plurality of channel holes and the plurality of auxiliary holes pass through the cell array region of the stacking structure and are arranged in a plurality of rows; forming a memory layer along a surface of each of the plurality of channel holes; forming a channel structure on the memory layer; forming a first groove passing through the contact region of the stacking structure; and removing a portion of the stacking structure through the plurality of auxiliary holes and the first groove so as to form a slit, wherein the plurality of auxiliary holes and the first groove are connected in the slit. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram of a semiconductor memory device according to an embodiment;

[0008] Figure 2 It is shown Figure 1 A circuit diagram of an embodiment of a memory cell array is shown;

[0009] Figure 3 is a plan view of a semiconductor memory device according to an embodiment;

[0010] Figure 4 is an enlarged plan view of a portion of a semiconductor memory device according to an embodiment;

[0011] Figure 5A and Figure 5B It is shown Figure 3 A cross-sectional view of a semiconductor memory device shown;

[0012] Figure 6 , Fig. 7A and Figure 7B is a diagram showing a process of forming a lower structure according to an embodiment;

[0013] Figure 8 , Fig. 9A , Fig. 9B , Fig.10 , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A and Fig. 13B is a diagram showing a process of forming a stacked structure and a hole group and a process of forming a plurality of sacrificial posts according to an embodiment;

[0014] Fig.14A , Fig. 14B , Fig.15A and Fig. 15B is a diagram showing a process of forming a plurality of unit plugs and a process of forming a stepped stack structure according to an embodiment;

[0015] Fig.16 , Fig.17A and Fig. 17B is a diagram showing a process of forming a plurality of grooves and a plurality of support holes according to an embodiment;

[0016] Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B and Fig.21 is a diagram illustrating a process of forming a vertical insulating structure and a plurality of supporting pillars and a process of forming a sacrificial structure according to an embodiment;

[0017] Fig.22A , Fig. 22B , Fig.23, Fig.24 and Fig.25 is a diagram showing a process of forming a slit according to an embodiment;

[0018] Fig.26A and Fig.26B yes Fig.25 An enlarged plan view of some areas of the stepped laminate structure shown penetrated by the slits;

[0019] Fig.27A , Fig.27B , Fig.27C , Fig.27D and Fig.27E is an enlarged cross-sectional view showing a process of forming a source structure according to an embodiment;

[0020] Fig.28A , Fig.28B , Fig.29A and Fig.29B is a diagram showing a process of forming a conductive pattern according to an embodiment;

[0021] Fig.30 is a cross-sectional view showing a process of forming a conductive source contact according to an embodiment;

[0022] Fig.31 is a block diagram showing a configuration of a memory system according to an embodiment; and

[0023] Fig.32 is a block diagram showing a configuration of a computing system according to an embodiment. DETAILED DESCRIPTION

[0024] In order to describe the implementation of the concept according to the present disclosure, the specific structure or function description disclosed below is only illustrative. The implementation of the concept according to the present disclosure should not be interpreted as limited to the specific implementation described herein, but can be implemented in various forms and replaced by equivalent implementations.

[0025] Hereinafter, various components may be described using terms such as "first" and "second". However, the components should not be limited by these terms. The above terms are used to distinguish one component from another.

[0026] Various embodiments relate to a semiconductor memory device capable of improving process stability and a method of manufacturing the semiconductor memory device.

[0027] Figure 1 is a block diagram of a semiconductor memory device 100 according to an embodiment.

[0028] Reference Figure 1 , the semiconductor memory device 100 may include a peripheral circuit structure 190 and a memory cell array 110 .

[0029] The peripheral circuit structure 190 may be configured to perform a program operation and a verification operation for storing data in the memory cell array 110, a read operation for outputting data stored in the memory cell array 110, and an erase operation for erasing data stored in the memory cell array 110. The peripheral circuit structure 190 may include an input / output circuit 180, a control circuit 150, a voltage generation circuit 130, a row decoder 120, a column decoder 170, a page buffer 160, and a source line driver 140.

[0030] The memory cell array 110 may include a plurality of memory cells storing data. According to an embodiment, the memory cell array 110 may include a three-dimensional memory cell array. The plurality of memory cells may store single-bit data or multi-bit (i.e., two or more bits) data per cell. The plurality of memory cells may form a plurality of memory cell strings. Each memory cell string may include a plurality of memory cells connected in series to each other through a channel structure. The channel structure may be connected to the page buffer 160 through a corresponding bit line BL among a plurality of bit lines BL.

[0031] The input / output circuit 180 may transfer a command CMD and an address ADD received from an external device (eg, a memory controller) of the semiconductor memory device 100 to the control circuit 150. The input / output circuit 180 may exchange data DATA with the external device and the column decoder 170.

[0032] The control circuit 150 may output an operation signal OP_S, a row address RADD, a source line control signal SL_S, a page buffer control signal PB_S, and a column address CADD in response to a command CMD and an address ADD.

[0033] The voltage generation circuit 130 may generate various operation voltages Vop for performing a program operation, a verification operation, a read operation, and an erase operation in response to an operation signal OP_S.

[0034] The row decoder 120 may be coupled to the memory cell array 110 through a plurality of drain select lines DSL, a plurality of word lines WL, and a plurality of source select lines SSL. The row decoder 120 may transmit an operation voltage Vop to the plurality of drain select lines DSL, a plurality of word lines WL, and a plurality of source select lines SSL in response to a row address RADD.

[0035] The column decoder 170 may transmit data DATA input from the input / output circuit 180 to the page buffer 160 or transmit data DATA stored in the page buffer 160 to the input / output circuit 180 in response to the column address CADD. The column decoder 170 may exchange data DATA with the input / output circuit 180 through the column line CLL. The column decoder 170 may exchange data DATA with the page buffer 160 through the data line DTL.

[0036] The page buffer 160 may be coupled to the memory cell array 110 through the bit lines BL. The page buffer 160 may temporarily store data DATA received through the plurality of bit lines BL in response to a page buffer control signal PB_S. The page buffer 160 may sense voltages or currents of the plurality of bit lines BL during a read operation.

[0037] The source line driver 140 may transmit a source voltage Vsl to the memory cell array 110 in response to a source line control signal SL_S.

[0038] Figure 2 It is shown Figure 1 A circuit diagram of an embodiment of a memory cell array is shown.

[0039] Reference Figure 2 , the memory cell array may include a plurality of memory cell strings CS1 and CS2 connected to a plurality of bit lines BL. The plurality of memory cell strings CS1 and CS2 may be commonly connected to a source line SL. According to an embodiment, a plurality of first memory cell strings CS1 and a plurality of second memory cell strings CS2 may be commonly connected to a source line SL.

[0040] At least one pair of first and second memory cell strings CS1 and CS2 may be connected to each of the plurality of bit lines BL.

[0041] Each of the plurality of first memory cell strings CS1 and each of the plurality of second memory cell strings CS2 may include a source select transistor SST disposed between a source line SL and a bit line BL, a plurality of memory cells MC, and a drain select transistor DST.

[0042] The source selection transistor SST may control the electrical connection between the plurality of memory cells MC and the source line SL. One source selection transistor SST may be provided between the source line SL and the plurality of memory cells MC. Figure 2 Not shown, two or more source selection transistors connected in series to each other may be provided between the source line SL and the plurality of memory cells MC. The gate of the source selection transistor SST may be connected to the source selection line SSL. The operation of the source selection transistor SST may be controlled by a source selection signal applied to the source selection line SSL.

[0043] A plurality of memory cells MC may be disposed between a source selection transistor SST and a drain selection transistor DST. The plurality of memory cells MC between the source selection transistor SST and the drain selection transistor DST may be connected in series. The gates of the plurality of memory cells MC may be connected to each of the plurality of word lines WL. The operation of each of the plurality of memory cells MC may be controlled by a cell selection signal applied to the word line WL corresponding to each of the plurality of memory cells MC.

[0044] The drain select transistor DST may control electrical coupling between a plurality of memory cells MC and a bit line BL. A gate of the drain select transistor DST may be connected to a drain select line DSL1 or DSL2. The operation of the drain select transistor DST may be controlled by a drain selection signal applied to the drain select line DSL1 or DSL2.

[0045] A plurality of first memory cell strings CS1 may be connected to a first drain selection line DSL1. A plurality of second memory cell strings CS2 may be connected to a second drain selection line DSL2. Thus, one memory cell string (among the plurality of first memory cell strings CS1 and the plurality of second memory cell strings CS2) may be selected by selecting one bit line (among the plurality of bit lines BL) and one drain selection line (among the first drain selection line DSL1 and the second drain selection line DSL2).

[0046] The plurality of first memory cell strings CS1 and the plurality of second memory cell strings CS2 may be commonly connected to each of the plurality of word lines WL.

[0047] The plurality of first memory cell strings CS1 and the plurality of second memory cell strings CS2 may be commonly connected to a source selection line SSL. However, the embodiments of the present disclosure are not limited thereto. Figure 2 Not shown, according to an embodiment, the memory cell array may include a first source selection line and a second source selection line separated from each other. The first source selection line may be connected to a plurality of first memory cell strings and the second source selection line may be connected to a plurality of second memory cell strings.

[0048] Figure 3 is a plan view of a semiconductor memory device according to an embodiment. More specifically, Figure 3 This is a layout diagram of a gate stack structure of a semiconductor memory device.

[0049] Reference Figure 3 , the semiconductor memory device may include a plurality of gate stack structures GST. Each gate stack structure GST may extend along a plane. According to an embodiment, the gate stack structure GST may extend along an XY plane in an XYZ coordinate system.

[0050] The gate stack structure GST may include a cell array region CAR and a contact region CTR. The contact region CTR of the gate stack structure GST may extend from the cell array region CAR. According to an embodiment, the contact region CTR of the gate stack structure GST may extend from the cell array region CAR in the X-axis direction. The contact region CTR of the gate stack structure GST may include a plurality of pad portions P11, P12, P13, P14, P21, P22, P23, and P24. The plurality of pad portions P11 to P14 and P21 to P24 may be arranged at different heights in the Z-axis direction and may form a stepped structure in the contact region CTR.

[0051] The gate stack structure GST may include a first side wall SW1 defined along the cell array region CAR and a second side wall SW2 defined along the contact region CTR. The roughness of the first side wall SW1 may be greater than the roughness of the second side wall SW2. The first side wall SW1 may extend in a winding manner to have a recess and a protrusion. According to an embodiment, the first side wall SW1 may have a winding recess and a protrusion defined along the X-axis direction. The second side wall SW2 may extend in a substantially straight manner. According to an embodiment, the second side wall SW2 may extend in the X-axis direction.

[0052] A plurality of vertical structures 280 may be disposed between a plurality of gate stack structures GST spaced apart from each other. For example, the plurality of gate stack structures GST may include a first gate stack structure GST1 and a second gate stack structure GST2. One of the plurality of vertical structures 280 may be disposed between the first gate stack structure GST1 and the second gate stack structure GST2.

[0053] Each of the plurality of vertical structures 280 may include a first portion 280A and a second portion 280B. The first portion 280A of the vertical structure 280 may extend along the cell array region CAR of the gate stack structure GST, and the second portion 280B of the vertical structure 280 may extend along the contact region CTR of the gate stack structure GST. For example, the first portion 280A of the vertical structure 280 may be disposed between the first gate stack structure GST1 of the cell array region CAR and the second gate stack structure GST2 of the cell array region CAR. In addition, the second portion 280B of the vertical structure 280 may be disposed between the first gate stack structure GST1 of the contact region CTR and the second gate stack structure GST2 of the contact region CTR.

[0054] The semiconductor memory device may include a plurality of cell plugs CPL disposed adjacent to both sides of a first portion 280A of a vertical structure 280. The plurality of cell plugs CPL may pass through a cell array region CAR of a gate stack structure GST in a Z-axis direction. The first portion 280A of the vertical structure 280 may have a recess and a protrusion facing the plurality of cell plugs CPL. The recess and the protrusion of the first portion 280A may be defined along a first sidewall SW1 of the gate stack structure GST.

[0055] The gate isolation structure 253 may be embedded in the gate stack structure GST. Figure 2 The first drain selection line DSL1 and the second drain selection line DSL2 shown are separated from each other by an insulating material. The gate isolation structure 253 may extend in the same direction as the first portion 280A of the vertical structure 280. According to an embodiment, the gate isolation structure 253 may extend in the X-axis direction. A plurality of cell plugs CPL may be divided into a first group and a second group adjacent to both sides of the gate isolation structure 253. A plurality of dummy plugs DPL may be disposed between the cell plugs CPL of the first group and the cell plugs CPL of the second group. A plurality of dummy plugs DPL may pass through the gate stack structure GST in the Z-axis direction and may be arranged in a row adjacent to each other along the direction in which the gate isolation structure 253 extends. The gate isolation structure 253 may extend into a plurality of dummy plugs DPL. The gate isolation structure 253 may be formed to be shorter than the dummy plugs DPL in the Z-axis direction.

[0056] The semiconductor memory device may include a plurality of conductive gate contacts 293. The plurality of conductive gate contacts 293 may be disposed adjacent to both sides of the second portion 280B of the vertical structure 280. The plurality of conductive gate contacts 293 may contact the plurality of pad portions P11 to P14 and P21 to P24 of the gate stack structure GST and may extend in the Z-axis direction.

[0057] Each of the first portion 280A and the second portion 280B of the vertical structure 280 may include an insulating material, or may include an insulating material and a conductive material passing through the insulating material. According to an embodiment, each of the first portion 280A and the second portion 280B of the vertical structure 280 may include an insulating layer 281 and a conductive electrode contact 283.

[0058] The insulating layer 281 may extend along the first side wall SW1 and the second side wall SW2 of the gate stack structure GST. The conductive source contact 283 may be spaced apart from the gate stack structure GST with the insulating layer 281 interposed therebetween. The conductive source contact 283 may include at least one of a doped semiconductor layer, a metal silicide layer, a metal barrier layer, and a metal layer. The conductive source contact 283 may extend along the insulating layer 281 and may be formed to have a linear shape. According to an embodiment, each of the insulating layer 281 and the conductive source contact 283 may extend along the X-axis direction.

[0059] The contact region CTR of the gate stack structure GST may be penetrated by the vertical insulating structure 257 and the plurality of supporting pillars 255. The vertical insulating structure 257 and the plurality of supporting pillars 255 may include the same insulating material.

[0060] The vertical insulating structure 257 may extend linearly in the contact region CTR of the gate stack structure GST. According to an embodiment, the vertical insulating structure 257 may extend in the X-axis direction in the contact region CTR of the gate stack structure GST.

[0061] The plurality of support pillars 255 and the plurality of conductive gate contacts 293 may be alternately disposed. According to an embodiment, the plurality of support pillars 255 and the plurality of conductive gate contacts 293 may be alternately disposed in the X-axis direction.

[0062] Figure 4 is an enlarged plan view of a portion of a semiconductor memory device according to an embodiment. More specifically, Figure 4 2 is an enlarged plan view of a boundary portion between the first side wall SW1 and the second side wall SW2 of the gate stacked structure GST and a boundary portion between the first portion 280A and the second portion 280B of the vertical structure 280 .

[0063] Reference Figure 4 The first sidewall SW1 and the second sidewall SW2 of each gate stack structure GST may be coupled to each other. Each of the insulating layer 281 and the conductive source contact 283 may extend from the first portion 280A of the vertical structure 280 to the second portion 280B of the vertical structure 280 .

[0064] Figure 5A and Figure 5B It is shown Figure 3 A cross-sectional view of a semiconductor memory device is shown. Figure 5A It is along Figure 3 The cross-sectional view of the semiconductor memory device taken along the line II-I' and the line II-II' shown in FIG. Figure 5B It is along Figure 3 FIG. 1 is a cross-sectional view of the semiconductor memory device taken along line III-III′.

[0065] Reference Figure 5A and Figure 5B , a plurality of gate stacked structures GST may be disposed over the source structure 260. A lower insulating layer 235 may be disposed between the source structure 260 and each of the gate stacked structures GST.

[0066] The source structure 260 may extend along a plane to overlap the cell array region CAR and the contact region CTR of each gate stack structure GST. According to an embodiment, the source structure 260 may extend along an XY plane. Figure 5A and Figure 5B Not shown, Figure 1 The semiconductor substrate (not shown) shown with transistors forming the peripheral circuit structure 190 may be disposed below the source structure 260. In these embodiments, the source structure 260 may be disposed over an insulating structure (not shown) covering the semiconductor substrate.

[0067] The source structure 260 may include a doped semiconductor layer. According to an embodiment, the source structure 260 may include a first semiconductor layer 231, a channel contact layer 263, and a second semiconductor layer 233 stacked on each other. Each of the first semiconductor layer 231, the channel contact layer 263, and the second semiconductor layer 233 may include a doped semiconductor layer having a conductive type impurity. According to an embodiment, each of the first semiconductor layer 231, the channel contact layer 263, and the second semiconductor layer 233 may include an n-type doped semiconductor layer.

[0068] The second semiconductor layer 233 may be disposed over the first semiconductor layer 231. The channel contact layer 263 may be disposed between the first semiconductor layer 231 and the second semiconductor layer 233.

[0069] The first portion 280A and the second portion 280B of the vertical structure 280 may extend into the source structure 260. According to an embodiment, the first portion 280A and the second portion 280B of the vertical structure 280 may pass through the lower insulating layer 235, the second semiconductor layer 233, and the channel contact layer 263.

[0070] The conductive source contact 283 may be connected to the source structure 260. According to an embodiment, the conductive source contact 283 may be in contact with the first semiconductor layer 231 of the source structure 260. The source structure 260 and the conductive source contact 283 may be connected to Figure 2 According to an embodiment, the source structure 260 can be connected to the source line SL via the conductive source contact 283. Figure 2 The source line SL is shown.

[0071] The insulating layer 281 may be disposed between the conductive source contact 283 and each of the plurality of gate stack structures GST. The insulating layer 281 may pass through the lower insulating layer 235 and may extend toward the first semiconductor layer 231. According to an embodiment, the oxide layer 265 may be interposed between the insulating layer 281 and each of the first semiconductor layer 231, the channel contact layer 263, and the second semiconductor layer 233 of the source structure 260.

[0072] The plurality of memory cell strings CS may include a plurality of cell plugs CPL. Each of the plurality of memory cell strings CS may be connected not only to the source structure 260, but also to the plurality of conductive patterns CP of the gate stack structure GST. The gate stack structure GST may include not only a plurality of conductive patterns CP, but also a plurality of interlayer insulating layers ILD. The plurality of conductive patterns CP and the plurality of interlayer insulating layers ILD may be alternately stacked in the Z-axis direction above the source structure 260. Each conductive pattern CP may include various conductive materials such as a doped semiconductor layer, a metal layer, and a conductive metal nitride. The conductive pattern CP may include a single type of conductive material or two or more types of conductive materials. Each interlayer insulating layer ILD may include a silicon oxide layer.

[0073] Each cell plug CPL may include a first memory pattern ML1 , a channel structure CH, a core insulating layer CO, and a second memory pattern ML2 .

[0074] The channel structure CH may pass through the gate stack structure GST. The channel structure CH may extend into the source structure 260 to contact the source structure 260. According to an embodiment, the channel structure CH may pass through the second semiconductor layer 233 and may extend into the first semiconductor layer 231 of the source structure 260. The channel contact layer 263 of the source structure 260 may contact the sidewall of the channel structure CH and may surround the sidewall of the channel structure CH. The channel structure CH may be used as a channel region of the memory cell string CS. The channel structure CH may include a semiconductor layer. The channel structure CH may extend along the sidewall, bottom surface, and top surface of the core insulating layer CO. The doping region DPA may be defined by an end of the channel structure CH formed on the core insulating layer CO. The doping region DPA of the channel structure CH may include n-type impurities.

[0075] The first memory pattern ML1 may be disposed between the gate stack structure GST and the channel structure CH. The first memory pattern ML1 may extend between the second semiconductor layer 233 of the source structure 260 and the channel structure CH. The second memory pattern ML2 may be disposed between the first semiconductor layer 231 of the source structure 260 and the channel structure CH.

[0076] A plurality of conductive patterns CP may be used as Figure 2The first drain selection line DSL1, the second drain selection line DSL2, the plurality of word lines WL, and the source selection line SSL are shown. According to an embodiment, at least one conductive pattern adjacent to the source structure 260 among the plurality of conductive patterns CP may be used as Figure 2 The uppermost conductive pattern among the plurality of conductive patterns CP may be used as a source selection line SSL. Figure 2 The first drain selection line DSL1 and the second drain selection line DSL2 are shown. A conductive pattern disposed between the source selection line SSL and each of the first drain selection line DSL1 and the second drain selection line DSL2 among the plurality of conductive patterns CP may be used as Figure 2 The word line WL is shown.

[0077] According to the above structure, Figure 2 The memory cell MC shown may be defined at the intersection of the channel structure CH and the conductive pattern CP used as a word line. Figure 2 The drain selection transistor DST shown may be defined at an intersection of the channel structure CH and the conductive pattern CP used as the first drain selection line or the second drain selection line. Figure 2 The source select transistor SST shown may be defined at an intersection of the channel structure CH and the conductive pattern CP serving as a source select line. The source select transistor SST, the memory cells MC, and the drain select transistor DST may be coupled in series through the channel structure CH and may form a memory cell string CS.

[0078] A plurality of interlayer insulating layers ILD and a plurality of conductive patterns CP may form a plurality of pad portions P11 to P14 and P21 to P24 in the contact region CTR of the gate stack structure GST. Each of the plurality of pad portions P11 to P14 and P21 to P24 may include an interlayer insulating layer ILD and a conductive pattern CP corresponding to each pad portion. In other words, each of the plurality of pad portions P11 to P14 and P21 to P24 may include a corresponding pair of interlayer insulating layers ILD and a conductive pattern CP.

[0079] The plurality of gate stack structures GST and the plurality of cell plugs CPL may be covered by the first upper insulating layer 251. The vertical insulating structure 257 and the support pillar 255 may pass through the first upper insulating layer 251 and the gate stack structure GST. The bottom surface of each of the vertical insulating structure 257 and the support pillar 255 may extend along the top surface of the second semiconductor layer 233.

[0080] The first upper insulating layer 251, the vertical insulating structure 257, and the supporting pillar 255 may be covered by the second upper insulating layer 271. The second upper insulating layer 271 may be penetrated by the plurality of conductive bit line contacts 291 and the plurality of conductive gate contacts 293.

[0081] Each conductive bit line contact 291 may extend from a corresponding channel structure CH of the cell plug CPL to pass through the first upper insulating layer 251 and the second upper insulating layer 271. The channel structure CH may be connected to the cell plug CPL via the conductive bit line contact 291. Figure 2 The bit line BL is shown.

[0082] Each conductive gate contact 293 may extend to contact a corresponding conductive pattern CP of a pad portion among a plurality of pad portions P11 to P14 and P21 to P24 of the gate stack structure GST. Each conductive gate contact 293 may pass through the first upper insulating layer 251 and the second upper insulating layer 271. The plurality of conductive patterns CP may be connected to the gate stack structure GST via the plurality of conductive gate contacts 293. Figure 1 A row decoder 120 is shown.

[0083] Hereinafter, a method for manufacturing a semiconductor memory device according to an embodiment will be described mainly based on a cell array region CAR and a contact region CTR of the semiconductor memory device. Figure 3 , Figure 4 , Figure 5A and Figure 5B A detailed description of the description.

[0084] Figure 6 , Fig. 7A and Figure 7B is a diagram illustrating a process of forming the lower structure 300 according to an embodiment. Figure 6 is a plan view showing the lower structure 300, Fig. 7A It is along Figure 6 The cross-sectional view of the lower structure 300 taken along the lines II' and II-II' is shown. Figure 7B It is along Figure 6 The cross-sectional view of the lower structure 300 is taken along line III-III'.

[0085] Reference Figure 6 , Fig. 7A and Figure 7B, the lower structure 300 may include a first semiconductor layer 231, a sacrificial source layer 303 above the first semiconductor layer 231, a second semiconductor layer 233 above the sacrificial source layer 303, and an etch stop pattern 310 passing through the second semiconductor layer 233. The first semiconductor layer 231 may include a conductive type dopant. According to an embodiment, the first semiconductor layer 231 may include n-type doped silicon. The second semiconductor layer 233 may include a conductive type dopant or may be an undoped layer. According to an embodiment, the second semiconductor layer 233 may include n-type doped silicon or undoped silicon. According to an embodiment, the sacrificial source layer 303 may include undoped silicon. The etch stop pattern 310 may include a metal having an etch selectivity with respect to the second semiconductor layer 233. According to an embodiment, the etch stop pattern 310 may include a first metal nitride layer 313 extending along a sidewall and a bottom surface of the etch stop pattern 310 and may include a first metal layer 315 above the first metal nitride layer 313. According to an embodiment, the first metal nitride layer 313 may include a titanium nitride layer, and the first metal layer 315 may include tungsten.

[0086] The lower structure 300 may further include a first protective layer 301 between the first semiconductor layer 231 and the sacrificial source layer 303, and may include a second protective layer 305 between the sacrificial source layer 303 and the second semiconductor layer 233. The first protective layer 301 and the second protective layer 305 may include a material having an etching selectivity with respect to the sacrificial source layer 303. According to an embodiment, the first protective layer 301 and the second protective layer 305 may include an oxide layer.

[0087] The lower structure 300 may further include a lower insulating layer 235 on the second semiconductor layer 233. The lower insulating layer 235 may include an oxide layer.

[0088] Forming the lower structure 300 may include: stacking the first semiconductor layer 231, the first protective layer 301, the sacrificial source layer 303, the second protective layer 305, the second semiconductor layer 233 and the lower insulating layer 235 as described above; forming a plurality of grooves 311 passing through the lower insulating layer 235 and the second semiconductor layer 233; forming a first metal nitride layer 313 along the surface of each of the plurality of grooves 311; forming a first metal layer 315 on the first metal nitride layer 313; and planarizing the first metal layer 315 and the first metal nitride layer 313 to expose the lower insulating layer 235.

[0089] Each of the plurality of grooves 311 may extend from the cell array region CAR of the lower structure 300 to the contact region CTR of the lower structure 300. According to an embodiment, the plurality of grooves 311 may be formed to have a linear shape extending in the X-axis direction and may be spaced apart from each other in the Y-axis direction.

[0090] although Figure 6 , Fig. 7A and Figure 7B According to the embodiment, before forming the lower structure 300, a Figure 1 The first semiconductor substrate of the transistor of the peripheral circuit structure 190 shown in FIG. According to this embodiment, the lower structure 300 may be disposed over an insulating structure covering the first semiconductor substrate. According to another embodiment, the lower structure 300 may be formed over a second semiconductor substrate separate from the first semiconductor substrate, and a subsequent process of forming a memory cell array over the second semiconductor substrate may be performed ... Figure 1 The first semiconductor substrate of the transistors of the peripheral circuit structure 190 shown may be bonded to a memory cell array over a second semiconductor substrate via bonding pads.

[0091] Figure 8 , Fig. 9A , Fig. 9B , Fig.10 , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A and Fig. 13B is a diagram illustrating a process of forming a stacked structure and a hole group and a process of forming a plurality of sacrificial posts according to an embodiment.

[0092] Figure 8 is a plan view showing the first stack structure 320A and the first hole group HG1. Fig. 9A It is along Figure 8 The cross-sectional views of the first stack structure 320A are taken along lines II′ and II-II′. Fig. 9B It is along Figure 8 The cross-sectional view of the first stack structure 320A is taken along line III-III′.

[0093] Reference Figure 8 , Fig. 9A and Fig. 9B , the process of forming the stack structure and the hole group may include forming a first stack structure 320A and forming a first hole group HG1.

[0094] Forming the first stack structure 320A may include alternately stacking a plurality of lower first material layers 321A and a plurality of lower second material layers 323A over the lower structure 300. The first stack structure 320A may include a cell array region CAR and a contact region CTR. The plurality of lower first material layers 321A and the plurality of lower second material layers 323A may extend from the cell array region CAR to the contact region CTR.

[0095] Each of the plurality of lower first material layers 321A may include Figure 5A and Figure 5B The first metal layer 315 may be made of the same material as the interlayer insulating layer ILD shown. Each of the plurality of lower second material layers 323A may include a material having an etching selectivity relative to the plurality of lower first material layers 321A. According to an embodiment, the lower first material layer 321A may include an oxide such as a silicon oxide layer, and the lower second material layer 323A may include a nitride such as a silicon nitride layer. The etching selectivity of the first metal layer 315 relative to each of the plurality of lower first material layers 321A and the plurality of lower second material layers 323A may be higher than the etching selectivity of the second semiconductor layer 233 relative to each of the plurality of lower first material layers 321A and the plurality of lower second material layers 323A.

[0096] Subsequently, a first hard mask pattern 325 may be formed over the first stack structure 320A. The first hard mask pattern 325 may include a carbon layer. The first hard mask pattern 325 may include a plurality of first openings OP1 formed by a photolithography process. Each of the plurality of first openings OP1 may overlap with the cell array region CAR of the first stack structure 320A, and the contact region CTR of the first stack structure 320A may be blocked by the first hard mask pattern 325.

[0097] Thereafter, the first hole group HG1 may be formed by etching the plurality of lower first material layers 321A and the plurality of lower second material layers 323A through each of the plurality of first openings OP1. The lower insulating layer 235 may be etched during the etching process for forming the first hole group HG1.

[0098] The cell array region CAR of the first stacked structure 320A may include a plurality of first regions AR1 and a plurality of second regions AR2 arranged alternately with each other in one direction. The direction in which the plurality of first regions AR1 and the plurality of second regions AR2 are arranged may be different from the direction in which the cell array region CAR and the contact region CTR are arranged. According to an embodiment, the plurality of first regions AR1 and the plurality of second regions AR2 may be arranged alternately in the Y-axis direction. Two adjacent first regions AR1 may be arranged adjacent to both sides of the etching stop pattern 310. The second region AR2 may overlap with the corresponding etching stop pattern 310.

[0099] Each of the plurality of first regions AR1 may include two or more memory cell string regions MSA and a dummy region DMA between the memory cell string regions MSA. The memory cell string regions MSA of the first region AR1 may be arranged in a direction in which the plurality of first regions AR1 and the plurality of second regions AR2 are arranged.

[0100] The first hole group HG1 may include a plurality of lower channel holes 327A, a plurality of lower dummy holes 327B, and a plurality of lower auxiliary holes 327C. Each of the plurality of lower channel holes 327A and each of the plurality of lower dummy holes 327B may pass through the first region AR1 of the first stack structure 320A. Each of the plurality of lower auxiliary holes 327C may pass through the second region AR2 of the first stack structure 320A. The second semiconductor layer 233 may be exposed through the lower channel hole 327A and the lower dummy hole 327B, and the first metal layer 315 of the etch stop pattern 310 may be exposed through the lower auxiliary hole 327C. The cross-sectional shape of each of the lower channel hole 327A, the lower dummy hole 327B, and the lower auxiliary hole 327C may be circular, elliptical, or polygonal.

[0101] A plurality of lower channel holes 327A may be arranged in a plurality of rows. The lower channel holes of each row may be aligned with each other in a row in the first direction of the cell array region CAR facing the contact region CTR. According to an embodiment, the lower channel holes of each row may be aligned with each other in a row in the X-axis direction. The plurality of lower channel holes 327A may include a plurality of first lower channel holes 327A1 arranged in the first row and a plurality of second lower channel holes 327A2 arranged in the second row. The first row and the second row may be respectively arranged on both sides of the second region AR2. The plurality of lower auxiliary holes 327C may include lower auxiliary holes arranged in two rows in the second region AR2. For example, the plurality of lower auxiliary holes 327C may include a plurality of first lower auxiliary holes 327C1 arranged in a third row adjacent to the first row and a plurality of second lower auxiliary holes 327C2 arranged in a fourth row adjacent to the second row. According to the above arrangement, the first lower auxiliary hole 327C1 and the second lower auxiliary hole 327C2 may be arranged between the first lower channel hole 327A1 and the second lower channel hole 327A2.

[0102] The lower dummy hole 327B may have substantially the same width as the lower channel hole 327 A. Therefore, uniformity of the hole pattern in the first area AR1 may be improved.

[0103] The distance between the first lower auxiliary hole 327C1 and the second lower auxiliary hole 327C2 arranged in adjacent rows may be defined as being smaller than the distance D1 between the lower auxiliary hole 327C and the lower channel hole 327A arranged in adjacent rows. For example, the distance between the first lower auxiliary hole 327C1 and the second lower auxiliary hole 327C2 may be defined as being smaller than the distance D1 between the first lower channel hole 327A1 and the first lower auxiliary hole 327C1 or the distance D1 between the second lower channel hole 327A2 and the second lower auxiliary hole 327C2. The distance D1 between the lower auxiliary hole 327C and the lower channel hole 327A arranged in adjacent rows may be defined as being greater than each of the distance D2 between the lower channel holes 327A arranged in adjacent rows and the distance D3 between the lower channel hole 327A and the lower dummy hole 327B arranged in adjacent rows. When performing a subsequent process (which will be referred to below), Fig.25 The above design conditions may be beneficial when ensuring process margin in the process description).

[0104] A distance D3 between the lower channel holes 327A and the lower dummy holes 327B arranged in adjacent rows may be substantially the same as a distance D2 between the lower channel holes 327A arranged in adjacent rows. Therefore, uniformity of the hole pattern in the first area AR1 may be improved.

[0105] In the second direction in which the plurality of first regions AR1 and the plurality of second regions AR2 are arranged, the lower auxiliary hole 327C may have a width smaller than each of the lower channel hole 327A and the lower dummy hole 327B. According to an embodiment, the lower auxiliary hole 327C may have a width smaller than each of the lower channel hole 327A and the lower dummy hole 327B in the Y-axis direction. Therefore, the area of ​​the second region AR2 provided for the plurality of lower auxiliary holes 327C may be reduced, thereby increasing the integration density of the semiconductor memory device.

[0106] According to an embodiment, when the lower channel hole 327A and the lower dummy hole 327B are formed in the first region AR1 of the first stacked structure 320A, the lower auxiliary hole 327C may be formed in the second region AR2 of the first stacked structure 320A. Therefore, according to an embodiment, the continuity of the hole pattern in the unit array region CAR may be increased. For example, when the lower auxiliary hole 327C is not arranged in the second region AR2, the unit array region CAR may be divided into a region where the hole pattern is continuously arranged and a region where the hole pattern is not formed. In this example, when a photolithography process for defining the first opening is performed, an optical distortion phenomenon may occur, and the shape of the first opening adjacent to the region where the hole pattern is not formed may be distorted. According to an embodiment, a photomask for a plurality of first openings OP1 may be designed so that when the lower channel hole 327A and the lower dummy hole 327B are formed in the first region AR1 of the first stacked structure 320A, the lower auxiliary hole 327C is formed in the second region AR2 of the first stacked structure 320A. According to this design, optical distortion may be alleviated during a photolithography process for defining a plurality of first openings OP1. Therefore, according to an embodiment, shape distortion with respect to the plurality of first openings OP1 can be alleviated, and shape distortion of the first hole group HG1 defined by the plurality of first openings OP1 can also be alleviated. For example, the shape of each of the lower channel holes 327A1 or 327A2 in a row adjacent to the second area AR2 can be substantially the same as the shape of each of the plurality of lower channel holes 327A3 in rows other than the row adjacent to the second area AR2.

[0107] According to an embodiment, since an optical distortion phenomenon is alleviated, the plurality of lower channel holes 327A and the plurality of lower dummy holes 327B may be formed to have substantially the same width in the first area AR1 .

[0108] Fig.10 Is to show the expansion Figure 8 and Fig. 9A A plan view of the process showing the depth of each of the plurality of lower channel holes 327A is shown.

[0109] Reference Fig.10 The process of forming the stacked structure and the hole group may include forming a plurality of lower channel holes 327A' having an expanded depth. In order to form the plurality of lower channel holes 327A' having an expanded depth, the plurality of lower channel holes 327A' may be selectively etched through Figure 8 and Fig. 9A The first hole group HG1 shown exposes the second semiconductor layer 233, the second protection layer 305, the sacrificial source layer 303 and the first protection layer 301. Therefore, Figure 8 and Fig. 9AEach of the illustrated plurality of lower channel holes 327A may be expanded to a depth sufficient to pass through the second semiconductor layer 233 , the second protection layer 305 , the sacrificial source layer 303 , and the first protection layer 301 , thereby defining a plurality of lower channel holes 327A′ having an expanded depth.

[0110] The plurality of lower channel holes 327A' having an expanded depth may extend into the first semiconductor layer 231. When the plurality of lower channel holes 327A' having an expanded depth are formed, similar to the lower channel holes, Figure 8 The depth of each lower dummy hole 327B shown may be enlarged to extend into the first semiconductor layer 231 .

[0111] When the above-described selective etching process is performed, the second semiconductor layer 233 , the second protection layer 305 , the sacrificial source layer 303 , and the first protection layer 301 overlapping the lower auxiliary hole 327C may be protected by the etch stop pattern 310 .

[0112] Fig.11A and Fig. 11B is a cross-sectional view showing the lower sacrificial group 330 .

[0113] Reference Fig.11A and Fig. 11B , the process of forming the plurality of sacrificial pillars may include forming a lower sacrificial group 330. Forming the lower sacrificial group 330 may include: forming a sacrificial material; filling each of the plurality of lower auxiliary holes 327C and the plurality of lower channel holes 327A' having an expanded depth; and planarizing the surface of the sacrificial material to expose the first stack structure 320A. Although Fig.11A and Fig. 11B Not shown in FIG. 1 , the lower dummy hole having an enlarged depth may also be filled with a sacrificial material.

[0114] The sacrificial material may include a material having an etching selectivity not only with respect to the lower first material layer 321A and the lower second material layer 323A of the first stack structure 320A, but also with respect to the first semiconductor layer 231, the sacrificial source layer 303, and the second semiconductor layer 233. According to an embodiment, the sacrificial material may include a second metal nitride layer 331, a second metal layer 333, and a third metal nitride layer 335. For example, similar to the first metal nitride layer 313, the second metal nitride layer 331 and the third metal nitride layer 335 may include a titanium nitride layer. Similar to the first metal layer 315, the second metal layer 333 may include tungsten.

[0115] The second metal nitride layer 331 may extend along the surface of each of the plurality of lower auxiliary holes 327C and the plurality of lower channel holes 327A' having an expanded depth. The second metal layer 333 may be formed on the second metal nitride layer 331 and may be formed to have a height that opens the upper portion of each of the plurality of lower auxiliary holes 327C and the plurality of lower channel holes 327A' having an expanded depth. The third metal nitride layer 335 may be disposed on the second metal layer 333 in each of the plurality of lower auxiliary holes 327C and the plurality of lower channel holes 327A' having an expanded depth.

[0116] The lower sacrificial group 330 may include a first lower sacrificial pillar 330A filling the lower channel hole 327A′ having an expanded depth and a second lower sacrificial pillar 330C filling the lower auxiliary hole 327C. Fig.11A and Fig. 11B Not shown, the lower sacrificial group 330 may further include lower dummy pillars filling the lower dummy holes having the expanded depth, and a cross-section of the lower dummy pillars may be substantially the same as that of the first lower sacrificial pillars 330A.

[0117] Fig. 12A and Fig. 12B is a cross-sectional view showing the second stack structure 320B and the second hole group HG2.

[0118] Reference Fig. 12A and Fig. 12B , the process of forming the stacked structure and the hole group may include forming a second stacked structure 320B and forming a second hole group HG2.

[0119] Forming the second stack structure 320B may include alternately stacking a plurality of upper first material layers 321B and a plurality of upper second material layers 323B over the first stack structure 320A. Similar to the first stack structure 320A, the second stack structure 320B may include a cell array region CAR and a contact region CTR. Figure 8 The cell array region CAR of the first stacked structure 320A and the second stacked structure 320B shown in FIG. 3 may be divided into a first region AR1 and a second region AR2. Figure 8 The first stacked structure 320A shown, the first region AR1 of the second stacked structure 320B may be divided into two or more memory cell string regions MSA and a dummy region DMA between adjacent memory cell string regions MSA. The upper first material layer 321B may include the same material as the lower first material layer 321A, and the upper second material layer 323B may include the same material as the lower second material layer 323A.

[0120] Subsequently, an etch stop layer 341 and a second hard mask pattern 343 may be stacked over the second stack structure 320B. The etch stop layer 341 may include a nitride layer. The second hard mask pattern 343 may include a carbon layer. The second hard mask pattern 343 may include a plurality of second openings OP2 formed by a photolithography process. Each of the plurality of second openings OP2 may overlap with the cell array region CAR of the second stack structure 320B, and the contact region CTR of the second stack structure 320B may be blocked by the second hard mask pattern 343.

[0121] Subsequently, the etch stop layer 341, the plurality of upper first material layers 321B, and the plurality of upper second material layers 323B may be etched through the plurality of second openings OP2 of the second hard mask pattern 343. As a result, the second hole group HG2 may be formed.

[0122] The second hole group HG2 may include a plurality of upper channel holes 347A and a plurality of upper auxiliary holes 347C. The plurality of upper channel holes 347A may be provided to have the same Figure 8 Each of the plurality of upper channel holes 347A may pass through the cell array region CAR of the second stack structure 320B and may expose the first lower sacrificial pillar 330A corresponding thereto. The plurality of upper auxiliary holes 347C may be arranged to have the same Figure 8 Each of the plurality of upper auxiliary holes 347C may pass through the cell array region CAR of the second stack structure 320B and may expose the second lower sacrificial pillar 330C corresponding thereto. Fig. 12A and Fig. 12B Not shown, the second hole group HG2 may include Figure 8 The plurality of lower dummy holes 327B are shown arranged identically to the plurality of upper dummy holes of the second stack structure 320B. The cross-section of the upper dummy holes may be substantially the same as the cross-section of the upper channel hole 347A.

[0123] A plurality of channel holes CHH, a plurality of auxiliary holes AH, and a plurality of dummy holes may be formed by the above-mentioned process. Each of the plurality of channel holes CHH may include a corresponding upper channel hole 347A and a corresponding lower channel hole 327A' having an enlarged depth coupled to the upper channel hole 347A. Each of the plurality of auxiliary holes AH may include a corresponding upper auxiliary hole 347C and a corresponding lower auxiliary hole 327C coupled to the upper auxiliary hole 347C. Similar to the channel hole CHH, each of the plurality of dummy holes may include a corresponding upper dummy hole and a corresponding lower dummy hole having an enlarged depth coupled to the upper dummy hole.

[0124] The first stack structure 320A and the second stack structure 320B may form a stack structure 320 .

[0125] In the XY plane, the plurality of channel holes CHH may be arranged to have Figure 8 In addition, in the XY plane, the plurality of auxiliary holes AH may be arranged to have the same arrangement as the plurality of lower channel holes 327A shown in FIG. Figure 8 The plurality of lower auxiliary holes 327C shown are arranged substantially the same.

[0126] Fig.13A and Fig. 13B is a cross-sectional view showing the upper sacrificial group 350 .

[0127] Reference Fig.13A and Fig. 13B The process of forming the plurality of sacrificial pillars SP1 and SP2 may include forming an upper sacrificial group 350. Forming the upper sacrificial group 350 may include: forming a filling Fig. 12A The sacrificial material of each of the plurality of upper channel holes 347A and the plurality of upper auxiliary holes 347C is shown; and the surface of the sacrificial material is planarized to expose the etch stop layer 341. Fig.13A and Fig. 13B Not shown, the plurality of upper dummy holes may also be filled with a sacrificial material.

[0128] The sacrificial material may include a material having an etching selectivity relative to the upper first material layer 321B and the upper second material layer 323B. According to an embodiment, the sacrificial material may include a fourth metal nitride layer 351 and a third metal layer 353. For example, similar to the first metal nitride layer 313, the fourth metal nitride layer 351 may include a titanium nitride layer. Similar to the first metal layer 315, the third metal layer 353 may include tungsten. The sacrificial material may also include a capping layer 355. The capping layer 355 may include a material having an etching selectivity relative to a dry etching process of an oxide. According to an embodiment, the capping layer 355 may include a polysilicon layer.

[0129] The fourth metal nitride layer 351 may be formed along Fig. 12A The third metal layer 353 may be formed on the fourth metal nitride layer 351 and may be formed to have a thickness such that the thickness of the fourth metal nitride layer 351 is greater than the thickness of the fourth metal nitride layer 351. Fig. 12A The height of the upper opening of each of the plurality of upper channel holes 347A and the plurality of upper auxiliary holes 347C shown. The cover layer 355 may be disposed at Fig. 12A In each of the plurality of upper channel holes 347A and the plurality of upper auxiliary holes 347C shown.

[0130] The upper sacrificial group 350 may include a filler Fig. 12A The plurality of first upper sacrificial pillars 350A of the plurality of upper channel holes 347A and the filling Fig. 12A The plurality of second upper sacrificial pillars 350C of the plurality of upper auxiliary holes 347C are shown. Fig.13A and Fig. 13B Not shown in FIG. 3 , the upper sacrificial group 350 may further include upper dummy pillars filling the upper dummy holes, and a cross-section of the upper dummy pillars may be substantially the same as a cross-section of the first upper sacrificial pillars 350A.

[0131] A plurality of first sacrificial columns SP1, a plurality of second sacrificial columns SP2, and a plurality of dummy columns may be formed by the above-mentioned process. Each of the plurality of first sacrificial columns SP1 may include a corresponding first upper sacrificial column 350A and a corresponding first lower sacrificial column 330A connected to the first upper sacrificial column 350A. Each of the plurality of second sacrificial columns SP2 may include a corresponding second upper sacrificial column 350C and a corresponding second lower sacrificial column 330C connected to the second upper sacrificial column 350C. Similar to the first sacrificial column SP1, each of the plurality of dummy columns may include a corresponding lower dummy column corresponding thereto and a corresponding upper dummy column connected to the lower dummy column. The cross-sectional structure of the dummy column may be the same as the cross-sectional structure of the first sacrificial column SP1.

[0132] Fig.14A , Fig. 14B , Fig.15A and Fig. 15B 2 is a diagram illustrating a process of forming a plurality of cell plugs and a process of forming a stepped stack structure according to an embodiment.

[0133] Fig.14A and Fig. 14B It may be a cross-sectional view showing that a plurality of channel holes CHH are opened.

[0134] Reference Fig.14A and Fig. 14B The process of forming the plurality of cell plugs may include opening the plurality of channel holes CHH. Opening the plurality of channel holes CHH may include: forming a photoresist pattern 361 on the etch stop layer 341; and removing the photoresist pattern 361 by an etching process using the photoresist pattern 361 as an etching barrier. Fig.13A A plurality of first sacrificial studs SP1 are shown.

[0135] The photoresist pattern 361 may overlap the cell array region CAR of the stack structure 320 to block the plurality of second sacrificial pillars SP2. The photoresist pattern 361 may expose the cell array region CAR on both sides of the etch stop pattern 310. The photoresist pattern 361 may extend to overlap the contact region CTR of the stack structure 320.

[0136] When the plurality of first sacrificial pillars SP1 are removed, the plurality of dummy pillars may be removed, and the plurality of dummy holes may be opened. The cross-sectional structure of the opened dummy holes may be the same as the cross-sectional structure of the opened channel holes CHH.

[0137] Fig.15A and Fig. 15Bis a cross-sectional view showing a plurality of cell plugs CPL surrounded by a stepped stack structure 320ST.

[0138] Reference Fig.15A and Fig. 15B , a plurality of channel holes CHH may be filled with a plurality of cell plugs CPL. Forming a plurality of cell plugs CPL may include: forming a memory layer ML along the surface of each channel hole CHH; forming a semiconductor layer along the surface of the memory layer ML; and filling a central area of ​​the channel hole CHH opened through the semiconductor layer with a core insulating layer CO and a doped semiconductor layer. The core insulating layer CO may include an oxide. Before forming the doped semiconductor layer, a portion of the core insulating layer may be removed by a dry etching process so that an upper portion of the channel hole CHH is opened. The capping layer 355 may protect the plurality of second sacrificial pillars SP2 from the dry etching process. The semiconductor layer and the doped semiconductor layer in the channel hole CHH may form a channel structure CH.

[0139] although Fig.15A and Fig. 15B Not shown in FIG. 1 , a dummy plug filling the dummy hole may be formed using the above-described process of forming the cell plug CPL.

[0140] Later, in Fig.14A After the etching stop layer 341 shown is removed, the plurality of lower first material layers 321A, the plurality of lower second material layers 323A, the plurality of upper first material layers 321B, and the plurality of upper second material layers 323B may be etched into a stepped shape. Thus, a stepped stacked structure 320ST may be formed. Each of the plurality of lower first material layers 321A, the plurality of lower second material layers 323A, the plurality of upper first material layers 321B, and the plurality of upper second material layers 323B of the stepped stacked structure 320ST may surround the second sacrificial column SP2, the cell plug CPL, and the dummy plug (not shown) in the cell array region CAR. The plurality of lower first material layers 321A, the plurality of lower second material layers 323A, the plurality of upper first material layers 321B, and the plurality of upper second material layers 323B of the stepped stacked structure 320ST may form a stepped structure in the contact region CTR.

[0141] Thereafter, a first upper insulating layer 251 may be formed on the stepped stack structure 320ST. A surface of the first upper insulating layer 251 may be planarized, and the first upper insulating layer 251 may extend to cover the plurality of cell plugs CPL, the plurality of second sacrificial pillars SP2, and the plurality of dummy plugs (not shown).

[0142] Fig.16 , Fig.17A and Fig. 17B is a diagram illustrating a process of forming a plurality of trenches and a plurality of supporting holes according to an embodiment. Fig.163 is a plan view showing a plurality of channel holes CHH, a plurality of dummy holes DH, a plurality of auxiliary holes AH, a plurality of trenches T1 and T2 , and a plurality of supporting holes SH passing through the stepped stack structure 320ST. Fig.17A It is along Fig.16 The cross-sectional view of the stepped stacked structure 320ST taken along the lines II' and II-II' is shown. Fig. 17B It is along Fig.16 The cross-sectional view of the stepped stacked structure 320ST is taken along line III-III′.

[0143] Reference Fig.16 , Fig.17A and Fig. 17B , a plurality of trenches T1 and T2 and a plurality of support holes SH may be formed by etching the contact region CTR of the first upper insulating layer 251 and the stepped stack structure 320ST. When the contact region CTR of the first upper insulating layer 251 and the stepped stack structure 320ST is etched, the cell array region CAR of the stepped stack structure 320ST may be blocked by the third hard mask pattern 363 disposed on the first upper insulating layer 251.

[0144] The third hard mask pattern 363 may include a carbon layer. The third hard mask pattern 363 may include a plurality of third openings OP3. The plurality of third openings OP3 may partially open the contact region CTR of the stepped stack structure 320ST. According to an embodiment, the plurality of third openings OP3 may open a portion of the stepped stack structure 320ST overlapping with the etching stop pattern 310 in the contact region CTR and a portion of the stepped stack structure 320ST on both sides of the etching stop pattern 310 in the contact region CTR. The contact region CTR of the stepped stack structure 320ST and the first upper insulating layer 251 may be etched through the plurality of third openings OP3. The plurality of trenches T1 and T2 and the plurality of support holes SH may be defined by the plurality of third openings OP3.

[0145] The plurality of trenches T1 and T2 may include a first trench T1 and a second trench T2. The first trench T1 may pass through a portion of the stepped stack structure 320ST and a portion of the first upper insulating layer 251 overlapping the etch stop pattern 310. The first trench T1 may extend straight along the contact region CTR. The second trench T2 may pass through the contact region CTR of the stepped stack structure 320ST adjacent to each side of the first trench T1. The second trench T2 may extend in one direction along the contact region CTR.

[0146] A plurality of supporting holes SH may pass through the contact region CTR of the stepped stack structure 320ST between the first trench T1 and the second trench T2 .

[0147] The stepped stack structure 320ST may be penetrated by the plurality of supporting holes SH, the first and second trenches T1 and T2 , the channel holes CHH filled with the cell plugs CPL, the dummy holes DH filled with the dummy plugs DPL, and the auxiliary holes AH filled with the second sacrificial pillars SP2 through the above-described processes.

[0148] Reference Fig.16 , similar to Figure 8 The cell array region CAR of the first stacked structure 320A and the stepped stacked structure 320ST may include a plurality of first regions AR1 and a plurality of second regions AR2. Figure 8 As shown in the first stack structure 320A, the first region AR1 of the stepped stack structure 320ST may include the memory cell string regions MSA and the dummy regions DMA between the memory cell string regions MSA.

[0149] Similar to Figure 8 The plurality of lower channel holes 327A shown, and the plurality of channel holes CHH passing through the stepped stacked structure 320ST may be arranged in a plurality of rows. Figure 8 The multiple lower channel holes 327A shown, the multiple channel holes CHH passing through the stepped stack structure 320ST may include a plurality of first channel holes CHH1 arranged along a first row in a first direction (e.g., in the X-axis direction) and a plurality of second channel holes CHH2 arranged along a second row in the first direction (e.g., in the X-axis direction).

[0150] Similar to Figure 8 As shown in the plurality of lower auxiliary holes 327C, the plurality of auxiliary holes AH passing through the stepped stack structure 320ST may include a plurality of first auxiliary holes AH1 arranged along a third row adjacent to the first row in the first direction (e.g., in the X-axis direction) and a plurality of second auxiliary holes AH2 arranged along a fourth row adjacent to the second row in the first direction (e.g., in the X-axis direction). The third row and the fourth row may be disposed between the first row and the second row.

[0151] Similar to Figure 8 As shown in the plurality of lower dummy holes 327B, the plurality of dummy holes DH passing through the stepped stack structure 320ST may be arranged along the dummy area DMA of the stepped stack structure 320ST.

[0152] The distances and widths between the plurality of channel holes CHH, the plurality of dummy holes DH, and the plurality of auxiliary holes AH may be the same as those described above. Figure 8The distances and widths between the described multiple lower channel holes 327A, multiple lower dummy holes 327B, and multiple lower auxiliary holes 327C are similar. For example, the distance between the first auxiliary hole AH1 and the second auxiliary hole AH2 may be smaller than the distance between the first channel hole CHH1 and the first auxiliary hole AH1 or the first distance D1' between the second channel hole CHH2 and the second auxiliary hole AH2. The first distance D1' may be greater than each of the second distance D2' between the channel holes CHH arranged in adjacent rows and the third distance D3' between the channel holes CHH and the dummy holes DH adjacent to each other. The third distance D3' may be substantially the same as the second distance D2'. The width of each of the first auxiliary hole AH1 and the second auxiliary hole AH2 may be smaller than the width of each of the first channel hole CHH1 and the second channel hole CHH2 in the second direction (e.g., in the Y-axis direction).

[0153] The distance between the auxiliary holes AH adjacent to each other in the X-axis direction may be smaller than the distance between the channel holes CHH adjacent to each other in the X-axis direction. The distance between the auxiliary holes AH adjacent to each other in the Y-axis direction may be smaller than the distance between the channel holes CHH adjacent to each other in the Y-axis direction.

[0154] The gate isolation structure 253 extending into the stepped stack structure 320ST may be formed after forming the dummy plug DPL.

[0155] The arrangement density of the first trench T1, the second trench T2, and the support hole SH in the contact region CTR may be lower than the arrangement density of the channel hole CHH, the dummy hole DH, and the auxiliary hole AH in the cell array region CAR. Considering the arrangement density, the process of forming the channel hole CHH, the dummy hole DH, and the auxiliary hole AH in the cell array region CAR may be performed separately from the process of forming the first trench T1, the second trench T2, and the support hole SH in the contact region CTR, thereby alleviating or reducing the phenomenon of pattern shape distortion. Therefore, according to an embodiment, process stability may be improved.

[0156] According to the embodiment, it is possible not only to form Fig.13A The first trench T1, the second trench T2, and the support hole SH are formed after the first sacrificial pillar SP1 and the second sacrificial pillar SP2 shown, and after the first sacrificial pillar SP1 is removed. Therefore, the stress applied to the stepped stack structure 320ST by the first sacrificial pillar SP1 and the second sacrificial pillar SP2 including a material different from the lower first material layer 321A, the lower second material layer 323A, the upper first material layer 321B, and the upper second material layer 323B of the stepped stack structure 320ST can be reduced. For example, when the first trench T1, the second trench T2, and the support hole SH are formed by the process of forming the channel hole CHH, the dummy hole DH, and the auxiliary hole AH, each of the first trench T1, the second trench T2, and the support hole SH can be as shown. Fig.13AAs shown, the step stack structure 320ST is filled with a sacrificial column. According to the above-described embodiment, the proportion of the material applying stress to the step stack structure 320ST increases due to the sacrificial column filling each of the first trench T1, the second trench T2, and the support hole SH, and therefore, a process failure such as warping of the step stack structure 320ST may occur. According to an embodiment, the proportion of the material applying stress to the step stack structure 320ST may be reduced, thereby improving process stability.

[0157] Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B and Fig.21 2 is a diagram illustrating a process of forming a vertical insulating structure and a plurality of supporting pillars and a process of forming a sacrificial structure according to an embodiment.

[0158] Fig.18A and Fig.18B is a cross-sectional view showing the horizontal layer 365 .

[0159] Reference Fig.18A and Fig.18B The process of forming the vertical insulating structure and the plurality of support pillars may include forming a horizontal layer 365. Fig.17A and Fig. 17B The third hard mask pattern 363 shown may form a horizontal layer 365 on the first upper insulating layer 251 after exposing the first upper insulating layer 251. The horizontal layer 365 may be deposited by a deposition method with a step coverage difference. Therefore, a void V may be formed in each of the first trench T1, the second trench T2, and the support hole SH. The horizontal layer 365 may include an oxide layer.

[0160] Reference Fig.19A and Fig.19B The process of forming the vertical insulating structure and the plurality of supporting pillars may include partially removing the horizontal layer 365 through a photolithography process to expose the second trench T2 and the supporting hole SH.

[0161] Reference Fig. 20A and Fig. 20B The process of forming the vertical insulating structure and the plurality of supporting pillars may include filling the vertical insulating structure with an insulating material. Fig.19A and Fig.19B The process shown in FIG. 1 opens the second trench T2 and the support hole SH. Thus, a filling hole T2 can be formed. Fig.19A The vertical insulating structure 257 and the filling structure of the second trench T2 are shown Fig.19B A plurality of support posts 255 are shown supporting the plurality of support holes SH.

[0162] Subsequently, the Fig.19A and Fig.19B The horizontal layer 365 is shown to open the first trench T1. The etch stop pattern 310 may be exposed through the opened first trench T1.

[0163] Fig.21 is a cross-sectional view showing the sacrificial structure 370 .

[0164] Reference Fig.21 , Fig. 20A The first trench T1 shown may be filled with a sacrificial structure 370. The sacrificial structure 370 may include a Fig. 20B The support pillars 255, the stepped stacked structure 320ST, the first upper insulating layer 251, and the vertical insulating structure 257 shown have materials with etching selectivity. According to an embodiment, the sacrificial structure 370 may include a Fig. 20A The fifth metal nitride layer 371 extending from the sidewall and bottom surface of the first trench T1 is shown, and the fourth metal layer 373 is on the fifth metal nitride layer 371. For example, the fifth metal nitride layer 371 may include a titanium nitride layer similar to the first metal nitride layer 313, and the fourth metal layer 373 may include tungsten similar to the first metal layer 315.

[0165] Fig.22A , Fig. 22B , Fig.23 , Fig.24 and Fig.25 is a diagram illustrating a process of forming slits according to an embodiment.

[0166] Reference Fig.22A and Fig. 22B , a second upper insulating layer 271 may be formed on the first upper insulating layer 251. The second upper insulating layer 271 may extend to cover the vertical insulating structures 257, the sacrificial structures 370, and the supporting pillars 255.

[0167] Subsequently, a third trench 375 may be formed through the second upper insulating layer 271. The third trench 375 may pass through a portion of the second upper insulating layer 271 overlapping the etch stop pattern 310. The third trench 375 may extend along a direction in which the etch stop pattern 310 extends and may overlap the cell array region CAR and the contact region CTR of the stepped stack structure 320ST.

[0168] The third trench 375 may include a first portion 375A overlapping the cell array region CAR of the stepped stacked structure 320ST and a second portion 375B overlapping the contact region CTR of the stepped stacked structure 320ST. The first portion 375A may extend into the first upper insulating layer 251 to expose a plurality of second sacrificial pillars SP2. The second portion 375B may expose the sacrificial structure 370. The width of the first portion 375A may be controlled so that the edge of the first portion 375A is disposed between the cell plugs CPL and the second sacrificial pillars SP2 adjacent to each other. The second portion 375B may be formed to have a width less than the width of the sacrificial structure 370 to mitigate over-etching of the stepped stacked structure 320ST.

[0169] Reference Fig.23 , can be removed through the third trench 375 by a selective etching process Fig.22A and Fig. 22B The plurality of second sacrificial pillars SP2, sacrificial structures 370 and etching stop patterns 310 are shown. Therefore, the first and second auxiliary holes AH1 and AH2 among the plurality of auxiliary holes AH, the groove 311 and the first trench T1 may be opened. The first and second auxiliary holes AH1 and AH2 may be coupled to the first trench T1 through the groove 311.

[0170] Fig.24 yes Fig.23 FIG. 3 is an enlarged plan view of a portion of the cell array region CAR of the stepped stack structure 320ST.

[0171] Reference Fig.24 , the cell array region CAR of the stepped stack structure 320ST may include a second region AR2 penetrated by the plurality of auxiliary holes AH and a memory cell string region MSA adjacent to both sides of the second region AR2 penetrated by the plurality of cell plugs CPL.

[0172] The memory layer ML of each of the plurality of cell plugs CPL may include a tunnel insulating layer TI surrounding the channel structure CH, a data storage layer DS surrounding the tunnel insulating layer TI, and a blocking insulating layer BI surrounding the data storage layer DS. The tunnel insulating layer TI may include an insulating material that allows charge tunneling. According to an embodiment, the tunnel insulating layer TI may include a silicon oxide layer. The data storage layer DS may include an insulating material that allows charge capture. According to an embodiment, the data storage layer DS may include a nitride layer. The blocking insulating layer BI may include an insulating material capable of blocking the movement of charges. According to an embodiment, the blocking insulating layer BI may include at least one of a silicon oxide layer and a metal oxide layer having a higher dielectric constant than the silicon oxide layer.

[0173] A plurality of unit plugs CPL may include Fig.16 The first cell plug CPL1 filling the first channel hole CHH1 in the first row and Fig.16 The second cell plug CPL2 filling the second channel hole CHH2 in the second row is shown. Fig.16 According to the above arrangement, the first cell plug CPL1 and the first auxiliary hole AH1 may be spaced apart from each other by the first distance D1', and the second cell plug CPL2 and the second auxiliary hole AH2 may be spaced apart from each other by the first distance D1'. In addition, the cell plugs CPL adjacent to each other in the Y-axis direction may be spaced apart from each other by the second distance D2'. The first distance D1' may be defined to be greater than the second distance D2'. In addition, the distance DD between the first auxiliary hole AH1 and the second auxiliary hole AH2 may be less than each of the first distance D1' and the second distance D2'.

[0174] Fig.25 It shows that Fig.24 FIG. 1 is a cross-sectional view showing a process of connecting the auxiliary hole AH and the first trench T1 .

[0175] Reference Fig.25 , can be Fig.24 The auxiliary hole AH and the first trench T1 shown remove a portion of each of the plurality of lower first material layers 321A, the plurality of lower second material layers 323A, the plurality of upper first material layers 321B, and the plurality of upper second material layers 323B of the stepped stack structure 320ST, so that Fig.24 The auxiliary hole AH and the first trench T1 are shown coupled to each other. As a result, a slit SI may be formed.

[0176] Fig.26A and Fig.26B is Fig.25 An enlarged plan view of some areas of the stepped stacked structure 320ST penetrated by the slit SI is shown. Fig.26A is an enlarged plan view of the cell array region CAR of the stepped stacked structure 320ST. Fig.26B is an enlarged plan view of a structure in which portions of the enlarged first and second auxiliary holes AH1 and AH2 and portions of the enlarged first trench T1 are coupled.

[0177] Reference Fig.26A and Fig.26B The first auxiliary hole AH1 and the second auxiliary hole AH2 adjacent to each other among the plurality of auxiliary holes AH can be identified by referring to the above Fig.25 The step stack structure 320ST may be expanded by the etching process described above to be connected to each other. The first distance D1′ between the cell plug CPL and the first auxiliary hole AH1 or between the cell plug CPL and the second auxiliary hole AH2 may be relatively greater than the distance DD between the first auxiliary hole AH1 and the second auxiliary hole AH2. Therefore, by controlling the width of the stepped stack structure 320ST to be etched, the stepped stack structure 320ST may remain between the slit SI and the cell plug CPL.

[0178] The first trench T1 can be Fig.25 The first auxiliary hole AH1 and the second auxiliary hole AH2 are enlarged by the etching process described above to be coupled to the enlarged portions of the first auxiliary hole AH1 and the second auxiliary hole AH2.

[0179] The slit SI may be divided into a first portion SI1 including the first and second auxiliary holes AH1 and AH2 enlarged to be coupled to each other and a second portion SI2 including the enlarged first trench T1.

[0180] Fig.27A , Fig.27B , Fig.27C , Fig.27D and Fig.27E is an enlarged cross-sectional view illustrating a process of forming a source structure according to an embodiment. Fig.27A , Fig.27B , Fig.27C , Fig.27D and Fig.27E yes Fig.25 An enlarged view of area A is shown.

[0181] Reference Fig.27A , the process of forming the source structure may include forming a sealing layer 380 along the surface of the slit SI and the groove 311. The sealing layer 380 may include a first sealing layer 381 formed along the surface of the slit SI and the groove 311, a second sealing layer 383 formed along the surface of the first sealing layer 381, and a third sealing layer 385 formed along the surface of the second sealing layer 383. The first sealing layer 381, the second sealing layer 383, and the third sealing layer 385 may include a material having an etching selectivity relative to the sacrificial source layer 303. The third sealing layer 385 may include a material having an etching selectivity relative to the blocking insulating layer BI, the second sealing layer 383 may include a material having an etching selectivity relative to the data storage layer DS, and the first sealing layer 381 may include a material having an etching selectivity relative to the tunnel insulating layer TI. According to an embodiment, the first sealing layer 381 and the third sealing layer 385 may include a nitride layer, and the second sealing layer 383 may include an oxide layer.

[0182] Reference Fig.27B The process of forming the source structure may include etching a portion of the sealing layer 380 and a portion of the second protective layer 305 through the slit S1 and removing the Fig.27A The fourth trench 391 is formed by sacrificing the source layer 303 as shown. Therefore, a fourth opening 393 exposing the memory layer ML, the first protection layer 301 and the second protection layer 305 may be defined.

[0183] Reference Fig.27C , the process of forming the source structure may include expanding Fig.27BThe fourth opening 393 is shown to expose the sidewalls of the channel structure CH, the first semiconductor layer 231 and the second semiconductor layer 233. The blocking insulating layer BI can be removed by Fig.27B The portion exposed by the fourth opening 393 shown is removed by removing the portion of the data storage layer DS exposed by the removed portion of the blocking insulating layer BI, and removing the portion of the tunnel insulating layer TI exposed by the removed portion of the data storage layer DS to form an enlarged fourth opening 393'.

[0184] When part of the blocking insulating layer BI is removed, Fig.27B The first protective layer 301 and the second protective layer 305 shown can be removed. Fig.27B The third sealing layer 385 shown has an etching resistance to the material of the etching blocking insulating layer BI, so the stepped stacked structure 320ST can be formed by Fig.27B A third sealing layer 385 is shown for protection.

[0185] When part of the data storage layer DS is removed, Fig.27B The third sealing layer 385 shown can be removed. Fig.27B The second sealing layer 383 shown has an etching resistance to the material of the data storage layer DS, so the stepped stacked structure 320ST can be formed by Fig.27B A second sealing layer 383 is shown for protection.

[0186] When part of the tunnel insulating layer TI is removed, Fig.27B The second sealing layer 383 shown may be removed. Since the first sealing layer 381 has etching resistance to the material of the etching tunnel insulating layer TI, the stepped stack structure 320ST may be protected by the first sealing layer 381 .

[0187] When a portion of each of the blocking insulating layer BI, the data storage layer DS, and the tunnel insulating layer TI is removed, the sidewall of the second semiconductor layer 233 may be exposed through the groove 311 . Fig.27B The illustrated memory layer ML may be divided into a first memory pattern ML1 and a second memory pattern ML2 with the enlarged fourth opening 393 ′ interposed therebetween.

[0188] Reference Fig.27D , a doped semiconductor layer 263L may be formed to fill Fig.27C The enlarged fourth opening 393 ′ is shown. The doped semiconductor layer 263L may include conductive type impurities. According to an embodiment, the doped semiconductor layer 263L may include n-type doped silicon. The conductive type impurities of the doped semiconductor layer 263L may diffuse into the first semiconductor layer 231 and the second semiconductor layer 233 .

[0189] Reference Fig.27E ,exist Fig.27DThe portion of doped semiconductor layer 263L shown is removed to expose Fig.27D After the first sealing layer 381 is shown, Fig.27D The first sealing layer 381 shown may be removed. Therefore, the stepped stack structure 320ST may be exposed, and the groove 311 may be opened through the slit S1. Fig.27D The doped semiconductor layer 263L shown may be penetrated by the fifth trench 395 extending from the groove 311. Thereafter, an oxide layer 265 may be formed by oxidizing the second semiconductor layer 233 and the doped semiconductor layer 263L through the fifth trench 395 and the groove 311. The doped semiconductor layer 263L remaining after forming the oxide layer 265 may be defined as a channel contact layer 263. The first semiconductor layer 231, the channel contact layer 263, and the second semiconductor layer 233 may form a source structure 260. The source structure 260 may be connected to the channel structure CH through the channel contact layer 263.

[0190] As mentioned above Fig.27A , Fig.27B , Fig.27C , Fig.27D and Fig.27E As described, the source structure 260 connected to the channel structure CH may be formed by replacing the sacrificial source layer with the channel contact layer 263 through the slit S1 and the groove 311.

[0191] Fig.28A , Fig.28B , Fig.29A and Fig.29B is a cross-sectional view illustrating a process of forming a conductive pattern according to an embodiment.

[0192] Reference Fig.28A and Fig.28B , the process of forming the conductive pattern may include removing a plurality of lower second material layers and a plurality of upper second material layers through the slits S1. The region where the plurality of lower second material layers and the plurality of upper second material layers are removed may be defined as a plurality of gate spaces 397. Each of the plurality of gate spaces 397 may be defined between the lower first material layers 321A adjacent to each other along the longitudinal direction of the channel structure CH, between the lower first material layers 321A and the upper first material layers 321B adjacent to each other along the longitudinal direction of the channel structure CH, or between the upper first material layers 321B adjacent to each other along the longitudinal direction of the channel structure CH.

[0193] Reference Fig.29A and Fig.29B , multiple conductive patterns CP can be used to fill Fig.28A and Fig.28B A plurality of gate spaces 397 are shown. The plurality of lower first material layers and the plurality of upper first material layers may remain as a plurality of interlayer insulating layers ILD.

[0194] Please refer to the above Fig.28A , Fig.28B , Fig.29A and Fig.29B The gate stack structure GST is formed by replacing the plurality of lower second material layers and the plurality of upper second material layers with the plurality of conductive patterns CP through the slits SI. Figure 8 , Fig. 9A and Fig. 12A As described above, the slit SI is formed to define a portion of the lower second material layer and the upper second material layer for replacing the lower second material layer and the upper second material layer with the conductive pattern CP. Figure 8 , Fig. 9A and Fig. 12A As described, since the auxiliary holes AH are formed using the process of forming the channel holes CHH in the cell array region CAR, the manufacturing process may be simplified.

[0195] Fig.30 is a cross-sectional view illustrating a process of forming a conductive source contact according to an embodiment.

[0196] Reference Fig.30 , can form filling Fig.29A The insulating layer 281 of the third trench 375, the slit S1, the groove 311 and the fifth trench 395 shown. Subsequently, a conductive source contact 283 may be formed through the insulating layer 281 and the oxide layer 265. The conductive source contact 283 may contact the first semiconductor layer 231 of the source structure 260. Thereafter, a process such as forming Figure 5A and Figure 5B Subsequent processing of a plurality of conductive bit line contacts 291 and a plurality of conductive gate contacts 293 is shown.

[0197] Fig.31 is a block diagram showing a configuration of a memory system 1100 according to an embodiment.

[0198] Reference Fig.31 , the memory system 1100 may include a memory device 1120 and a memory controller 1110 .

[0199] The memory device 1120 may be a multi-chip package having a plurality of flash memory chips. The memory device 1120 may include a gate stack structure having a cell array region and a contact region, and the roughness of the first sidewall of the cell array region may be greater than the roughness of the second sidewall of the contact region.

[0200] The memory controller 1110 may be configured to control the memory device 1120 and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 may be used as an operation memory of the CPU 1112, the CPU 1112 may perform a general control operation on data exchange of the memory controller 1110, and the host interface 1113 may include a data exchange protocol of a host accessing the memory system 1100. The error correction block 1114 may detect and correct errors included in data read from the memory device 1120. The memory interface 1115 may interface with the memory device 1120. The memory controller 1110 may also include a read-only memory (ROM) storing code data for interfacing with the host.

[0201] The memory system 1100 having the above configuration may be a solid state drive (SSD) or a memory card in which the memory device 1120 and the memory controller 1110 are combined. For example, when the memory system 1100 is an SSD, the memory controller 1110 may communicate with an external device (e.g., a host) through one of various interface protocols including a universal serial bus (USB), a multimedia card (MMC), a peripheral component interconnect-express (PCI-e), a serial advanced technology attachment (SATA), a parallel advanced technology attachment (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), and an integrated drive electronics (IDE).

[0202] Fig.32 is a block diagram showing a configuration of a computing system 1200 according to an embodiment.

[0203] Reference Fig.32 , the computing system 1200 may include a CPU 1220 electrically coupled to a system bus 1260, a random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210. When the computing system 1200 is a mobile device, a battery for supplying an operating voltage to the computing system 1200 may also be included, and an application chipset, an image processor, a mobile DRAM, and the like may also be included.

[0204] The memory system 1210 may include a memory device 1212 and a memory controller 1211 .

[0205] The memory device 1212 may include a gate stack structure having a cell array region and a contact region, and a first sidewall of the cell array region may have a roughness greater than a roughness of a second sidewall of the contact region.

[0206] The storage controller 1211 may be configured as described above. Fig.31The storage controller 1110 is configured in the same manner as described.

[0207] According to an embodiment of the present disclosure, a slit can be formed by performing an etching process so that an auxiliary hole passing through a cell array region of a stacked structure and a groove passing through a contact region of the stacked structure are connected together. The auxiliary hole can increase the regularity of a pattern in the cell array region, and the groove can increase the regularity of a pattern in the contact region. Therefore, according to an embodiment of the present disclosure, the process stability of a semiconductor memory device can be improved.

[0208] CROSS-REFERENCE TO RELATED APPLICATIONS

[0209] This application claims the priority of Korean Patent Application No. 10-2021-0077456 filed in the Korean Intellectual Property Office on June 15, 2021, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, comprising: Source structure; as well as a gate stack structure, the gate stack structure being disposed above the source structure, the gate stack structure having a cell array region and a contact region having a stepped shape, The roughness of the first side wall of the cell array region of the gate stack structure is greater than the roughness of the second side wall of the contact region of the gate stack structure, and The first side wall and the second side wall both extend to the source structure to serve as outer walls of the gate stack structure.

2. The semiconductor memory device according to claim 1, wherein The first side wall extends in a winding manner, and Wherein, the second side wall extends straightly.

3. The semiconductor memory device according to claim 1, wherein: The first side wall and the second side wall are coupled to each other.

4. The semiconductor memory device according to claim 1, further comprising: A channel structure, the channel structure is connected to the source structure, and the channel structure passes through the gate stack structure; as well as A memory pattern is between the channel structure and the gate stack structure.

5. The semiconductor memory device according to claim 1, further comprising: an insulating layer extending along the first sidewall and the second sidewall of the gate stack structure; as well as A conductive source contact is spaced apart from the gate stack structure with the insulating layer interposed between the conductive source contact and the gate stack structure, and the conductive source contact is connected to the source structure.

6. The semiconductor memory device according to claim 1, wherein: The source structure includes a doped semiconductor layer.

7. The semiconductor memory device according to claim 1, wherein: The gate stack structure includes interlayer insulating layers and conductive patterns alternately stacked with each other over the source structure.

8. A semiconductor memory device, the semiconductor memory device comprising: Source structure; a first gate stack structure and a second gate stack structure, the first gate stack structure and the second gate stack structure are spaced apart from each other and disposed above the source structure; a vertical structure between the first gate stack structure and the second gate stack structure and extending to the source structure, the vertical structure comprising a first portion and a second portion; as well as a plurality of cell plugs passing through the first gate stack structure and the second gate stack structure to be adjacent to both sides of the first portion of the vertical structure, wherein the first portion of the vertical structure includes a depression and a protrusion facing the plurality of unit plugs, and Wherein, the second portion of the vertical structure is formed in a straight shape.

9. The semiconductor memory device according to claim 8, further comprising a plurality of conductive gate contacts, wherein the plurality of conductive gate contacts are arranged adjacent to both sides of the second portion of the vertical structure and in contact with the first gate stack structure and the second gate stack structure.

10. The semiconductor memory device according to claim 8, wherein: Each of the first gate stack structure and the second gate stack structure includes a contact region having a step shape, and The second portion of the vertical structure is disposed between a contact region of the first gate stack structure having a stepped shape and a contact region of the second gate stack structure having a stepped shape.

11. The semiconductor memory device according to claim 8, wherein: The source structure is connected to the plurality of cell plugs.

12. The semiconductor memory device according to claim 11, wherein The vertical structure also includes: an insulating layer extending along a sidewall of each of the first gate stack structure and the second gate stack structure; and A conductive source contact is spaced apart from the first gate stack structure and the second gate stack structure with the insulating layer interposed therebetween, the conductive source contact being connected to the source structure.

13. The semiconductor memory device according to claim 11, wherein: The source structure includes a doped semiconductor layer.

14. The semiconductor memory device according to claim 11, wherein: Each of the first gate stacked structure and the second gate stacked structure includes an interlayer insulating layer and a conductive pattern alternately stacked with each other over the source structure.

15. The semiconductor memory device according to claim 11, wherein The plurality of unit plugs include: a channel structure, the channel structure passing through the first gate stack structure and the second gate stack structure, the channel structure contacting the source structure; and A memory pattern surrounds a sidewall of the channel structure.

16. A method for manufacturing a semiconductor memory device, the method comprising the steps of: forming a stacked structure having a cell array region and a contact region; forming a hole group having a plurality of channel holes and a plurality of auxiliary holes, the plurality of channel holes and the plurality of auxiliary holes passing through the cell array region of the stacked structure and arranged in a plurality of rows; forming a memory layer along a surface of each of the plurality of channel holes; forming a channel structure on the memory layer; forming a first trench through the contact region of the stacked structure; as well as removing a portion of the stacked structure through the plurality of auxiliary holes and the first trench so that a slit is formed, Wherein, the plurality of auxiliary holes and the first groove are connected in the slit.

17. The method according to claim 16, wherein: The plurality of channel holes include a plurality of first channel holes arranged along a first row in a first direction and a plurality of second channel holes arranged along a second row in the first direction, wherein the plurality of auxiliary holes include a plurality of first auxiliary holes arranged along a third row adjacent to the first row in the first direction and a plurality of second auxiliary holes arranged along a fourth row adjacent to the second row in the first direction, and Wherein, the third row and the fourth row are arranged between the first row and the second row.

18. The method according to claim 17, wherein: A distance between each of the plurality of first auxiliary holes and each of the plurality of second auxiliary holes is smaller than each of a distance between each of the plurality of first auxiliary holes and each of the plurality of first channel holes and a distance between each of the plurality of second auxiliary holes and each of the plurality of second channel holes.

19. The method according to claim 17, wherein: In the second direction of the plurality of rows, a width of each of the plurality of first auxiliary holes and the plurality of second auxiliary holes is smaller than a width of each of the plurality of first channel holes and the plurality of second channel holes.

20. The method according to claim 16, wherein: A distance between the plurality of auxiliary holes is smaller than a distance between the plurality of channel holes.

21. The method according to claim 16, wherein: When the first trench is formed, a second trench passing through the contact region of the stacked structure to be adjacent to both sides of the first trench and a supporting hole passing through the contact region of the stacked structure between the first trench and the second trench are formed.

22. The method according to claim 21, further comprising the steps of: forming a support column filling the support hole and a vertical insulating structure filling the second trench; as well as A sacrificial structure filling the first trench is formed, the sacrificial structure having an etching selectivity relative to the supporting pillar and the vertical insulating structure.

23. The method according to claim 22, further comprising the steps of: Before forming the memory layer, forming a first sacrificial column filling each of the plurality of channel holes, forming a second sacrificial column filling each of the plurality of auxiliary holes, and removing the first sacrificial column; as well as After forming the sacrificial structure, the sacrificial structure and the second sacrificial pillar are removed to open each of the plurality of auxiliary holes and the first trench.

24. The method according to claim 16, wherein: The first groove extends straight.

25. The method of claim 16, wherein: The stacked structure includes first material layers and second material layers alternately stacked on each other over a lower structure.

26. The method according to claim 25, further comprising the steps of: The second material layer is replaced with a conductive pattern through the slit.

27. The method according to claim 25, wherein: The lower structure includes a first semiconductor layer, a sacrificial source layer above the first semiconductor layer, a second semiconductor layer above the sacrificial source layer, and an etch stop pattern passing through the second semiconductor layer, and Wherein, the plurality of auxiliary holes and the first trench overlap with the etch stop pattern.

28. The method according to claim 27, further comprising the steps of: removing the etch stop pattern; removing the sacrificial source layer through the slit and the area where the etch stop pattern is removed; exposing the channel structure by removing a portion of the memory layer through the area where the sacrificial source layer is removed; as well as The region where the sacrificial source layer is removed is filled with a doped semiconductor layer to contact the channel structure.

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