Phase comparison circuit

Abstract

Embodiments of the present disclosure provide a phase comparison circuit, wherein the phase comparison circuit comprises a phase comparator, a latch, and a secondary flip optimization circuit; the phase comparator receives a reference signal for phase comparison and a control signal for quantization time, and converts phase changes of the two into a first phase indication signal and a second phase indication signal; the latch receives the first phase indication signal and the second phase indication signal, and outputs a phase overlap indication signal according to the first phase indication signal and the second phase indication signal, so as to determine an overlap time of a first signal and a second signal; the secondary flip optimization circuit keeps the phase overlap indication signal unchanged in a period after the phase overlap indication signal is flipped for the first time according to the phase overlap indication signal output by the latch, the second phase indication signal, and the first signal. The problem that the existing phase comparator may have a distorted detection result is solved.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to phase comparison circuits. Background Technology

[0002] Phase comparator circuits primarily detect the phase overlap (with simultaneous flipping) between a reference signal corresponding to the physical quantity to be detected and a control signal for the quantization time of a known physical quantity. Based on the detection result, the value of the physical quantity corresponding to the reference signal is determined. Phase comparator circuits are widely used in scientific research and engineering fields, such as particle lifetime measurement in high-energy physics, laser detection range, medical bioimaging, and time-of-flight (TOF) measurement.

[0003] like Figure 1 The diagram shows a schematic of a conventional phase comparison circuit 100. ENP is the reference signal corresponding to the physical quantity to be detected (a fixed voltage, temperature, etc.), and C is the control signal for the quantization time corresponding to a known physical quantity (a voltage, temperature, etc. that changes at a fixed frequency). The number of bits n used in the digital signal conversion based on the known physical quantity allows the known physical quantity to be converted into 2... n Two C signals with different delays, 2 n Controlled by C signals with different delays 2 n Each identical phase comparator is compared with ENP to determine which delayed C signal overlaps with ENP first. Then, the value of the physical quantity to be detected corresponding to ENP is determined based on the known value of the physical quantity corresponding to the overlapping C signal. The circuit for phase comparison between each C signal and the ENP signal is identical. Figure 1 Only one phase comparison circuit is provided for illustration.

[0004] right Figure 1To explain the working principle, PUP is a normally high pull-down signal. When the ENP signal is low, points A and B are pulled up to VS by PM1 and PM2, and the output signal Z maintains the previous output state. When ENP goes from low to high, if the C signal is low at this time, NM1 is turned on, point A is pulled down, NM4 is turned off, PM4 is turned on, and point B is high, so the output Z is 0 at this time. When ENP goes from low to high, if the C signal is high at this time, NM1 and NM2 are turned on simultaneously. Since NM2 is larger than NM1, point B is pulled down first, and NM3 is turned off. PM3 is on, so point A is high and output signal Z is 1. When ENP goes from low to high, if signal C goes from high to low at the same time, NM2 and NM6 will be on simultaneously for a very short time. Point B is pulled down by NM2, but before it reaches ground, NM2 is turned off. At this time, the logic gate determines that the potential of point B is low, and output Z is 1. However, because B has not yet reached ground, NM3 cannot be turned off, and point A is slowly pulled down. After being pulled down to a certain extent, it will cause NM4 to turn off and PM4 to turn on, pulling point B back up to VS, and output Z becomes 0. The above process continues from... Figure 1 The circuit corresponding Figure 2 As can also be seen in the waveform diagram, Figure 2 From top to bottom, the signals are: ENP signal, PUP signal, C signal, output signal at point A, output signal at point B, and output Z signal. After... Figure 1 and Figure 2 Through analysis, the inventors discovered that the first rise in the output signal indicates that the C signal and ENP have overlapped, but the overlap time is very short. If it cannot be clearly identified, it will cause distortion of the final detection result. Summary of the Invention

[0005] The embodiments described herein provide a phase comparison circuit to address the problem of distorted detection results in existing phase comparators.

[0006] This disclosure provides a phase comparison circuit comprising: a phase comparator, a latch, and a double-flip optimization circuit; wherein, the phase comparator is configured to receive a first signal and a second signal for phase comparison, and convert the phase changes of the first signal and the second signal into a first phase indication signal and a second phase indication signal, wherein the first signal is a reference generation signal and the second signal is a control signal for quantization time; the latch is configured to receive the first phase indication signal and the second phase indication signal output by the phase comparator, and output a phase overlap indication signal based on the first phase indication signal and the second phase indication signal, so as to determine the overlap time of the first signal and the second signal based on the phase overlap indication signal; the double-flip optimization circuit is configured to keep the phase overlap indication signal unchanged for one cycle after flipping the phase overlap indication signal for the first time based on the phase overlap indication signal, the second phase indication signal, and the first signal output by the latch.

[0007] Optionally, the secondary flip-over optimization circuit includes: a pull-down circuit and an anti-lock-up circuit; wherein, the pull-down circuit is configured to pull down the second phase indication signal after the phase overlap indication signal flips for the first time via a transistor; the anti-lock-up circuit is configured to determine a control signal for the gate of the transistor in the pull-down circuit based on the first signal, the phase overlap indication signal, and the second phase indication signal, to prevent the phase overlap indication signal from being locked in other cycles after the flip-over.

[0008] Optionally, the pull-down circuit includes: a first transistor, the source of the first transistor being grounded, the drain of the first transistor being connected to the source of the second transistor in the anti-lock-down circuit, and the gate of the first transistor being connected to the output of the second NOT gate in the anti-lock-down circuit.

[0009] Optionally, the anti-lock-up circuit includes: a second transistor, a first NOT gate, a second NOT gate, and a first NAND gate; wherein the drain of the second transistor receives the second phase indication signal, and the gate of the second transistor receives the first signal; the input of the first NOT gate receives the second phase indication signal, and the output of the first NOT gate is connected to one input of the first NAND gate; the other input of the first NAND gate receives the phase overlap indication signal, and the output of the first NAND gate is connected to the input of the second NOT gate.

[0010] Optionally, the phase comparator includes a comparator circuit and a reset circuit; wherein, the comparator circuit is configured to convert the phase changes of the first signal and the second signal into a first phase indication signal and a second phase indication signal based on the first signal, the second signal, and a normally high pull-down signal; the reset circuit is configured to restore the first phase indication signal and the second phase indication signal to a set initial state after one cycle ends.

[0011] Optionally, the comparator circuit includes a third to a tenth transistor: wherein the gate of the third transistor receives the normally high pull-down signal, the source of the third transistor is grounded, and the drain of the third transistor is connected to the source of the fifth transistor; the gate of the fourth transistor receives the second signal, the source of the fourth transistor is grounded, and the drain of the fourth transistor is connected to the source of the sixth transistor; the gate of the fifth transistor receives the first signal, and the drain of the fifth transistor is connected to the source of the seventh transistor; the gate of the sixth transistor receives the first signal, and the drain of the sixth transistor is connected to the source of the eighth transistor; the gate of the seventh transistor is connected to the drain of the eighth transistor and the drain of the tenth transistor, and the drain of the seventh transistor is connected to the drain of the ninth transistor and the gate of the eighth transistor; the gate of the ninth transistor is connected to the drain of the tenth transistor, and the source of the ninth transistor is connected to a power supply terminal; the gate of the tenth transistor is connected to the drain of the ninth transistor, and the source of the tenth transistor is connected to a power supply terminal; the first phase indication signal is output from the intermediate node where the seventh transistor and the ninth transistor are connected; and the second phase indication signal is output from the intermediate node where the eighth transistor and the tenth transistor are connected.

[0012] Optionally, the reset circuit includes an eleventh transistor and a twelfth transistor; wherein the gates of the eleventh transistor and the twelfth transistor both receive the first signal, the sources of the eleventh transistor and the twelfth transistor are both connected to a power supply terminal, the drain of the eleventh transistor is connected to the output terminal of the second phase indication signal in the comparator circuit, and the drain of the twelfth transistor is connected to the output terminal of the first phase indication signal in the comparator circuit.

[0013] Optionally, the latch includes: a second NAND gate and a third NAND gate, one input of the second NAND gate receives the first phase indication signal, and the other input of the second NAND gate receives feedback of the phase overlap indication signal; one input of the third NAND gate is connected to the output of the second NAND gate, the other input of the third NAND gate receives the second phase indication signal, and the output of the third NAND gate outputs the phase overlap indication signal.

[0014] Optionally, the first to the eighth transistors are N-type transistors, and the ninth to the twelfth transistors are P-type transistors.

[0015] Optionally, the fourth transistor is larger than the third transistor.

[0016] The phase comparison circuit of this disclosure includes: a phase comparator, a latch, and a double-flip optimization circuit. The phase comparator is configured to receive a first signal and a second signal for phase comparison, and convert the phase change of the first signal and the second signal into a first phase indication signal and a second phase indication signal. The first signal is a reference generation signal, and the second signal is a control signal for quantization time. The latch is configured to receive the first phase indication signal and the second phase indication signal output by the phase comparator, and output a phase overlap indication signal based on the first phase indication signal and the second phase indication signal to determine the overlap time of the first signal and the second signal. The double-flip optimization circuit is configured to maintain the phase overlap indication signal unchanged for one cycle after the first flip based on the phase overlap indication signal, the second phase indication signal, and the first signal output by the latch. The phase comparison circuit of this disclosure adds a double-flip optimization circuit, which can maintain the phase overlap indication signal unchanged for one cycle after the first flip, ensuring that the phase overlap indication signal can be clearly detected during the first flip, effectively preventing distortion of the detection result. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0018] Figure 1 This is an exemplary circuit diagram of an existing phase comparator circuit;

[0019] Figure 2 yes Figure 1 Waveform diagram of the signal corresponding to the circuit;

[0020] Figure 3 This is a schematic diagram of the structure of a phase comparison circuit according to an embodiment of the present disclosure;

[0021] Figure 4 This is a schematic diagram of another phase comparison circuit according to an embodiment of the present disclosure;

[0022] Figure 5 This is an exemplary circuit diagram of a phase comparison circuit according to an embodiment of the present disclosure;

[0023] Figure 6 yes Figure 5 Waveform of the signal corresponding to the phase comparator circuit.

[0024] The elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0026] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0027] In all embodiments of this disclosure, terms such as “first” and “second” are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0028] To address the problem of distorted detection results in existing phase comparators, this disclosure proposes a novel phase comparison circuit. The phase comparison circuit of this disclosure is described in detail below.

[0029] like Figure 3The diagram shown is a schematic representation of a phase comparison circuit 200 according to an embodiment of this disclosure. The phase comparison circuit 200 includes a phase comparator 210, a latch 220, and a double-flip optimization circuit 230. The phase comparator 210 is connected to both the latch 220 and the double-flip optimization circuit 230. The phase comparator 210 is configured to receive a first signal ENP and a second signal C for phase comparison, and to convert the phase changes of the first signal ENP and the second signal C into a first phase indication signal A and a second phase indication signal B. The first signal ENP is a reference generation signal, and the second signal C is a control signal for quantization time. The first signal ENP can be a digital signal corresponding to a physical quantity to be detected (voltage value, temperature value, etc.), and the second signal C can be a digital signal corresponding to a known physical quantity (voltage value, temperature value, etc. that changes at a fixed frequency). A digital signal; a latch 220, connected to a phase comparator 210 and a double-flip optimization circuit 230, is configured to receive a first phase indication signal A and a second phase indication signal B output by the phase comparator 210, and output a phase overlap indication signal Z based on the first phase indication signal A and the second phase indication signal B. The overlap indication signal Z is used to determine the overlap time of the first signal ENP and the second signal C, thereby detecting the physical quantity corresponding to the first signal ENP. The double-flip optimization circuit 230, connected to the phase comparator 210 and the latch 220, is configured to flip the phase overlap indication signal Z for the first time based on the phase overlap indication signal Z, the second phase indication signal B, and the first signal ENP, and then maintain its state unchanged for one cycle. It should be noted that the number of bits n when performing digital signal conversion based on a known physical quantity can convert the known physical quantity into 2... n Two C signals with different delays, 2 n Controlled by C signals with different delays 2 n Each identical phase comparator is compared with ENP to determine which delayed C signal overlaps with ENP first. Then, the value of the physical quantity to be detected corresponding to ENP is determined based on the known value of the physical quantity corresponding to the overlapping C signal. The circuit for phase comparison between each C signal and the ENP signal is identical. Figure 2 Only one phase comparison circuit is described in this embodiment. Compared with the existing phase comparison circuit, the present embodiment adds a secondary flip optimization circuit 230. This circuit can maintain the state unchanged for one cycle after the phase overlap indication signal Z flips for the first time, so that the phase overlap indication signal Z can be clearly detected at the first flip, effectively avoiding the problem of detection result distortion caused by the existing phase comparison circuit 100.

[0030] Furthermore, such as Figure 4The diagram shows an exemplary circuit diagram of a phase comparison circuit 200 according to an embodiment of this disclosure. The phase comparator 210 includes a comparison circuit 211 and a reset circuit 212. The comparison circuit 211 is configured to convert the phase changes of the first signal ENP and the second signal C into a first phase indication signal A and a second phase indication signal B based on the first signal ENP, the second signal C, and a normally high pull-down signal PUP. The reset circuit 212 is configured to restore the first phase indication signal A and the second phase indication signal B to a set initial state after one cycle ends (after the ENP signal goes low). The secondary flip optimization circuit 230 includes a pull-down circuit 231 and an anti-lock-up circuit 232. The pull-down circuit 231 is configured to pull down the second phase indication signal B through a transistor after the first flip of the phase overlap indication signal Z. After the second phase indication signal B is pulled down, NM3 can be turned off, preventing [the following issue]. Figure 1 In the case where the potential at point B is determined to be low by the logic gate, but the potential at point B has not yet been pulled to ground, this avoids the situation where the phase overlap indicator signal Z rises and then quickly returns to 0. The anti-lock-up circuit 232 is configured to determine the control signal of the gate of the transistor in the pull-down circuit 231 based on the first signal ENP, the phase overlap indicator signal Z, and the second phase indicator signal B, preventing the phase overlap indicator signal Z from being locked in the state in other cycles after the flip. This anti-lock-up circuit 232 is designed to prevent the change of Z in subsequent cycles from being affected while pulling the potential at point B to ground, thus preventing the output phase overlap indicator signal Z from being locked in a high state.

[0031] Furthermore, such as Figure 5 As shown, the pull-down circuit 231 includes: a first transistor NM7, the source of which is grounded; the drain of which is connected to the source of the second transistor NM8 in the anti-lock-up circuit 232; and the gate of which is connected to the output of the second NOT gate 2323 in the anti-lock-up circuit 232. The anti-lock-up circuit 232 includes: a second transistor NM8, a first NOT gate 2322, a second NOT gate 2323, and a first NAND gate 2321; wherein the drain of the second transistor NM8 receives a second phase indication signal B, and the gate of the second transistor NM8 receives a first signal ENP; the input of the first NOT gate 2322 receives the second phase indication signal B, and the output of the first NOT gate 2322 is connected to one input of the first NAND gate 2321; the other input of the first NAND gate 2321 receives a phase overlap indication signal Z, and the output of the first NAND gate 2321 is connected to the input of the second NOT gate 2323. Figure 5 In the diagram, point A outputs the first phase indication signal A, and point B outputs the second phase indication signal B. NM7 and NM8 are N-type transistors.

[0032] Furthermore, such as Figure 5 As shown, the comparator circuit 211 includes transistors NM1 to PM4: the gate of transistor NM1 receives the normally high pull-down signal PUP, the source of transistor NM1 is grounded, and the drain of transistor NM1 is connected to the source of transistor NM5; the gate of transistor NM2 receives the second signal C, the source of transistor NM2 is grounded, and the drain of transistor NM2 is connected to the source of transistor NM6; the gate of transistor NM5 receives the first signal ENP, and the drain of transistor NM5 is connected to the source of transistor NM3; the gate of transistor NM6 receives the first signal ENP, and the drain of transistor NM6 is connected to transistor NM4. The source of the seventh transistor NM3 is connected to the drain of the eighth transistor and the drain of the tenth transistor PM4. The drain of the seventh transistor NM3 is connected to the drain of the ninth transistor PM3 and the gate of the eighth transistor NM4. The gate of the ninth transistor PM3 is connected to the drain of the tenth transistor PM4, and the source of the ninth transistor PM3 is connected to the power supply terminal VS. The gate of the tenth transistor PM4 is connected to the drain of the ninth transistor PM3, and the source of the tenth transistor PM4 is connected to the power supply terminal VS. The first phase indication signal A is output from the intermediate node where the seventh transistor NM3 and the ninth transistor PM3 are connected. The second phase indication signal B is output from the intermediate node where the eighth transistor NM4 and the tenth transistor PM4 are connected. The reset circuit 212 includes an eleventh transistor PM1 and a twelfth transistor PM2; wherein the gates of both the eleventh transistor PM1 and the twelfth transistor PM2 receive the first signal ENP, the sources of both the eleventh transistor PM1 and the twelfth transistor PM2 are connected to the power supply terminal VS, the drain of the eleventh transistor PM1 is connected to the output terminal of the second phase indication signal B in the comparator circuit 211, and the drain of the twelfth transistor PM2 is connected to the output terminal of the first phase indication signal A in the comparator circuit 211. It should be noted that the size of the fourth transistor NM2 is larger than the size of the third transistor NM1. Furthermore, it should be noted that transistors NM1, NM2, NM3, NM4, NM5, and NM6 are N-type transistors, and transistors PM1, PM2, PM3, and PM4 are P-type transistors.

[0033] Furthermore, such as Figure 5As shown, the latch 220 includes a second NAND gate 221 and a third NAND gate 222. One input of the second NAND gate 221 receives the first phase indication signal A, and the other input of the second NAND gate 221 receives feedback of the phase overlap indication signal Z. One input of the third NAND gate 222 is connected to the output of the second NAND gate 221, the other input of the third NAND gate 222 receives the second phase indication signal B, and the output of the third NAND gate 222 outputs the phase overlap indication signal Z.

[0034] In combination with the above Figure 5 The phase comparator circuit 200 is described in detail below. When ENP is 0, the circuit is set, points A and B are both high, and the output Z remains in the previous state. When ENP goes from low to high, if signal C is low, PUP is always high, NM1 is on, C is low, NM2 is not on, ENP is high, NM5 is on, point A is pulled down, PM4 is on, NM4 is off, point B is high, therefore the output Z is 0, point D is 0, and NM7 is off. When ENP goes from low to high, if signal C is high, NM1 and NM2 are on simultaneously, ENP is high, NM5 and NM6 are on. Since NM2 is larger than NM1, point B is pulled down, NM3 is off, and PM3 is on. Therefore, the potential at point A is high, the output signal Z is 1, and the potential at point D is 1. NM8 and NM7 are both on, further pulling down point B, keeping the output Z high. When ENP goes from low to high, if the C signal goes from high to low at the same time, NM2, NM5, and NM6 will be turned on simultaneously for a very short period of time. B is pulled down and is recognized as low by the third NAND gate 222, so the output Z becomes high. At this time, the potential of point D is high, and NM8 and NM7 are both turned on, further pulling down the B signal. Even if the C signal has already gone low and NM2 has been turned off, B can still be pulled down to ground through NM8 and NM7. Therefore, point B always remains low, point A always remains high, and the output Z will not change.

[0035] Furthermore, as can be seen from the above analysis, the control logic of the NM7 control electrode (point D position) is B NOT multiplied by Z. The purpose of this logic is that it is only necessary to pull down when B = 0 and Z = 1 (at this time, the logic determines that B = 0, but the actual potential of B is not 0).

[0036] Additionally, it should be noted that if the output signal Z is directly connected to point D, the output Z will not change. However, once the output Z becomes high, the output will remain latched high regardless of how the ENP and C signals change. Therefore, in order to prevent Z from being locked, an anti-lock-up circuit 232 is provided in the secondary flip-up optimization circuit 230 in this embodiment.

[0037] To further illustrate the effects of the phase comparison circuit 200 in the embodiments of this disclosure, Figure 6 It shows Figure 5 The waveform diagrams of the signals corresponding to the phase comparison circuit 200 are shown below, from top to bottom: ENP signal, C signal, B-point signal (second phase indicator signal B), A-point signal (first phase indicator signal A), Z signal, F-point output signal of the first NAND gate 2321, and D-point signal (NM7 control electrode signal). Figure 6 As can be seen in the diagram, when the ENP and C signals overlap, the potential at point B is pulled down to a relatively low position. At this point, it is logically considered low, but still sufficient to weakly conduct NM3. This weak conduction could potentially cause the potential at point A to drop, leading to a flip in the output signal Z, which is undesirable. However, due to the improved circuitry, as the Z signal goes high, the potential at point D also goes high, causing NM7 and NM8 to conduct, pulling down point B and reducing its potential to 0. This prevents the aforementioned problem from occurring.

[0038] In summary, the phase comparison circuit 200 of this embodiment adds a secondary flip optimization circuit 230, which can keep the state unchanged for one cycle after the phase overlap indicator signal Z flips for the first time, so that the phase overlap indicator signal Z can be clearly detected during the first flip, effectively preventing the detection result from being distorted, and the output signal Z will not be locked during the optimization process, affecting the change of the output signal in subsequent cycles.

[0039] The descriptions of the same or corresponding module units in the various embodiments of this disclosure can be referenced in turn.

[0040] In the above description, well-known structural elements and steps have not been described in detail. However, those skilled in the art should understand that the corresponding structural elements and steps can be implemented through various technical means. Furthermore, in order to form the same structural elements, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0041] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims of this invention.

[0042] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0043] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this disclosure may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0044] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A phase comparator circuit, characterized in that, The phase comparison circuit includes: a phase comparator, a latch, and a double-flip optimization circuit; The phase comparator is configured to receive a first signal and a second signal for phase comparison, and to convert the phase changes of the first signal and the second signal into a first phase indication signal and a second phase indication signal. The first signal is a reference generation signal, and the second signal is a control signal for quantization time. The latch is configured to receive the first phase indication signal and the second phase indication signal output by the phase comparator, and output a phase overlap indication signal based on the first phase indication signal and the second phase indication signal, so as to determine the overlap time of the first signal and the second signal based on the phase overlap indication signal; The secondary flip-optimization circuit is configured to keep the phase overlap indication signal unchanged for one cycle after flipping the phase overlap indication signal for the first time according to the phase overlap indication signal, the second phase indication signal and the first signal output by the latch; The secondary flip-over optimization circuit includes: a pull-down circuit and an anti-lock-up circuit; wherein, the pull-down circuit is configured to pull down the second phase indication signal after the phase overlap indication signal has flipped for the first time via a transistor; the anti-lock-up circuit includes: a second transistor, a first NOT gate, a second NOT gate, and a first NAND gate; wherein, the drain of the second transistor receives the second phase indication signal, and the gate of the second transistor receives the first signal; the input of the first NOT gate receives the second phase indication signal, and the output of the first NOT gate is connected to one input of the first NAND gate; the other input of the first NAND gate receives the phase overlap indication signal, and the output of the first NAND gate is connected to the input of the second NOT gate.

2. The phase comparison circuit according to claim 1, characterized in that, The anti-lock-up circuit is configured to determine the control signal of the gate of the transistor in the pull-down circuit based on the first signal, the phase overlap indication signal, and the second phase indication signal, so as to prevent the phase overlap indication signal from being locked in the state during other cycles after the flip.

3. The phase comparison circuit according to claim 2, characterized in that, The pull-down circuit includes: a first transistor, the source of the first transistor being grounded, the drain of the first transistor being connected to the source of the second transistor in the anti-lock-down circuit, and the gate of the first transistor being connected to the output of the second NOT gate in the anti-lock-down circuit.

4. The phase comparison circuit according to claim 3, characterized in that, The phase comparator includes a comparator circuit and a reset circuit; The comparison circuit is configured to convert the phase changes of the first signal and the second signal into a first phase indication signal and a second phase indication signal based on the first signal, the second signal and a normally high pull-down signal. The reset circuit is configured to restore the first phase indicator signal and the second phase indicator signal to a set initial state after one cycle ends.

5. The phase comparison circuit according to claim 4, characterized in that, The comparator circuit includes transistors three through ten: The gate of the third transistor receives the normally high pull-down signal, the source of the third transistor is grounded, and the drain of the third transistor is connected to the source of the fifth transistor. The gate of the fourth transistor receives the second signal, the source of the fourth transistor is grounded, and the drain of the fourth transistor is connected to the source of the sixth transistor. The gate of the fifth transistor receives the first signal, and the drain of the fifth transistor is connected to the source of the seventh transistor; The gate of the sixth transistor receives the first signal, and the drain of the sixth transistor is connected to the source of the eighth transistor. The gate of the seventh transistor is connected to the drain of the eighth transistor and the drain of the tenth transistor, and the drain of the seventh transistor is connected to the drain of the ninth transistor and the gate of the eighth transistor. The gate of the ninth transistor is connected to the drain of the tenth transistor, and the source of the ninth transistor is connected to the power supply terminal. The gate of the tenth transistor is connected to the drain of the ninth transistor, and the source of the tenth transistor is connected to the power supply terminal. The first phase indication signal is output from the intermediate node where the seventh transistor and the ninth transistor are connected; The second phase indication signal is output from the intermediate node where the eighth transistor and the tenth transistor are connected.

6. The phase comparison circuit according to claim 5, characterized in that, The reset circuit includes an eleventh transistor and a twelfth transistor; In this circuit, the gates of both the eleventh and twelfth transistors receive the first signal, the sources of both transistors are connected to a power supply terminal, the drain of the eleventh transistor is connected to the output terminal of the second phase indication signal in the comparator circuit, and the drain of the twelfth transistor is connected to the output terminal of the first phase indication signal in the comparator circuit.

7. The phase comparison circuit according to claim 1, characterized in that, The latch includes: a second NAND gate and a third NAND gate. One input of the second NAND gate receives the first phase indication signal, and the other input of the second NAND gate receives feedback of the phase overlap indication signal; One input of the third NAND gate is connected to the output of the second NAND gate, the other input of the third NAND gate receives the second phase indication signal, and the output of the third NAND gate outputs the phase overlap indication signal.

8. The phase comparison circuit according to claim 6, characterized in that, The first to the eighth transistors are N-type transistors, and the ninth to the twelfth transistors are P-type transistors.

9. The phase comparison circuit according to claim 5, characterized in that, The fourth transistor is larger than the third transistor.

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