Switch assembly

Abstract

An integrated switch assembly having a stacked configuration, the integrated switch assembly comprising: a first layer comprising a photonic integrated circuit (PIC); a second layer comprising a switch ASIC; wherein the first layer is disposed onto a substrate and the second layer is disposed on top of the first layer.

Description

Technical Field

[0001] One or more aspects of embodiments of the present invention relate to an integrated switch assembly having a stacked configuration, and more specifically to an integrated switch assembly having a stacked configuration, the integrated switch assembly comprising a photonic integrated circuit, a PIC, and a switch ASIC disposed on top of the PIC. Background Technology

[0002] Integrated photonic platforms are well-known and often key to the mass production of photonic products. Typically, the concept of integration or co-packaging involves arranging photonic inputs / outputs around the periphery of a digital ASIC. Photonic components (such as modulators and photodiodes) are also typically arranged around the periphery of the ASIC, and any drivers for these components reside within the digital ASIC or are integrated onto a photonic integrated chip arranged around the periphery of the ASIC. The problem with such arrangements is that very long, high-speed traces (on the order of mm or cm) are typically required to connect the components within the digital ASIC to the optical inputs / outputs. Some embodiments of the present invention aim to reduce the need for long, high-speed traces in integrated platforms. Summary of the Invention

[0003] Therefore, some embodiments of the present invention aim to solve the above problems by providing an integrated switch assembly having a stacked configuration, the integrated switch assembly comprising:

[0004] The first layer includes a photonic integrated circuit (PIC).

[0005] The second layer includes a switching ASIC.

[0006] The first layer is disposed on the substrate and the second layer is disposed on top of the first layer.

[0007] The resulting stacked assembly is a 3D assembly. Typically, the substrate may include one of the following: a substrate, a motherboard, an organic substrate, or a next higher assembly. The material of the PIC may be silicon-on-insulator (SI), and it will be understood that the ASIC is any relevant application-specific integrated circuit.

[0008] When the second layer is placed on top of the first layer, the second layer is directly on top of the first layer and certain components can be precisely aligned to minimize any electrical connection between the two components, which is a vertical connection between the two layers. Therefore, the components to be connected can be aligned in the x and y directions and shifted relative to each other only along the z-axis, because one component (e.g., a modulator driver) is directly above the other component (e.g., a modulator).

[0009] Optional features of the invention will now be stated. These may be applied individually or in any combination with any aspect of the invention.

[0010] Optionally, the PIC includes one or more through-holes for providing electrical contact between components on the ASIC above the PIC and the substrate.

[0011] In some embodiments, the PIC is a silicon photonic PIC (e.g., silicon-on-insulator), and therefore the via is a through-silicon via (TSV). TSVs are low-speed interconnects. Thus, the stacking configuration of some embodiments of the invention involves minimizing the high-speed RF path length. This generally maximizes the speed performance of the assembly and improves scalability.

[0012] Optionally, the PIC includes a plurality of vias, each via providing an electrical contact between a component on the ASIC above the PIC and the substrate.

[0013] Optionally, the PIC of the first layer includes one or more modulators. Each modulator converts an unmodulated optical signal and a modulated electrical signal into a modulated optical signal.

[0014] ASICs are typically high-density ASICs and can therefore include compact optoelectronic modulators such as MTP EAM (micro-transfer electro-absorption modulator) or ring resonators (RR).

[0015] Optionally, the ASIC includes one or more modulator drivers, each of which is configured to drive a corresponding modulator among the one or more modulators, each modulator converting an unmodulated optical signal and a modulated electrical signal into a modulated optical signal.

[0016] Optionally, the PIC of the first layer includes one or more photodiodes.

[0017] Optionally, the ASIC includes one or more transimpedance amplifiers (TIAs), each of which is configured to amplify a signal from a corresponding photodiode among the one or more photodiodes.

[0018] Optionally, the PIC includes an arrangement of modulators and photodiodes scattered among each other.

[0019] Optionally, the ASIC includes an arrangement of modulator drivers and TIAs that are distributed among themselves, such that each modulator on the PIC is aligned with a modulator driver on the ASIC above the PIC, and each photodiode is aligned with a TIA on the ASIC above the PIC. In this arrangement, the distributed arrangement of modulator drivers and TIAs on the ASIC generally reflects the corresponding distributed arrangement of a modulator in the PIC with a photodiode below it. In this way, the connection between each modulator and its corresponding modulator driver is minimized, and each electrical connection between each photodiode and its corresponding TIA is also minimized.

[0020] Optionally, the PIC includes at least one serializer / deserializer, SerDes.

[0021] Optionally, the PIC itself is arranged on two layers: a photonic component layer including a modulator and / or a photodiode; and a driver layer including a modulator driver and / or a TIA for the respective modulator and / or photodiode.

[0022] Optionally, the driver layer is located between the photonic component layer and the substrate.

[0023] Optionally, the driver layer is located between the photonic component layer and the switch ASIC.

[0024] Optionally, the PIC includes one or more data input points, at which optical fibers are connected to components on the PIC to allow optical signals to enter the PIC components.

[0025] Optionally, the one or more data input points include an optical demultiplexer.

[0026] Optionally, the PIC includes one or more data output points, at which optical fibers are connected to components on the PIC to extract optical signals from the PIC components.

[0027] Optionally, the one or more data output points include optical multiplexers.

[0028] Optionally, the PIC also includes one or more groups of lasers. Typically, the laser group will be a hybrid laser group. A power divider may also be present to split the laser input across multiple components.

[0029] Optionally, the electrical connection between the PIC and the substrate includes one or more of the following: Cu bars, solder bumps, controlled collapse chip connections (C4), ball grid arrays (BGA), and pillar grid arrays (CGA). Attached Figure Description

[0030] These and other features and advantages of the invention will be understood and appreciated by referring to the specification, claims, and drawings, in which:

[0031] Figure 1 This is a schematic diagram illustrating (a) a first related technical design, (b) a second related technical design, and (c) an integrated solution according to an embodiment of the present invention;

[0032] Figure 2 shows two examples of ASIC layouts for integrated switch assemblies according to some embodiments of the present invention; in Figure 2A In the ASIC layer, a single switching logic is included, which includes a driver for the modulator; and it also includes a TIA that amplifies the signal from the photodiode; Figure 2B In this context, the ASIC layer consists of two separate switching logic areas;

[0033] Figure 3 shows two examples of PIC layouts for integrated switch assemblies according to some embodiments of the present invention, the PIC layouts being adapted to be disposed on top of an ASIC layer in a 3D stacked configuration; Figure 3A Public will be with Figure 2A An instance of an ASIC-compatible PIC layer; Figure 3B Public will be with Figure 2B An instance of an ASIC-compatible PIC layer;

[0034] Figure 4 shows two examples of PIC layouts containing on-chip hybrid lasers. Figure 4A A first configuration has one set of lasers located at the end of the chip furthest from the data output terminal; Figure 4B A group of lasers having a neighboring driver and positioned along the length of a PIC, the length of which extends laterally to the side where the data output is located;

[0035] Figure 5 illustrates an example of a cross-section of an integrated switch assembly according to some embodiments of the present invention, wherein Figure 5A Showing with Figure 2A ASIC layer and Figure 3A PIC layer compatible instances, and Figure 5B Showing with Figure 2B ASIC layer and Figure 3B PIC layer compatible instances;

[0036] Figure 6 illustrates another example of a cross-section of an integrated switch assembly according to some embodiments of the present invention, in which a PIC itself is arranged on two layers, a sub-layer of the two PIC layers including a modulator driver and a TIA; Figure 6A Showing with Figure 2A ASIC layer and Figure 3A PIC layer compatible instances, and Figure 6B Showing with Figure 2B ASIC layer and Figure 3B PIC layer compatible instances;

[0037] Figure 7 An example of an ASIC layer of an integrated switch assembly according to an embodiment of the present invention is illustrated, the ASIC layer including a distributed arrangement of a modulator driver and a TIA;

[0038] Figure 8 An example of a PIC layer of an integrated switch assembly according to an embodiment of the present invention is illustrated, the PIC layer comprising a distributed arrangement of modulators and photodiodes, the distributed arrangement being configured to... Figure 7 The ASIC's modulator driver and TIA are arranged in a matching manner.

[0039] Figure 9 Another example of a PIC layer of an integrated switch assembly according to an embodiment of the present invention is illustrated, the PIC layer comprising a modulator and a photodiode with an integrated hybrid laser in a distributed arrangement, the distributed arrangement being configured with the modulator and Figure 7 The arrangement of the ASIC's TIA shown is matched.

[0040] Figure 10 The illustration includes Figure 7 ASIC layer and Figure 9 or Figure 10 Cross-section of the integrated switch assembly in the PIC layer;

[0041] Figure 11 A cross-section of another embodiment of the integrated switch assembly is illustrated, wherein the connection between the PIC and the substrate includes a column grid array (CGA);

[0042] Figure 12 A cross-section of another embodiment of the integrated switch assembly is illustrated, wherein the connection between the PIC and the substrate includes a ball grid array (BGA);

[0043] Figure 13 illustrates cross-sections of two further embodiments of the integrated switch array according to some embodiments of the present invention, wherein the connections between the various layers of the 3D switch assembly include controlled collapse chip connections (C4); in Figure 13A In one implementation, the sublayer containing the driver is located between the PIC and the substrate; Figure 13B In one implementation, the sublayer containing the driver is located between the PIC layer and the ASIC; and

[0044] Figure 14 illustrates Figure 11 , Figure 12 , Figure 13A and Figure 13B The floor plan of the implementation scheme disclosed in the document. Detailed Implementation

[0045] The detailed description set forth below with reference to the accompanying drawings is intended as a description of an exemplary embodiment of an integrated switch assembly provided according to the invention, and is not intended to represent the only form in which the invention can be constructed or utilized. The description illustrates the features of the invention in conjunction with the illustrated embodiments. However, it should be understood that the same or equivalent functions and structures may be implemented by different embodiments that are also intended to be encompassed within the spirit and scope of the invention. As noted elsewhere herein, similar element designations are intended to indicate similar elements or features.

[0046] The following description, with reference to Figures 2 through 6, describes a first embodiment of the integrated switch assembly. The integrated switch assembly has a stacked configuration such that the components are arranged in 3D. The stacked arrangement includes: a first layer, namely a PIC layer containing a photonic integrated circuit (PIC); and a second layer, namely an ASIC layer containing a switching ASIC. The switching ASIC includes: switching logic, multiple drivers including multiple modulator drivers, and multiple optical transimpedance amplifiers (TIAs). Figure 2A In the illustrated implementation, these are located on the direct switching logic, the modulator driver array on one side of the switching logic, and the TIA array on the other side of the switching logic. Figure 2B In the implementation scheme, the driver is located adjacent to the switch logic. More specifically, there are two switch logic regions located on the ASIC layer, wherein the TIA array is located between the two switch logic regions and the modulator driver array is located on both sides of the switch logic regions opposite to the TIA.

[0047] like Figure 3A and Figure 3B As shown, the PIC layer includes a modulator and a photodiode. Figure 3A The implementation plan is configured to be placed in Figure 2A The PIC layer is located on top of the ASIC layer and consists of a first part, which includes a laser input, a modulator array, and an optical multiplexer (MUX). The laser input is in the form of multiple (e.g., a given integer f) laser inputs, which may be fiber optic inputs. The PIC layer also includes multiple power dividers (in this case, f*1 to P power dividers (i.e., f power dividers, each of which is a 1 to P power divider)) and an optical multiplexer (in this case, N to 1 or k*L to 1 MUX). The second part of the PIC layer includes a photodiode array and an optical demultiplexer (DeMUX) (in this case, 1 to N or k*1 to L DeMUX). Figure 3B The implementation plan is configured to be placed in Figure 2BOn top of the ASIC layer, and therefore with Figure 3A The implementation differs in that it includes: two outer regions, each comprising a modulator array, a power divider, and a multiplexer; and an inner region comprising a photodiode array and a DeMUX. The modulators and photodiodes of the PIC layer are arranged such that when the PIC layer is located on top of the direct ASIC layer, the modulators and photodiodes are aligned with their corresponding modulator drivers and TIAs located on the ASIC layer. Figure 4A and Figure 4B Show the area of ​​the PIC containing the modulator and with Figure 3A and Figure 3B The difference in the area of ​​the PIC shown is that it also includes a set of lasers, typically hybrid lasers located directly on the PIC. From Figure 5A and Figure 5B As can be seen in the cross-section, the PIC contains multiple low-speed through-silicon vias (TSVs) for providing electrical connections between the substrate and the switching ASIC through the PIC. Figure 6A and Figure 6B In this implementation, the PIC itself consists of two layers: a first sublayer containing photonic components and a second sublayer containing drivers for these components. In this implementation, the ASIC layer therefore no longer needs to contain drivers / TIAs other than switching logic.

[0048] Cu bars or solder bumps can form electrical connections between the PIC and any underlying substrate, and also between the PIC layer and the ASIC layer.

[0049] The following text is for reference only. Figures 7 to 10 The second set of implementation schemes is described. These implementation schemes relate to an integrated switch assembly having an ASIC layer ( Figure 7 The ASIC layer has a distributed arrangement of modulator drivers and TIAs; and a corresponding PIC layer. Figure 8 The PIC layer includes a distributed arrangement of modulators and photodiodes, and the distributed arrangement of the PICs is configured to... Figure 7 The modulator driver of the ASIC shown is matched to the arrangement of the TIA. In previous embodiments, the PIC layer also includes a power divider, a MUX, and a DeMUX. However, in this embodiment, these are located at the periphery, with the modulator and photodiodes located in a scattered array at the center of the PIC layer. The scattered array may be in the form of alternating rows of modulators and rows of photodiodes. In some embodiments ( Figure 9 In this configuration, the PIC layer also includes one or more groups of lasers, which are typically located around the periphery of the PIC. Typically, the laser groups are positioned close to a power divider that receives optical input from the laser groups and feeds it into the optical components.

[0050] The following text is for reference only. <a href="javascript:;" class="see-img-anchor" img-id="HDA0003926247200000121,HDA0003926247200000131,HDA0003926247200000141,HDA0003926247200000151,HDA0003926247200000161" title="图14(转下页--> Figures 11 through 13 describe other embodiments. In each case, the ASIC layer, including the switching ASIC, is located directly above the PIC layer, and the PIC layer is located directly above the substrate (also referred to as the next higher assembly). At least one driver layer, including the modulator driver and / or TIA, is located between the PIC and the substrate. The driver layer is smaller than the PIC and is located directly below the PIC area where the modulator and / or photodiode are located. Figure 11 The embodiment shown depicts two driver layers, each located on a corresponding side of the PIC adjacent to the laser input fiber. This is clearly visible in the plan view shown in Figure 14, which shows the fiber input / output ends located on two opposite sides of the PIC. The TSV is located throughout the PIC, including within the central area. Figure 11 In the embodiment shown, the connection between the PIC and the substrate includes a column grid array (CGA).

[0051] Figure 12 Implementation plan and Figure 11 The implementation scheme differs in that the connection between the PIC and the substrate includes a ball grid array (BGA). Figure 13A and Figure 13B In the implementation scheme, the connections between the layers of the 3D switch assembly include controlled collapse chip connections (C4); Figure 13A In the implementation scheme, the sublayer containing the driver is located between the PIC and the substrate, while Figure 13B In this implementation, the driver sublayer is located between the PIC and the switch ASIC.

[0052] As used in this article, "non-collapseable chip connection" refers to a pin or non-collapseable bump.

[0053] Although exemplary embodiments of integrated switch assemblies have been specifically described and illustrated herein, those skilled in the art will appreciate numerous modifications and variations. Therefore, it should be understood that integrated switch assemblies constructed according to the principles of the invention may have embodiments other than those specifically described herein. The invention is also defined by the following claims and their equivalents.

Claims

1. An application-specific integrated circuit (ASIC) layer for use in a vertically stacked multilayer switch assembly, the multilayer switch assembly including a substrate, a photonic integrated circuit (PIC) layer stacked on the substrate, and an ASIC layer stacked on the PIC layer, the ASIC layer comprising: A two-dimensional modulator driver array including modulator driver rows and modulator driver columns; as well as A two-dimensional transimpedance amplifier array comprising rows and columns of transimpedance amplifiers. The two-dimensional modulator driver array and the two-dimensional transimpedance amplifier array are arranged in the ASIC layer, wherein modulator driver rows alternate with transimpedance amplifier rows, or modulator driver columns alternate with transimpedance amplifier columns. The PIC layer includes a two-dimensional modulator array and a two-dimensional photodiode array, wherein the two-dimensional modulator array and the two-dimensional photodiode array are arranged in the PIC layer, wherein modulator rows and photodiode rows alternate, or modulator columns and photodiode columns alternate. The arrangement of the two-dimensional modulator driver array and the two-dimensional transimpedance amplifier array in the ASIC layer is a mirror image of the arrangement of the two-dimensional modulator array and the two-dimensional photodiode array in the PIC layer, such that each modulator driver in the ASIC layer corresponds to a modulator in the mirrored PIC layer, and each transimpedance amplifier in the ASIC layer corresponds to a photodiode in the mirrored PIC layer. Wherein, when the ASIC layer and the PIC layer are stacked in the vertically stacked multilayer switch assembly, the arrangement of the two-dimensional modulator driver array and the two-dimensional transimpedance amplifier array in the ASIC layer is aligned with the arrangement of the two-dimensional modulator array and the two-dimensional photodiode array in the PIC layer, such that each modulator driver in the ASIC layer is electrically connected to and configured to drive the modulator in its mirror arrangement in the PIC layer, and each transimpedance amplifier is electrically connected to and configured to amplify the signal from the photodiode in its mirror arrangement in the PIC layer.

2. The ASIC layer according to claim 1, wherein, The ASIC layer and the PIC layer are aligned to minimize the length of the electrical connection between each modulator driver in the ASIC layer and the corresponding modulator in the PIC layer, and to minimize the length of the electrical connection between each transimpedance amplifier in the ASIC layer and the corresponding photodiode in the PIC layer.

3. The ASIC layer of claim 1, wherein the electrical connection between each modulator driver of the ASIC layer and the corresponding modulator of the PIC layer comprises a copper rod or a solder bump.

4. The ASIC layer of claim 1, wherein the electrical connection between each transimpedance amplifier of the ASIC layer and the corresponding photodiode of the PIC layer comprises a copper rod or solder bump.

5. The ASIC layer of claim 1, wherein the PIC layer further comprises one or more data input points, at which an optical fiber is connected to allow an optical signal to enter a component of the PIC layer.

6. The ASIC layer of claim 5, wherein the one or more data input points comprise an optical demultiplexer.

7. The ASIC layer of claim 1, wherein the PIC layer further comprises one or more data output points, at which optical fibers are connected to extract optical signals from components in the PIC layer.

8. The ASIC layer of claim 7, wherein the one or more data output points comprise an optical multiplexer.

9. The ASIC layer of claim 1, wherein the PIC layer further comprises one or more sets of lasers.

10. The ASIC layer of claim 9, wherein the group or groups of lasers comprises hybrid lasers disposed around the periphery of the PIC layer.

11. The ASIC layer of claim 1, wherein the PIC layer further comprises a power divider, a multiplexer and a demultiplexer disposed around the periphery of the PIC layer, and wherein the two-dimensional modulator array and the two-dimensional photodiode array are disposed within the central region of the PIC layer.

12. The ASIC layer of claim 1, wherein the PIC layer further comprises at least one serializer / deserializer (SerDes).

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