Display substrate and manufacturing method thereof, and display device

Abstract

A display substrate and a preparation method thereof, and a display device, wherein the display substrate comprises a substrate, a driving circuit layer arranged on the substrate, and a light-emitting structure layer arranged on a side of the driving circuit layer away from the substrate, wherein the driving circuit layer comprises a transistor, and the light-emitting structure layer comprises a first electrode, a pixel definition layer, an organic light-emitting layer, and a second electrode, wherein the first electrode is connected to a drain electrode of the transistor, and the organic light-emitting layer is located between the first electrode and the second electrode; the pixel definition layer comprises a plurality of first retaining walls and a plurality of second retaining walls, wherein the height of the first retaining wall is less than the height of the second retaining wall, the first retaining wall and the second retaining wall cross-define a plurality of pixel opening areas, the pixel opening areas comprise a first pixel opening area and a second pixel opening area, the area of ​​the first pixel opening area is greater than the area of ​​the second pixel opening area, and two adjacent first pixel opening areas and second pixel opening areas are separated by the first retaining wall.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to but are not limited to the field of display technology, and in particular to a display substrate and a method for preparing the same, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) is an active light-emitting display device with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED as the light-emitting device and thin film transistor (TFT) for signal control have become the mainstream products in the current display field. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] The present disclosure provides a display substrate, comprising a substrate, a driving circuit layer arranged on the substrate, and a light-emitting structure layer arranged on a side of the driving circuit layer away from the substrate, wherein the driving circuit layer comprises a transistor, and the light-emitting structure layer comprises a first electrode, a pixel definition layer, an organic light-emitting layer, and a second electrode, wherein the first electrode is connected to a drain electrode of the transistor, and the organic light-emitting layer is located between the first electrode and the second electrode; the pixel definition layer comprises a plurality of first retaining walls and a plurality of second retaining walls, wherein the height of the first retaining wall is less than the height of the second retaining wall, and the first retaining wall and the second retaining wall intersect to define a plurality of pixel opening areas, wherein the pixel opening areas comprise a first pixel opening area and a second pixel opening area, wherein the area of ​​the first pixel opening area is greater than the area of ​​the second pixel opening area, and two adjacent first pixel opening areas and second pixel opening areas are separated by the first retaining wall.

[0005] In an exemplary embodiment, the second retaining wall extends along the second direction, a plurality of the second retaining walls are sequentially arranged along the first direction, a plurality of the first retaining walls sequentially arranged along the second direction are provided between two adjacent second retaining walls, and the first direction and the second direction intersect;

[0006] The second retaining wall includes a first sub-retaining wall and a second sub-retaining wall arranged at intervals, the first sub-retaining wall has a plurality of first bending portions and a plurality of second extending portions arranged alternately, the first bending portions extend in the first direction, and the second extending portions extend in the second direction.

[0007] In an exemplary embodiment, two adjacent first bending portions of the same first sub-blocking wall, a second extension portion between two adjacent first bending portions, a second sub-blocking wall adjacent to the first sub-blocking wall, and a first blocking wall between the first sub-blocking wall and the second sub-blocking wall form a first pixel opening area;

[0008] The second extending portion between two adjacent first bending portions of the same first sub-blocking wall, the second sub-blocking wall adjacent to the first sub-blocking wall, and the first blocking wall between the first sub-blocking wall and the second sub-blocking wall form a second pixel opening area.

[0009] In an exemplary embodiment, the bending times and bending directions of the first bending portions of the first sub-retaining walls are the same.

[0010] In an exemplary embodiment, a width of the second retaining wall along the first direction is between 1 / 3 and 2 / 3 of a width of the first bending portion along the first direction.

[0011] In an exemplary embodiment, the height of the first barrier wall is less than or equal to 1 micrometer, and the height of the second barrier wall is 1.2 micrometers to 1.5 micrometers.

[0012] In an exemplary embodiment, a width of the first retaining wall is smaller than a width of the second retaining wall.

[0013] In an exemplary embodiment, the material of the first retaining wall is a liquid-philic material, and the material of the second retaining wall is a liquid-phobic material.

[0014] In an exemplary embodiment, the first electrodes of all sub-pixels have the same width along the first direction, and the first electrodes of all sub-pixels are arranged in a matrix along the first direction and the second direction. The distances between the first electrodes in adjacent rows are equal, and the distance between the first electrode in the (2n+1)th column and the first electrode in the (2n+2)th column is greater than the distance between the first electrode in the (2n+2)th column and the first electrode in the (2n+3)th column, and n is an integer greater than or equal to 0.

[0015] In an exemplary embodiment, the first pixel opening area includes a light-emitting area and a non-light-emitting area, and the second pixel opening area only includes a light-emitting area, the orthographic projection of the light-emitting area on the substrate coincides with the orthographic projection of the first electrode on the substrate, and the orthographic projection of the non-light-emitting area on the substrate has no overlapping area with the orthographic projection of the first electrode on the substrate.

[0016] In an exemplary embodiment, the first electrodes of adjacent sub-pixels have different widths along the first direction, the first electrodes of all sub-pixels are arranged in a matrix along the first direction and the second direction, the distances between the first electrodes in adjacent rows are equal, and the distances between the first electrodes in adjacent columns are equal.

[0017] In an exemplary embodiment, a width of the second pixel opening region along the first direction is between 1 / 3 and 2 / 3 of a width of the first pixel opening region along the first direction.

[0018] The present disclosure also provides a display device, comprising the aforementioned display substrate.

[0019] The present disclosure also provides a method for preparing a display substrate, comprising:

[0020] forming a driving circuit layer on the substrate, wherein the driving circuit layer includes transistors;

[0021] A light-emitting structure layer is formed on the driving circuit layer, the light-emitting structure layer includes a first electrode, a pixel definition layer, an organic light-emitting layer and a second electrode, the first electrode is connected to the drain electrode of the transistor, and the organic light-emitting layer is located between the first electrode and the second electrode; the pixel definition layer includes a plurality of first retaining walls and a plurality of second retaining walls, the height of the first retaining wall is less than the height of the second retaining wall, the first retaining wall and the second retaining wall cross-define a plurality of pixel opening areas, the pixel opening areas include a first pixel opening area and a second pixel opening area, the area of ​​the first pixel opening area is greater than the area of ​​the second pixel opening area, and two adjacent first pixel opening areas and second pixel opening areas are separated by the first retaining wall.

[0022] In an exemplary embodiment, a light emitting structure layer is formed on the driving circuit layer, including:

[0023] forming a first electrode pattern on the driving circuit layer;

[0024] forming a pixel definition layer pattern by a single half-tone mask patterning process;

[0025] Forming an organic light-emitting layer pattern by inkjet printing process, wherein during inkjet printing, the organic light-emitting layer material ink is only printed to the first pixel opening area;

[0026] A second electrode pattern is formed on the organic light emitting layer.

[0027] In an exemplary embodiment, a light emitting structure layer is formed on the driving circuit layer, including:

[0028] forming a first electrode pattern on the driving circuit layer;

[0029] forming a first barrier wall pattern in the pixel definition layer by a first single-tone mask patterning process;

[0030] forming a second barrier wall pattern in the pixel definition layer by a second single-tone mask patterning process;

[0031] Forming an organic light-emitting layer pattern by inkjet printing process, wherein during inkjet printing, the organic light-emitting layer material ink is only printed to the first pixel opening area;

[0032] A second electrode pattern is formed on the organic light emitting layer.

[0033] In an exemplary embodiment, the organic light emitting layer pattern is formed by an inkjet printing process, including any one or more of the following:

[0034] Inkjet printing a hole injection material ink on the first pixel opening area, allowing the hole injection material ink to flow to the second pixel opening area adjacent to the first pixel opening area, drying to remove the solvent of the hole injection material ink, and then baking to form a hole injection layer pattern;

[0035] Inkjet printing a hole transport material ink on the first pixel opening area, allowing the hole transport material ink to flow to a second pixel opening area adjacent to the first pixel opening area, drying to remove the solvent of the hole transport material ink, and then baking to form a hole transport layer pattern;

[0036] The luminescent material ink is inkjet printed in the first pixel opening area, and the luminescent material ink flows to the second pixel opening area adjacent to the first pixel opening area, and is dried to remove the solvent of the luminescent material ink and then baked to form a luminescent layer pattern.

[0037] In an exemplary embodiment, the second retaining wall extends along the second direction, a plurality of the second retaining walls are sequentially arranged along the first direction, a plurality of the first retaining walls sequentially arranged along the second direction are provided between two adjacent second retaining walls, and the first direction and the second direction intersect;

[0038] The second retaining wall includes a first sub-retaining wall and a second sub-retaining wall arranged at intervals, the first sub-retaining wall has a plurality of first bending portions and a plurality of second extending portions arranged alternately, the first bending portions extend in the first direction, and the second extending portions extend in the second direction.

[0039] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present disclosure.

[0041] Figure 1 A schematic diagram of the calculation principle of the highest resolution of the substrate that can be printed by the printing device;

[0042] Figure 2 It is a structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0043] Figure 3 and Figure 4 for Figure 2 Schematic diagram of two cross-sectional structures in the AA' region;

[0044] Figure 5 for Figure 2 Schematic diagram of two cross-sectional structures in the middle BB' region;

[0045] Figure 6 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0046] Figure 7 It is a schematic diagram of an exemplary embodiment of the present disclosure after forming a driving circuit layer pattern;

[0047] Figure 8 It is a schematic diagram of an exemplary embodiment of the present disclosure after forming a first electrode pattern;

[0048] Fig. 9 for Figure 8 A schematic diagram of the planar structure of the first electrode pattern shown;

[0049] Fig.10 It is a schematic diagram of another exemplary embodiment of the present disclosure after forming a first electrode pattern;

[0050] Fig.11 for Fig.10 A schematic diagram of the planar structure of the first electrode pattern shown;

[0051] Fig.12 It is a schematic diagram of an exemplary embodiment of the present disclosure after forming a pixel definition layer pattern;

[0052] Fig.13 It is a schematic diagram of another exemplary embodiment of the present disclosure after forming a pixel definition layer pattern;

[0053] Fig.14 for Fig.12 or Fig.13 A schematic diagram of the planar structure of the pixel definition layer pattern shown;

[0054] Fig.15 and Fig.16 Schematic plan views of two first electrodes and pixel definition layer patterns formed in exemplary embodiments of the present disclosure;

[0055] Fig.17 This is a schematic diagram of an exemplary embodiment of the present disclosure after an organic light-emitting layer pattern is formed;

[0056] Fig.18 It is a schematic diagram of another exemplary embodiment of the present disclosure after forming an organic light-emitting layer pattern;

[0057] Fig.19 It is a schematic diagram of an exemplary embodiment of the present disclosure after forming a second electrode pattern;

[0058] Fig. 20 It is a schematic diagram of another exemplary embodiment of the present disclosure after forming a second electrode pattern;

[0059] Fig.21 The figure is a schematic structural diagram of a display device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0060] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings below. Note that the embodiments can be implemented in multiple different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0061] In the drawings, the size of each component, the thickness of a layer, or the area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to this size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0062] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0063] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0064] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0065] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0066] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0067] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0068] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0069] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0070] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0071] The film-forming methods of OLED mainly include evaporation process or solution process. The evaporation process is more mature in small-size applications, and the technology has been applied to mass production. The solution process OLED film-forming methods mainly include inkjet printing, nozzle coating, spin coating, screen printing, etc. Among them, inkjet printing technology is considered to be an important way to achieve mass production of large-size OLEDs due to its high material utilization rate and ability to achieve large sizes.

[0072] Currently, high-resolution OLED devices have become a development trend. However, for inkjet-printed OLED devices, the resolution is limited by the size of the printer nozzle. Figure 1 As shown, in general, the maximum resolution that a printing device can print is calculated as follows:

[0073]

[0074] If the printer is used to print display substrates with a higher resolution than the highest resolution it can print, there is a risk of ink overflow.

[0075] The embodiment of the present disclosure provides a display substrate, comprising a substrate, a driving circuit layer arranged on the substrate, and a light-emitting structure layer arranged on a side of the driving circuit layer away from the substrate, wherein the driving circuit layer comprises a transistor, the light-emitting structure layer comprises a first electrode, a pixel definition layer, an organic light-emitting layer, and a second electrode, wherein the first electrode is connected to a drain electrode of the transistor, and the organic light-emitting layer is located between the first electrode and the second electrode;

[0076] The pixel definition layer includes multiple first retaining walls and multiple second retaining walls, the height of the first retaining wall is smaller than the height of the second retaining wall, the first retaining wall and the second retaining wall cross-define multiple pixel opening areas, the pixel opening areas include a first pixel opening area and a second pixel opening area, the area of ​​the first pixel opening area is larger than the area of ​​the second pixel opening area, and two adjacent first pixel opening areas and second pixel opening areas are separated by the first retaining wall.

[0077] The display substrate of the disclosed embodiment uses two retaining walls of different heights to enclose a first pixel opening area and a second pixel opening area of ​​different areas. During inkjet printing, ink is only printed on the first pixel opening area. Since the height of the first retaining wall is relatively low, the ink in the first pixel opening area can flow to the second pixel opening area adjacent thereto, thereby effectively avoiding the problem of low pixel resolution caused by ink overflow. This can significantly improve process defects, increase processing yield, and reduce the distance between adjacent sub-pixel openings, thereby improving resolution and display quality.

[0078] Figure 2 is a schematic diagram of a planar structure of a display substrate according to an embodiment of the present disclosure, Figure 3 and Figure 4 for Figure 2 The following are schematic diagrams showing two cross-sectional structures of the substrate AA' region. Figure 5 for Figure 2 FIG. 2 is a schematic diagram showing the cross-sectional structure of the substrate BB' region. Figures 2 to 5 As shown, the display substrate may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first light emitting unit (sub-pixel) P1 emitting a first color light, a second light emitting unit P2 emitting a second color light, and a third light emitting unit P3 emitting a third color light, and the first light emitting unit P1, the second light emitting unit P2, and the third light emitting unit P3 each include a pixel driving circuit and a light emitting device. The pixel driving circuits in the first light emitting unit P1, the second light emitting unit P2, and the third light emitting unit P3 are respectively connected to the scanning signal line, the data signal line, and the light emitting signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light emitting signal line, and output a corresponding current to the light emitting device. The light emitting devices in the first light emitting unit P1, the second light emitting unit P2, and the third light emitting unit P3 are respectively connected to the pixel driving circuits of the light emitting units, and the light emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the light emitting unit.

[0079] In an exemplary embodiment, the pixel unit P may include a red (R) light-emitting unit, a green (G) light-emitting unit, and a blue (B) light-emitting unit, or may include a red light-emitting unit, a green light-emitting unit, a blue light-emitting unit, and a white light-emitting unit, which is not limited in the present disclosure. In an exemplary embodiment, the shape of the light-emitting unit in the pixel unit may be rectangular, rhombus, pentagonal, or hexagonal. When the pixel unit includes three light-emitting units, the three light-emitting units may be arranged in parallel horizontally, vertically, or in a triangle pattern. When the pixel unit includes four light-emitting units, the four light-emitting units may be arranged in parallel horizontally, vertically, or in a square pattern, which is not limited in the present disclosure.

[0080] Figure 3 and Figure 4 It only illustrates the structure of three sub-pixels in the OLED display substrate. Figure 3 or Figure 4 As shown, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on a substrate 10, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 10, and an encapsulation layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 10. In some possible implementations, the display substrate may include other film layers, such as spacers, etc., which are not limited in the present disclosure.

[0081] In an exemplary embodiment, the substrate 10 may be a flexible substrate, or may be a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit. Figure 3 In the figure, each sub-pixel includes a transistor 101 as an example. The light-emitting structure layer 103 may include a first electrode 21, a pixel definition layer, an organic light-emitting layer and a second electrode 26. The first electrode 21 is connected to the drain electrode of the transistor 101 through a via, the organic light-emitting layer is connected to the first electrode 21, and the second electrode 26 is connected to the organic light-emitting layer. The organic light-emitting layer emits light of corresponding colors under the drive of the first electrode 21 and the second electrode 26. The encapsulation layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402 and a third encapsulation layer 403 stacked together. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is arranged between the first encapsulation layer 401 and the third encapsulation layer 403, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0082] In an exemplary embodiment, if Figure 2As shown, the pixel definition layer includes multiple first retaining walls 22a and multiple second retaining walls 22b, the height of the first retaining wall 22a is less than the height of the second retaining wall 22b, the first retaining wall 22a and the second retaining wall 22b cross-define multiple pixel opening areas, the pixel opening areas include a first pixel opening area 221 and a second pixel opening area 222, the area of ​​the first pixel opening area 221 is greater than the area of ​​the second pixel opening area 222, and two adjacent first pixel opening areas 221 and second pixel opening areas 222 are separated by the first retaining wall 22a.

[0083] In an exemplary embodiment, if Figure 2 As shown, the first retaining wall 22a extends along the first direction D1, and a plurality of first retaining walls 22a are sequentially arranged along the second direction D2; the second retaining wall 22b extends along the second direction D2, and a plurality of second retaining walls 22b are sequentially arranged along the first direction D1; a plurality of first retaining walls 22a sequentially arranged along the second direction D2 are provided between two adjacent second retaining walls 22b, and the first direction D1 and the second direction D2 intersect;

[0084] The second retaining wall 22b includes a first sub-retaining wall 22b1 and a second sub-retaining wall 22b2 arranged at intervals, the first sub-retaining wall 22b1 has a plurality of first bending portions 22b1a and a plurality of second extending portions 22b1b arranged alternately, the first bending portions 22b1a extend in the first direction D1, the second extending portions 22b1b extend in the second direction D2, and the second sub-retaining wall 22b2 extends along the second direction D2.

[0085] In an exemplary embodiment, the first direction D1 is the same as an extending direction of the gate lines, and the second direction D2 is the same as an extending direction of the data lines. Exemplarily, the first direction D1 and the second direction D2 may be perpendicular to each other.

[0086] In an exemplary embodiment, if Figure 2 As shown, the first pixel opening regions 221 and the second pixel opening regions 222 are alternately arranged along the second direction D2, the sub-pixels in the same column have the same color, and adjacent sub-pixels in the same column are separated by the first blocking wall 22a.

[0087] In an exemplary embodiment, if Figure 2 As shown, the first pixel opening regions 221 and the second pixel opening regions 222 are alternately arranged along the first direction D1, adjacent sub-pixels in the same row of sub-pixels have different colors, and adjacent sub-pixels in the same row of sub-pixels are separated by second blocking walls 22b.

[0088] In an exemplary embodiment, if Figure 2As shown, two adjacent first bending portions 22b1a of the same first sub-blocking wall 22b1, a second extending portion 22b1b between the two adjacent first bending portions 22b1a, a second sub-blocking wall 22b2 adjacent to the first sub-blocking wall 22b1, and a first blocking wall 22a between the first sub-blocking wall 22b1 and the second sub-blocking wall 22b2 form a first pixel opening area 221;

[0089] The second extending portion 22b1b between two adjacent first bending portions 22b1a of the same first sub-blocking wall 22b1, the second sub-blocking wall 22b2 adjacent to the first sub-blocking wall 22b1, and the first blocking wall 22a between the first sub-blocking wall 22b1 and the second sub-blocking wall 22b2 form a second pixel opening area 222.

[0090] In an exemplary embodiment, if Figure 2 As shown, the bending times and bending directions of the multiple first bending portions 22b1a of the multiple first sub-blocking walls 22b1 are the same.

[0091] In an exemplary embodiment, if Figure 2 As shown, the width of the first retaining wall 22a is smaller than the width of the second retaining wall 22b.

[0092] In this embodiment, since the first retaining wall 22a only needs to separate the first electrodes 21 in adjacent sub-pixels and does not need to separate the organic light-emitting layer, the first retaining wall 22a can be designed to be as narrow as possible. The second retaining wall 22b needs to separate the organic light-emitting layers of adjacent sub-pixels, so the width of the second retaining wall 22b can be greater than the width of the first retaining wall 22a.

[0093] In an exemplary embodiment, the material of the first retaining wall 22 a is a liquid-philic material, and the material of the second retaining wall 22 b is a liquid-repellent material.

[0094] In an exemplary embodiment, if Figure 3 and Figure 4 As shown, the width of the first electrode 21 exposed by the first pixel opening region 221 is greater than or equal to the width of the first electrode 21 exposed by the second pixel opening region 222 .

[0095] In this embodiment, Figure 3As shown, when the width of the first electrode 21 exposed by the first pixel opening area 221 is equal to the width of the first electrode 21 exposed by the second pixel opening area 222, the width of the light-emitting areas of multiple sub-pixels in each pixel unit is the same. At this time, the first pixel opening area 221 is divided into a light-emitting area and a non-light-emitting area, and the first electrode 21 and the corresponding transistor 101 connected to the first electrode 21 are only arranged below the light-emitting area, and the first electrode or the transistor connected to the first electrode is not arranged below the non-light-emitting area. This scheme can keep the sizes of the three sub-pixels consistent, making the display edge smoother.

[0096] like Figure 4 As shown, when the width of the first electrode 21 exposed by the first pixel opening area 221 is greater than the width of the first electrode 21 exposed by the second pixel opening area 222, the width of the light-emitting area of ​​the sub-pixel in the first pixel opening area 221 in each pixel unit is greater than the width of the light-emitting area of ​​the sub-pixel in the second pixel opening area 222.

[0097] In exemplary embodiments, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. Figure 6 FIG. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. Figure 6 As shown, the pixel driving circuit is a 3T1C structure, which may include three switch transistors (a first transistor T1, a second transistor T2 and a third transistor T3), a storage capacitor C STand 6 signal lines (data line Dn, first scan line Gn, second scan line Sn, compensation line Se, first power line VDD and second power line VSS). In an exemplary embodiment, the first transistor T1 is a switch transistor, the second transistor T2 is a drive transistor, and the third transistor T3 is a compensation transistor. The gate electrode of the first transistor T1 is coupled to the first scan line Gn, the first electrode of the first transistor T1 is coupled to the data line Dn, the second electrode of the first transistor T1 is coupled to the gate electrode of the second transistor T2, and the first transistor T1 is used to receive the data signal transmitted by the data line Dn under the control of the first scan line Gn, so that the gate electrode of the second transistor T2 receives the data signal. The gate electrode of the second transistor T2 is coupled to the second electrode of the first transistor T1, the first electrode of the second transistor T2 is coupled to the first power line VDD, the second electrode of the second transistor T2 is coupled to the first electrode of the OLED, and the second transistor T2 is used to generate a corresponding current at the second electrode under the control of the data signal received by its gate electrode. The gate electrode of the third transistor T3 is coupled to the second scan line Sn, the first electrode of the third transistor T3 is connected to the compensation line Se, the second electrode of the third transistor T3 is coupled to the second electrode of the second transistor T2, and the third transistor T3 is used to extract the threshold voltage Vth and mobility of the second transistor T2 in response to the compensation timing to compensate for the threshold voltage Vth. The first electrode of the OLED is coupled to the second electrode of the second transistor T2, the second electrode of the OLED is coupled to the second power line VSS, and the OLED is used to emit light of corresponding brightness in response to the current of the second electrode of the second transistor T2. The storage capacitor C ST The first electrode of the storage capacitor C is coupled to the gate electrode of the second transistor T2. ST The second electrode of the second transistor T2 is coupled to the second electrode of the storage capacitor C ST Used to store the potential of the gate electrode of the second transistor T2.

[0098] In an exemplary embodiment, the signal of the first power line VDD is to continuously provide a high level signal, and the signal of the second power line VSS is a low level signal. The first transistor T1 to the third transistor T3 can be a P-type transistor, or can be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the third transistor T3 may include a P-type transistor and an N-type transistor. In an exemplary embodiment, the light-emitting device may be an organic light-emitting diode (OLED), including a stacked first electrode (anode) 21, an organic light-emitting layer, and a second electrode (cathode) 26.

[0099] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0100] In an exemplary embodiment, a process of preparing a display substrate may include the following operations.

[0101] (1) First, a driving circuit layer 102 pattern is prepared on a substrate 10, such as Figure 7 As shown. The driving circuit layer 102 includes a plurality of gate lines and a plurality of data lines, and the plurality of gate lines and the plurality of data lines cross to define a plurality of pixel units arranged in a matrix, each pixel unit includes at least 3 sub-pixels, and each sub-pixel includes a thin film transistor (TFT). In the present embodiment, a pixel unit includes 3 sub-pixels, namely, a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. Of course, the scheme of the present embodiment is also applicable to the case where a pixel unit includes 4 sub-pixels (red sub-pixel R, green sub-pixel G, blue sub-pixel B, and white sub-pixel W).

[0102] In an exemplary embodiment, the substrate 10 may be a flexible substrate, or may be a rigid substrate. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc. The materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate. The first and second inorganic material layers are also called barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-si). In an exemplary embodiment, taking a stacked structure as an example, its preparation process may include: first coating a layer of polyimide on a glass carrier, and forming a first flexible (PI1) layer after curing; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating the amorphous silicon layer with another layer of polyimide, and forming a second flexible (PI2) layer after curing; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thereby completing the preparation of the substrate 10.

[0103] In an exemplary embodiment, the preparation process of the driving circuit layer 102 may include:

[0104] A shielding film is deposited on the substrate 10 , and the shielding film is patterned through a patterning process to form a shielding layer pattern disposed on the substrate 10 .

[0105] Subsequently, a first insulating film and a semiconductor film are deposited in sequence, and the semiconductor film is patterned through a patterning process to form a first insulating layer covering the blocking layer pattern, and a semiconductor layer pattern arranged on the first insulating layer, wherein the semiconductor layer pattern includes at least an active layer, and the orthographic projection of the active layer on the substrate 10 is within the range of the orthographic projection of the blocking layer on the substrate 10.

[0106] Subsequently, a second insulating film and a first metal film are deposited in sequence, and the first metal film is patterned through a patterning process to form a second insulating layer arranged on the semiconductor layer pattern, and a first metal layer pattern arranged on the second insulating layer, the first metal layer pattern at least includes a gate electrode, the orthographic projection of the second insulating layer on the substrate 10 is within the range of the orthographic projection of the active layer on the substrate 10, and the orthographic projection of the gate electrode on the substrate 10 is within the range of the orthographic projection of the second insulating layer on the substrate 10.

[0107] Subsequently, a third insulating film is deposited and patterned by a patterning process to form a third insulating layer covering the pattern of the first metal layer, and an active via pattern is provided on the third insulating layer. Two active vias are located at the two ends of the active layer, and the third insulating layer in the active vias is etched away to expose the surface of the active layer.

[0108] Subsequently, a second metal film is deposited and patterned by a patterning process to form a second metal layer pattern on the third insulating layer. The second metal layer pattern includes at least a source electrode and a drain electrode. The source electrode and the drain electrode are respectively connected to the active layer through active vias.

[0109] Subsequently, a flat film is coated and patterned by a patterning process to form a flat layer covering the second metal layer pattern, an anode via pattern is opened on the flat layer, and the flat layer in the anode via is etched away to expose the surface of the drain electrode.

[0110] At this point, the pattern of the driving circuit layer 102 is completed on the substrate 10. Figure 7 In an exemplary embodiment, the active layer, the gate electrode, the source electrode and the drain electrode constitute the transistor 101. In an exemplary embodiment, the transistor 101 may be a driving transistor in a pixel driving circuit, and the driving transistor may be a thin film transistor (TFT).

[0111] In an exemplary embodiment, the first insulating layer, the second insulating layer and the third insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer. The first insulating layer is called a buffer layer, the second insulating layer is called a gate insulation (GI) layer, and the third insulating layer is called an interlayer insulation (ILD) layer. The flat film may be made of an organic material, such as a resin, etc. The first metal film and the second metal film may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or an alloy material of the above metals, such as an aluminum neodymium alloy (AlNd) or a molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multilayer composite structure, such as Ti / Al / Ti, etc. The shielding film may be made of a metal material, or a non-metallic material that is opaque. The active layer film can be made of various materials such as amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, polythiophene, etc., that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology and organic technology.

[0112] (2) forming a first electrode 21 pattern on the substrate on which the aforementioned pattern is formed. In an exemplary embodiment, forming the first electrode 21 pattern may include: depositing a first transparent conductive film on the substrate on which the aforementioned pattern is formed, patterning the first transparent conductive film through a patterning process to form the first electrode 21 pattern, wherein the first electrode 21 of each sub-pixel is connected to the drain electrode of the thin film transistor in the sub-pixel, such as Figures 8 to 9 or Figure 10 to Figure 11 shown.

[0113] In an exemplary embodiment, if Figures 8 to 9 As shown, the width a1 of the first electrodes 21 of all sub-pixels along the first direction D1 is the same, the first electrodes 21 of all sub-pixels are arranged in a matrix along the first direction D1 and the second direction D2, the distance b1 between the first electrodes 21 in adjacent rows is equal, the distance c1 between the first electrode 21 in the (2n+1)th column and the first electrode 21 in the (2n+2)th column is greater than the distance d1 between the first electrode 21 in the (2n+2)th column and the first electrode 21 in the (2n+3)th column, and n is an integer greater than or equal to 0.

[0114] In an exemplary embodiment, the first transparent conductive film may be made of indium tin oxide (ITO) or indium zinc oxide (IZO).

[0115] In an exemplary embodiment, if Figure 10 to Figure 11 As shown, the widths of the first electrodes 21 of adjacent sub-pixels along the first direction D1 are different. Among the first electrodes 21 of every two adjacent sub-pixels, the width of one electrode 21 along the first direction D1 is a2, and the width of the other electrode 21 along the first direction D1 is b2, a2>b2, and the first electrodes 21 of all sub-pixels are arranged in a matrix along the first direction D1 and the second direction D2, the distances c2 between the first electrodes 21 in adjacent rows are equal, and the distances d2 between the first electrodes 21 in adjacent columns are equal.

[0116] In an exemplary embodiment, the first electrode 21 may also be made of a metal with high reflectivity, such as silver Ag, gold Au, palladium Pd, platinum Pt, etc., or an alloy of these metals, or a composite layer of these metals. It may also be made of a composite layer structure of an indium tin oxide ITO layer and a metal reflective layer, which has good conductivity, high reflectivity, and good morphological stability.

[0117] (3) A pixel definition layer pattern is formed on the substrate formed with the aforementioned pattern. The pixel definition layer is used to define a light-emitting area in each sub-pixel. The light-emitting area exposes the first electrode 21. Figures 12 to 16 shown.

[0118] In an exemplary embodiment, forming a pixel definition layer pattern includes: coating a pixel definition film on the substrate forming the aforementioned pattern, and using a halftone mask to expose and develop the pixel definition film once to form a pixel definition layer pattern including both the first retaining wall 22a and the second retaining wall 22b.

[0119] In another exemplary embodiment, forming a pixel definition layer pattern includes: coating a first pixel definition film on the substrate forming the aforementioned pattern, and exposing and developing the first pixel definition film using a single-tone mask to form a first retaining wall 22a pattern; coating a second pixel definition film on the substrate forming the aforementioned pattern, and exposing and developing the second pixel definition film using a single-tone mask to form a second retaining wall 22b pattern.

[0120] In an exemplary embodiment, the pixel definition layer includes a plurality of first retaining walls 22a extending along a first direction D1 and a plurality of second retaining walls 22b extending along a second direction D2, the first direction D1 and the second direction D2 intersect, the first retaining walls 22a and the second retaining walls 22b cross-define a plurality of pixel opening areas, the pixel opening areas include a first pixel opening area 221 and a second pixel opening area 222, the first pixel opening areas 221 and the second pixel opening areas 222 are alternately arranged along the second direction D2, and the area of ​​the first pixel opening area 221 is greater than the area of ​​the second pixel opening area 222.

[0121] In an exemplary embodiment, the second retaining wall 22b includes a first sub-retaining wall 22b1 and a second sub-retaining wall 22b2 arranged at intervals, wherein the first sub-retaining wall 22b1 has a plurality of first bending portions 22b1a and a plurality of second extension portions 22b1b arranged alternately, the first bending portions 22b1a extend in the first direction D1, and the second extension portions 22b1b extend in the second direction D2.

[0122] In an exemplary embodiment, two adjacent first bending portions 22b1a of the same first sub-blocking wall 22b1, a second extension portion 22b1b between the two adjacent first bending portions 22b1a, a second sub-blocking wall 22b2 adjacent to the first sub-blocking wall 22b1, and a first blocking wall 22a between the first sub-blocking wall 22b1 and the second sub-blocking wall 22b2 form a first pixel opening area 221;

[0123] The second extending portion 22b1b between two adjacent first bending portions 22b1a of the same first sub-blocking wall 22b1, the second sub-blocking wall 22b2 adjacent to the first sub-blocking wall 22b1, and the first blocking wall 22a between the first sub-blocking wall 22b1 and the second sub-blocking wall 22b2 form a second pixel opening area 222.

[0124] In an exemplary embodiment, the width a3 of the second retaining wall 22 b along the first direction D1 is between 1 / 3 and 2 / 3 of the width b3 of the first bending portion 22 b 1 a along the first direction D1 .

[0125] In an exemplary embodiment, a width d3 of the second pixel opening region 222 along the first direction D1 is between 1 / 3 and 2 / 3 of a width d4 of the first pixel opening region 221 along the first direction D1.

[0126] In an exemplary embodiment, the height of the first retaining wall 22a is smaller than the height of the second retaining wall 22b.

[0127] In an exemplary embodiment, the height of the first barrier wall 22 a is less than 1 micrometer.

[0128] In an exemplary embodiment, the height of the second barrier wall 22 b is 1.2 micrometers to 1.5 micrometers.

[0129] In this embodiment, since the ink is only printed to the first pixel opening area 221 when the organic light-emitting layer is printed, the ink in the second pixel opening area 222 is the ink in the first pixel opening area 221. Therefore, the first retaining wall 22a does not need to consider the overflow problem of the ink. The first retaining wall 22a only needs to isolate the first electrode 21 of the adjacent sub-pixel. The width c3 of the first retaining wall 22a along the second direction D2 can be designed to be as narrow as possible, thereby improving the pixel resolution. In an exemplary embodiment, the first retaining wall 22a only needs to cover the edges of the two adjacent first electrodes 21, for example, the first electrode edge extends inwardly less than 3 microns, and further, it can be less than 2 microns. In an exemplary embodiment, the second retaining wall 22b covers the edges of the two adjacent first electrodes 21, for example, the first electrode edge extends inwardly less than 4 microns, and further, it can be less than 3 microns, and further, it can be less than 2 microns. In an exemplary embodiment, the size of the second retaining wall 22b covering the edge of the first electrode can be greater than or equal to the size of the first retaining wall 22a covering the edge of the first electrode.

[0130] In an exemplary embodiment, the material of the first retaining wall 22 a is a liquid-philic material, and the material of the second retaining wall 22 b is a liquid-repellent material.

[0131] In an exemplary embodiment, the first bending portions 22b1a of the first sub-blocking walls 22b1 have the same number of bending times and same bending directions.

[0132] For example, Fig.14As shown, from top to bottom, the first bending portions 22b1a of the first sub-blocking walls 22b1 are all bent to the left, to the right, to the left, to the right, etc., that is, the bending times and bending directions of the first bending portions 22b1a of the first sub-blocking walls 22b1 are the same, so that the first pixel opening areas 221 and the second pixel opening areas 222 defined by the intersection of the first blocking wall 22a and the second blocking wall 22b are alternately arranged along the first direction D1. Since the ink is only printed to the first pixel opening area 221 when the organic light-emitting layer is printed, the ink in the second pixel opening area 222 is the ink in the first pixel opening area 221. Therefore, the second blocking wall 22b only needs to consider the overflow problem of the ink on one side, and the width a3 of the second blocking wall 22b along the first direction D1 can be designed to be narrower. In addition, the first retaining wall 22a only needs to separate the first electrodes 21 in adjacent sub-pixels, and does not need to separate the organic light-emitting layer. Therefore, the width c3 of the first retaining wall 22a along the second direction D2 can be designed to be as narrow as possible, thereby greatly improving the pixel resolution.

[0133] In an exemplary embodiment, the width a3 of the second barrier rib 22b along the first direction D1 is 5 to 30 micrometers. Exemplarily, the width a3 of the second barrier rib 22b along the first direction D1 is 5 to 10 micrometers.

[0134] In an exemplary embodiment, in a plane parallel to the display substrate, the shape of the first pixel opening region 221 and the second pixel opening region 222 may be a triangle, a rectangle, a polygon, a circle, an ellipse, etc. In a plane perpendicular to the display substrate, the cross-sectional shape of the first pixel opening region 221 and the second pixel opening region 222 may be a rectangle or a trapezoid, etc.

[0135] (4) forming an organic light-emitting layer pattern on the substrate on which the aforementioned pattern is formed. In an exemplary embodiment, forming the organic light-emitting layer pattern may include: inkjet printing a hole injection material ink on the first pixel opening region 221, and since the first retaining wall 22a is made of a lyophilic material and has a relatively low height, the hole injection material ink flows to the second pixel opening region 222 adjacent to the first pixel opening region 221, and drying to remove the solvent of the hole injection material ink and then baking to form a hole injection layer 23 pattern;

[0136] The hole transport material ink is inkjet printed on the first pixel opening area 221. Since the first retaining wall 22a is a lyophilic material and has a relatively low height, the hole transport material ink flows to the second pixel opening area 222 adjacent to the first pixel opening area 221. The hole transport material ink is dried to remove the solvent and then baked to form a hole transport layer 24 pattern.

[0137] The luminescent material ink is inkjet printed on the first pixel opening area 221. Since the first retaining wall 22a is a lyophilic material and has a low height, the luminescent material ink flows to the second pixel opening area 222 adjacent to the first pixel opening area 221. The luminescent material ink is dried to remove the solvent and then baked to form a luminescent layer 25 pattern, such as Figure 17 to Figure 18 shown.

[0138] In an exemplary embodiment, the organic light-emitting layer may include any one or more of the following layers in addition to the above-mentioned hole injection layer (HIL) 23, hole transport layer (HTL) 24, and emitting layer (EML) 25: electron blocking layer (EBL), hole blocking layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In an exemplary embodiment, the electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer may be formed by open mask evaporation.

[0139] In an exemplary embodiment, the electron blocking layer can be used as a microcavity adjustment layer of the light-emitting device. By designing the thickness of the electron blocking layer, the thickness of the organic light-emitting layer between the cathode and the anode can meet the design of the microcavity length. In some exemplary embodiments, the hole transport layer, the hole blocking layer or the electron transport layer in the organic light-emitting layer can be used as the microcavity adjustment layer of the light-emitting device, which is not limited in the present disclosure.

[0140] In an exemplary embodiment, the light-emitting layer may include a host material and a guest material doped in the host material, and the doping ratio of the guest material in the light-emitting layer is 1% to 20%. Within the doping ratio range, on the one hand, the host material of the light-emitting layer can effectively transfer the exciton energy to the guest material of the light-emitting layer to excite the guest material of the light-emitting layer to emit light, and on the other hand, the host material of the light-emitting layer "dilutes" the guest material of the light-emitting layer, effectively improving the mutual collision between the molecules of the guest material of the light-emitting layer, and the fluorescence quenching caused by the mutual collision between the energy, thereby improving the luminous efficiency and the life of the device. In an exemplary embodiment, the doping ratio refers to the ratio of the mass of the guest material to the mass of the light-emitting layer, that is, the mass percentage. In an exemplary embodiment, the thickness of the light-emitting layer may be about 10nm to 50nm.

[0141] In an exemplary embodiment, the hole injection layer may be made of an inorganic oxide, such as molybdenum oxide, titanium oxide, vanadium oxide, rhenium oxide, ruthenium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silver oxide, tungsten oxide or manganese oxide, or may be made of a p-type dopant of a strong electron-withdrawing system and a dopant of a hole transport material. In an exemplary embodiment, the hole injection layer may have a thickness of about 5 nm to 20 nm.

[0142] In an exemplary embodiment, in an exemplary embodiment, the hole transport layer may be made of a material with high hole mobility, such as an aromatic amine compound, and its substituent group may be carbazole, methylfluorene, spirofluorene, dibenzothiophene or furan, etc. In an exemplary embodiment, the thickness of the hole transport layer may be about 40 nm to 150 nm.

[0143] In an exemplary embodiment, the hole blocking layer and the electron transport layer may be made of aromatic heterocyclic compounds, such as imidazole derivatives such as benzimidazole derivatives, imidazopyridine derivatives, benzimidazolephenanthridine derivatives; oxazine derivatives such as pyrimidine derivatives and triazine derivatives; compounds containing nitrogen-containing six-membered ring structures such as quinoline derivatives, isoquinoline derivatives, and phenanthroline derivatives (including compounds having phosphine oxide-based substituents on heterocyclic rings), etc. In an exemplary embodiment, the thickness of the hole blocking layer may be about 5nm to 15nm, and the thickness of the electron transport layer may be about 20nm to 50nm.

[0144] In an exemplary embodiment, the electron injection layer may be made of an alkali metal or metal, such as lithium fluoride (LiF), ytterbium (Yb), magnesium (Mg) or calcium (Ca), or a compound of these alkali metals or metals. In an exemplary embodiment, the thickness of the electron injection layer may be about 0.5 nm to 2 nm.

[0145] (5) forming a second electrode 26 pattern on the substrate having the aforementioned pattern. In an exemplary embodiment, forming the second electrode 26 pattern may include: evaporating a second electrode material on the substrate having the aforementioned pattern to form the second electrode 26 pattern, wherein the second electrode 26 is connected to the light emitting layer 25, such as Figures 19 to 20 In an exemplary embodiment, the second electrode 26 may be an integral structure that is connected together.

[0146] At this point, the pattern of the light emitting structure layer 103 is completed on the driving circuit layer 102 . The light emitting structure layer 103 includes a first electrode 21 , a pixel definition layer, an organic light emitting layer and a second electrode 26 . The organic light emitting layer is connected to the first electrode 21 and the second electrode 26 , respectively.

[0147] (6) Forming a pattern of the encapsulation layer 104 on the substrate having the aforementioned pattern, such as Figure 3 or Figure 4As shown. Forming the pattern of the encapsulation layer 104 may include: first using an open mask plate to deposit a first inorganic thin film by plasma enhanced chemical vapor deposition (PECVD) to form a first encapsulation layer 401. Subsequently, an organic material is inkjet printed on the first encapsulation layer 401 by an inkjet printing process, and after curing into a film, a second encapsulation layer 402 is formed. Subsequently, a second inorganic thin film is deposited by an open mask plate to form a third encapsulation layer 403, and the first encapsulation layer 401, the second encapsulation layer 402 and the third encapsulation layer 403 constitute the encapsulation layer 104. In an exemplary embodiment, the first encapsulation layer 401 and the third encapsulation layer 403 may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer. The second encapsulation layer 402 may be made of a resin material to form a laminated structure of inorganic material / organic material / inorganic material. The organic material layer is arranged between the two inorganic material layers to ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0148] In an exemplary embodiment, after the encapsulation layer 104 is prepared, a touch structure layer (TSP) may be formed on the encapsulation layer 104 , and the touch structure layer may include a touch electrode layer, or include a touch electrode layer and a touch insulating layer.

[0149] In an exemplary embodiment, when preparing a flexible display substrate, the preparation process of the display substrate may include processes such as peeling off a glass carrier, attaching a back film, and cutting, which are not limited in the present disclosure.

[0150] It can be seen from the structure of the display substrate and its preparation process of the exemplary embodiment of the present disclosure that in a plane perpendicular to the display substrate, the exemplary embodiment of the present disclosure forms two retaining walls with different heights (and liquid affinity) to enclose the first pixel opening area 221 and the second pixel opening area 222 arranged alternately. When the organic light-emitting layer is printed, the ink is only printed to the first pixel opening area 221, and the ink in the first pixel opening area 221 can flow into the second pixel opening area 222, so that the pixels in the second pixel opening area 222 can be designed to be as narrow as possible. Since the ink in the second pixel opening area 222 flows from the first pixel opening area 221, the first retaining wall 22a does not need to consider the overflow problem of ink on both sides. Therefore, the first retaining wall 22a can be designed to be as narrow as possible. The second retaining wall 22b only considers the overflow problem of ink on one side. Therefore, the second retaining wall 22b can also be designed to be narrower, thereby improving the pixel resolution, solving the problem caused by the error of ink spraying amount between multiple nozzles, and helping to improve the display quality. The exemplary embodiments of the present disclosure show that the method for preparing the substrate has good process compatibility, simple process realization, easy implementation, high production efficiency, low production cost, easy printing and mass production, and high yield rate.

[0151] The structure and preparation process shown in the exemplary embodiment of the present disclosure are merely exemplary. In the exemplary embodiment, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. For example, the transistor in the driving circuit layer 102 can be a top gate structure, or a bottom gate structure, a single gate structure, or a double gate structure. For another example, other film layer structures, electrode structures, or lead structures can also be provided in the driving circuit layer 102 and the light emitting structure layer 103. For another example, the substrate 10 can be a glass substrate, which is not specifically limited in the present disclosure.

[0152] The present disclosure also provides a method for preparing a display substrate. In an exemplary embodiment, the preparation method may include:

[0153] forming a driving circuit layer on the substrate, wherein the driving circuit layer includes transistors;

[0154] A light-emitting structure layer is formed on the driving circuit layer, and the light-emitting structure layer includes a first electrode, a pixel definition layer, an organic light-emitting layer and a second electrode, the first electrode is connected to the drain electrode of the transistor, and the organic light-emitting layer is connected to the first electrode and the second electrode respectively; the pixel definition layer includes a plurality of first retaining walls and a plurality of second retaining walls, the height of the first retaining wall is less than the height of the second retaining wall, the first retaining wall and the second retaining wall cross-define a plurality of pixel opening areas, the pixel opening areas include a first pixel opening area and a second pixel opening area, the area of ​​the first pixel opening area is greater than the area of ​​the second pixel opening area, and at least one group of adjacent first pixel opening areas and second pixel opening areas are separated by the first retaining wall.

[0155] In an exemplary embodiment, forming a light emitting structure layer on the driving circuit layer includes:

[0156] forming a first electrode pattern on the driving circuit layer;

[0157] forming a pixel definition layer pattern by a single half-tone mask patterning process;

[0158] Forming an organic light-emitting layer pattern by inkjet printing process, wherein during inkjet printing, the organic light-emitting layer material ink is only printed to the first pixel opening area;

[0159] A second electrode pattern is formed, wherein the second electrode is connected to the organic light emitting layer.

[0160] In an exemplary embodiment, forming a light emitting structure layer on the driving circuit layer includes:

[0161] forming a first electrode pattern on the driving circuit layer;

[0162] forming a first barrier wall pattern in the pixel definition layer by a first single-tone mask patterning process;

[0163] forming a second barrier wall pattern in the pixel definition layer by a second single-tone mask patterning process;

[0164] Forming an organic light-emitting layer pattern by inkjet printing process, wherein during inkjet printing, the organic light-emitting layer material ink is only printed to the first pixel opening area;

[0165] A second electrode pattern is formed, wherein the second electrode is connected to the organic light emitting layer.

[0166] In an exemplary embodiment, the organic light emitting layer pattern is formed by an inkjet printing process, including any one or more of the following:

[0167] Inkjet printing a hole injection material ink on the first pixel opening area, allowing the hole injection material ink to flow to the second pixel opening area adjacent to the first pixel opening area, drying to remove the solvent of the hole injection material ink, and then baking to form a hole injection layer pattern;

[0168] Inkjet printing a hole transport material ink on the first pixel opening area, allowing the hole transport material ink to flow to a second pixel opening area adjacent to the first pixel opening area, drying to remove the solvent of the hole transport material ink, and then baking to form a hole transport layer pattern;

[0169] The luminescent material ink is inkjet printed in the first pixel opening area, and the luminescent material ink flows to the second pixel opening area adjacent to the first pixel opening area, and is dried to remove the solvent of the luminescent material ink and then baked to form a luminescent layer pattern.

[0170] In an exemplary embodiment, the first retaining wall extends along a first direction, a plurality of the first retaining walls are arranged in sequence along a second direction, a plurality of the second retaining walls are arranged in sequence along the first direction, and the first direction and the second direction intersect;

[0171] The second retaining wall includes a first sub-retaining wall and a second sub-retaining wall arranged at intervals, the first sub-retaining wall has a plurality of first bending portions and a plurality of second extending portions arranged alternately, the first bending portions extend in the first direction, and the second extending portions extend in the second direction.

[0172] In an exemplary embodiment, any two adjacent first bending portions of the same first sub-blocking wall, a second extension portion between two adjacent first bending portions, a second sub-blocking wall adjacent to the first sub-blocking wall, and a first blocking wall between the first sub-blocking wall and the second sub-blocking wall form a first pixel opening area;

[0173] The second extending portion between any two adjacent first bending portions of the same first sub-blocking wall, the second sub-blocking wall adjacent to the first sub-blocking wall, and the first blocking wall between the first sub-blocking wall and the second sub-blocking wall form a second pixel opening area.

[0174] In an exemplary embodiment, the bending times and bending directions of the first bending portions of the first sub-retaining walls are the same.

[0175] In an exemplary embodiment, the height of the first barrier wall is less than or equal to 1 micrometer, and the height of the second barrier wall is 1.2 micrometers to 1.5 micrometers.

[0176] In an exemplary embodiment, the width of the first retaining wall is smaller than the width of the second retaining wall.

[0177] In an exemplary embodiment, the material of the first retaining wall is a liquid-philic material, and the material of the second retaining wall is a liquid-phobic material.

[0178] In an exemplary embodiment, a width of the first electrode exposed by the first pixel opening region is greater than or equal to a width of the first electrode exposed by the second pixel opening region.

[0179] The present disclosure provides a method for preparing a display substrate, by using two retaining walls of different heights to enclose a first pixel opening area and a second pixel opening area of ​​different areas, the ink is only printed to the first pixel opening area during inkjet printing, and since the height of the first retaining wall is relatively low, the ink in the first pixel opening area can flow to the second pixel opening area adjacent thereto, thereby effectively avoiding the problem of low pixel resolution caused by ink overflow, and further significantly improving process defects, increasing processing yield, and reducing the distance between adjacent sub-pixel openings, thereby improving resolution and display quality.

[0180] The present disclosure also provides a display device, including the display substrate of the above embodiment. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame or a navigator.

[0181] Fig.21 FIG. 1 is a schematic diagram of a display device according to an embodiment of the present disclosure. Fig.21As shown, the OLED display device may include a timing controller, a data driver, a scan driver and a pixel array, and the pixel array may include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn) and a plurality of sub-pixels Pxij. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driver to the data driver, and may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan driver to the scan driver. The data driver may generate a data voltage to be provided to the data signal lines D1, D2, D3, ... and Dn using the grayscale value and the control signal received from the timing controller. For example, the data driver may sample the grayscale value using a clock signal, and apply a data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of sub-pixel rows, where n may be a natural number. The scan driver may generate a scan signal to be provided to the scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan driver may sequentially provide a scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan driver may be constructed in the form of a shift register, and may generate a scan signal in a manner that sequentially transmits a scan start signal provided in the form of an on-level pulse to a next-level circuit under the control of a clock signal, and m may be a natural number. The sub-pixel array may include a plurality of pixel sub-PXij. Each sub-pixel PXij may be connected to a corresponding data signal line and a corresponding scan signal line, and i and j may be natural numbers. The sub-pixel PXij may refer to a sub-pixel in which a transistor is connected to the i-th scan signal line and to the j-th data signal line.

[0182] Although the embodiments disclosed in the present disclosure are as above, the contents described are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any technician in the field to which the present disclosure belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the scope of patent protection of the present disclosure shall still be subject to the scope defined in the attached claims.

Claims

1. A display substrate, comprising a substrate, a driving circuit layer arranged on the substrate, and a light-emitting structure layer arranged on a side of the driving circuit layer away from the substrate, wherein the driving circuit layer comprises a transistor, the light-emitting structure layer comprises a first electrode, a pixel definition layer, an organic light-emitting layer, and a second electrode, wherein the first electrode is connected to a drain electrode of the transistor, and the organic light-emitting layer is located between the first electrode and the second electrode; The pixel definition layer includes a plurality of first retaining walls and a plurality of second retaining walls, the height of the first retaining walls is less than the height of the second retaining walls, the first retaining walls and the second retaining walls intersect to define a plurality of pixel opening areas, the pixel opening areas include a first pixel opening area and a second pixel opening area, the area of ​​the first pixel opening area is greater than the area of ​​the second pixel opening area, and two adjacent first pixel opening areas and second pixel opening areas are separated by the first retaining walls; The second retaining wall extends along the second direction, a plurality of the second retaining walls are sequentially arranged along the first direction, a plurality of the first retaining walls sequentially arranged along the second direction are provided between two adjacent second retaining walls, and the first direction and the second direction intersect; The second retaining wall includes a first sub-retaining wall and a second sub-retaining wall arranged at intervals, the first sub-retaining wall has a plurality of first bending portions and a plurality of second extending portions arranged alternately, the first bending portions extend in the first direction, and the second extending portions extend in the second direction.

2. The display substrate according to claim 1, wherein: Two adjacent first bending portions of the same first sub-blocking wall, a second extension portion between two adjacent first bending portions, a second sub-blocking wall adjacent to the first sub-blocking wall, and a first blocking wall between the first sub-blocking wall and the second sub-blocking wall form a first pixel opening area; The second extending portion between two adjacent first bending portions of the same first sub-blocking wall, the second sub-blocking wall adjacent to the first sub-blocking wall, and the first blocking wall between the first sub-blocking wall and the second sub-blocking wall form a second pixel opening area.

3. The display substrate according to claim 1, wherein: The bending times and bending directions of the first bending portions of the first sub-retaining walls are the same.

4. The display substrate according to claim 1, wherein: The width of the second retaining wall along the first direction is between 1 / 3 and 2 / 3 of the width of the first bending portion along the first direction.

5. The display substrate according to claim 1, wherein: A width of the first retaining wall along the second direction is smaller than a width of the second retaining wall along the first direction.

6. The display substrate according to any one of claims 1 to 5, wherein: The first electrodes of all sub-pixels have the same width along the first direction, and the first electrodes of all sub-pixels are arranged in a matrix along the first direction and the second direction. The distances between the first electrodes in adjacent rows are equal, and the distance between the first electrode in the (2n+1)th column and the first electrode in the (2n+2)th column is greater than the distance between the first electrode in the (2n+2)th column and the first electrode in the (2n+3)th column, where n is an integer greater than or equal to 0.

7. The display substrate according to claim 6, wherein: The first pixel opening area includes a luminous area and a non-luminous area, and the second pixel opening area only includes a luminous area. The orthographic projection of the luminous area on the substrate coincides with the orthographic projection of the first electrode on the substrate, and the orthographic projection of the non-luminous area on the substrate has no overlapping area with the orthographic projection of the first electrode on the substrate.

8. The display substrate according to any one of claims 1 to 5, wherein: The first electrodes of adjacent sub-pixels have different widths along the first direction. The first electrodes of all sub-pixels are arranged in a matrix along the first direction and the second direction. The distances between the first electrodes in adjacent rows are equal, and the distances between the first electrodes in adjacent columns are equal.

9. The display substrate according to any one of claims 1 to 5, wherein: The width of the second pixel opening area along the first direction is between 1 / 3 and 2 / 3 of the width of the first pixel opening area along the first direction.

10. The display substrate according to claim 1, wherein: The height of the first retaining wall is less than or equal to 1 micrometer, and the height of the second retaining wall is 1.2 micrometers to 1.5 micrometers.

11. The display substrate according to claim 1, wherein: The material of the first retaining wall is a liquid-philic material, and the material of the second retaining wall is a liquid-repellent material.

12. A display device comprising the display substrate according to any one of claims 1 to 11.

13. A method for preparing a display substrate, comprising: forming a driving circuit layer on the substrate, wherein the driving circuit layer includes transistors; A light-emitting structure layer is formed on the driving circuit layer, wherein the light-emitting structure layer includes a first electrode, a pixel definition layer, an organic light-emitting layer, and a second electrode, wherein the first electrode is connected to the drain electrode of the transistor, and the organic light-emitting layer is located between the first electrode and the second electrode; the pixel definition layer includes a plurality of first retaining walls and a plurality of second retaining walls, wherein the height of the first retaining wall is less than the height of the second retaining wall, the first retaining wall and the second retaining wall intersect to define a plurality of pixel opening regions, wherein the pixel opening regions include a first pixel opening region and a second pixel opening region, wherein the area of ​​the first pixel opening region is greater than the area of ​​the second pixel opening region, and two adjacent first pixel opening regions and second pixel opening regions are separated by the first retaining wall; The second retaining wall extends along the second direction, and a plurality of the second retaining walls are arranged in sequence along the first direction. A plurality of the first retaining walls arranged in sequence along the second direction are provided between two adjacent second retaining walls, and the first direction and the second direction intersect; the second retaining wall includes a first sub-retaining wall and a second sub-retaining wall arranged at intervals, and the first sub-retaining wall has a plurality of first bending portions and a plurality of second extension portions arranged alternately, the first bending portion extends in the first direction, and the second extension portion extends in the second direction.

14. The preparation method according to claim 13, wherein: A light emitting structure layer is formed on the driving circuit layer, comprising: forming a first electrode pattern on the driving circuit layer; forming a pixel definition layer pattern by a single half-tone mask patterning process; Forming an organic light-emitting layer pattern by inkjet printing process, wherein during inkjet printing, the organic light-emitting layer material ink is only printed to the first pixel opening area; A second electrode pattern is formed on the organic light emitting layer.

15. The preparation method according to claim 13, wherein: A light emitting structure layer is formed on the driving circuit layer, comprising: forming a first electrode pattern on the driving circuit layer; forming a first barrier wall pattern in the pixel definition layer by a first single-tone mask patterning process; forming a second barrier wall pattern in the pixel definition layer by a second single-tone mask patterning process; Forming an organic light-emitting layer pattern by inkjet printing process, wherein during inkjet printing, the organic light-emitting layer material ink is only printed to the first pixel opening area; A second electrode pattern is formed on the organic light emitting layer.

16. The preparation method according to any one of claims 14 or 15, wherein: The organic light-emitting layer pattern is formed by an inkjet printing process, including any one or more of the following: Inkjet printing a hole injection material ink on the first pixel opening area, allowing the hole injection material ink to flow to the second pixel opening area adjacent to the first pixel opening area, drying to remove the solvent of the hole injection material ink, and then baking to form a hole injection layer pattern; Inkjet printing a hole transport material ink on the first pixel opening area, allowing the hole transport material ink to flow to a second pixel opening area adjacent to the first pixel opening area, drying to remove the solvent of the hole transport material ink, and then baking to form a hole transport layer pattern; The luminescent material ink is inkjet printed in the first pixel opening area, and the luminescent material ink flows to the second pixel opening area adjacent to the first pixel opening area, and is dried to remove the solvent of the luminescent material ink and then baked to form a luminescent layer pattern.

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