Method for manufacturing a composite substrate and composite substrate

Abstract

Provided is a composite substrate capable of improving temperature characteristics while suppressing the generation of cracks, and a method for manufacturing such a composite substrate. The method for manufacturing the composite substrate of the present invention includes: a step of preparing a substrate of a piezoelectric material having a rough surface; a step of removing a damaged layer by etching the rough surface of the substrate of the piezoelectric material by a chemical method; a step of depositing an interlayer on the rough surface of the substrate of the piezoelectric material from which the damaged layer has been removed; a step of planarizing the surface of the deposited interlayer; a step of joining the substrate of the piezoelectric material to a support substrate having a smaller coefficient of thermal expansion than the piezoelectric material via the deposited interlayer; and a step of thinning the joined substrate of the piezoelectric material. As the piezoelectric material, lithium tantalate (LT) or lithium niobate (LN) is preferable.

Description

Technical Field

[0001] This invention relates to composite substrates used as materials for surface acoustic wave devices and methods for manufacturing the same. Background Technology

[0002] In recent years, the mobile communication market, represented by smartphones, has seen a dramatic increase in communication volume. To address this, the need to increase the required bandwidth necessitates the miniaturization and high performance of various components. Lithium tantalate (LT) and lithium niobate (LN), as common piezoelectric materials, are widely used in surface acoustic wave (SAW) devices. However, while these materials possess large electromechanical coupling coefficients, enabling wide bandwidth, they also suffer from low temperature stability, causing frequency shifts due to temperature variations. This is because lithium tantalate and lithium niobate have very high coefficients of thermal expansion.

[0003] To mitigate this problem, a method has been proposed that involves bonding a material with a low coefficient of thermal expansion onto lithium tantalate (LT) or lithium niobate (LN), and then thinning the LT or LN side to a thickness of several μm to tens of μm using grinding or similar methods to obtain a composite substrate (composite wafer). Additionally, a method has been proposed to suppress the thermal expansion of LT and improve temperature characteristics by bonding a support wafer made of a low coefficient of thermal expansion material (sapphire, silicon, etc.) (see, for example, Non-Patent Literature 1). For reference, the coefficients of thermal expansion of various materials are graphically illustrated. Figure 1 .

[0004] However, this method has the following problem: by stacking a thin LT film on the support wafer, noise known as sprite is generated in the anti-resonant frequency band. This noise is generated due to reflections from the interface between the LT film and the support wafer. For example, Figure 2 An example is shown of the spectrum of the reflection coefficient (S11) in a resonator made from a composite substrate consisting of a 20 μm thick LT film stacked on a silicon substrate. Figure 2 In this context, the difference between the peaks and troughs of the spectrum is defined as the amplitude.

[0005] To address this issue, Patent Document 1 describes a method that successfully suppresses inconsistencies by using free abrasive particles to roughen the bonding surface of the LT (grinding process) and achieving a roughness of approximately 300 nm with Ra before bonding it to the support wafer via an interlayer. This method has the advantage of being able to directly utilize the roughened surfaces generated during wafer fabrication processes (dicing, grinding, polishing, etc.).

[0006] However, although the method in Patent Document 1 is extremely effective in suppressing spoofing, there is a problem of filter characteristic degradation during repeated thermal shock tests (tests that go back and forth between high and low temperature regions in a short time) which are one of the reliability tests. Figure 3 This presents an example of the results of a thermal shock test on a wafer manufactured using the method described in Patent Document 1. It is evident that after the thermal shock test, the insertion loss increased and the bandwidth narrowed compared to before the test. An investigation into the cause of this characteristic degradation revealed that cracking (fissures) extending from the rough surfaces of the LT and interlayer onto the LT film was one contributing factor. Cracks can sometimes reach the wafer surface. These cracks are caused by the significant difference in thermal expansion coefficients between LT and Si. During repeated thermal shocks, minute defects within the LT film near the interface between LT and the interlayer become cracks, ultimately affecting the characteristics.

[0007] On the other hand, by using Si, which has a low coefficient of thermal expansion, as the supporting wafer, it is difficult to give up the advantage of improving the temperature characteristics (temperature-induced property variations) of LT. It can be said that it is very difficult to balance the problem of cracking and the improvement of temperature characteristics. Existing technical documents Patent documents

[0008] Patent Document 1: Japanese Patent No. 6250856 Non-patent literature

[0009] Non-patent literature 1: Radio Wave Newspaper High Technology, November 8, 2012, "Temperature Compensation Technology for SAW-Duplexer in RF Front-End of Smartphones" Summary of the Invention The problem that the invention aims to solve

[0010] In view of these problems, the object of the present invention is to provide a composite substrate that can improve temperature characteristics while suppressing crack formation, and a method for manufacturing such a composite substrate. Methods for solving problems

[0011] To address the aforementioned issues, the method for manufacturing a composite substrate according to embodiments of the present invention includes: a step of preparing a substrate of a piezoelectric material having a rough surface; a step of removing a damaged layer by etching the rough surface of the piezoelectric material substrate using a chemical method; a step of depositing an interlayer on the rough surface of the piezoelectric material substrate where the damaged layer has been removed; a step of planarizing the surface of the deposited interlayer; a step of bonding the piezoelectric material substrate to a support substrate with a coefficient of thermal expansion smaller than that of the piezoelectric material via the deposited interlayer; and a step of thinning the bonded piezoelectric material substrate. Furthermore, lithium tantalate (LT) or lithium niobate (LN) is preferably used as the piezoelectric material. Additionally, the rough surface can be a surface with a surface roughness greater than approximately 0.03 μm in the arithmetic mean roughness Ra.

[0012] In this invention, chemical etching using a solution can be performed in the step of removing the damaged layer. Alternatively, dry etching can be performed in the step of removing the damaged layer.

[0013] In this invention, surface activation treatment can be performed on one or both of the substrate and the support substrate of the piezoelectric material before the bonding step. The surface activation treatment can be any one of ozone water treatment, UV ozone treatment, ion beam treatment, and plasma treatment.

[0014] In this invention, the interlayer may contain any one of SiO2, SiON, SiN, SiC, AlN, Al2O3, Y2O3, TiO2, Ta2O5, and ZrO2.

[0015] In this invention, during the step of thinning the piezoelectric material substrate, the substrate can be prepared by grinding and / or polishing. Alternatively, the piezoelectric material substrate can be pre-implanted with ion implantation, and thinning can be performed by peeling at the ion implantation interface during the step of thinning the substrate after bonding. In this case, the implanted ions may contain H+. + or H2 + Any one of them.

[0016] Furthermore, the composite substrate involved in the embodiments of the present invention is a composite substrate formed by bonding a piezoelectric material substrate and a support substrate with a smaller coefficient of thermal expansion than the piezoelectric material via an interlayer. In this composite substrate, the interface between the piezoelectric material substrate and the interlayer is characterized as a rough surface with the damaged layer removed; the piezoelectric material is lithium tantalate (LT) or lithium niobate (LN). Additionally, the interface between the interlayer and the support substrate is characterized as a planarized surface. It should be noted that the rough surface can be a surface with a surface roughness greater than approximately 0.03 μm in terms of arithmetic mean roughness Ra. Attached Figure Description

[0017] Figure 1It is a chart that compares the coefficients of thermal expansion of various materials. Figure 2 The spectrum represents the reflection coefficient in a resonator made from an existing composite substrate. Figure 3 This indicates the results of thermal shock tests on wafers manufactured using conventional methods. Figure 4 This shows a cross-sectional TEM image of the vicinity of the surface of an LT wafer roughened by a grinding process. Figure 5 This shows a cross-sectional TEM image of the area near the surface of the etched LT wafer. Figure 6 This is a diagram showing the steps involved in fabricating composite substrate 1. Figure 7 This is a graph showing the evaluation results of each wafer fabricated in Example 3. Detailed Implementation

[0018] The embodiments of the present invention will be described in detail below, but the present invention is not limited thereto.

[0019] To address this problem, the inventors first conducted a detailed investigation of the defects. The samples used were obtained by grinding the surface of an LT wafer with GC (green silicon carbide) 3000 abrasive grains. In cross-sectional observation, the defects were not clearly visible using conventional surface-observation SEM (scanning electron microscopy), but when observed using transmission electron microscopy (TEM), which can reveal internal crystal defects, numerous cracks were identified near the surface. The cross-sectional TEM image at this time is shown below. Figure 4 In this invention, the cracked layer is removed by chemical etching near the cracked surface without using mechanical / physical methods. This reduces the number of cracks. A TEM image of the etched cross-section is shown below. Figure 5 Furthermore, by bonding the wafers after this chemical etching, it is possible to create composite wafers that are highly resistant to thermal shock.

[0020] Reference Figure 6 The steps for fabricating the composite substrate 1 using the present invention will be described.

[0021] First, a substrate 2 of piezoelectric material with a rough surface (rough surface) 21 is prepared. Figure 6 (a)). Lithium tantalate (LT) or lithium niobate (LN) is preferred as the piezoelectric material. A rough surface refers to, for example, a surface with a surface roughness greater than approximately 0.03 μm in terms of arithmetic mean roughness Ra. A damage layer 22 exists near the rough surface 21. Next, the damage layer 22 is removed by etching the rough surface 21 of the piezoelectric material substrate using a chemical method. Figure 6(b)). At this point, etching can be either chemical etching using a solution (wet etching) or dry etching. Next, an interlayer 3 is deposited on the rough surface 21 of the piezoelectric material substrate from which the damaged layer has been removed by etching. Figure 6 (c)). The interlayer 3 may comprise any one of SiO2, SiON, SiN, SiC, AlN, Al2O3, Y2O3, TiO2, Ta2O5, and ZrO2. The interlayer 3 may be deposited with a thickness sufficient to fill the unevenness of the rough surface, more preferably with a thickness sufficient to further ensure sufficient grinding allowance. The surface of the deposited interlayer 3 becomes a rough surface mimicking the rough surface 21 of the piezoelectric substrate 2. Next, the surface of the deposited interlayer 3 is planarized to become the bonding surface 31 ( Figure 6 (d)). The planarization method is arbitrary; for example, planarization can be achieved through grinding.

[0022] Parallel to the substrate 2, which is prepared with a piezoelectric material having a sandwich layer 3 as described above, a support substrate 4 is also prepared. Figure 6 (e)). The support substrate 4 is a substrate made of a material with a smaller coefficient of thermal expansion than the piezoelectric material (LT or LN), such as Si, sapphire, glass, quartz, etc.

[0023] Next, the prepared piezoelectric material substrate 2 and the support substrate 4 are bonded together through the interlayer 3 of substrate 2. Figure 6 (f)). Preferably, before bonding, surface activation treatment is performed on either or both of the piezoelectric material substrate 2 and the support substrate 4. The surface activation treatment can be any one of ozone water treatment, UV ozone treatment, ion beam treatment, plasma treatment, or a combination thereof.

[0024] Next, the substrate 2 of the bonded piezoelectric material is thinned to obtain the composite substrate 1. Figure 6 (g)). At this time, for example, the substrate 2 of the piezoelectric material can be thinned by grinding and / or polishing. Alternatively, H can be pre-injected into the substrate 2 of the piezoelectric material at any stage before bonding. + ions or H2 + Ion plasma is used to thin the material by peeling it off at the ion implantation interface after bonding. Example

[0025] [Example 1] The wafers, prepared in a sliced ​​state (Japanese: アズスライス, cut from an ingot into a wafer shape), were polished using GC (green silicon carbide) 3000 (#3000) abrasives. Then, chemical etching was performed to remove surface damage. The etching solution used was the HF:HNO3 = 2:3 solution described in the Spring Academic Conference Proceedings of the Chinese Society of Applied Physics, pp. 11-D5-7 (2015). Observation Figure 5 The TEM image of the etched cross-section shown indicates that tiny cracks near the surface have disappeared.

[0026] [Example 2] The wafers, prepared in a sliced ​​state (cut from an ingot into a wafer shape), were polished using GC (green silicon carbide) 3000 abrasive grains. Then, dry etching was performed to remove surface damage. The dry etching was performed using a Samco RIE-10NR dry etching apparatus, with a mixture of CF4 and O2 as the etching gas. Upon observation of the etched cross-section, similar to Example 1, it was observed that the tiny cracks present near the surface had disappeared. This demonstrates that the removal of the damaged layer is not limited to any chemical method.

[0027] [Example 3] Various roughening treatments were performed on the LT wafers (i.e., slicing, grinding wheel #1700, grinding wheel #4000, GC#1000, GC#2500, and GC#4000). The wafers were fabricated by etching for 0, 2, 4, or 6 hours as described in Example 1. After cleaning each wafer, a SiO2 film of approximately 6 μm was formed using chemical vapor deposition (CVD). Following heat treatment at 300°C, the surface was polished to approximately 3–4 μm for mirror finishing. The resulting wafers were then bonded to a silicon wafer serving as a support wafer after plasma activation. Finally, after heat treatment at 120°C, the LT wafer side was ground. · The LT (thickness layer) was thinned to 10 μm by grinding. Each wafer obtained was then subjected to 300 thermal shock tests ranging from -50°C to 135°C. During the thermal shock tests, the residence time at each temperature was 10 minutes. The transition time at each temperature was approximately 15 seconds. The number of defects was then visually counted from the LT side under a spotlight. Furthermore, cracks that elongate to the surface appear as bright spots under the spotlight, allowing for visual evaluation. The evaluation results for each wafer are shown below. Figure 7 . The results show that etching can reduce defects caused by cracks. Furthermore, it is known that the greater the roughness before etching, the longer the etching process is required to eliminate defects.

[0028] [Example 4] Various roughening treatments were applied to the LT wafers (i.e., slicing, grinding wheel #1500, grinding wheel #4000, GC#1000, GC#3000, and GC#4000). Wafers were fabricated using the etching process of Example 2, with etching times of 0, 10, 20, or 40 minutes for each grade. After cleaning, a SiO2 film of approximately 6 μm was formed using chemical vapor deposition (CVD). Next, after heat treatment at 300°C, the surface was polished to approximately 3–4 μm for mirror finishing. The resulting wafers were then bonded to a silicon wafer serving as a support wafer after plasma activation. Following heat treatment at 120°C, the LT wafer side was ground and polished to thin the LT to 10 μm. Each resulting wafer was subjected to 300 thermal shock tests ranging from -50°C to 135°C. During the thermal shock tests, the residence time at each temperature was 10 minutes. Furthermore, the transition time for each temperature was approximately 15 seconds. Then, the number of defects was counted visually from the LT side under a spotlight. Additionally, cracks that elongate to the surface appear as bright spots under the spotlight, allowing for visual evaluation. Results and Figure 7 The results were largely the same, indicating that removing the damaged layer using chemical methods could improve the properties.

[0029] [Example 5] Various roughening treatments were applied to the LT wafer (grinding wheel #1500, grinding wheel #4000, GC#1000, GC#3000, and GC#4000). Wafers from Example 1, etched for 0, 2, 4, or 6 hours at various levels, were fabricated. After cleaning, a film of approximately 6 μm was formed using physicochemical vapor deposition (PVD) of any one of SiO2, SiON, SiN, SiC, AlN, Al2O3, Y2O3, TiO2, Ta2O5, and ZrO2. Following heat treatment at 300°C, the surface was polished to approximately 3–4 μm for mirror finishing. The resulting wafer was then bonded to a silicon wafer serving as a support wafer after plasma activation. Finally, after heat treatment at 120°C, the LT wafer side was ground and polished to thin the LT to 10 μm. Each wafer obtained in this way was subjected to 300 thermal shock tests ranging from 50°C to 135°C. During the thermal shock tests, the residence time at each temperature was 10 minutes. Additionally, the transition time at each temperature was approximately 15 seconds. Then, the number of defects was counted starting from the LT side under a spotlight. The results were identical to those of Example 3. These results demonstrate that this method is independent of the type of interlayer or the film formation method.

[0030] [Example 6] The support wafer was changed to sapphire, glass, and quartz, and the wafer was fabricated and evaluated under the same conditions as in Example 3. This also showed the same tendency as in Example 3. That is, by performing etching, defects caused by cracks can be reduced; the greater the roughness before etching, the longer the etching process time required to eliminate defects. Therefore, this method is independent of the support wafer.

[0031] Based on the above-described embodiments and examples, it can be seen that the manufacturing method of the present invention can produce a composite substrate that can suppress crack generation and improve temperature characteristics.

[0032] The above-described embodiments and examples are merely illustrative. Any invention that has a substantially identical structure to the technical concept described in the claims of this invention and can achieve the same effect can be included within the technical scope of this invention. Symbol Explanation

[0033] 1 Composite substrate 2 substrate 3. Mezzanine 4 Support base plate.

Claims

1. A method for manufacturing a composite substrate, comprising: The step of preparing a substrate of a piezoelectric material with a rough surface, wherein the rough surface is a surface with a surface roughness greater than 0.03 μm in terms of arithmetic mean roughness Ra; The step of removing the damaged layer by etching the rough surface of the substrate of the piezoelectric material by chemical method, wherein the damaged layer is a layer with cracks formed near the surface; The step of depositing an interlayer on the rough surface of the piezoelectric material substrate after the damaged layer has been removed; The step of planarizing the surface of the deposited interlayer; The step of bonding the substrate of the piezoelectric material to a support substrate with a smaller coefficient of thermal expansion than the piezoelectric material through the deposited interlayer; as well as The step of thinning the substrate of the piezoelectric material after bonding. The piezoelectric material is lithium tantalate LT or lithium niobate LN.

2. The method for manufacturing a composite substrate according to claim 1, characterized in that, In the step of removing the damaged layer, chemical etching is performed using a solution.

3. The method for manufacturing a composite substrate according to claim 1, characterized in that, In the step of removing the damaged layer, dry etching is performed.

4. The method for manufacturing the composite substrate according to any one of claims 1 to 3, characterized in that, Prior to the bonding step, surface activation treatment is performed on one or both of the substrate of the piezoelectric material and the support substrate.

5. The method for manufacturing a composite substrate according to claim 4, characterized in that, Surface activation treatment can be any one of ozone water treatment, UV ozone treatment, ion beam treatment, or plasma treatment.

6. The method for manufacturing a composite substrate according to claim 1, characterized in that, The interlayer contains any one of SiO2, SiON, SiN, SiC, AlN, Al2O3, Y2O3, TiO2, Ta2O5, and ZrO2.

7. The method for manufacturing a composite substrate according to any one of claims 1 to 6, characterized in that, In the step of thinning the substrate of the piezoelectric material, the substrate of the piezoelectric material is ground and / or polished.

8. The method for manufacturing a composite substrate according to any one of claims 1 to 6, characterized in that, In the step of pre-implanting the substrate of the piezoelectric material with ion implantation and thinning the substrate of the piezoelectric material after bonding, peeling is performed at the ion implantation interface to achieve thinning.

9. The method for manufacturing a composite substrate according to claim 8, characterized in that, The injected ions contain H + or H2 + Any one of them.

10. A composite substrate, characterized in that, It is a composite substrate formed by bonding a piezoelectric material substrate and a support substrate with a smaller coefficient of thermal expansion than the piezoelectric material through an interlayer. The interface between the piezoelectric material substrate and the interlayer is a rough surface where a damaged layer has been removed by chemically etching the rough surface of the piezoelectric material substrate. The damaged layer is a layer with cracks forming near the surface, and the rough surface is a surface with a surface roughness greater than 0.03 μm, expressed as an arithmetic mean roughness Ra. The substrate of the piezoelectric material is thinned after lamination. The piezoelectric material is lithium tantalate LT or lithium niobate LN.

11. The composite substrate according to claim 10, characterized in that, The interface between the interlayer and the supporting substrate is a planarized surface.

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