半导体存储装置
By configuring bit line selection circuits within the memory cell array and employing a multi-layer wiring structure and current sensing method, the miniaturization and coupling effects of bit line selection circuits in NAND flash memory are solved, achieving high integration and improved reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WINBOND ELECTRONICS CORP
- Filing Date
- 2022-06-10
- Publication Date
- 2026-07-17
AI Technical Summary
In NAND flash memory, with the development of high integration, miniaturization of bit line selection circuits has become an important issue. Existing technologies cannot effectively suppress the effects of floating gate coupling between memory cells or coupling between bit lines, leading to read noise and reliability problems.
A bit line selection circuit is configured within the memory cell array. By selecting a bit line pair consisting of an even-numbered bit line and an odd-numbered bit line, and using adjacent non-selected bit line pairs to shield the selected bit line pair, the effects of floating gate coupling and inter-bit line coupling are reduced. A multi-layer wiring structure and current sensing method are adopted to improve reliability.
This achieves high integration and improved reliability of semiconductor memory devices, reduces read noise, and improves the stability of memory operation.
Smart Images
Figure CN115497538B_ABST