Method of operating memory, memory and storage system

Abstract

The application provides a memory, an operating method of the memory and a storage system. The memory comprises a memory cell array, the memory cell array comprising a plurality of memory cell rows coupled to a plurality of word lines and a plurality of memory strings coupled to a plurality of bit lines, the memory string comprising a plurality of memory cells connected in series; the operating method comprises: in a programming phase, providing a programming voltage to a selected word line; in a first time period after the programming phase, providing a first word line voltage lower than the programming voltage to the selected word line; in a second time period, providing a second word line voltage lower than the first word line voltage to the selected word line; wherein the second word line voltage can make the memory cells coupled to the selected word line conductive. The time required for the high programming voltage on the selected word line to drop at the end of the programming operation is utilized, and the difference in the channel potential of the memory string after the programming operation is reduced in a shorter time.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more specifically, to memory, memory operation methods, and memory systems. Background Technology

[0002] Semiconductor memories can include volatile and non-volatile memories. Non-volatile memories can include flash memory, electrically erasable and programmable read-only memory (EEPROM), ferroelectric memory (FRAM), etc. Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory can include NOR flash memory and NAND flash memory. Various operations can be performed on flash memory, such as reading, programming (writing), and erasing. Summary of the Invention

[0003] This application provides a method for operating a memory, the memory comprising: a memory cell array, the memory cell array including multiple rows of memory cells coupled to multiple word lines and multiple memory strings coupled to multiple bit lines, the memory strings including multiple memory cells connected in series; the operation method comprising: during a programming phase, providing a programming voltage to a selected word line among the multiple word lines to program selected memory cells coupled to the selected word line; during a first time period after the programming phase, providing a first word line voltage lower than the programming voltage to the selected word line; and during a second time period after the first time period, providing a second word line voltage lower than the first word line voltage to the selected word line; wherein the second word line voltage enables memory cells coupled to the selected word line to conduct.

[0004] Optionally, during the programming phase, a voltage is provided to a non-selected word line among the plurality of word lines; during the second time period, a third word line voltage is provided to the non-selected word line; wherein the third word line voltage turns on the memory cell coupled to the non-selected word line.

[0005] Optionally, the second word line voltage is equal to the third word line voltage.

[0006] Optionally, the first word line voltage is equal to the through voltage.

[0007] Optionally, the memory further includes multiple source lines coupled to the multiple memory strings; each memory string includes at least one source select transistor; during the second time period, a first select voltage is provided to the source select line coupled to the source select transistor to enable the source select transistor; during the second time period, a source line voltage is provided to the source line; wherein the source line voltage is a ground voltage.

[0008] Optionally, the memory string includes at least one drain select transistor; during the second time period, a second select voltage is provided to the drain select line coupled to the drain select transistor to turn on the drain select transistor; during the second time period, a bit line voltage is provided to the bit line; wherein the bit line voltage is a ground voltage.

[0009] Optionally, the first selection voltage is equal to the second word line voltage.

[0010] Optionally, the second selection voltage is equal to the second word line voltage.

[0011] Optionally, in a third time period following the second time period, a fourth word line voltage lower than the second word line voltage is provided to the selected word line and the unselected word line; in the third time period, the first selection voltage is provided to the source selection line to turn on the indicated source selection transistor.

[0012] Optionally, during the third time period, the second selection voltage is provided to the drain selection line to turn on the drain selection transistor.

[0013] Optionally, the memory string has at least one drain select transistor; in a fourth time period following the third time period, the fourth word line voltage is provided to the source select line and the drain select line coupled to the drain select transistor.

[0014] Optionally, the memory string includes at least one source select transistor and at least one drain select transistor; during the first time period, a third select voltage is provided to the source select line coupled to the source select transistor, and a fourth select voltage is provided to the drain select line coupled to the drain select transistor of the unselected memory string, to turn off the source select transistor and the drain select transistor of the unselected memory string.

[0015] Optionally, the programming voltage is used for single-level cell (SLC) programming operations.

[0016] In another aspect, this application provides a memory comprising: a memory cell array including a plurality of memory cell rows coupled to a plurality of word lines and a plurality of memory strings coupled to a plurality of bit lines, the memory strings including a plurality of memory cells connected in series; and peripheral circuitry configured to: during a programming phase, provide a programming voltage to a selected word line among the plurality of word lines to program a selected memory cell coupled to the selected word line; during a first time period after the programming phase, provide a first word line voltage lower than the programming voltage to the selected word line; and during a second time period after the first time period, provide a second word line voltage lower than the first word line voltage to the selected word line; wherein the second word line voltage enables a memory cell coupled to the selected word line to conduct.

[0017] Optionally, the peripheral circuitry is further configured to: provide a pass voltage to a non-selected word line among the plurality of word lines during the programming phase; and provide a third word line voltage to the non-selected word line during the second time period; wherein the third word line voltage turns on the memory cell coupled to the non-selected word line.

[0018] Optionally, the second word line voltage is equal to the third word line voltage.

[0019] Optionally, the first word line voltage is equal to the through voltage.

[0020] Optionally, the memory further includes multiple source lines coupled to the multiple memory strings; the memory string includes at least one source selection transistor; the peripheral circuitry is further configured to: provide a first selection voltage to the source selection line coupled to the source selection transistor during the second time period to enable the source selection transistor; and provide a source line voltage to the source line during the second time period; wherein the source line voltage is a ground voltage.

[0021] Optionally, the memory string includes at least one drain select transistor; the peripheral circuitry is further configured to: during the second time period, provide a second select voltage to the drain select line coupled to the drain select transistor to turn on the drain select transistor; and during the second time period, provide a bit line voltage to the bit line; wherein the bit line voltage is a ground voltage.

[0022] Optionally, the first selection voltage is equal to the second word line voltage.

[0023] Optionally, the second selection voltage is equal to the second word line voltage.

[0024] Optionally, the peripheral circuit is further configured to: provide a fourth word line voltage lower than the second word line voltage to the selected word line and the unselected word line during a third time period following the second time period; and provide the first selection voltage to the source selection line during the third time period to turn on the indicated source selection transistor.

[0025] Optionally, the peripheral circuit is configured to provide the second selection voltage to the drain selection line during the third time period to turn on the drain selection transistor.

[0026] Optionally, the memory string includes at least one drain select transistor; the peripheral circuitry is further configured to provide the fourth word line voltage to the source select line and the drain select line coupled to the drain select transistor in a fourth time period following the third time period.

[0027] Optionally, the memory string includes at least one source select transistor and at least one drain select transistor; the peripheral circuitry is configured to: during the first time period, provide a third select voltage to the source select line coupled to the source select transistor, and provide a fourth select voltage to the drain select line coupled to the drain select transistor of the unselected memory string, to turn off the source select transistor and the drain select transistor of the unselected memory string.

[0028] Optionally, the programming voltage is used for single-level cell (SLC) programming operations.

[0029] In another aspect of this application, a storage system is provided, including at least one memory as provided above, and a memory controller coupled to the memory and configured to control the memory.

[0030] This application provides a memory, a method for operating the memory, and a storage system. By providing a first word line voltage lower than the programming voltage to a selected word line during a first time period after the programming phase, and then providing a second word line voltage lower than the first word line voltage to the selected word line during a second time period after the first time period, the difference in channel potential between the selected and non-selected memory strings is reduced in a shorter time by utilizing the time required for the high programming voltage on the selected word line to drop at the end of the programming operation. This increases the accuracy and stability of performing other operations (e.g., read operations) after the programming operation. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of a storage device including peripheral circuitry provided in an embodiment of this application.

[0033] Figure 2 This is a schematic diagram of the structure of a storage array provided in an embodiment of this application;

[0034] Figure 3 This is a schematic diagram of the structure of a memory provided in an embodiment of this application;

[0035] Figure 4 This is an operation timing diagram of a single-level cell (SLC) programming operation provided in an embodiment of this application;

[0036] Figure 5 This is an operation timing diagram of another single-level unit SLC programming operation provided in an embodiment of this application;

[0037] Figure 6 This is an operation timing diagram of another single-level unit SLC programming operation provided in the embodiments of this application;

[0038] Figure 7 This is a schematic diagram of a word line voltage applied to a selected word line during a programming operation, as provided in an embodiment of this application.

[0039] Figure 8 This is an operation timing diagram of a memory provided in an embodiment of this application;

[0040] Figure 9 This is a flowchart of a memory operation method provided in an embodiment of this application;

[0041] Figure 10 This is an operation timing diagram of another memory provided in an embodiment of this application;

[0042] Figure 11 This is a flowchart of another memory operation method provided in an embodiment of this application.

[0043] Figure 12 This is a schematic diagram of the structure of a storage system provided in an embodiment of this application;

[0044] Figure 13A This is a schematic diagram of a memory card provided in an embodiment of this application;

[0045] Figure 13B This is a schematic diagram of a solid-state driver provided in an embodiment of this application; Detailed Implementation

[0046] Although specific constructions and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Thus, other constructions and arrangements may be used without departing from the scope of this application. Furthermore, it is obvious that this application can also be used for various other applications. The functional and structural features described in this application can be combined, adjusted, and modified with each other, as well as combined, adjusted, and modified in ways not specifically depicted in the drawings, such combinations, adjustments, and modifications are within the scope of this application.

[0047] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a," "the," or "the" can also be understood to convey either a singular or a plural usage. Additionally, also depending at least in part on the context, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and alternatively, it can allow for the presence of additional factors that are not necessarily explicitly described.

[0048] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0049] Figure 1 A schematic circuit diagram of an exemplary storage device 100 including peripheral circuitry according to some aspects of this application is shown. The storage device 100 may include a storage cell array 101 and peripheral circuitry 102 coupled to the storage cell array 101. The storage cell array 101 may be a flash memory storage cell array in which storage cells 106 are arranged in the form of an array of storage strings 108. In some embodiments, each storage string 108 includes a plurality of storage cells 106 that are series-coupled and vertically stacked.

[0050] In some implementations, each memory cell 106 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 106 is capable of storing more than a single bit of data in more than two memory states. For example, a multi-level cell (MLC) may store two bits of data per cell, a triple-level cell (TLC) may store three bits of data per cell, or a quad-level cell (QLC) may store four bits of data per cell.

[0051] like Figure 1 As shown, each memory string 108 may include a source select gate (SSG) transistor 110 (also referred to as a source select transistor) at its source end and a drain select gate (DSG) transistor 112 (also referred to as a drain select transistor) at its drain end. The SSG transistor 110 and DSG transistor 112 may be configured to activate the selected memory string 108 during read and program operations. In some embodiments, multiple memory strings 108 may be organized into multiple blocks 104, with the sources of memory strings 108 in the same block 104 coupled via the same source line (SL) 114. According to some embodiments, the DSG transistor 112 of each memory string 108 is coupled to a corresponding bit line 116. In some implementations, each memory string 108 is configured to be selected or deselected by applying a DSG select voltage or DSG deselect voltage to the gate of the corresponding DSG transistor 112 via one or more DSG lines 113 and / or by applying a select voltage or deselect voltage to the gate of the corresponding SSG transistor 110 via one or more SSG lines 115.

[0052] like Figure 1As shown, multiple memory strings 108 can be organized into multiple blocks 104. In some implementations, each block 104 is the basic data unit for erase operations, i.e., all memory cells 106 on the same block 104 are erased simultaneously. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at any suitable number of blocks or any suitable fraction of blocks. Memory cells 106 of adjacent memory strings 108 can be coupled via word lines 118, which select which row of memory cells 106 is affected by read and program operations.

[0053] like Figure 1 As shown, the memory cell array 101 may include an array of memory cells 106 in multiple rows and columns within each block 104. According to some embodiments, a row of memory cells 106 corresponds to one or more pages, and a column of memory cells corresponds to a memory string 108. Multiple rows of memory cells 106 may be coupled to word lines 118, and multiple columns of memory cells 106 may be coupled to bit lines 116.

[0054] Figure 2 A partial side view of a cross-section of an exemplary memory cell array 101 including memory strings 108, according to some aspects of this application, is shown. Figure 2 As shown, the memory string 108 may extend vertically through the stacked structure 204 above the substrate 202. The substrate 202 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0055] The stacked structure 204 may include alternating conductive layers 206 and dielectric layers 208. The number of pairs of conductive layers 206 and dielectric layers 208 in the stacked structure 204 determines the number of memory cells 106 in the memory cell array 101. The conductive layers 206 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, each conductive layer 206 includes a metal layer, such as a tungsten layer. In some embodiments, each conductive layer 206 includes a doped polysilicon layer. The conductive layers 206 may include multiple word lines 118, at least one DSG line 113, and at least one SSG line 115. The conductive layer 206 may include the control gate terminal of the memory cell 106, the gate terminal of the DSG transistor 112, or the gate terminal of the SSG transistor 110, and may extend laterally as the DSG line 113 in the upper part of the stacked structure 204, the SSG line 115 in the lower part of the stacked structure 204, or the word line 118 between the DSG line 113 and the SSG line 115. It should be understood that, although in Figure 2 The diagram shows one SSG line 115 and one DSG line 113, but in other examples, the number of SSG lines 115 and the number of DSG lines 113 (as well as the number of SSG transistors 110 and DSG transistors 112 coupled to SSG lines 115 and 113 respectively) can vary.

[0056] Return to reference Figure 1 The peripheral circuitry 102 can be coupled to the memory cell array 101 via bit line 116, word line 118, source line 114, SSG line 115, and DSG line 113. The peripheral circuitry 102 can include any suitable analog, digital, and mixed-signal circuitry for operating the memory cell array 101 by applying voltage and / or current signals to each target memory cell 106 via bit line 116, word line 118, source line 114, SSG line 115, and DSG line 113, and by sensing voltage and / or current signals from each target memory cell 106. The peripheral circuitry 102 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 3 Some exemplary peripheral circuitry is shown. Peripheral circuitry 102 includes a page buffer 304, a column decoder 306, a row decoder 308, a voltage generator 310, a control logic unit 312, a register 314, and input / output (I / O) circuitry 316. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 3 Additional peripheral circuitry not shown.

[0057] Page buffer 304 can be connected to memory cell array 101 via bit line 106 and is configured to read data from and program (write) data to memory cell array 101 according to control signals from control logic unit 312. In one example, page buffer 304 can store a page of programming data (write data) to be programmed into memory cell array 101. In another example, page buffer 304 can sense signals from bit line 116 to verify that data has been correctly programmed into target memory cell 106 coupled to selected word line 118. In yet another example, during a read operation, page buffer 304 can also sense low-power signals from bit line 116 representing data bits stored in memory cell 106 and amplify small voltage swings to a recognizable logic level. Column decoder 306 can be configured to be controlled by control logic unit 312 and to select one or more memory strings 108 by applying bit line voltages generated from voltage generator 310.

[0058] The row decoder 308 can be connected to the memory cell array 101 via word lines and can select word lines based on row addresses. The row decoder 308 can be configured to be controlled by the control logic unit 312 according to control signals, and to select / deselect block 104 of the memory cell array 101 and select / deselect selected rows of block 104. The row decoder 308 can also be configured to provide word line voltages generated from the voltage generator 310 to word lines 118. In some embodiments, the row decoder 308 can also provide SSG and DSG voltages generated from the voltage generator 310 to drive SSG lines 115 and DSG lines 113.

[0059] The voltage generator 310 can be configured to be controlled by the control logic unit 312 and generate various voltages provided to the memory cell array 101, such as word line voltages (e.g., read voltage, programming voltage, pass voltage, verification voltage, etc.), SSG voltage (select / deselect voltage), DSG voltage (select / deselect voltage), bit line voltage, and source line voltage, etc.

[0060] Control logic unit 312 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 314 can be coupled to control logic unit 312 and includes a status register, a command register, and an address register for storing status information, command opcodes, and command addresses for controlling the operation of each peripheral circuit.

[0061] Input / output circuitry 316 can be coupled to control logic unit 312 and acts as a control buffer to buffer control commands received from memory controller and relay them to control logic unit 312, as well as to buffer status information received from control logic unit 312 and relay it to memory controller. Input / output circuitry 316 can also be coupled to column decoder 306 and acts as a data input / output interface and data buffer to buffer data and relay it to or from memory cell array 101.

[0062] Figure 4 This diagram illustrates an operational timing diagram of a single-level cell (SLC) programming operation according to an embodiment of this application. In some embodiments of this application, the single-level cell (SLC) programming operation may include a first programming stage (PGM), a verification stage (VFY), and a second programming stage (PGM). During the programming stage, a programming voltage is applied to a selected word line (selWL) among multiple word lines. The selected word line (selWL) is coupled to a selected memory cell in the memory cell array. The selected memory cell is the memory cell that needs to be programmed during the programming stage. In some embodiments, the voltage applied to the selected word line (selWL) during the first programming stage is no greater than the voltage applied to the selected word line (selWL) during the second programming stage. During the programming stage, a pass voltage is applied to a non-selected word line (unselWL) among the multiple word lines. The pass voltage can be used to prevent programming interference during the programming operation. In some embodiments, the pass voltage is less than the programming voltage. During the programming stage, a third selection voltage (Vsel3) is provided to the source select line (GSL) to turn off the source select transistor. A fourth selection voltage, Vsel4, is provided to the unselected drain select line, unsel SSL, to turn off the selected drain select transistor coupled to the unselected memory cell. A fifth selection voltage, Vsel5, is provided to the selected drain select line, sel SSL, to turn on the selected drain select transistor.

[0063] During the verification phase, a verification voltage is applied to a selected word line (sel WL) among multiple word lines. An on-state voltage is applied to a non-selected word line (unsel WL) among the multiple word lines, and the non-selected memory cell coupled to the non-selected word line is turned on. A first source select voltage is provided to the source select line (GSL), and the source select transistor is turned on. A first drain select voltage is provided to the selected drain select line (sel SSL), and the selected drain select transistor coupled to the selected memory cell is turned on. A first drain select voltage is provided to an unselected drain select line (unsel SSL), and the unselected drain select transistor is turned on.

[0064] The programming voltage, pass voltage, and verification voltage can be generated by the voltage generator 310 and provided to the memory cell array under the control of the control logic unit 312.

[0065] Figure 5 This is an operation timing diagram of another single-level cell (SLC) programming operation provided in an embodiment of this application. In some embodiments of this application, the single-level cell (SLC) programming operation may include a programming phase PGM and a verification phase VFY. The voltages provided to the selected word line sel WL, the unselected word line unsel WL, the source selection line GSL, and the drain selection line SSL during the programming and verification phases can be referred to the relevant descriptions of single-level cell (SLC) in the above embodiments, and will not be repeated here.

[0066] Figure 6 This is an operation timing diagram of another single-level cell (SLC) programming operation provided in the embodiments of this application. In some embodiments of this application, the single-level cell (SLC) programming operation may include a programming stage PGM. The voltages provided to the selected word line sel WL, the unselected word line unsel WL, the source selection line GSL, and the drain selection line SSL during the programming stage can be referred to the relevant descriptions of the single-level cell (SLC) in the above embodiments, and will not be repeated here.

[0067] Figure 7 This is a schematic diagram illustrating the word line voltage applied to a selected word line during a programming operation according to an embodiment of this application. In some embodiments of this application, the memory programming operation may include a cycle of one or more programming and verification phases. In each programming / verification phase cycle, an incremental programming voltage is applied to the selected word line to program the selected memory cell, and then a verification voltage is applied to the selected word line to verify the selected memory cell. The programming and verification phases can continue until the selected memory cell reaches the desired programming state, at which point the programming operation is complete. The programming operation may end with either a programming phase or a verification phase.

[0068] In some of the above embodiments, the programming process includes a programming phase. During the programming phase, to reduce programming interference to unselected memory cells coupled to the selected word line, the unselected memory string containing the corresponding unselected memory cells is made to reach a higher channel potential. In some embodiments, the voltage difference between the selected word line and the channel potential of the unselected memory string is not greater than a critical voltage that enables programming of the memory cells.

[0069] Figure 8 and Figure 9 This application provides an embodiment of a memory operation method. Figure 8 The diagram shows the operation timing of a memory according to an embodiment of this application. Figure 9A flowchart illustrating an operation method of a memory according to an embodiment of this application is shown. The memory can be any suitable memory disclosed in this application, such as memory 100. The operation method can be implemented by peripheral circuitry 102.

[0070] like Figure 8 and Figure 9 In some embodiments shown, the final stage of the programming operation is a programming stage, in which a programming voltage is provided to a selected word line among multiple word lines to program selected memory cells coupled to the selected word line. During the programming stage, a through voltage is provided to a non-selected word line among multiple word lines, a third selection voltage Vsel3 is provided to the source select line coupled to the source select transistor, a fourth selection voltage Vsel4 is provided to the drain select line coupled to the drain select transistor of the selected memory string, and a fifth selection voltage Vsel5 is provided to the drain select line coupled to the drain select transistor of the non-selected memory string. The through voltage is less than the programming voltage. During the programming stage, the drain select transistor of the selected memory string is turned on, and the source select transistor and the drain select transistor of the non-selected memory string are turned off.

[0071] In a first time period after the programming operation ends, a first word line voltage Vwl1 lower than the programming voltage is provided to the selected word line. During this first time period, the voltage on the selected word line decreases from the programming voltage to the first word line voltage Vwl1. In some embodiments, the line decoder 308 can be configured to discharge the selected word line from the programming voltage to the first word line voltage Vwl1 during the first time period. In some embodiments, the first word line voltage Vwl1 is less than a threshold voltage that allows the memory cell to be programmed, thereby reducing misprogramming of unselected memory cells coupled to the selected word line in the next stage. In some embodiments, the first word line voltage Vwl1 may be equal to the pass voltage applied to the unselected word line during the programming stage. The pass voltage satisfies the requirement of not programming the coupled memory cell and is a commonly used voltage in the peripheral circuitry, making adjustment more convenient. During the first time period, a pass voltage is provided to the unselected word line. Providing a first word line voltage Vwl1 equal to the pass voltage to the selected word line ensures that the voltage provided to the word line is of the same magnitude, improving the uniformity of channel potential adjustment in the next stage.

[0072] During a first time period, a third selection voltage Vsel3 is provided to the source select line coupled to the source select transistor to turn off the source select transistor. During the first time period, a fourth selection voltage Vsel4 is provided to the drain select line coupled to the drain select transistor of the unselected memory string to turn off the drain select transistor of the unselected memory string. In some embodiments, the voltage states on the source select line and the drain select line can be kept unchanged. Keeping the source select transistor and the drain select transistor of the unselected memory string off during the first time period can reduce misprogramming of unselected memory cells coupled to the selected word line.

[0073] In a second time period following the first time period, a second word line voltage Vwl2, lower than the first word line voltage Vwl1, is provided to the selected word line. The second word line voltage Vwl2 enables the memory cell coupled to the selected word line to conduct. In some embodiments, the second word line voltage Vwl2 may be greater than the threshold voltage corresponding to the highest programming state of the memory cell. In the second time period, the voltage on the selected word line decreases from the first word line voltage Vwl1 to the second word line voltage Vwl2. In some embodiments, the line decoder 308 may be configured to discharge the selected word line from the first word line voltage Vwl1 to the second word line voltage Vwl2 during the second time period.

[0074] In the second time period, a third word line voltage Vwl3 is provided to the unselected word line. The third word line voltage Vwl3 enables the memory cell coupled to the unselected word line to conduct. In some embodiments, the third word line voltage Vwl3 may be greater than the threshold voltage corresponding to the highest programming state of the memory cell. In some embodiments, the third word line voltage Vwl3 is less than the pass voltage, and in the second time period, the voltage on the unselected word line decreases from the pass voltage to the third word line voltage Vwl3. The line decoder 308 can be configured to discharge the unselected word line from the pass voltage to the third word line voltage Vwl3 in the second time period. In some embodiments, the third word line voltage Vwl3 may be equal to the pass voltage. In the second time period, the voltage on the unselected word line is the same as in the first time period, and the unselected word line is not discharged.

[0075] In some embodiments, the second word line voltage Vwl2 can be equal to the third word line voltage Vwl3, which can improve the convenience of peripheral circuit control. Providing the same voltage to both selected and unselected word lines in the second time period can also reduce the coupling effect between word lines.

[0076] During the second time period, a first selection voltage Vsel1 is provided to the source selection line coupled to the source selection transistor to turn on the source selection transistor. During the second time period, the voltage on the source selection line increases from a third selection voltage Vsel3 to the first selection voltage Vsel1. In some embodiments, the row decoder 308 can be configured to charge the source selection line from the third selection voltage Vsel3 to the first selection voltage Vsel1 during the second time period. In some embodiments, the first selection voltage can be equal to the second word line voltage, and the first selection voltage can be equal to the third word line voltage. This ensures that the source selection transistor is turned on while reducing the variety of voltages provided to the word line during the second time period, improving the convenience of peripheral circuit control. During the second time period, a source line voltage is provided to the source line SL. In some embodiments, the source line voltage can be ground voltage. Discharging the memory strings coupled to the source line SL reduces the channel potential of unselected memory strings, thus reducing the difference in channel potential between selected and unselected memory strings.

[0077] During the second time period, a second selection voltage Vsel2 is provided to the drain selection line coupled to the drain selection transistor to turn on the drain selection transistor. During the second time period, the voltage on the drain selection line increases from the fourth selection voltage Vsel4 / fifth selection voltage Vsel5 to the second selection voltage Vsel2. In some embodiments, the row decoder 308 can be configured to charge the drain selection line from the fourth selection voltage Vsel4 / fifth selection voltage Vsel5 to the second selection voltage Vsel2 during the second time period. In some embodiments, the second selection voltage Vsel2 can be equal to the second word line voltage Vwl2, and the second selection voltage Vsel2 can be equal to the third word line voltage Vwl3. This can improve the convenience of peripheral circuit control. During the second time period, a bit line voltage is provided to the bit line BL. In some embodiments, the bit line voltage can be ground voltage. Discharging the memory strings coupled to the bit line BL reduces the channel potential of the unselected memory strings, thereby reducing the difference in channel potential between the selected and unselected memory strings.

[0078] In the second time period, the memory string can be discharged simultaneously through both the source line and the bit line, which can better discharge the memory string, reduce the channel potential of the unselected memory string, and further reduce the difference in channel potential between the selected and unselected memory strings. In some embodiments, the difference in channel potential between the selected and unselected memory strings can be reduced by discharging only through the source line or the bit line, that is, only one of the source selection transistor and the drain selection transistor is turned on in the second time period.

[0079] As mentioned above, when the programming phase ends, the channel potential of the non-selected memory string will be higher, while the channel potential of the selected and non-selected memory strings will have a certain difference. If a read operation is performed directly after the programming operation that ends at the programming phase, the large difference in channel potential between the selected and non-selected memory strings will have a certain impact on the read operation. During the read operation, if the channel potential in the memory string is relatively high, it will lead to a larger sensing current during the read process, resulting in read deviation. In some embodiments of this application, at the end of the programming operation, the programming voltage on the selected word line is reduced to a second word line voltage that allows the memory cell to conduct without generating programming interference. The source selection transistor and / or drain selection transistor are turned on, and the memory string is discharged through the source line and / or bit line, reducing the difference in channel potential between the selected and non-selected memory strings after the programming operation that ends at the programming phase. This reduces the impact on subsequent operations (such as read operations). In the embodiments of this application, the time required for the high programming voltage on the selected word line to drop at the end of the programming operation is utilized to reduce the difference in storage string channel potential after the programming operation in a shorter time.

[0080] In a third time period following the second time period, a fourth word line voltage Vwl4, lower than the second word line voltage Vwl2, is provided to the selected word line and the unselected word line. During the third time period, the voltage on the selected word line decreases from the second word line voltage Vwl2 to the fourth word line voltage Vwl4, and the voltage on the unselected word line decreases from the third word line voltage Vwl3 to the fourth word line voltage Vwl4. In some embodiments, the line decoder 308 can be configured to discharge the selected word line from the second word line voltage Vwl2 to the fourth word line voltage Vwl4, and discharge the unselected word line from the third word line voltage Vwl3 to the fourth word line voltage Vwl4 during the third time period. In some embodiments, the fourth word line voltage can be ground. During the third time period, a first selection voltage Vsel1 is provided to the source select line, and a second selection voltage Vsel2 is provided to the drain select line, keeping the source select transistor and the drain select transistor in the ON state. When the source select transistor and drain select transistor are turned on, the voltage on the selected word line and the unselected word line drops to the fourth word line voltage Vwl4, which can reduce the impact of the word line voltage drop on the storage string channel potential.

[0081] In a fourth time period following the third time period, a sixth selection voltage Vsel6 is provided to the source select line and the drain select line. During the fourth time period, the voltages on the source select line and the drain select line decrease from the first selection voltage Vsel1 and the second selection voltage Vsel2 to the sixth selection voltage, respectively. In some embodiments, the line decoder 308 can be configured to discharge the source select line and the drain select line from the first selection voltage Vsel1 and the second selection voltage Vsel2 to the sixth selection voltage Vsel6, respectively, during the fourth time period. In some embodiments, the sixth selection voltage can be equal to the fourth word line voltage. In some embodiments, the sixth selection voltage can be ground.

[0082] Figure 10 and Figure 11 This application illustrates another method of operating a memory provided by an embodiment of the present application. Figure 10 Figure 13 is an operation timing diagram of another memory provided in an embodiment of this application. Figure 14 is a flowchart of an operation method of another memory provided in an embodiment of this application.

[0083] like Figure 10 and Figure 11 In some embodiments shown, the final stage of the programming operation is a programming stage, in which a programming voltage is provided to a selected word line among multiple word lines to program a selected memory cell coupled to the selected word line. During the programming stage, the voltages provided to the non-selected word lines, source select line, and drain select line are the same as described above; additional descriptions are omitted here to avoid redundancy.

[0084] In the first time period after the programming phase, a first word line voltage Vwl1 lower than the programming voltage is provided to the selected word line. In the first time period, a fifth word line voltage Vwl5 lower than the pass voltage is provided to the unselected word line. The voltage on the unselected word line decreases from the pass voltage to the fifth word line voltage Vwl5. Discharging the unselected word line simultaneously with discharging the selected word line, reducing its potential to the fifth word line voltage Vwl5, reduces the time required to discharge the unselected word line to the third word line voltage Vwl3 in the next phase. In some embodiments, the first word line voltage and the fifth word line voltage are equal. During the first time period, the voltage states on the source select line and drain select line are the same as described above; additional descriptions are omitted here to avoid redundancy.

[0085] In a second time period following the first time period, a second word line voltage Vwl2, lower than the first word line voltage Vwl1, is provided to the selected word line, and a third word line voltage Vwl3 is provided to the unselected word line. In some embodiments, the third word line voltage Vwl3 is less than the fifth word line voltage Vwl5, and in the second time period, the unselected word line drops from the fifth word line voltage Vwl5 to the third word line voltage Vwl3. In some embodiments, the line decoder 308 can be configured to discharge the unselected word line from the fifth word line voltage Vwl5 to the third word line voltage Vwl3 in the second time period. In some embodiments, the third word line voltage is equal to the fifth word line voltage, and in the second time period, the voltage on the unselected word line remains unchanged. In the second time period, the voltage states on the source select line and drain select line are the same as described above; additional descriptions are omitted here to avoid redundancy.

[0086] In the third time period following the second time period, the voltage states of the selected word line, non-selected word line, source select line, and drain select line are the same as described above. Additional descriptions are omitted here to avoid redundancy.

[0087] In the fourth time period following the third time period, the voltage states of the selected word line, non-selected word line, source select line, and drain select line are the same as described above. Additional descriptions are omitted here to avoid redundancy.

[0088] Figure 12 A block diagram of an exemplary system 1200 having memory according to some aspects of this application is shown. System 1200 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 12As shown, system 1200 may include a host 1208 and a storage system 1202, the storage system 1202 having one or more memories 1204 and a memory controller 1206. The host 1208 may include a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 1208 may also include a storage interface for coupling with the storage system 1202, the storage interface being configured to conform to a corresponding protocol (e.g., NVMe, PCIe, etc.), and the host 1208 may be configured to send data to or receive data from the memory 1204 via, for example, the storage interface. In addition to data, the host 1208 may also send instructions to the storage system 1202 to send data to or receive data from the memory 1204. The memory 1204 may be any memory disclosed in this application.

[0089] According to some embodiments, memory controller 1206 is coupled to memory 1204 and host 1208 and is configured to control memory 1204. Memory controller 1206 may specifically be implemented by a microprocessor, microcontroller (also known as a microcontroller unit (MCU)), central processing unit (CPU), digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), programmable logic device (PLD), state machine, gated logic unit, discrete hardware circuitry, or combinations thereof, as well as other suitable hardware, firmware, and / or software configured to perform the various functions described in detail below. Memory controller 1206 can manage data stored in storage device 1204 and communicate with host 1208 via its front-end interface. In some embodiments, memory controller 1206 is designed to operate in low duty cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some implementations, the memory controller 1206 is designed to operate in a high duty cycle environment within an SSD or embedded multi-media card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays. The memory controller 1206 can be configured to control the operation of the storage device 1204, such as read, erase, and program operations.

[0090] The memory controller 1206 can also be configured to manage various functions relating to data stored or to be stored in the storage device 1204, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 1206 is also configured to process error correction codes (ECCs) relating to data read from or written to the storage device 1204. The memory controller 1206 can also perform any other suitable functions, such as formatting the storage device 1204. The memory controller 1206 can communicate with external devices (e.g., host 1208) according to specific communication protocols. For example, the memory controller 1206 can communicate with external devices through at least one of various interface protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Peripheral Component Interconnection (PCI), PCI-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0091] The memory controller 1206 and one or more storage devices 1204 can be integrated into various types of storage systems, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the storage system 1202 can be implemented and packaged into different types of end electronic products. Figure 13AIn one example shown, the memory controller 1206 and a single storage device 1204 can be integrated into a memory card 1302. The memory card 1302 may include PC cards (Personal Computer Memory Card International Association, PCMCIA), CF cards, smart media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMC micro), SD cards (SD, mini SD, micro SD, SDHC), UFS, etc. The memory card 1302 may also include a memory card connector 1304 configured to couple the memory card 1302 to a host computer (e.g., ...). Figure 12 (Host 1208 in the middle). In such Figure 13B In another example shown, the memory controller 1206 and multiple storage devices 1204 can be integrated into the SSD 1306. The SSD 1306 may also include an SSD connector 1308 configured to couple the SSD 1306 to a host computer (e.g., ...). Figure 12 (Host 1208 in the middle).

[0092] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "at least one" means one or more, and the term "multiple" means two or more, unless otherwise expressly defined.

[0093] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. The scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for operating a memory, characterized in that, The memory includes: A storage cell array, the storage cell array comprising multiple rows of storage cells coupled to multiple word lines and multiple strings of storage cells coupled to multiple bit lines, the strings of storage cells comprising multiple storage cells connected in series; The operation method includes: During the programming phase, a programming voltage is provided to a selected word line among the plurality of word lines to program a selected memory cell coupled to the selected word line; In a first time period following the programming phase, a first word line voltage lower than the programming voltage is provided to the selected word line; In a second time period following the first time period, a second word line voltage lower than the first word line voltage is provided to the selected word line; wherein The second word line voltage can turn on the memory cell coupled to the selected word line.

2. The operating method as described in claim 1, characterized in that, During the programming phase, voltage is applied to unselected word lines among the plurality of word lines; During the second time period, a third word line voltage is provided to the unselected word line; The third word line voltage enables the memory cell coupled to the non-selected word line to conduct.

3. The operating method as described in claim 2, characterized in that, The second word line voltage is equal to the third word line voltage.

4. The operating method as described in claim 2, characterized in that, The voltage of the first word line is equal to the voltage through it.

5. The operating method as described in claim 1, characterized in that, The memory also includes multiple source-level lines, which are coupled to the multiple memory strings; The memory string includes at least one source-level selection transistor; During the second time period, a first selection voltage is provided to the source selection line coupled to the source selection transistor to turn on the source selection transistor; During the second time period, a source line voltage is provided to the source line; The source line voltage is the ground voltage.

6. The operating method as described in claim 1, characterized in that, The memory string includes at least one drain-select transistor; During the second time period, a second selection voltage is provided to the drain selection line coupled to the drain selection transistor to turn on the drain selection transistor; During the second time period, a bit line voltage is provided to the bit line; The bit line voltage is the ground voltage.

7. The operating method as described in claim 5, characterized in that, The first selected voltage is equal to the second word line voltage.

8. The operating method as described in claim 6, characterized in that, The second selection voltage is equal to the second word line voltage.

9. The operating method as described in claim 5, characterized in that, In a third time period following the second time period, a fourth word line voltage lower than the second word line voltage is provided to the selected word line and the unselected word line; During the third time period, the first selection voltage is provided to the source selection line to turn on the indicated source selection transistor.

10. The operating method as described in claim 6, characterized in that, In a third time period following the second time period, the second selection voltage is provided to the drain selection line to turn on the drain selection transistor.

11. The operating method as described in claim 9, characterized in that, The memory string includes at least one drain-select transistor; In a fourth time period following the third time period, the fourth word line voltage is provided to the source select line and the drain select line coupled to the drain select transistor.

12. The operating method as described in claim 1, characterized in that, The memory string includes at least one source-select transistor and at least one drain-select transistor; During the first time period, a third selection voltage is provided to the source select line coupled to the source select transistor, and a fourth selection voltage is provided to the drain select line coupled to the drain select transistor of the unselected memory string, so as to turn off the source select transistor and the drain select transistor of the unselected memory string.

13. The operating method as described in claim 1, characterized in that, The programming voltage is used for single-level cell (SLC) programming operations.

14. A memory comprising: A storage cell array, the storage cell array comprising multiple rows of storage cells coupled to multiple word lines and multiple strings of storage cells coupled to multiple bit lines, the strings of storage cells comprising multiple storage cells connected in series; Peripheral circuitry, wherein the peripheral circuitry is configured as follows: During the programming phase, a programming voltage is provided to a selected word line among the plurality of word lines to program a selected memory cell coupled to the selected word line; In a first time period following the programming phase, a first word line voltage lower than the programming voltage is provided to the selected word line; In a second time period following the first time period, a second word line voltage lower than the first word line voltage is provided to the selected word line; in The second word line voltage can turn on the memory cell coupled to the selected word line.

15. The memory as claimed in claim 14, characterized in that, The peripheral circuit is also configured to: During the programming phase, voltage is applied to unselected word lines among the plurality of word lines; During the second time period, a third word line voltage is provided to the unselected word line; The third word line voltage enables the memory cell coupled to the non-selected word line to conduct.

16. The memory as claimed in claim 15, characterized in that, The second word line voltage is equal to the third word line voltage.

17. The memory as claimed in claim 15, characterized in that, The voltage of the first word line is equal to the voltage through it.

18. The memory as claimed in claim 14, characterized in that, The memory also includes multiple source lines, which are coupled to the multiple memory strings; The memory string includes at least one source-level selection transistor; The peripheral circuit is also configured to: During the second time period, a first selection voltage is provided to the source selection line coupled to the source selection transistor to turn on the source selection transistor; During the second time period, a source line voltage is provided to the source line; The source line voltage is the ground voltage.

19. The memory as claimed in claim 14, characterized in that, The memory string includes at least one drain-select transistor; The peripheral circuit is also configured to: During the second time period, a second selection voltage is provided to the drain selection line coupled to the drain selection transistor to turn on the drain selection transistor; During the second time period, a bit line voltage is provided to the bit line; The bit line voltage is the ground voltage.

20. The memory as claimed in claim 18, characterized in that, The first selected voltage is equal to the second word line voltage.

21. The memory as claimed in claim 19, characterized in that, The second selection voltage is equal to the second word line voltage.

22. The memory as claimed in claim 18, characterized in that, The peripheral circuit is also configured to: In a third time period following the second time period, a fourth word line voltage lower than the second word line voltage is provided to the selected word line and the unselected word line; During the third time period, the first selection voltage is provided to the source selection line to turn on the indicated source selection transistor.

23. The memory as claimed in claim 19, characterized in that, The peripheral circuit is configured as follows: In a third time period following the second time period, the second selection voltage is provided to the drain selection line to turn on the drain selection transistor.

24. The memory as claimed in claim 22, characterized in that, The memory string includes at least one drain-select transistor; The peripheral circuit is also configured to: In a fourth time period following the third time period, the fourth word line voltage is provided to the source select line and the drain select line coupled to the drain select transistor.

25. The memory as claimed in claim 14, characterized in that, The memory string includes at least one source-select transistor and at least one drain-select transistor; The peripheral circuit is configured as follows: During the first time period, a third selection voltage is provided to the source select line coupled to the source select transistor, and a fourth selection voltage is provided to the drain select line coupled to the drain select transistor of the unselected memory string, so as to turn off the source select transistor and the drain select transistor of the unselected memory string.

26. The memory as claimed in claim 14, characterized in that, The programming voltage is used for single-level cell (SLC) programming operations.

27. A storage system, comprising: The memory as described in claims 14-26; and a memory controller, coupled to the memory and configured to control the memory.

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