Method of forming a semiconductor device structure

Abstract

Methods of forming a semiconductor element structure are described. In some embodiments, a method includes forming an interconnect structure over a substrate. Forming the interconnect structure over the semiconductor element structure includes forming a dielectric layer, followed by performing an anneal process, followed by forming one or more openings in the dielectric layer, followed by performing a first ultraviolet cure process, and followed by forming a conductive feature in the one or more openings.

Description

Technical Field

[0001] This case concerns a method for forming a semiconductor device structure. Background Technology

[0002] An integrated chip can contain billions of semiconductor elements. These semiconductor elements are formed in a front-end-of-the-line (FEOL) process and electrically interconnected in an interconnect structure formed on the integrated chip via back-end-of-the-line (BEOL) metal interconnect layers. A typical integrated chip includes multiple metal interconnect layers, including metal lines of different sizes vertically coupled to metal contacts (i.e., vias).

[0003] The manufacturing process for FEOL semiconductor devices and BEOL interconnect structures may include depositing a dielectric layer, etching the dielectric layer to form openings in the dielectric layer, filling the openings with a conductive material, forming a capping layer on the conductive material, and other operations. At least some of these operations will leave charge accumulation on the dielectric material, which can cause incomplete etching and burn-out of metal lines and / or vias.

[0004] Therefore, an improved method is needed to form semiconductor device structures. Summary of the Invention

[0005] In some embodiments, a method of forming a semiconductor element structure includes: forming an interconnect structure over a substrate, including: forming a dielectric layer; performing an annealing process after forming the dielectric layer; forming one or more openings in the dielectric layer after performing the annealing process; performing a first ultraviolet curing process after forming one or more openings; and forming a plurality of conductive features in one or more openings after performing the first ultraviolet curing process.

[0006] In some embodiments, a method of forming a semiconductor device structure includes: forming one or more semiconductor fins; forming an insulating structure to embed one or more semiconductor fins; performing an annealing process; recessing the insulating structure to form a shallow trench isolation region; removing the charge accumulated on the insulating structure by performing a first ultraviolet curing process; and forming one or more sacrificial gate structures.

[0007] In some embodiments, a method of forming a semiconductor device structure includes: forming an insulating structure over a substrate; performing a first annealing process; recessing the insulating structure; performing a first ultraviolet curing process; forming a plurality of source / drain epitaxial features over the substrate; forming a gate electrode layer over the substrate; forming a dielectric layer over the source / drain epitaxial features and the gate electrode layer; performing a second annealing process; forming one or more openings in the dielectric layer; performing a second ultraviolet curing process; and forming a plurality of conductive features in the one or more openings. Attached Figure Description

[0008] The state of this disclosure is in relation to the accompanying documents. Figure 1 The best way to understand this text is by referring to the detailed description below. Note that, according to industry standards, the features are not drawn to scale. In practice, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0009] Figures 1 to 4 This is a perspective view of a semiconductor device structure according to some embodiments;

[0010] Figures 5A to 12A It is a manufacturing process based on the AA section along some embodiments. Figure 4 Cross-sectional side views of various stages of a semiconductor device structure;

[0011] Figures 5B to 12B Manufacturing based on BB cut-off along some embodiments Figure 4 Cross-sectional side views of various stages of a semiconductor device structure;

[0012] Figures 5C to 12C Manufacturing based on CC-cutting along the line according to some embodiments Figure 4 Cross-sectional side views of various stages of a semiconductor device structure.

[0013] [Symbol Explanation]

[0014] 100: Semiconductor Component Structure

[0015] 102: Substrate

[0016] 102N: NMOS region

[0017] 102P: PMOS region

[0018] 103N: N-type well

[0019] 103P: P-type well

[0020] 104: First semiconductor layer

[0021] 106: Second semiconductor layer

[0022] 108a: Fin

[0023] 108b: Fin

[0024] 109: Top surface

[0025] 110a: Fin

[0026] 110b: Fin

[0027] 111: Top surface

[0028] 112: Insulation structure

[0029] 128: Sacrificial Gate Stack

[0030] 130: Sacrificial gate dielectric layer

[0031] 132: Sacrificial gate electrode layer

[0032] 134: Masking Structure

[0033] 140: Spacer

[0034] 149: Conical profile

[0035] 152: S / D epitaxial characteristics

[0036] 154: S / D epitaxial characteristics

[0037] 160:CESL

[0038] 162: First ILD layer

[0039] 166: Gate dielectric layer

[0040] 168n: Gate electrode layer

[0041] 168p: Gate electrode layer

[0042] 170: Silicide layer

[0043] 172: Electrical conductivity characteristics

[0044] 174: Interconnection Structure

[0045] 176: Second ILD layer

[0046] 177: Replacement of gate structure

[0047] 178: IMD layer

[0048] 179: SAC layer

[0049] 185: Conductive socket

[0050] 187: Conductive wire

[0051] 189: Conductive via

[0052] 192: Etching stop layer

[0053] 194: Overlay

[0054] AA: Line

[0055] BB: Line

[0056] CC: Line Detailed Implementation

[0057] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0058] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “above,” “top,” “upper,” and similar terms are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted similarly accordingly.

[0059] Figures 1 to 12C Various stages of manufacturing a semiconductor device structure 100 according to various embodiments of this disclosure are illustrated. Of course, for additional embodiments of the method, it is possible to [further details about the process are needed]. Figures 1 to 12C Additional operations are provided before, during, and after the processes shown, and some of the operations described below can be replaced or eliminated. The order of operations / processes is interchangeable.

[0060] Figures 1 to 4 This is a perspective view of a semiconductor device structure 100 according to some embodiments. Figure 1In this embodiment, a first semiconductor layer 104 is formed on a substrate 102. The substrate may be part of a wafer in a wafer. In some embodiments, the substrate 102 is a bulk semiconductor substrate, such as a semiconductor wafer. For example, the substrate 102 is a silicon wafer. The substrate 102 may include silicon or another basic semiconductor material such as germanium. In some other embodiments, the substrate 102 includes a compound semiconductor. The compound semiconductor may include gallium arsenide, silicon carbide, indium arsenide, indium phosphide, another suitable semiconductor material, or a combination thereof. In some embodiments, the substrate 102 is a semiconductor-on-insulator (SOI) substrate. The SOI substrate may be manufactured using a separation by implantation of oxygen (SIMOX) process, a wafer bonding process, another suitable method, or a combination thereof.

[0061] The substrate 102 may be doped with P-type or N-type impurities. For example... Figure 1 As shown, according to some embodiments, substrate 102 has a P-type metal-oxide-semiconductor region 102P (PMOS region 102P) and an N-type metal-oxide-semiconductor region 102N (NMOS region 102N) adjacent to the PMOS region 102P. Although not shown to scale in some figures, the PMOS region 102P and the NMOS region 102N are continuous substrate 102. In some embodiments of this disclosure, the PMOS region 102P is used to form a PMOS structure thereon, and the NMOS region 102N is used to form an NMOS structure thereon. In some embodiments, such as Figure 1 As shown, the N-well region 103N and the P-well region 103P are formed in the substrate 102. For example, the N-well region 103N is formed in the substrate 102 within the PMOS region 102P, while the P-well region 103P is formed in the substrate 102 within the NMOS region 102N. The P-well region 103P and the N-well region 103N can be formed by any suitable technique, for example, in some embodiments, by separate ion implantation processes. By using two different implantation masking layers (not shown), the P-well region 103P and the N-well region 103N can be formed sequentially in different ion implantation processes.

[0062] The first semiconductor layer 104 is deposited on top of the substrate 102, such as Figure 1As shown in the figure. The first semiconductor layer 104 may be made of any suitable semiconductor material, such as silicon, germanium, III-V semiconductor materials, or combinations thereof. In some embodiments, the first semiconductor layer 104 is substantially made of silicon. The first semiconductor layer 104 may be formed by epitaxial growth processes, such as metal-organic chemical vapor deposition (MOCVD), metal-organic vapor phase epitaxy (MOVPE), plasma-enhanced chemical vapor deposition (PECVD), remote plasma chemical vapor deposition (RP-CVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride vapor phase epitaxy (Cl-VPE), or any other suitable process.

[0063] exist Figure 2In this process, a portion of the first semiconductor layer 104 disposed above the N-well region 103N is removed, and a second semiconductor layer 106 is formed above the N-well region 103N and adjacent to a portion of the first semiconductor layer 104 disposed above the P-well region 103P. First, a patterned masking layer (not shown) can be formed on the portion of the first semiconductor layer 104 disposed above the P-well region 103P, exposing the portion of the first semiconductor layer 104 disposed above the N-well region 103N. Removal processes such as dry etching, wet etching, or combinations thereof can be performed to remove the portion of the first semiconductor layer 104 disposed above the N-well region 103N and expose the N-well region 103N. The removal process substantially does not affect the masking layer (not shown) formed on the portion of the first semiconductor layer 104 disposed above the P-well region 103P, which protects the portion of the first semiconductor layer 104 disposed above the P-well region 103P. Next, the second semiconductor layer 106 is formed above the exposed N-well region 103N. The second semiconductor layer 106 can be made of any suitable semiconductor material, such as silicon, germanium, III-V semiconductor materials, or combinations thereof. In some embodiments, the second semiconductor layer 106 is substantially made of silicon-germanium. The second semiconductor layer 106 can be formed using the same process as the first semiconductor layer 104. For example, the second semiconductor layer 106 can be formed on the exposed N-well region 103N using an epitaxial growth process, without forming the second semiconductor layer 106 on the mask layer (not shown) disposed on the first semiconductor layer 104. Therefore, the first semiconductor layer 104 is disposed above the P-well region 103P in the NMOS region 102N, and the second semiconductor layer 106 is disposed on the N-well region 103N in the PMOS region 102P.

[0064] A portion of the first semiconductor layer 104 can be used as a channel in a subsequently formed NMOS structure in the NMOS region 102N. A portion of the second semiconductor layer 106 can be used as a channel in a subsequently formed PMOS structure in the PMOS region 102P. In some embodiments, the NMOS structure and the PMOS structure are FinFETs. Although the embodiments described in this disclosure are described in the context of FinFETs, some implementations of this disclosure can be used in other processes and / or other devices, such as planar FETs, nanosheet channel FETs, horizontal gate all around (HGAA) FETs, vertical gate all around (VGAA) FETs, and other suitable devices.

[0065] exist Figure 3In this design, multiple fins 108a, 108b, 110a, and 110b are formed from a first semiconductor layer 104 and a second semiconductor layer 106, respectively. The fins 108a, 108b, 110a, and 110b can be patterned using any suitable method. For example, the fins 108a, 108b, 110a, and 110b can be patterned using one or more optical lithography processes (including dual patterning or multiple patterning processes). Typically, dual patterning or multiple patterning processes combine optical lithography and self-alignment processes, allowing the production of patterns with, for example, smaller pitches than patterns obtainable using a single, direct optical lithography process. For example, in one embodiment, a sacrificial layer (not shown) is formed over a substrate and patterned using an optical lithography process. Spacers (not shown) are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the substrate and form fins.

[0066] Fins 108a and 108b may each include a first semiconductor layer 104, and a portion of the first semiconductor layer 104 may be used as an NMOS channel. Each fin 108a and 108b may also include a P-well region 103P. Similarly, fins 110a and 110b may each include a second semiconductor layer 106, and a portion of the second semiconductor layer 106 may be used as a PMOS channel. Each fin 110a and 110b may also include an N-well region 103N. A mask (not shown) may be formed on the first semiconductor layer 104 and the second semiconductor layer 106, and may be retained on fins 108a-b and 110a-b.

[0067] Next, an insulating structure 112 is formed between adjacent fins 108a-b and 110a-b. The insulating structure 112 may be formed first between and above the adjacent fins 108a-b and 110a-b, thus embedding the fins 108a-b and 110a-b within the insulating structure 112. The insulating structure 112 may include oxygen-containing materials, such as silicon oxide, carbon or nitrogen-doped oxides, or fluorosilicate glass (FSG); nitrogen-containing materials, such as silicon nitride, silicon oxynitride (SiON), SiOCN, or SiCN; low-k dielectric materials (e.g., materials with a k-value lower than that of silicon dioxide); or any suitable dielectric material. The insulating structure 112 may be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD). The annealing process can be performed after the formation of the insulating structure 112 with embedded fins 108a-b and 110a-b, to improve the physical properties of the insulating structure 112, such as hardness or wet etch rate (WER). The annealing process can be a thermal annealing process performed at a temperature greater than about 600 degrees Celsius.

[0068] Next, a planarization process, such as chemical-mechanical polishing (CMP), can be performed to expose the tops of the fins 108a-b and 110a-b. In some embodiments, the planarization process exposes the top of a mask (not shown) disposed on the fins 108a-b and 110a-b. The insulating structure 112 is then recessed by removing portions of the insulating structure 112 located on both sides of each fin 108a-b and 110a-b. The recessed insulating structure 112 can be a shallow trench isolation (STI) area.

[0069] The insulating structure 112 can be recessed using any suitable removal process (such as dry etching or wet etching), which selectively removes portions of the insulating structure 112 without substantially affecting the semiconductor material of the fins 108a-b and 110a-b. As a result of the dry or wet etching process that recesses portions of the insulating structure 112, charge can accumulate on the insulating structure 112. The charge accumulated on the insulating structure 112 can lead to problems such as under-etching. Furthermore, if the charge accumulated on the insulating structure 112 is not removed, the breakdown voltage of the insulating structure 112 can be reduced, resulting in a reduced time-dependent dielectric breakdown (TDDB).

[0070] To remove the charge accumulated on the insulating structure 112, an ultraviolet (UV) curing process is performed on the semiconductor device structure 100 after the etching process of the recessed insulating structure 112. The UV curing process involves exposing the insulating structure 112 to ultraviolet light having a wavelength range of about 200 nm to about 400 nm. The processing temperature of the UV curing process ranges from about 70 degrees Celsius to about 400 degrees Celsius, and the processing pressure ranges from about 1 Torr to about 10 Torr. The UV curing time ranges from about 1 s to about 120 s. The UV curing process removes the charge accumulated on the insulating structure 112 while substantially not affecting the physical properties of the insulating structure 112 and other materials of the semiconductor device structure 100. In some embodiments, the UV curing process can be performed immediately after the etching process of the recessed insulating structure 112. In some embodiments, after the etching process of the recessed insulating structure 112, a cleaning process is performed to remove residual etchant from the insulating structure 112, and the UV curing process is performed immediately after the cleaning process. In some embodiments, the cleaning process may use solutions such as HF, high-temperature sulfur peroxide mixture (HTSPM), and ammonia plus hydrogen peroxide. In some embodiments, the UV curing process is performed after the etching process and before any subsequent deposition process.

[0071] exist Figure 4In this configuration, one or more sacrificial gate stacks 128 are formed on a portion of fins 108a-b and 110a-b. Each sacrificial gate stack 128 may include a sacrificial gate dielectric layer 130, a sacrificial gate electrode layer 132, and a masking structure 134. The sacrificial gate dielectric layer 130 may include one or more layers of dielectric material, such as SiO2, SiN, high-k dielectric material, and / or other suitable dielectric material. In some embodiments, the sacrificial gate dielectric layer 130 may be deposited using CVD, sub-atmospheric CVD (SACVD), FCVD, ALD, PVD, or other suitable processes. The sacrificial gate electrode layer 132 may include polysilicon (polysilicon). The masking structure 134 may include an oxygen-containing layer and a nitrogen-containing layer. In some embodiments, the sacrificial gate electrode layer 132 and the mask structure 134 are formed by various processes such as layer deposition, for example, CVD (including LPCVD and PECVD), PVD, ALD, thermal oxidation, electron beam evaporation, or other suitable deposition techniques, or combinations thereof.

[0072] The sacrificial gate stack 128 can be formed by first depositing a sacrificial gate dielectric layer 130, a sacrificial gate electrode layer 132, and a blanket layer of a mask structure 134, followed by patterning and etching processes. For example, the patterning process includes lithography processes (e.g., optical lithography or e-beam lithography), which may further include photoresist coating (e.g., spin-on coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE), wet etching, other etching methods, and / or combinations thereof. By patterning the sacrificial gate stack 128, portions of fins 108a-b and 110a-b are exposed on opposite sides of the sacrificial gate stack 128. Portions of the insulating structure 112 are exposed due to the etching processes (multiple) to form the sacrificial gate stack 128. Figure 4 Three sacrificial gate stacks 128 are shown in the figure. It should be understood that they are for illustrative purposes only and any number of sacrificial gate stacks 128 can be formed.

[0073] The etching process forming the sacrificial gate stack 128 can cause charge accumulation on the exposed portions of the insulating structure 112, and the UV curing process can be performed immediately after the formation of the sacrificial gate stack 128 to remove the charge accumulated on the insulating structure 112, while substantially not affecting the physical properties of the insulating structure 112 and other materials of the semiconductor device structure 100. The UV curing process can be combined with... Figure 3 The UV curing process described herein is the same. In some embodiments, the cleaning process (such as...) Figure 3The cleaning process described herein can be performed immediately after the etching process that forms the sacrificial gate stack 128, and the UV curing process can be performed immediately after the cleaning process.

[0074] Figures 5A to 12A It is a manufacturing process based on the AA section along some embodiments. Figure 4 Cross-sectional side view of each stage of the semiconductor element structure 100. Figures 5B to 12B Manufacturing based on BB cut-off along some embodiments Figure 4 Cross-sectional side view of each stage of the semiconductor element structure 100. Figures 5C to 12C Manufacturing based on CC-cutting along the line according to some embodiments Figure 4 Cross-sectional side view of each stage of the semiconductor element structure 100.

[0075] Figures 6A to 6C This illustrates a stage following the formation of a sacrificial gate stack 128 on a portion of fins 108a-b and 110a-b. Spacers 140 are formed over the sacrificial gate stack 128 and exposed portions of the first semiconductor layer 104 and the second semiconductor layer 106. The spacers 140 may be conformally deposited on the exposed surfaces of the semiconductor device structure 100. The conformal spacers 140 may be formed by ALD or any suitable process. Anisotropic etching is then performed over the spacers 140 using, for example, RIE. During the anisotropic etching process, most of the spacers 140 are removed from horizontal surfaces, such as the top of the sacrificial gate stack 128 and the top of fins 108a-b and 110a-b, leaving the spacers 140 on vertical surfaces, such as the opposing sidewalls of the sacrificial gate stack 128. Figure 6A As shown, spacers 140 may be partially retained on the opposite sidewalls of fins 108a-b and 110a-b. In some embodiments, spacers 140 formed on the source / drain regions of fins 108a-b and 110a-b are completely removed.

[0076] The spacer 140 may be made of a dielectric material, such as silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), an air gap, and / or any combination thereof. In some embodiments, the spacer 140 comprises one or more layers of the above-described dielectric material.

[0077] In various embodiments where the spacer 140 includes multiple layers, the top portions of the fins 108a-b, 110a-b not covered by the sacrificial gate stack 128 may have a tapered profile 149, such as Figure 6B , Figure 6CAs shown in the diagram, the tapered profile 149 may be formed due to repeated exposure of the first semiconductor layer 104 and the second semiconductor layer 106 to the etchant used during the formation of the spacer 140. The tapered profiles 149 between adjacent sacrificial gate stacks 128 form shallow V-shaped top surfaces in the first conductor layer 104 and the second semiconductor layer 106, respectively.

[0078] The etching process forming spacer 140 can cause charge accumulation on the exposed portion of insulating structure 112, and a UV curing process can be performed immediately after the formation of spacer 140 to remove the charge accumulated on insulating structure 112, while substantially not affecting the physical properties of insulating structure 112 and other materials of semiconductor device structure 100. The UV curing process can be combined with... Figure 3 The UV curing process described herein is the same. In some embodiments, the cleaning process (such as...) Figure 3 The cleaning process described herein can be performed immediately after the etching process that forms the spacer 140, and the UV curing process can be performed immediately after the cleaning process.

[0079] exist Figures 7A to 7C In this embodiment, the first semiconductor layer 104 and the second semiconductor layer 106 of the fins 108a-b and 110a-b, which are not covered by the sacrificial gate stack 128 and the spacer 140, are recessed, and source / drain (S / D) epitaxial features 152 and 154 are formed. The etchant used to recess the first semiconductor layer 104 and the second semiconductor layer 106 is selected such that different materials have different etch rates. For example, the first semiconductor layer 104 of the fins 108a-b may have a first etch rate to the etchant, and the second semiconductor layer 106 of the fins 110a-b may have a second etch rate to the etchant. In embodiments where the first semiconductor layer 104 in the NMOS region 102N and the second semiconductor layer 106 in the PMOS region 102P each include different materials (e.g., the first semiconductor layer 104 in the NMOS region 102N is SiGe, and the second semiconductor layer 106 in the PMOS region 102P is Si), the first etch rate is faster than the second etch rate. Before completely etching away the second semiconductor layer 106 in the PMOS region 102P, a portion of the P-well region 103P of the fins 108a-b can be lightly etched. As a result, the top surface 109 of the fins 108a-b in the NMOS region 102N is positioned below the top surface 111 of the fins 110a-b in the PMOS region 102P (e.g., about 2 nm to about 10 nm below), resulting in a deeper S / D junction depth in the NMOS region 102N than in the PMOS region 102P. Although not shown, it is conceivable that this difference between the top surface 109 and the top surface 111 applies to various embodiments of this disclosure.

[0080] The etching process that recesses the first semiconductor layer 104 and the second semiconductor layer 106 can cause charge accumulation on the exposed portion of the insulating structure 112, and the ultraviolet curing process can be performed immediately after the etching process to remove the charge accumulated on the insulating structure 112, while substantially not affecting the physical properties of the insulating structure 112 and other materials of the semiconductor device structure 100. The ultraviolet curing process can be combined with... Figure 3 The UV curing process described herein is the same. In some embodiments, the cleaning process (such as...) Figure 3 The cleaning process described herein can be performed immediately after the etching process, and the UV curing process is performed immediately after the cleaning process. S / D epitaxial features 152 and 154 are formed after the UV curing process.

[0081] For the device in the NMOS region 102N, each S / D epitaxial feature 152 may include one or more layers of Si, SiP, SiC, SiCP, SiAs, or group III-V materials (InP, GaAs, AlAs, InAs, InAlAs, InGaAs). In some embodiments, each S / D epitaxial feature 152 includes two or more layers of Si, SiP, SiC, SiCP, or group III-V materials, and each layer may have a different silicon concentration. Each S / D epitaxial feature 152 may include an N-type dopant, such as phosphorus (P), arsenic (As), or other suitable N-type dopant. The S / D epitaxial feature 152 may be formed by any suitable method, such as CVD, CVD epitaxy, MBE, or other suitable methods. Figure 7B As shown, S / D epitaxial features 152 can be formed on the exposed surfaces of fins 108a-b on both sides of each sacrificial gate stack 128. In some embodiments, portions of the first semiconductor layer 104 on both sides of each sacrificial gate stack 128 are completely removed, and S / D epitaxial features 152 are formed on the P-well regions 103P of the fins 108a-b. S / D epitaxial features 152 can be grown vertically and horizontally to form facets that correspond to the crystal planes of the material used for the substrate 102. In some embodiments, the S / D epitaxial features 152 formed on the P-well regions 103P of the fins 108a and 108b are merged, as shown... Figure 7A As shown. Figure 7B As shown, each of the S / D epitaxial features 152 may have a top surface at a level higher than the top surface of the first semiconductor layer 104.

[0082] For the device in PMOS region 102P, each S / D epitaxial feature 154 may comprise one or more layers of Si, SiGe, SiGeB, Ge, or III-V group materials (InSb, GaSb, InGaSb), and each layer may have different silicon or germanium concentrations. Each S / D epitaxial feature 154 may comprise a P-type dopant, such as boron (B) or other suitable P-type dopant. In some embodiments, both the S / D epitaxial feature 152 in NMOS region 102N and the S / D epitaxial feature 154 in PMOS region 102P are Si. In some embodiments, the S / D epitaxial feature 152 in NMOS region 102N is Si, while the S / D epitaxial feature 154 in PMOS region 102P is SiGe. The S / D epitaxial feature 154 may be formed by any suitable method, such as CVD, CVD epitaxy, MBE, or other suitable methods. In some embodiments, portions of the second semiconductor layers 106 on both sides of each sacrificial gate stack 128 are completely removed, and S / D epitaxial features 154 are formed on the N-well regions 103N of the fins 110a-b. The S / D epitaxial features 154 can be grown vertically and horizontally to form facets that correspond to the crystal planes of the material used for the substrate 102. In some embodiments, the S / D epitaxial features 154 formed on the N-well regions 103N of the fins 110a and 110b are merged, such as... Figure 7A As shown. Figure 7C As shown, each of the S / D epitaxial features 154 may have a top surface at a level higher than the top surface of the second semiconductor layer 106.

[0083] exist Figures 8A to 8C In this process, a contact etch stop layer (CESL) 160 is conformally formed on the exposed surface of the semiconductor device structure 100. CESL 160 covers the sidewalls of the sacrificial gate stack 128, the insulating structure 112, and the S / D epitaxial features 152 and 154. CESL 160 may comprise an oxygen-containing or nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbide, or similar materials, or combinations thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. In some embodiments, CESL 160 is formed by a plasma process such as PECVD, and as a result of the plasma process, charge may accumulate on CESL 160. To remove the accumulated charge from CESL 160, a UV curing process is performed. The UV curing process may be combined with… Figure 3 The UV curing process described herein is the same. The UV curing process can be performed immediately after a plasma process such as PECVD to remove the charge accumulated on CESL 160, while substantially not affecting the physical properties of CESL 160 and other materials of the semiconductor device structure 100.

[0084] Next, a first interlayer dielectric (ILD) layer 162 is formed on the CESL 160. The material used for the ILD layer 162 may include compounds comprising Si, O, C, and / or H, such as SiOCH, oxides formed using tetraethyl orthosilicate (TEOS), undoped silicate glass, silicon oxide, or doped silicon oxide (such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG)), and / or other suitable dielectric materials. The first ILD layer 162 may be deposited using a PECVD process or other suitable deposition techniques. Similarly, because the first ILD layer 162 may be deposited using a plasma process, charge may accumulate on the first ILD layer 162 as a result of the plasma process. To remove the accumulated charge from the first ILD layer 162, a UV curing process is performed. The UV curing process may be combined with… Figure 3 The UV curing process described herein is the same. The UV curing process can be performed immediately after a plasma process such as PECVD to remove the charge accumulated on the first ILD layer 162, while substantially not affecting the physical properties of the first ILD layer 162 and other materials of the semiconductor device structure 100.

[0085] After the formation of the first ILD layer 162 and the UV curing process, a planarization process is performed to expose the sacrificial gate electrode layer 132. The planarization process can be any suitable process, such as CMP. The planarization process removes portions of the first ILD layer 162 and CESL 160 disposed on the sacrificial gate stack 128. The planarization process may also remove the masking structure 134.

[0086] exist Figures 9A to 9C In the process, the mask structure 134 (if not removed during the CMP process) and the sacrificial gate electrode layer 132 are removed. Figure 8B ), and sacrificial gate dielectric layer 130 ( Figure 8B The sacrificial gate electrode layer 132 and the sacrificial gate dielectric layer 130 can be removed by one or more etching processes (such as dry etching, wet etching, or a combination thereof). One or more etching processes selectively remove the sacrificial gate electrode layer 132 and the sacrificial gate dielectric layer 130 without substantially affecting the spacer 140, CESL 160, and the first ILD layer 162. As a result of one or more etching processes, charge may accumulate on CESL 160 and the first ILD layer 162. To remove the accumulated charge from CESL 160 and the first ILD layer 162, a UV curing process is performed. The UV curing process can be combined with… Figure 3The UV curing process described herein is the same. The UV curing process can be performed immediately after one or more etching processes to remove the charge accumulated on CESL 160 and the first ILD layer 162, while substantially not affecting the physical properties of CESL 160, the first ILD layer 162, and other materials of the semiconductor device structure 100. The removal of the sacrificial gate electrode layer 132 and the sacrificial gate dielectric layer 130 exposes the top portions of the first semiconductor layer 104 and the second semiconductor layer 106 in the channel region.

[0087] exist Figures 10A to 10C In this process, a replacement gate structure 177 is formed. The replacement gate structure 177 may include a gate dielectric layer 166 and gate electrode layers 168p and 168n formed on the gate dielectric layer 166. Figure 10B and Figure 10C As shown, a gate dielectric layer 166 is formed on a first semiconductor layer 104 and a second semiconductor layer 106. The gate dielectric layer 166 may include one or more dielectric layers and may include the same material (multiple types) as the sacrificial gate dielectric layer 130. In some embodiments, the gate dielectric layer 166 may be deposited using one or more ALD processes or other suitable processes. Gate electrode layers 168p and 186n may include one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, AlTi, AlTiO, AlTiC, AlTiN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. For devices in the NMOS region 102N, the gate electrode layer 168n may be AlTiO, AlTiC, or a combination thereof. For devices in the PMOS region 102P, the gate electrode layer 168p may be AlTiO, AlTiC, AlTiN, or a combination thereof. The gate electrode layer 168 can be formed by PVD, CVD, ALD, electroplating, or other suitable methods.

[0088] Optionally, a metal gate etching back (MGEB) process is performed to remove portions of the gate dielectric layer 166 and gate electrode layers 168p and 168n. The MGEB process may be a plasma etching process using one or more etchants (such as chlorine-containing gases, bromine-containing gases, and / or fluorine-containing gases). After the MGEB process, the top surfaces of the gate electrode layers 168p and 168n may be lower than the top surface of the gate dielectric layer 166. In some embodiments, portions of the spacer 140 are etched back such that the top surface of the spacer 140 is higher than the top surfaces of the gate dielectric layer 166 and the gate electrode layers 168p and 168n. As a result of the plasma etching of the MGEB process, charge may accumulate on CESL 160 and the first ILD layer 162. To remove the accumulated charge from CESL 160 and the first ILD layer 162, a UV curing process is performed. The UV curing process may be combined with… Figure 3 The UV curing process described herein is the same. The UV curing process can be performed immediately after the plasma etching of the MGEB process to remove the charge accumulated on CESL 160 and the first ILD layer 162, while substantially not affecting the physical properties of CESL 160, the first ILD layer 162 and other materials of the semiconductor device structure 100.

[0089] Next, as a result of the MGEB process, trenches are formed over the gate dielectric layer 166 and gate electrode layers 168p and 168n, and these trenches are filled with a self-aligned contact (SAC) layer 179. The SAC layer 179 can be formed from any dielectric material having a different etch selectivity than CESL160 and serves as an etch stop layer during the subsequent patterning of trenches and vias for the metal contacts. A CMP process is then performed to remove excess deposition of the SAC layer 179 until the top surface of the first ILD layer 162 is exposed.

[0090] exist Figures 11A to 11C In this process, portions of the first ILD layer 162 and CESL 160 disposed on both sides of the replacement gate structure 177 are removed. The removal of portions of the first ILD layer 162 and CESL 160 forms contact openings that expose S / D epitaxial features 152 and 154, respectively. In some embodiments, the upper portions of the exposed S / D epitaxial features 152 and 154 are removed. The removal of portions of the first ILD layer 162 and CESL 160 can be performed using a dry etching or wet etching process. As a result of the dry etching or wet etching process, charge may accumulate on the remaining portions of CESL 160 and the first ILD layer 162. To remove the accumulated charge from CESL 160 and the first ILD layer 162, a UV curing process is performed. The UV curing process can be combined with... Figure 3The UV curing process described herein is the same. The UV curing process can be performed immediately after a dry etching or wet etching process to remove the charge accumulated on the remaining portion of CESL 160 and the first ILD layer 162, while substantially not affecting the physical properties of CESL 160, the first ILD layer 162 and other materials of the semiconductor device structure 100.

[0091] Next, after forming the contact openings and following the UV curing process, conductive features 172 (i.e., S / D contacts) are formed in the contact openings above the S / D epitaxial features 152 and 154. Conductive features 172 may include conductive materials such as one or more of Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, and TaN. Conductive features 172 can be formed by any suitable process, such as PVD, CVD, ALD, electroplating, or other suitable methods. A silicide layer 170 is formed between each S / D epitaxial feature 152, 154 and the conductive feature 172, such as... Figures 11A to 11C As shown in the diagram, silicide layer 170 conductively couples S / D epitaxial features 152, 154 to conductive feature 172. Silicide layer 170 is a metal or metal alloy silicide, and the metal includes noble metals, refractory metals, rare earth metals, alloys thereof, or combinations thereof. Once conductive feature 172 is formed, a planarization process such as CMP is performed on semiconductor device structure 100 until the top surface of SAC layer 179 (if used) is exposed.

[0092] like Figures 12A to 12C As shown, a second ILD layer 176 can be formed over the first ILD layer 162. An annealing process can be performed after the formation of the second ILD layer 176 to improve the physical properties of the second ILD layer 176, such as hardness or wet etch rate (WER). The annealing process can be a thermal annealing process performed at a temperature below approximately 450 degrees Celsius. Next, an opening for forming a conductive socket 185 is formed in the second ILD layer 176. The opening can be formed by an etching process, such as a dry etching or wet etching process. As a result of the etching process, charge can accumulate on the second ILD layer 176. To remove the accumulated charge from the second ILD layer 176, a UV curing process is performed. The UV curing process can be combined with… Figure 3 The UV curing process described herein is the same. The UV curing process can be performed immediately after the etching process to remove the charge accumulated on the second ILD layer 176, while substantially not affecting the physical properties of the second ILD layer 176 and other materials of the semiconductor device structure 100. Next, a conductive socket 185 is formed in an opening in the second ILD layer 176. The conductive socket 185 may comprise any conductive material, such as tungsten.

[0093] like Figures 12A to 12C As shown, an interconnect structure 174 is formed above the second ILD layer 176. The interconnect structure 174 may include one or more intermetallic dielectric (IMD) layers and multiple interconnect features formed in each IMD layer. Figures 12A to 12C In one exemplary embodiment shown, the interconnect structure 174 includes an IMD layer 178 formed above the second ILD layer 176, and a plurality of conductive lines 187 and conductive vias 189 embedded in the IMD layer 178. The conductive lines 187 and conductive vias 189 may include or be formed of W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, or combinations thereof. In some embodiments, the conductive lines 187 and vias 189 include Cu. The IMD layer 178 may be formed of the same material as the first ILD layer 162.

[0094] Next, an etch stop layer 192 is formed on the second ILD layer 176. The etch stop layer 192 may comprise the same material as CESL 160. In some embodiments, the etch stop layer 192 is formed by PECVD or PEALD. After the PECVD or PEALD process that forms the etch stop layer 192, an average charge of -7.838V accumulates on the etch stop layer 192. The charge accumulated on the etch stop layer 192 does not dissipate after 40 hours. A UV curing process, such as... Figure 3 The UV curing process described herein removes the charge accumulated on the etch stop layer 192. As a result of the UV curing process, the charge remaining on the etch stop layer 192 decreases to -1.857V. During the process, the UV curing process is performed immediately after the PECVD or PEALD process that forms the etch stop layer 192.

[0095] Next, a first IMD layer 178 is formed on the etch stop layer 192. An annealing process can be performed after the formation of the first IMD layer 178 to improve the physical properties of the first IMD layer 178, such as hardness or wet etch rate (WER). The annealing process can be a thermal annealing process performed at a temperature below approximately 450 degrees Celsius. Next, openings for forming conductive lines 187 are formed in the first IMD layer 178. The openings can be formed by an etching process, such as a dry etching or wet etching process. As a result of the etching process, charge can accumulate on the first IMD layer 178. To remove the accumulated charge from the first IMD layer 178, a UV curing process is performed. The UV curing process can be combined with… Figure 3The UV curing process described herein is the same. The UV curing process can be performed immediately after the etching process to remove the charge accumulated on the first IMD layer 178, while substantially not affecting the physical properties of the first IMD layer 178 and other materials of the semiconductor device structure 100.

[0096] Next, conductive lines 187 are formed in the openings of the first IMD layer 178. Optionally, a capping layer 194 is formed on the conductive lines 187. The capping layer 194 comprises a conductive material, such as Cu, Co, Ru, Mo, Cr, W, Mn, Rh, Ir, Ni, Pd, Pt, Ag, Au, Al, alloys thereof, or other suitable materials. The capping layer 194 can be formed by any suitable process, such as PVD, ALD, or PECVD. In some embodiments, the capping layer 194 comprises Co and is formed by PECVD. After the PECVD process forming the Co capping layer 194, an average charge of negative 1.413V accumulates on the first IMD layer 178. Ultraviolet curing processes, such as... Figure 3 The UV curing process is performed after the formation of the Co capping layer 194 to remove the charge accumulated on the first IMD layer 178. As a result of the UV curing process, the charge remaining on the IMD layer 178 decreases to -0.182V.

[0097] Interconnection structure 174 may include an additional IMD layer 178 and conductive lines 187 and vias 189 formed above the first IMD layer 178, such as Figures 12A to 12C As shown in the figure. In some embodiments, the conductive line 187 and the via 189 are formed by a dual damascene process, and the capping layer 194 is not formed on the conductive via 189. In some embodiments, the conductive line 187 and the via 189 are formed by a single damascene process, and the capping layer 194 is formed on both the conductive line 187 and the conductive via 189. Each time a plasma deposition process, plasma etching process, or wet etching process is performed, a UV curing process is performed to remove the charge accumulated on the exposed dielectric material. By removing the charge accumulated on the dielectric material, under-etching and reduced time-dependent dielectric breakdown (TDDB) can be avoided.

[0098] This disclosure provides a method for forming a semiconductor device structure 100. In some embodiments, the method includes performing a UV curing process after a plasma process or a wet etching process. The UV curing process removes the charge accumulated on the dielectric material of the semiconductor device structure 100, resulting in improved TDDB.

[0099] One embodiment is a method for forming a semiconductor device structure. The method includes forming an interconnect structure over a substrate. Forming the interconnect structure over the substrate includes forming a dielectric layer, then performing an annealing process, then forming one or more openings in the dielectric layer, then performing a first ultraviolet (UV) curing process, and then forming conductive features in the one or more openings. In some embodiments, the one or more openings are formed by a dry etching process or a wet etching process. In some embodiments, the first UV curing process includes exposing the dielectric layer to ultraviolet light having a wavelength range of about 200 nm to about 400 nm. In some embodiments, a processing temperature range of the first UV curing process is about 70 degrees Celsius to about 400 degrees Celsius. In some embodiments, a processing pressure range of the first UV curing process is about 1 Torr to about 10 Torr. In some embodiments, the method of forming the semiconductor device structure further includes forming a capping layer on the conductive features. In some embodiments, the method of forming the semiconductor device structure further includes performing a second UV curing process after forming the capping layer.

[0100] Another embodiment is a method. The method of forming a semiconductor device structure includes forming one or more semiconductor fins, forming an insulating structure to embed the one or more semiconductor fins, performing an annealing process to recess the insulating structure, removing accumulated charge on the insulating structure by performing a first ultraviolet (UV) curing process, and forming one or more sacrificial gate structures. In some embodiments, recessing the insulating structure is performed by a dry etching process or a wet etching process. In some embodiments, the first UV curing process includes exposing a shallow trench isolation region to ultraviolet light having a wavelength range of about 200 nm to about 400 nm. In some embodiments, a processing temperature range of the first UV curing process is about 70 degrees Celsius to about 400 degrees Celsius. In some embodiments, a processing pressure range of the first UV curing process is about 1 Torr to about 10 Torr. In some embodiments, forming one or more sacrificial gate structures includes: forming a sacrificial gate dielectric layer; forming a sacrificial gate electrode layer; and removing multiple portions of the sacrificial gate dielectric layer and multiple portions of the sacrificial gate electrode layer to expose multiple portions of a shallow trench isolation region. In some embodiments, the method of forming a semiconductor device structure further includes performing a second ultraviolet curing process to remove charge accumulated on multiple exposed portions of the shallow trench isolation region. In some embodiments, the method of forming a semiconductor device structure further includes recessing multiple portions of the one or more semiconductor fins not covered by the sacrificial gate structures. In some embodiments, the method of forming a semiconductor device structure further includes performing a third ultraviolet curing process after recessing the portions of the one or more semiconductor fins not covered by the one or more sacrificial gate structures.

[0101] A further embodiment is a method for forming a semiconductor device structure. The method includes forming an insulating structure over a substrate, performing a first annealing process to recess the insulating structure, performing a first ultraviolet (UV) curing process to form source / drain epitaxial features over the substrate, forming a gate electrode layer over the substrate, forming a dielectric layer on the source / drain epitaxial features and the gate electrode layer, performing a second annealing process to form one or more openings in the dielectric layer, performing a second UV curing process, and forming conductive features in the one or more openings. In some embodiments, the first UV curing process includes exposing the insulating structure to ultraviolet light having a wavelength range of about 200 nm to about 400 nm. In some embodiments, the second UV curing process is performed to remove charge accumulated on the dielectric layer. In some embodiments, the method of forming the semiconductor device structure further includes: forming a capping layer on each of the conductive features; and after forming the capping layer, performing a third UV curing process.

[0102] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor device structure, characterized in that, Include: An interconnect structure is formed over a substrate, comprising: A dielectric layer is formed; After the dielectric layer is formed, an annealing process is performed; After the annealing process is performed, one or more openings are formed in the dielectric layer; After the openings are formed, a first UV curing process is performed; After the first UV curing process is performed, multiple conductive features are formed in the openings; Multiple capping layers are formed on the multiple conductive features, wherein the multiple capping layers comprise Cu, Co, Ru, Mo, Cr, W, Mn, Rh, Ir, Ni, Pd, Pt, Ag, Au, Al, and their alloys, and are formed by a plasma-enhanced chemical vapor deposition process; and After the multiple coating layers are formed, a second ultraviolet curing process is performed.

2. The method as described in claim 1, characterized in that, The openings are formed by a dry etching process or a wet etching process.

3. The method as described in claim 2, characterized in that, The first ultraviolet curing process involves exposing the dielectric layer to ultraviolet light having a wavelength range of 200 nm to 400 nm.

4. The method as described in claim 3, characterized in that, The first UV curing process has a processing temperature range of 70 degrees Celsius to 400 degrees Celsius.

5. The method as described in claim 4, characterized in that, The processing pressure range for this first UV curing process is 1 Torr to 10 Torr.

6. The method as described in claim 1, characterized in that, Further includes: Before forming the dielectric layer, an etch stop layer is formed on the substrate; and A third UV curing process is performed on the etch stop layer.

7. A method for forming a semiconductor device structure, characterized in that, Include: Form one or more semiconductor fins; An insulating structure is formed to embed the semiconductor fins; Perform a first annealing process; The insulating structure is recessed to form a shallow trench isolation area, and the recessing of the insulating structure is performed by a wet etching process; The charge accumulated on the insulating structure as a result of the wet etching process is removed by performing a first ultraviolet curing process. as well as One or more sacrificial gate structures are formed.

8. The method as described in claim 7, characterized in that, The UV curing time for the first UV curing process is from 1 second to 120 seconds.

9. The method as described in claim 8, characterized in that, The first ultraviolet curing process involves exposing the shallow trench isolation area to ultraviolet light having a wavelength range of 200 nm to 400 nm.

10. The method as described in claim 9, characterized in that, One of the first UV curing processes has a processing temperature range of 70 degrees Celsius to 400 degrees Celsius.

11. The method as described in claim 10, characterized in that, One of the first UV curing processes has a processing pressure range of 1 Torr to 10 Torr.

12. The method as described in claim 7, characterized in that, The formation of the sacrificial gate structure includes: A sacrificial gate dielectric layer is formed; Forming a sacrificial gate electrode layer; and Multiple portions of the sacrificial gate dielectric layer and multiple portions of the sacrificial gate electrode layer are removed to expose multiple portions of the shallow trench isolation region.

13. The method as described in claim 12, characterized in that, Further includes: A second ultraviolet curing process is performed to remove the charge accumulated on the exposed portions of the shallow trench isolation area.

14. The method as described in claim 13, characterized in that, Further includes: The recesses are located in portions of the semiconductor fins that are not covered by the sacrificial gate structures.

15. The method as described in claim 14, characterized in that, Further includes: After recessing the portions of the semiconductor fins not covered by the sacrificial gate structures, a third ultraviolet curing process is performed.

16. A method for forming a semiconductor device structure, characterized in that, Include: An insulating structure is formed over a substrate; Perform the first annealing process; The insulation structure is recessed; Perform the first ultraviolet curing process; Multiple source / drain epitaxial features are formed on the substrate; A gate electrode layer is formed on the substrate; A dielectric layer is formed above these source / drain epitaxial features and the gate electrode layer; Perform a second annealing process; One or more openings are formed in the dielectric layer; Perform a second UV curing process; Multiple conductive features are formed in the openings; A capping layer is formed on each of these conductive features by a plasma-enhanced chemical vapor deposition process, wherein the capping layer comprises Cu, Co, Ru, Mo, Cr, W, Mn, Rh, Ir, Ni, Pd, Pt, Ag, Au, Al, and their alloys; and After the coating is formed, a third UV curing process is performed.

17. The method as described in claim 16, characterized in that, The first ultraviolet curing process involves exposing the insulating structure to ultraviolet light having a wavelength range of 200 nm to 400 nm.

18. The method as described in claim 16, characterized in that, The second UV curing process is performed to remove the charge accumulated on the dielectric layer.

19. The method as described in claim 16, characterized in that, The third UV curing process has a processing temperature range of 70 degrees Celsius to 400 degrees Celsius.

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