Packaging substrate, package, and method of forming a semiconductor structure

Abstract

This disclosure provides a packaging substrate. The packaging substrate includes a substrate having a cavity aperture and a semiconductor component located within the cavity aperture. The semiconductor component has a first terminal side and a second terminal side opposite to the first terminal side. The packaging substrate also includes a first rewiring structure on the first terminal side of the cavity substrate electrically coupled to a first pad and a second pad on the first terminal side of the semiconductor component; and a second rewiring structure on the second side of the cavity substrate electrically coupled to a third pad and a fourth pad on the second terminal side of the semiconductor component.

Description

Technical Field

[0001] This disclosure relates to packaging substrates, packaging, and methods for forming semiconductor structures. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration of various electronic components, such as transistors, diodes, resistors, and capacitors. In most cases, this increase in integration stems from the continuous reduction in the minimum feature size, allowing more and smaller components to be integrated into a given area. These smaller electronic components also require smaller packages, occupying less area than previous packages. Some smaller types of packages used for semiconductor components include Quad Flat Packages (QFP), Pin Grid Array (PGA) packages, Ball Grid Array (BGA) packages, Flip Chip (FC), 3D Integrated Circuit (3DIC), Chip Scale Package (WLP), and PoP (PoP) assemblies. The formation of redistribution circuit structures also plays a crucial role in the packaging process. Summary of the Invention

[0003] This disclosure relates to a packaging substrate, comprising: a substrate having a cavity aperture; a semiconductor component embedded in the cavity aperture, wherein the semiconductor component has a first terminal side and a second terminal side opposite to the first terminal side; a first redistribution structure electrically coupled to a first pad and a second pad on the first terminal side of the semiconductor component on a first side of the cavity substrate; and a second redistribution structure electrically coupled to a third pad and a fourth pad on the second terminal side of the semiconductor component on a second side of the cavity substrate.

[0004] This disclosure relates to a package comprising: a component bonded to and electrically coupled to a package substrate, wherein the package substrate includes: a cavity substrate having a cavity aperture therein; a semiconductor component embedded in the cavity aperture, wherein the semiconductor component has a first component component and a second component component bonded back-to-back, the first component component including a first pad, a second pad, and a first capacitor, the second component component including a third pad, a fourth pad, and a second capacitor; a first rewiring structure electrically coupled to a first electrode and a second electrode of the first capacitor on a first side of the cavity substrate; and a second rewiring structure electrically coupled to a third electrode and a fourth electrode of the second capacitor on a second side of the cavity substrate, wherein the first pad and the third pad are coupled to a first terminal, and the second pad and the fourth pad are coupled to a second terminal through the first rewiring structure and the second rewiring structure.

[0005] This disclosure relates to a method for forming a semiconductor structure, the method comprising: providing a semiconductor component; placing the semiconductor component in a cavity aperture of a cavity substrate, wherein the semiconductor component has a first terminal side and a second terminal side opposite to the first terminal side; forming a dielectric layer along a sidewall of the semiconductor component, the first terminal side and the second terminal side, and the cavity aperture, a first side and a second side opposite to the first side of the cavity substrate; forming a first rewiring structure on the first side of the cavity substrate to electrically couple the first terminal side of the semiconductor component; and forming a second rewiring structure on the second side of the cavity substrate to electrically couple the second terminal side of the semiconductor component. Attached Figure Description

[0006] The aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, as is customary in the industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features can be increased or decreased at will.

[0007] Figures 1A to 1O The diagram shows a cross-sectional view of an intermediate step in forming a package using a packaging substrate with embedded semiconductor components, according to some embodiments.

[0008] Figure 2A and 2B A top view of the cavity substrate is shown.

[0009] Figures 3A to 3D A cross-sectional view is shown of an intermediate step in forming a semiconductor component according to some embodiments.

[0010] Figure 4A and 4B This is a variety of views of the component components of a semiconductor component according to another embodiment.

[0011] Figure 5A and 5B A cross-sectional view of a component component of a semiconductor component according to yet another embodiment is shown.

[0012] Figure 5C A cross-sectional view is shown of an intermediate step in the packaging process using a packaging substrate with embedded semiconductor components, according to some other embodiments.

[0013] Figure 6A and 6B A cross-sectional view of a component component of a semiconductor component according to some other embodiments is shown. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the sake of brevity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of explanation, spatially relative terms such as "below," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. In addition to the orientations illustrated in the figures, these spatially relative terms are intended to cover different orientations of components in use or operation. Devices may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative terms used herein shall be interpreted accordingly.

[0016] The embodiments described below provide a package using a packaging substrate with embedded semiconductor components. Electrical terminals may be present on both sides of the semiconductor components to couple with components attached to the packaging substrate via a redistribution structure of the packaging substrate.

[0017] Figures 1A to 1O The diagram shows a cross-sectional view of an intermediate step in forming a package using a packaging substrate with embedded semiconductor components, according to some embodiments.

[0018] First refer to Figure 1A The diagram illustrates a substrate (or substrate core) 112 according to some embodiments. The substrate 112 includes an insulating layer 100 and conductive layers 110 located on both sides of the insulating layer 100. In some embodiments, the substrate 112 is a double-sided copper clad laminate (CCL). The insulating layer 100 may be a pre-impregnated composite fiber (prepreg), Ajinomoto build-up film (ABF), paper, glass fiber, nonwoven glass fabric, other insulating materials, or combinations thereof. The conductive layers 110 may be a laminate or formed on opposite sides 100-FS and 100-BS of the insulating layer 100, consisting of one or more layers of copper, nickel, aluminum, other conductive materials, or combinations thereof.

[0019] Reference Figure 1B A through-hole 114 is formed in the substrate 112. In some embodiments, the through-hole 114 is formed by laser drilling. Other processes, such as mechanical drilling, etching, etc., may also be used. The top view shape of the through-hole 114 may be circular (e.g., ...). Figure 2A and 2B (as shown), rectangle (not shown), or any other shape.

[0020] Reference Figure 1C Conductive material is formed on the conductive layer 110 and sidewalls of the through-hole 114 to form a conductive layer 115. The conductive material of the conductive layer 115 can be formed, for example, by electroplating. Before forming the conductive material on the conductive layer 110 and sidewalls of the through-hole 114, a surface treatment process can be performed. The surface treatment process can include cleaning the exposed surfaces of the substrate 112 (e.g., the surface of the conductive layer 110 and the surface of the insulating layer 100 in the through-hole 114) with one or more cleaning solutions (e.g., sulfuric acid, chromic acid, neutralizing alkaline solution, water rinsing, etc.) to remove or reduce contaminants, oil, and / or natural oxide films. A desmear process can be performed to clean the area near the through-hole 114, which may have been contaminated by the material that forms the insulating layer 100 of the through-hole 114. Desmearing can be achieved mechanically (e.g., by sandblasting with fine abrasives in a wet slurry), chemically (e.g., by rinsing with a combination of organic solvents, permanganates, etc.), or by a combination of mechanical and chemical desmearing. After cleaning, a chemical conditioner can be used to treat the surface, which facilitates the adsorption of activators used in subsequent electroless plating. In some embodiments, the conductive layer 110 can be micro-etched after the conditioning step to roughen the conductive surface of the conductive layer 110, thereby improving bonding between the metal foil and the conductive material deposited later.

[0021] Reference Figure 1D The conductive layer is patterned to form conductive traces 116. Conductive traces 116 may include conductive traces 116F, 116B, and 116P connected to each other. Conductive trace 116F is formed on side 100-FS of the insulating layer 100. Conductive trace 116B is formed on side 100-BS of the insulating layer 100. Conductive trace 116P is formed on the sidewall of the insulating layer 100 at the through-hole 114 and connects a portion of conductive traces 116F and 116B.

[0022] Reference Figure 1D To form a cavity 118 to form Figure 2AThe cavity substrate 120 is shown. A cavity aperture 118 is formed in region R1 of the substrate 112, and a through-hole 114 is formed in region R2 of the substrate 112. Region R1 is the region used to form a semiconductor component and can be referred to as the semiconductor component region. Region R2 is the region outside the semiconductor component region. According to some embodiments, the cavity aperture 118 can be formed by removing portions of the conductive layer 115 and the insulating layer 100 on opposite sides 100-FS and 100-BS. In some embodiments, the cavity aperture 118 is formed by laser drilling. Other processes, such as mechanical drilling and etching, can also be used for the cavity aperture 118. The top view shape of the cavity aperture 118 can be rectangular (e.g., ...). Figure 2A and 2B (as shown), circular (not shown), or any other shape.

[0023] although Figure 1D and 2A A cavity 118 formed in the substrate 112 is shown, but it should be understood that multiple cavities 118 may also be formed in the substrate 112, such as... Figure 2B As shown. In Figure 2B In the cavity substrate 120, the cavity holes 118 may have the same or different dimensions, and may have the same or different shapes. According to some embodiments, each cavity hole 118 is surrounded by a perforation 114, but is not limited thereto. The number of cavity holes 118 in the cavity substrate 120 may be from 2 to 50 or more.

[0024] Reference Figure 1E , Figure 1D The cavity substrate 120 shown is attached to the adhesive tape TP. The adhesive tape TP can be attached to a frame (not shown). The semiconductor component 600 can be placed in the cavity hole 118 of the cavity substrate 120 (e.g., using a pick-and-place (PnP) tool) using a pick-and-place tool. Figure 1D (As shown). The semiconductor component 600 can be an integrated circuit chip, a packaged chip, an integrated passive component (IPD), an interposer, an antenna package (AIP), a microelectromechanical system (MEMS) package, etc. In some embodiments, the semiconductor component 600 is adhered to adhesive tape TP, such as... Figure 1E As shown. Although Figure 1E A semiconductor component 600 is shown placed in each cavity aperture 118, but it should be understood that multiple chips may also be placed in the cavity apertures 118 of the cavity substrate 120. For example, in some embodiments, the semiconductor component 600 may be multiple components placed laterally adjacent to each other and / or stacked on top of each other, wherein the multiple components may have the same or different dimensions.

[0025] exist Figure 1EIn the example shown, semiconductor component 600 has dual electrical terminals. That is, semiconductor component 600 has two terminal sides, 600-FS and 600-BS. Semiconductor component 600 can be a semiconductor component, such as an integrated circuit chip, such as a passive chip, a logic chip (e.g., a microprocessor, microcontroller, etc.), a memory chip (e.g., dynamic random access memory (DRAM), static random access memory (SRAM), etc.), a system-on-a-chip (SoC) chip (e.g., a power management integrated circuit (PMIC), a mixed-signal integrated circuit, etc.), a radio frequency integrated circuit (RFIC) chip, a digital signal processing (DSP) chip, etc., or a combination thereof.

[0026] Before placing the semiconductor component 600 on the cavity substrate 120, the semiconductor component 600 can be processed according to applicable manufacturing processes to form a corresponding component structure. For example, the semiconductor component 600 may have been processed into an integrated circuit within the semiconductor component 600. Figure 1E As shown, in some embodiments, semiconductor component 600 includes component members 200 and 300, and an adhesive 400 therebetween.

[0027] Components 200 and 300 can be passive components, such as capacitors, resistors, and inductors. Components 200 and 300 can be passive components of the same type or different types. In some embodiments, components 200 and 300 are capacitor components. Alternatively, component 200 is a capacitor component, and component 300 is an inductor component or a resistor component.

[0028] In some embodiments where component members 200 and 300 of semiconductor component 600 are capacitor components, semiconductor component 600 may be... Figure 3D The semiconductor component 600A shown is Figure 5A The semiconductor component 600B shown Figure 6A The semiconductor component 600C shown is or Figure 6B The semiconductor component 600D shown is illustrated.

[0029] exist Figure 3D In this embodiment, semiconductor component 600A includes component members 200 and 300A. Component member 200 is bonded to component member 300A in a back-to-back manner by adhesive 400. Furthermore, the sidewalls in component members 200 and 300A are laterally encapsulated by encapsulation layer 500.

[0030] Figure 3D The semiconductor component 600A shown can be based on Figures 3A to 3D The manufacturing process shown is applied. More detailed structures of components 200 and 300A are as follows... Figure 4A As shown.

[0031] Reference Figure 3A and 4A The component 200 may be a passive component, including a semiconductor substrate 202, a capacitor 210, an interconnect structure 230, a conductive pad 250, and a passivation layer 260. In some embodiments, the component 200 may be referred to as a silicon cap. The semiconductor substrate 202 may be a bulk substrate or an active layer of a semiconductor-on-insulator (SOI) substrate, and may include group IV semiconductors such as silicon and germanium, compound semiconductors, and / or alloy semiconductors; it may be doped or undoped.

[0032] Reference Figure 4A The semiconductor substrate 202 includes a plurality of trenches 212 to construct capacitors 210 in the upper surface of the semiconductor substrate 202. The component 200 may include one or more capacitors 210. The capacitor 210 may be referred to as a metal-insulator-metal (MIM) capacitor, an MIM capacitor cell, or a trench capacitor. The capacitor 210 includes a bottom electrode layer 214, an insulating layer 216, and a top electrode layer 218 conformally disposed within the trenches 212 and on the semiconductor substrate 202.

[0033] The bottom electrode layer 214 and the top electrode layer 218 may each be or include, for example, doped polycrystalline silicon, titanium nitride (e.g., TiN), tantalum nitride (e.g., TaN), aluminum copper (e.g., AlCu), some other suitable metals and / or materials, or any combination thereof. In some embodiments, the bottom electrode layer 214 and the top electrode layer 218 each comprise a tantalum nitride layer and an aluminum copper layer stacked on top of each other. The insulating layer 216 may be, for example, or include silicon oxide, a high-k dielectric, some other suitable dielectric, or any combination thereof. The dielectric constant k of the high-k dielectric is greater than that of silicon nitride and / or greater than about 10, 20, or 50. However, other values ​​are also acceptable. The high-k dielectric may be or include, for example, hafnium oxide (e.g., HfO2), zirconium oxide (e.g., ZrO2), aluminum oxide (e.g., Al2O3), tantalum oxide (e.g., Ta2O5), titanium oxide (e.g., TiO2), some other suitable high-k dielectrics, or any combination thereof.

[0034] The interconnect structure 230 may include, for example, a metallization pattern 240 formed in one or more dielectric layers 232 of the semiconductor substrate 202 to the interconnect, a metallization pattern 240 formed in the capacitor 210, and / or the semiconductor substrate 202 forming the integrated circuit. The interconnect structure 230 may further include an etch stop layer 234 between the dielectric layers 232. The dielectric layer 232 and the etch stop layer 234 may each be or include, for example, silicon nitride, silicon oxide, or any combination thereof.

[0035] The metallization pattern 240 includes vias 242 and a conductive layer 244 to form a conductive path between the capacitor 210 and the conductive pad 250. The vias 242 include vias 242a and 242b, and the conductive layer 244 includes conductive layers 244a and 244b. The vias 242 and the conductive layer 244 can be or include, for example, copper, aluminum-copper, tungsten, some other suitable metal, or any combination thereof.

[0036] The conductive pad 250 may be a metal pad for external connection. The conductive pad 250 may be, or include, for example, copper, aluminum copper, tungsten, some other suitable metal, or any combination thereof. A passivation layer 260 is formed on the dielectric layer 232 or etch stop layer 234 of the interconnect structure 230 and a portion of the conductive pad 250. The passivation layer 260 may be one or more layers of conductive material. The passivation layer 260 may be, or include, for example, silicon oxide, silicon nitride, polyimide, some other suitable dielectric, or any combination thereof.

[0037] In some embodiments, via 242a, conductive layer 244a, and conductive pad 250a are coupled to the top electrode layer 218 and electrically contact the top electrode layer 218 through the dielectric layer 232 and the etch stop layer 234; via 242b, conductive layer 244b, and conductive pad 250b are coupled to the bottom electrode layer 214 through the dielectric layer 232 and the etch stop layer 234 and electrically contact the bottom electrode layer 214.

[0038] exist Figure 3A and 4A In this embodiment, component 300A may be a passive component, and the structure of component 300A may be similar to or different from that of component 200. In some embodiments, component 300A includes a semiconductor substrate 302, a capacitor 310, an interconnect structure 330, and a conductive pad 350. The semiconductor substrate 302, capacitor 310, interconnect structure 330, and conductive pad 350 of component 300B may be corresponding components similar to those of component 200. In some embodiments, component 300A does not have a passivation layer, so the top surface and sidewall surfaces of the conductive pad 350 are exposed. In some alternative embodiments, component 300B includes... Figure 5A and 5B The passivation layer 360 shown will be described in detail later. In some embodiments, the top region A3 of the conductive pad 350 is larger than the top region A2 of the conductive pad 250, such as... Figure 4B As shown, but not limited to.

[0039] Reference Figure 3BThe back side 200-BS of component member 200 is bonded to the back side 300-BS of component member 300A via adhesive 400. Adhesive 400 can be any suitable adhesive, epoxy resin, die-attach film (DAF), etc. Adhesive 400 can be applied to the back side 200-BS of component member 200 prior to monomerization, for example, applied to the back side of the corresponding semiconductor chip. Component member 200 and component member 300 can be monomerized separately, for example by sawing or dicing, and bonded to each other using, for example, a PnP tool via adhesive 400.

[0040] Reference Figure 3C An encapsulation layer 500 is formed to encapsulate component members 200 and 300A. The encapsulation layer 500 laterally encapsulates the sidewalls of component members 200 and 300A, and may extend laterally to the sidewalls and top surface of the conductive pad 350 of component member 300A. The material of the encapsulation layer 500 differs from the material of the insulating layer 100. In some embodiments, the material of the encapsulation layer 500 includes molding compounds, molding underfills, resins such as epoxy resins, combinations thereof, etc. In some alternative embodiments, the material of the encapsulation layer 500 may be a polymer, such as polybenzoxazole (PBO), benzocyclobutene (BCB)-based polymers, polyimides, etc.; nitrides such as silicon nitride; oxides, such as silicon oxide, PSG, BSG, BPSG, etc.; analogs or combinations thereof, and may be formed, for example, by spin coating, lamination, CVD, etc.

[0041] Reference Figure 3D Part of the encapsulation layer 500 is removed, exposing the top surface of the conductive pad 350 of the component component 300. The removal of the encapsulation layer 500 can be performed using a planarization process, such as chemical mechanical polishing (CMP) or polishing. Subsequently, the existing structure is monolithized using processes such as dicing, laser ablation, or etching. Thus, a monolithized semiconductor component 600A is formed.

[0042] The side of the semiconductor component 600A containing the conductive pad 250, passivation layer 260, and encapsulation layer 500 can be referred to as the terminal side 600-FS of the semiconductor component 600. The side opposite to the terminal side 600-FS containing the conductive pad 250 and encapsulation layer 500 can be referred to as the terminal side 600-BS of the semiconductor component 600A. On the terminal side 600-FS of the semiconductor component 600A, the top surface of the encapsulation layer 500 is coplanar with the top surface of the passivation layer 260, and the top surface of the conductive pad 250 is lower than the top surfaces of the passivation layer 260 and the encapsulation layer 500. On the terminal side 600-BS of the semiconductor component 600A, the top surface of the encapsulation layer 500 is coplanar with the top surface of the conductive pad 350.

[0043] exist Figure 1EIn this process, the semiconductor component 600 is placed into and embedded in the cavity hole 118 of the cavity substrate 120 (e.g., Figure 1D As shown, the top surface of the passivation layer 260 and the encapsulation layer 500 are coplanar with the top surface of the conductive trace 116F. The top surface of the conductive pad 350 on the terminal side 600-BS and another top surface of the encapsulation layer 500 are lower than the top surface of the conductive trace 116B, thus forming a step S between them according to some embodiments, but not limited thereto. In an alternative embodiment, the top surface of the conductive pad 350 and another top surface of the encapsulation layer 500 on the terminal side 600-BS are coplanar with the top surface of the conductive trace 116B.

[0044] Figure 1F to 1K This illustrates a redistribution structure 180F formed on the side 100-FS of the insulating layer 100 and the terminal side 600-FS of the semiconductor component 600, and the removal of... Figure 1E The redistribution structure 180B shown is formed on the side 100-BS of the insulating layer 100 and the terminal side 600-BS of the semiconductor component 600 after the tape TP. Redistribution structures 180F and 180B each include vertically stacked alternating dielectric and conductive trace layers. Each conductive trace layer is separated from its vertically adjacent conductive trace layer by a dielectric layer. The conductive traces extend through the underlying dielectric layer to form vias for vertical interconnection of adjacent conductive traces.

[0045] exist Figure 1F In some embodiments, the dielectric layer 122 is formed over the insulating layer 100 and fills the through-holes 114 of the insulating layer 100 (e.g., Figure 1E (as shown) and in the space between the semiconductor component 600 and the adjacent insulating layer 100.

[0046] In some embodiments, the dielectric layer 122 may also be formed of a non-photosensitive material, such as Ajinomoto supplemental film (ABF), silicon nitride, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BPSG), etc. In alternative embodiments, the dielectric layer 122 is formed of a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, etc., which can be patterned using a photolithographic mask. In alternative embodiments, the dielectric layer 122 is formed of or similar materials. The dielectric layer 122 may be formed by spin coating, deposition, chemical vapor deposition (CVD), etc., or combinations thereof.

[0047] More specifically, dielectric layer 122 may include dielectric layers 122F and 122B, and dielectric plug 122P. According to some embodiments, dielectric layer 122 further includes dielectric portion 122R.

[0048] Dielectric layer 122F is located on insulating layer 100, conductive trace 116F, conductive pad 250, and passivation layer 260 and encapsulation layer 500 on terminal side 600-FS of semiconductor component 600. Dielectric layer 122B is formed on insulating layer 100, conductive trace 116B, conductive pad 35, and encapsulation layer 5000 on terminal side 600-BS of semiconductor component 600. In some embodiments, the thickness T1 of dielectric layer 122F on conductive pad 250 and the thickness T2 of dielectric layer 122B on conductive pad 350 may be non-uniform. For example, thickness T1 is less than thickness T2. In some alternative embodiments, thickness T1 is equal to thickness T2.

[0049] Dielectric plug 122P is embedded in insulating layer 100 and connected to dielectric layers 122F and 122B. Dielectric portion 122R is buried between semiconductor component 600 and adjacent insulating layer 100 and is connected to dielectric layers 122F and 122B. In some embodiments, dielectric portion 122R may be annular or semi-annular, but is not limited thereto.

[0050] exist Figure 1G In the dielectric layer 122F, vias 124F and 126F are formed to expose a portion of the conductive trace 116F in region R2 and a portion of the conductive pad 250 in region R1, respectively. In the dielectric layer 122B, vias 124B and 126B are formed to expose a portion of the conductive trace 116B in region R2 and a portion of the conductive pad 350 in region R1, respectively. In some embodiments where thickness T1 is less than thickness T2 (e.g., ...), ... Figure 1F As shown), the width W1 of the via 126F and the width W2 of the via 126B may be different. For example, the width W1 is smaller than the width W2. In some embodiments, the thickness T1 is equal to the thickness T2 (e.g., ...). Figure 1F As shown in the figure), the width W1 is equal to the width W2.

[0051] In some embodiments, vias 124F, 126F, 124B, and 126B are formed by laser drilling, while the dielectric layer 122 is formed from a non-photosensitive material such as an ajinomoto supplemental film (ABF). In alternative embodiments, vias 124F, 126F, 124B, and 126B are formed by a patterning process using a patterned photoresist mask via a suitable etching process (e.g., anisotropic reactive ion etching). In other embodiments, when the dielectric layer 122 is a photosensitive material, vias 124F, 126F, 124B, and 126B can be formed by exposing the dielectric layer 122.

[0052] Figure 1H to 1JThe diagram shows a metallization pattern M11 formed on and extending through a patterned dielectric layer 122F, and a metallization pattern M21 formed on and extending through a patterned dielectric layer 122B. In some embodiments, the metallization patterns M11 and M21 are formed by first forming a metal seed layer 128F on the dielectric layer 122F and a metal seed layer 128B on the dielectric layer 122B. The metal seed layers 128F and 128B may be referred to as seed layers 128F and 128B.

[0053] Reference Figure 1H Specifically, seed layer 128F is formed on dielectric layer 122F, on the sidewalls of vias 124F and 126F passing through dielectric layer 122F, and on the exposed portions of conductive trace 116F at the bottom of via 124F and conductive pad 250 at the bottom of via 126F. Seed layer 128B is formed on dielectric layer 122B, on the sidewalls of vias 124B and 126B passing through dielectric layer 122B, and on the exposed portions of conductive trace 116B at the bottom of via 124B and conductive pad 350 at the bottom of via 126B. Seed layers 128F and 128B can each include one or more layers of conductive material, such as a composite layer of copper or titanium layers and a copper layer above a titanium layer. Layers of other conductive materials or composite layers of several other conductive materials can also be used to form the seed layer. Any suitable deposition process (e.g., physical vapor deposition (PVD), CVD, etc.) can be used to form a seed layer.

[0054] exist Figure 1H Then, patterned mask layers 130F and 130B, such as patterned photoresist mask layers, are formed above the seed layers 128F and 128B, respectively, to expose portions of the seed layers 128F and 128B to the openings 132F and 132B in the patterned mask layers 130F and 130B.

[0055] Referring to 1I, a conductive layer 138F is formed on the exposed portion of the seed layer 128F in the opening 132F of the patterned mask layer 130F. A conductive layer 138B can be formed on the exposed portion of the seed layer 128B in the opening 132B of the patterned mask layer 130B. The materials used to form the conductive layers 138F and 138B can include metals such as copper, titanium, tungsten, and aluminum, and can be deposited using suitable deposition processes, such as electroplating or electroless plating.

[0056] exist Figure 1J In the process, after the conductive layers 138F and 138B are formed by the deposition process, the patterned mask layers 130F and 130B (such as...) are then applied. Figure 1I(As shown) The photoresist pattern is stripped using acceptable processes such as ashing or exposure to oxygen plasma. The photoresist pattern is stripped away, exposing portions of the seed layers on which no material deposited using the photoresist mask has formed. These exposed portions of the seed layers 128F and 128B can be removed using any acceptable chemical etching process (e.g., wet chemical etching or plasma etching). The remaining portions of the seed layer 128F and conductive layer 138F are contained within the metallization pattern M11. The remaining portions of the seed layer 128B and conductive layer 138B are contained within the metallization pattern M21.

[0057] The metallization pattern M11 includes conductive traces t11 and t11' formed along the top surface of the dielectric layer 122F, and vias V11 and V11' passing through the dielectric layer 122F. Via V11 is formed in region R2 and connects the conductive trace t11 of the metallization pattern M11 to the conductive trace 116F. Via V11' is formed in region R1 and electrically and physically connects the conductive trace t11' of the metallization pattern M11 to the conductive pad 250 of the semiconductor component 600.

[0058] The metallization pattern M21 includes conductive traces t21 and t21' formed along the top surface of the dielectric layer 122B, and vias V21 and V21' passing through the dielectric layer 122B. Via V21 is formed in region R2 and connects the conductive trace t21 of the metallization pattern M21 to the conductive trace 116B directly below the dielectric layer 122B. Via V21' is formed in region R1 and connects the conductive trace t21' of the metallization pattern M21 to the conductive pad 350 of the semiconductor component 600.

[0059] In some embodiments, the width W11' of the via V11' may be different from the width W21' of the via V21'. For example, the width W11' is smaller than the width W21'. In other embodiments, the width W11' of the via V11' in region R1 may be different from the width W11 of the via V11 in region R2. The width W21' of the via V21' in region R1 may be different from the width W21 of the via V21 in region R2. For example, the width W11' is greater than the width W11, and the width W21' is greater than the width W21.

[0060] Patterned dielectric layers 122F and 122B (e.g.) are formed Figure 1G (as shown) and conductive traces t11, t11', t21 and t21' and metallization patterns M11 and M21 (as shown) Figures 1H to 1IThe method of using vias V11, V11', V21, and V21' (shown) is described as an example. It should be understood that the processes used to form dielectric layers 122F and 122B, and metallization patterns M11 and M21, can vary based on design specifications, such as the desired minimum size of the patterns. For example, in some embodiments, a damascene process (single damascene or dual damascene) may be used. Both redistribution structures 180F and 180B can be constructed by vertically stacking more dielectric and metallization patterns.

[0061] Figure 1K The diagram shows a patterned dielectric layer 142F formed on the top surface of dielectric layer 122F and metallization pattern M11, and a patterned dielectric layer 142B formed on the top surface of dielectric layer 122B and metallization pattern M21.

[0062] Figure 1K The image also shows metallization patterns M12 and M22. Metallization pattern M12 includes conductive traces t12 and t12' formed along the top surface of dielectric layer 142F, and vias V12 and V12' formed through dielectric layer 142F. The vias V12 and V12' of metallization pattern M12 connect the conductive traces t12 and t12' of metallization pattern M12 to a metal pattern directly below dielectric layer 142F (e.g., metallization pattern M11), respectively. Metallization pattern M22 includes conductive traces t22 and t22' formed along the top surface of dielectric layer 142B, and vias V22 and V22' formed through dielectric layer 142B. The vias V22 and V22' of the metallized pattern M22 connect the conductive traces t22 and t22' of the metallized pattern M22 to the metal pattern directly below the dielectric 142B (e.g., the metallized pattern M21).

[0063] In some embodiments, the width W12' of the via V12' may be the same as or different from the width W12 of the via V12, and may also be different from the width W11' of the via V11'. The width W22' of the via V22' may be the same as or different from the width W22 of the via V22, and may also be different from the width W21' of the via V21'. For example, the width W12' is equal to the width W12 and less than the width W11'; the width W22' is equal to the width W22 and less than the width W21'.

[0064] In some embodiments, the width W13' of the via V13' may be the same as or different from the width W13 of the via V13, and may be the same as or different from the width W12' of the via V12'. The width W23' of the via V23' may be the same as or different from the width W23 of the via V23, and may be the same as or different from the width W22' of the via V22'. For example, the width W13' is equal to the widths W13 and W12'; while the width W23' is equal to the widths W23 and W22'.

[0065] Figure 1K Also shown is a patterned dielectric layer 162F formed on the top surface of dielectric layer 142F and metallization pattern M12, and a patterned dielectric layer 162B formed on the top surface of dielectric layer 142B and metallization pattern M22.

[0066] Figure 1K The image also shows metallization patterns M13 and M23. Metallization pattern M13 includes conductive traces t13 and t13' formed along the top surface of dielectric layer 162F, and vias V13 and V13' formed through dielectric layer 162F. The vias V13 and V13' of metallization pattern M13 connect the conductive traces t13 and t13' of metallization pattern M13 to a metal pattern directly below dielectric layer 162F (e.g., metallization pattern M12), respectively. Metallization pattern M23 includes conductive traces t23 and t23' formed along the top surface of dielectric layer 162B, and vias V23 and V23' formed through dielectric layer 162B. The vias V23 and V23' of the metallized pattern M23 connect the conductive traces t23 and t23' of the metallized pattern M23 to the metal pattern directly below the dielectric layer 162B (e.g., the metallized pattern M22), respectively.

[0067] In some embodiments, one of the vias V13' is directly stacked on the via V12', and the via V12' is directly stacked on the via V11' to form a stacked via SV1'. Furthermore, vias V23', V22', and V21' may or may not form a stacked via SV2'. Vias V13, V12, and V11 may or may not form a stacked via SV1. Vias V23, V22, and V21 may or may not be combined to form a stacked via SV2.

[0068] The processes and materials used to form dielectric layers 142F, 142B, 162F, and 162B, and metallization patterns M12, M22, M13, and M23 can be repeated to form dielectric layers 122F and 122B, and metallization patterns M11 and M12. More or fewer dielectric layers and metallization patterns can be formed in the redistribution structures 180F and 180B. To form fewer dielectric layers and metallization patterns, the steps and processes discussed above can be omitted. To form more dielectric layers and metallization patterns, the steps and processes discussed above can be repeated.

[0069] Reference Figure 1L In some embodiments, a protective layer 182F (e.g., solder resist) is formed over the metallization pattern M13 and the dielectric layer 162F to protect the exposed areas of the dielectric layer 162F from external damage. A protective layer 180B (e.g., solder resist) is formed over the metallization pattern M23 and the dielectric layer 162B to protect the exposed areas of the dielectric layer 162B from external damage. In some embodiments, protective layers 182F and 182B are formed by depositing a photosensitive material, exposing the layer with an optical pattern, and then developing the exposed layer to form openings 184F and 184B, respectively. In other embodiments, protective layers 182F and 182B can both be formed by depositing a non-photosensitive dielectric layer (e.g., silicon oxide or silicon nitride), forming a patterned photoresist mask on the dielectric layer using photolithography, and etching the dielectric using a suitable etching process (e.g., dry etching), respectively. Other processes and materials may also be used. Opening 184F exposes the lower portion of conductive trace t13', which can be used as conductive pad P13' to which conductive connectors (e.g., chip connectors) can be attached. Opening 184B exposes the bottom portion of conductive traces t23 and t23', which can be used as conductive pad P23' to which external connectors can be attached.

[0070] exist Figure 1MIn some embodiments, conductive connectors 188F are formed on conductive pad P13' to form package substrate 190A. Conductive connectors 188F may be ball grid array (BGA) connectors, solder balls, conductive pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed by electroless nickel-palladium immersion gold (ENEPIG) technology, etc. Conductive connectors 188F may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, conductive connectors 188F are initially formed by processes such as evaporation, electroplating, printing, solder transfer, ball placement, etc., to form a solder layer. Once the solder layer is structurally formed, reflow can be performed to shape the solder material into the desired bump shape. In another embodiment, the conductive connector 188F is a conductive pillar (such as a copper pillar) formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The conductive pillar can be solderless and has substantially vertical sidewalls. In some embodiments, a metal capping layer (not shown) is formed on top of the conductive pillar. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or combinations thereof, and can be formed by an electroplating process.

[0071] Figure 1N The diagram illustrates, according to some embodiments, the use of conductive connector 188F to bond package substrate 190A to component 191. Component 191 may be made of a semiconductor material, such as silicon, germanium, compound semiconductor, or alloy semiconductor; it may be doped or undoped; or it may be an active layer in an insulating layer-over-insulator (SOI) substrate. Component 191 may include a chip, package, package substrate, interposer, PCB, etc. For example, component 191 may be a chip.

[0072] Component 191 may include active and passive component components (not shown). Various component components, such as transistors, capacitors, resistors, combinations thereof, etc., can be used to create the integrated circuits included in the package substrate 190A or any other package connected to the package substrate 190A to form a multi-chip module, to meet structural and functional requirements. Component components can be formed using any suitable method.

[0073] Component 191 may also include a metallization layer and vias (not shown), and pads 193 above the metallization layer and vias. The metallization layer may be formed over active and passive component components and is designed to connect various component components to form functional circuitry. The metallization layer may be formed of alternating layers of dielectric (e.g., a low-dielectric-constant dielectric material) and conductive material (e.g., copper), wherein vias interconnect the conductive material layers and can be formed by any suitable process (e.g., deposition, damascene, dual damascene, or similar). Electronic component components and interconnect systems can be formed using any suitable method.

[0074] In some embodiments, component 191 may be an integrated circuit, such as a memory integrated circuit, a PMIC, a digital logic integrated circuit, an RFIC, etc. Conductive connector 188F electrically and / or physically couples the package substrate 190A to component 191, including a metallization layer in component 191.

[0075] In some embodiments, conductive connector 188F is reflowed to attach package substrate 190A to pads 193 of component 191. In some embodiments, component 191 has conductive connector 195 that can be attached to conductive connector 188F of package substrate 190A to electrically couple component 191 to package substrate 190A. Before reflow, conductive connector 188F may have an epoxy flux (not shown) formed thereon, and at least some epoxy portion of the epoxy flux remains after package substrate 190A is attached to component 191. The remaining epoxy portion can serve as an underfill to reduce stress and protect contacts created by reflowing conductive connector 188F. In some embodiments, an underfill (not shown) is formed between package substrate 190A and component 191 surrounding conductive connector 188F. The underfill can be formed by a capillary flow process after attaching the encapsulation substrate 190A, or by a suitable deposition method before attaching the encapsulation substrate 190A.

[0076] Reference Figure 10 In some embodiments, a conductive connector 188B formed on the conductive pad P23' of the conductive trace t23' located on side 100-BS and terminal side 600-FS is used to bond the package substrate 190A to the additional member 196. The additional member 196 can be electrically coupled to the package substrate 190A by attaching the connection pad 198 of the member 196 to the conductive connector 188B of the package substrate 190A. In some embodiments, the additional member 196 has a conductive connector (not shown) that can be attached to the conductive connector 188B of the package substrate 190A to electrically couple the additional member 196.

[0077] The capacitors 210 and 310 of the semiconductor component 600 can be coupled in parallel or series via redistribution structures 180F and 180B and / or vias in the metallization layer and component 191. In some embodiments where capacitors 210 and 310 are connected in parallel, they are coupled to a first electrical terminal, such as a negative power supply voltage (V), via redistribution structures 180F and 180B, bump base metal 186F, conductive connector 188F, and pad 193, with conductive pads 250s and 350s. SS Conductive pads 250d and 350d are coupled to the second electrical terminal, for example, the positive power supply voltage (V). DD ).

[0078] According to some embodiments, conductive pads 250s and 350s are electrically connected to each other in the packaging substrate 190A via redistribution structures 180F and 180B, and then coupled to a first electrical terminal, such as a negative power supply voltage (V). SS The conductive pads 250d and 350d are interconnected with the package substrate 190A via redistribution structures 180F and 180B, and then coupled to a second electrical terminal, such as a positive power supply voltage (V). DD ).

[0079] According to an alternative embodiment, conductive pads 250s and 350s are electrically isolated from each other in the packaging substrate 190A, but interconnected through a metallization layer and a via in component 191 to couple to a first electrical terminal, such as a negative power supply voltage (V). SS The conductive pads 250d and 350d are isolated from each other in the package substrate 190A, but interconnected through the metallization layer and the via layer of component 191 to couple to a second electrical terminal, such as a positive power supply voltage (V). DD ).

[0080] The semiconductor component 600 can be composed of various component parts. In some alternative embodiments, the semiconductor component 600 can be... Figure 5A The semiconductor component 600B is shown in the figure. A more detailed structure of the semiconductor component 600B is shown in the figure. Figure 5B middle.

[0081] Reference Figure 5A and 5B Semiconductor component 600B may include component members 200 and 300B. Component member 200 is bonded to component member 300B in a back-to-back manner by adhesive 400. Semiconductor component 600B does not... Figure 3D The encapsulation layer 500 shown exposes the sidewalls of components 200 and 300B and the adhesive 400.

[0082] exist Figure 5A and 5BIn this context, component 200 can be a passive component, and can be similar to... Figure 4A Component member 200 is shown. Component member 300A can be a passive component and can be similar to... Figure 4A The component component 200 is shown in the diagram. In some embodiments, component component 300B includes a semiconductor substrate 302, a capacitor 310, an interconnect structure 330, a conductive pad 350, and a passivation layer 360. The semiconductor substrate 302, capacitor 310, interconnect structure 330, conductive pad 350, and passivation layer 360 of component component 300B may be similar to the corresponding components of component component 200. Passivation layer 360 is formed on the dielectric layer of interconnect structure 330 and a portion of conductive pad 350. Passivation layer 360 may be or include, for example, silicon oxide, silicon nitride, polyimide, some other suitable dielectric, or any combination thereof. In some embodiments, the top regions A3 of conductive pad 350 are each larger than the top regions A2 of conductive pad 250, such as... Figure 4B As shown, but not limited to.

[0083] Reference Figure 5C The diagram illustrates, according to some embodiments, the use of conductive connector 188F to bond the package substrate 190B to the component 191, and the use of conductive connector 188b to bond the package substrate 190B to the component 196. The package substrate 190B is similar to the package substrate 190A, but the semiconductor component 600A is replaced by the semiconductor component 600B.

[0084] exist Figure 5C In the process, semiconductor component 600B is encapsulated by dielectric part 122R, and component components 200 and 300B of semiconductor component 600B and sidewalls of adhesive 400 are in physical contact with dielectric part 122R.

[0085] The semiconductor component 600 can vary according to design specifications. The semiconductor component 600 can be composed of two or more layers (not shown). In some embodiments, the semiconductor component 600 is composed of two layers, including an upper component member (e.g., Figure 3D and 5A The component member 200 shown) and a lower component member (e.g. Figure 3D and 5A The component 300 shown is a semiconductor component 600. The semiconductor component 600 may be a semiconductor component 600C, consisting of two or more upper component components (e.g., component components 2001 and 2002) and a lower component component (e.g., component component 3001), as shown. Figure 6A As shown. According to some alternative embodiments, semiconductor component 600 may be semiconductor component 600D, which is composed of two or more upper component members (e.g., component members 2001 and 2002) and two or more lower component members (e.g., component members 3001 and 3002), as shown. Figure 6B As shown. Components 2001, 2002, 3001, and 3002 may have the same or different dimensions and shapes. Components 2001 and 2002 may be separated by an encapsulation layer 5001, while components 3001 and 3002 may be separated by another encapsulation layer 5002. Components 2001, 2002, 3001, and 3002 and the adhesive 400 may or may not be encapsulated by the encapsulation layer 500. Components 2001, 2002, 3001, and 3002 may each be a passive or active component. Components 2001, 2002, 3001, and 3002 may be the same or different types of passive components. Components 2001 and 2002 may be similar to or different from component 200, while components 3001 and 3002 may be similar to or different from component 300.

[0086] Embedding semiconductor components with dual-sided electrical terminals within a package substrate allows for coupling of components to the package substrate via a redistribution structure, providing greater integration capabilities, as exemplified by the embodiments discussed herein. Embodiments (such as those discussed here) also offer improved via / dielectric design to prevent reliability issues.

[0087] According to some embodiments, a packaging substrate is provided. The packaging substrate includes a substrate having a cavity via therein and a semiconductor component within the cavity via. The semiconductor component has a first terminal side and a second terminal side opposite to the first terminal side. The packaging substrate also includes a first rewiring structure on the first terminal side of the cavity substrate to electrically couple a first pad and a second pad on the first terminal side of the semiconductor component; and a second rewiring structure on the second side of the cavity substrate to electrically couple a third pad and a fourth pad on the second terminal side of the semiconductor component.

[0088] In some embodiments, the semiconductor component includes: a first component member having a first pad, a second pad, and a first trench capacitor; a second component member having a third pad, a fourth pad, and a second trench capacitor; and an adhesive inserted between the back side of the first component member and the back side of the second component member. In some embodiments, the first pad of the first component member connects to a first electrode and a first terminal of the first trench capacitor, the second pad of the first component member connects to a second electrode and a second terminal of the first trench capacitor; and the third pad of the second component connects to a third electrode and the first terminal of the second trench capacitor, and the fourth pad of the second component connects to a fourth electrode and the second terminal of the second trench capacitor. In some embodiments, the first component member further includes a passivation layer on a portion of the first pad and the second pad. In some embodiments, the semiconductor component further includes: an encapsulation layer laterally encapsulating the first component member, the second component member, and the adhesive, wherein the encapsulation layer contacts the sidewalls of the passivation layer, the sidewalls of the second component member, and the sidewalls of the fourth pad. In some embodiments, the area of ​​the first pad is smaller than the area of ​​the third pad, and the area of ​​the second pad is smaller than the area of ​​the fourth pad; the first redistribution structure includes a first via connecting the first pad and a second via connecting the second pad; and the second redistribution structure includes a third via connecting the third pad and a fourth via connecting the fourth pad, wherein the width of the first via and the second via is smaller than the width of the third via and the fourth via. In some embodiments, the height of the first via and the second via is smaller than the height of the third via and the fourth via. In some embodiments, the width of the first via is greater than the width of a fifth via of the first redistribution structure outside the region of the first component member. In some embodiments, the first component member further includes a first passivation layer on a portion of the first pad and the second pad; the second component member further includes a second passivation layer on a portion of the third pad and the fourth pad; and the package substrate further includes a dielectric layer filling the cavity, wherein the dielectric layer contacts the first component member, the second component member, and the sidewalls of the adhesive of the semiconductor assembly. In some embodiments, the substrate has a via; the substrate further includes conductive traces extending from a first side of the substrate through the sidewalls of the via to a second side of the substrate, and the dielectric layer further fills the via.

[0089] According to another embodiment, a package is provided. The package includes components that are bonded to and electrically coupled to a package substrate, wherein the package substrate includes: a cavity substrate having a cavity aperture therein; a semiconductor component in the cavity aperture, wherein the semiconductor component has a first component component and a second component component bonded back-to-back, the first component component including a first capacitor and the second component component including a second capacitor; a first rewiring structure on a first side of the cavity substrate electrically coupled to a first electrode and a second electrode of the first capacitor; and a second rewiring structure on a second side of the cavity substrate electrically coupled to a third electrode and a fourth electrode of the second capacitor. A first pad and a third pad are coupled to a first terminal, and a second pad and a fourth pad are coupled to a second terminal via the first and second rewiring structures.

[0090] In some embodiments, the first capacitor and the second capacitor comprise trench metal-insulator-metal (MIM) capacitors. In some embodiments, the first redistribution structure comprises: a first via, within a region of the semiconductor component; and a second via, outside the region of the semiconductor component, wherein the size of the first via is larger than the size of the second via. In some embodiments, the first redistribution structure comprises: a first stacked via connecting the first pad of the first component component; and a second stacked via connecting the second pad of the first component component.

[0091] According to yet another embodiment, a method for manufacturing a semiconductor component is provided. The method includes: providing a semiconductor component; placing the semiconductor component in a cavity aperture of a cavity substrate, wherein the semiconductor component has a first terminal side and a second terminal side opposite to the first terminal side; forming a dielectric layer along a sidewall of the semiconductor component, the first terminal side, the second terminal side, the cavity aperture of the cavity substrate, the first side, and the second side opposite to the first side; forming a first rewiring structure on the first side of the cavity substrate to electrically couple to the first terminal side of the semiconductor component; and forming a second rewiring structure on the second side of the cavity substrate to electrically couple to the second terminal side of the semiconductor component.

[0092] In some embodiments, the method of forming a semiconductor structure further includes forming the cavity substrate, wherein forming the cavity substrate includes: forming a via in the substrate; forming a conductive layer on the sidewalls of the via and on a first side and a second side of the substrate; patterning the conductive layer to form conductive traces; and forming the cavity via in the substrate after forming the conductive traces. In some embodiments, providing the semiconductor component includes: providing a first component member having a first terminal side and a first trench capacitor; providing a second component member having a second terminal side and a second trench capacitor; and bonding the back side of the first component member to the back side of the second component member using an adhesive. In some embodiments, the first component member has a first pad and a second pad, the first pad connecting a first electrode and a first terminal of the first trench capacitor, the second pad connecting a second electrode and a second terminal of the first trench capacitor; and the second component member has a third pad and a fourth pad, the third pad connecting a third electrode and the first terminal of the second trench capacitor, the fourth pad connecting a fourth electrode and the second terminal of the second trench capacitor. In some embodiments, the method of forming a semiconductor structure further includes: laterally encapsulating the first component member, the second component member, and the adhesive with an encapsulation layer. In some embodiments, the dielectric layer is formed to further fill the cavity holes of the cavity substrate and to contact the sidewalls of the first component member, the second component member, and the adhesive.

[0093] Several embodiments of the features have been outlined above to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and therefore various changes, substitutions, and variations can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A package substrate, characterized by include: Substrate, the substrate including a cavity aperture; A semiconductor component embedded in the cavity, wherein the semiconductor component has a first terminal side and a second terminal side opposite to the first terminal side; The first wiring structure is electrically coupled to a first pad and a second pad on the first terminal side of the semiconductor component on a first side of the substrate. as well as The second wiring structure is electrically coupled to the third and fourth pads on the second terminal side of the semiconductor component on the second side of the substrate. The semiconductor component includes: The first component has the first pad, the second pad, and the first trench capacitor; as well as The second component has the third pad, the fourth pad, and the second trench capacitor, wherein the back side of the first component is bonded to the back side of the second component. The first pad of the first component connects to the first electrode and the first terminal of the first trench capacitor, and the second pad of the first component connects to the second electrode and the second terminal of the first trench capacitor; and The third pad of the second component is connected to the third electrode of the second trench capacitor and the first terminal, and the fourth pad of the second component is connected to the fourth electrode of the second trench capacitor and the second terminal.

2. The packaging substrate of claim 1, wherein the semiconductor component comprises: An adhesive is inserted between the back surface of the first component and the back surface of the second component and adheres to the back surface of the first component and the back surface of the second component.

3. The packaging substrate according to claim 2, wherein: The first component further includes a passivation layer on portions of the first pad and the second pad.

4. The packaging substrate according to claim 3, wherein: The semiconductor component further includes: an encapsulation layer that laterally encapsulates the first component member, the second component member, and the adhesive, wherein the encapsulation layer is in contact with the sidewall of the passivation layer, the sidewall of the third pad of the second component member, and the sidewall of the fourth pad of the second component member.

5. The packaging substrate according to claim 2, wherein the area of ​​the first pad is smaller than the area of ​​the third pad, and the area of ​​the second pad is smaller than the area of ​​the fourth pad; The first rewiring structure includes a first through-hole connecting the first pad and a second through-hole connecting the second pad; and The second rewiring structure includes a third via connected to the third pad and a fourth via connected to the fourth pad. The widths of the first through hole and the second through hole are smaller than the widths of the third through hole and the fourth through hole.

6. The packaging substrate according to claim 5, wherein the heights of the first through-hole and the second through-hole are less than the heights of the third through-hole and the fourth through-hole.

7. The packaging substrate of claim 5, wherein the width of the first via is greater than the width of the fifth via of the first redistribution structure outside the region of the first component member.

8. The packaging substrate according to claim 2, wherein: The first component further includes a first passivation layer on portions of the first pad and the second pad; The second component further includes a second passivation layer on portions of the third and fourth pads; as well as The packaging substrate further includes a dielectric layer filling the cavity, wherein the dielectric layer is in contact with the first component member, the second component member, and the sidewall of the adhesive of the semiconductor assembly.

9. The packaging substrate of claim 8, wherein the substrate has a through-hole; the substrate further includes conductive traces extending from a first side of the substrate through a sidewall of the through-hole to a second side of the substrate, and the dielectric layer further fills the through-hole.

10. A package, characterized in that... include: A component that is bonded to and electrically coupled to a packaging substrate, wherein the packaging substrate includes: A cavity substrate, wherein the cavity substrate includes a cavity hole; A semiconductor component is embedded in the cavity, wherein the semiconductor component has a first component member and a second component member joined back to back, the first component member including a first pad, a second pad and a first capacitor, and the second component member including a third pad, a fourth pad and a second capacitor. A first wiring structure electrically couples the first electrode and the second electrode of the first capacitor on a first side of the cavity substrate; and The second wiring structure electrically couples the third and fourth electrodes of the second capacitor on the second side of the cavity substrate. The first pad and the third pad are coupled to the first terminal, and the second pad and the fourth pad are coupled to the second terminal through the first rewiring structure and the second rewiring structure.

11. The package of claim 10, wherein the first capacitor and the second capacitor comprise trench metal-insulator-metal capacitors.

12. The package of claim 10, wherein the first rewiring structure comprises: The first via is located within the region of the semiconductor component; as well as The second via is located outside the region of the semiconductor component. The size of the first through hole is larger than the size of the second through hole.

13. The package of claim 10, wherein the first rewiring structure comprises: A first stacked via is connected to the first pad of the first component; as well as The second stacked via connects to the second pad of the first component.

14. The package of claim 10, wherein: The first component further includes a passivation layer on portions of the first pad and the second pad.

15. The package of claim 14, wherein: The semiconductor component further includes: an encapsulation layer that laterally encapsulates the first component member and the second component member, wherein the encapsulation layer contacts the sidewall of the passivation layer and the sidewall of the third pad and the sidewall of the fourth pad of the second component member.

16. A method for forming a semiconductor structure, characterized in that... The method includes: Provide semiconductor components; The semiconductor component is placed in a cavity hole of a cavity substrate, wherein the semiconductor component has a first terminal side and a second terminal side opposite to the first terminal side; A dielectric layer is formed along the sidewall of the semiconductor component, the first terminal side and the second terminal side, as well as the cavity hole, the first side and the second side opposite to the first side of the cavity substrate; A first rewiring structure is formed on the first side of the cavity substrate to electrically couple the first terminal side of the semiconductor assembly; and A second rewiring structure is formed on the second side of the cavity substrate to electrically couple the second terminal side of the semiconductor component. The provision of the semiconductor component includes: Provides a first component having the first terminal side and a first trench capacitor; and A second component is provided, having the second terminal side and the second trench capacitor. The first component has a first pad and a second pad, the first pad connecting the first electrode and the first terminal of the first trench capacitor, and the second pad connecting the second electrode and the second terminal of the first trench capacitor. The second component has a third pad and a fourth pad, the third pad being connected to the third electrode of the second trench capacitor and the first terminal, and the fourth pad being connected to the fourth electrode of the second trench capacitor and the second terminal.

17. The method of forming a semiconductor structure according to claim 16, further comprising forming the cavity substrate, wherein forming the cavity substrate comprises: Forming perforations in the substrate; A conductive layer is formed on the sidewall of the perforation and on the first and second sides of the substrate; The conductive layer is patterned to form conductive traces; as well as After the conductive traces are formed, the cavity holes are formed in the substrate.

18. The method of forming a semiconductor structure according to claim 16, wherein providing the semiconductor component comprises: The back side of the first component is bonded to the back side of the second component using an adhesive.

19. The method for forming a semiconductor structure according to claim 18, further comprising: The first component, the second component, and the adhesive are laterally encapsulated by an encapsulation layer.

20. The method for forming a semiconductor structure according to claim 18, wherein: The dielectric layer is further formed to fill the cavity holes of the cavity substrate and to contact the sidewalls of the first component, the second component, and the adhesive.

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