Semiconductor component

Abstract

A semiconductor assembly includes a semiconductor die, a first conductive pad, a second conductive pad, a first connector structure, and a second connector structure. The first conductive pad is disposed on the semiconductor die, where the first conductive pad has a first lateral dimension. The second conductive pad is disposed on the semiconductor die, where the second conductive pad has a second lateral dimension. The first connector structure is disposed on the first conductive pad, where the first connector structure has a third lateral dimension that is greater than the first lateral dimension. The second connector structure is disposed on the second conductive pad, where a fourth lateral dimension of the second connector structure is less than the second lateral dimension.

Description

Technical Field

[0001] This disclosure relates to a semiconductor component. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration of various electronic components, such as transistors, diodes, resistors, and capacitors. In most cases, this improvement in integration stems from iterative reductions in the minimum feature size, allowing more components to be integrated into a given area. In other words, semiconductor components require better performance, reliability, and yield. Summary of the Invention

[0003] The embodiments disclosed herein relate to a semiconductor assembly including a semiconductor die, a first conductive pad, a second conductive pad, a first connector structure, and a second connector structure. The first conductive pad is disposed on the semiconductor die, wherein the first conductive pad has a first lateral dimension. The second conductive pad is disposed on the semiconductor die, wherein the second conductive pad has a second lateral dimension. The first connector structure is disposed on the first conductive pad, wherein the first connector structure has a third lateral dimension larger than the first lateral dimension. The second connector structure is disposed on the second conductive pad, wherein the second connector structure has a fourth lateral dimension smaller than the second lateral dimension. The fourth lateral dimension is the same as the third lateral dimension. The semiconductor assembly further includes a passivation layer disposed on the semiconductor die and covering the sidewalls of the first conductive pad and the sidewalls of the second conductive pad. The passivation layer is located between a portion of the first conductive pad and a portion of the first connector structure, and between a portion of the second conductive pad and a portion of the second connector structure. The semiconductor assembly further includes a protective layer disposed on the semiconductor die. The protective layer has a first opening above a first conductive pad and a second opening above a second conductive pad. A first connector structure is connected to the first conductive pad through the first opening, and a second connector structure is connected to the second conductive pad through the second opening. The first connector structure includes a first bump base metal (UBM) layer and a first columnar bump disposed on the first UBM layer. The second connector structure includes a second UBM layer and a second columnar bump disposed on the second UBM layer. The second conductive pad is located further from a corner of the semiconductor die than the first conductive pad. The distance between the first conductive pad and the corner of the semiconductor die is less than or equal to 0.04 times the length of the sidewall edge of the semiconductor die.

[0004] Another embodiment of this disclosure relates to a semiconductor assembly including a semiconductor die, a first conductive pad, a second conductive pad, a first connector structure, and a second connector structure. The first conductive pad is disposed on an upper first region of the semiconductor die. The second conductive pad is disposed on a second region of the semiconductor die, the second region being further away from a corner of the semiconductor die than the first region, wherein the first conductive pad has a first lateral dimension, and the second conductive pad has a second lateral dimension larger than the first lateral dimension. The first connector structure is disposed on the first conductive pad. The second connector structure is disposed on the second conductive pad. The first connector structure includes a first UBM layer and a first columnar bump disposed on the first UBM layer, and the second connector structure includes a second UBM layer and a second columnar bump disposed on the second UBM layer. The first connector structure and the second connector structure have the same lateral dimension. The distance between the first conductive pad and the corner of the semiconductor die is less than or equal to 0.04 times the length of the sidewall edge of the semiconductor die. The first connector structure has a third lateral dimension, and the second connector structure has a fourth lateral dimension identical to the third lateral dimension. The semiconductor assembly further includes a passivation layer disposed on the semiconductor die and covering the sidewalls of the first conductive pad and the second conductive pad. The passivation layer is located between a portion of the first conductive pad and a portion of the first connector structure, and between a portion of the second conductive pad and a portion of the second connector structure.

[0005] Another embodiment of this disclosure relates to a semiconductor assembly including a semiconductor die, a plurality of first conductive pads, a plurality of second conductive pads, a plurality of first connector structures, and a plurality of second connector structures. The first conductive pads are disposed on a first region of the semiconductor die, wherein two of the first conductive pads have different lateral dimensions. Second conductive pads are disposed on a second region of the semiconductor die, and the second region is farther from a corner of the semiconductor die than the first region. First connector structures are disposed on the first conductive pads, wherein the lateral dimension of each of the first connector structures is larger than that of the corresponding first conductive pad. Second connector structures are disposed on the second conductive pads. The semiconductor assembly further includes a passivation layer disposed on the semiconductor die and covering the sidewalls of the first and second conductive pads. The passivation layer is located between portions of the first conductive pads and portions of the first connector structures, and between portions of the second conductive pads and portions of the second connector structures. The lateral dimension of each of the second connector structures is smaller than that of the corresponding second conductive pad. The semiconductor assembly further includes a first solder mask and a second solder mask, the first solder mask being disposed on the first connector structure, and the second solder mask being disposed on the second connector structure. Attached Figure Description

[0006] The best understanding of all aspects of this disclosure can be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 A schematic plan view of a semiconductor component according to some embodiments of the present disclosure is shown.

[0008] Figure 2 and Figure 3 The arrangement of conductive pads and connector structures are illustrated using planar diagrams of semiconductor components.

[0009] Figure 4 A plan view of a semiconductor component according to some embodiments of the present disclosure is shown schematically.

[0010] Figure 5 A semiconductor component is schematically illustrated according to some embodiments of the present disclosure.

[0011] Figure 6 The arrangement of conductive pads is schematically shown in a plan view of a semiconductor component.

[0012] Figure 7 A cross-sectional view of a semiconductor component according to some embodiments of the present disclosure is shown schematically.

[0013] Figure 8 schematically shown Figure 7 The semiconductor die 410 is shown in the figure.

[0014] Figure 9 A partial plan view of a conductive pad layer within a semiconductor component according to some embodiments of the present disclosure is schematically shown.

[0015] Figure 10 A partial plan view of a conductive pad layer within a semiconductor component according to some other embodiments of the present disclosure is schematically shown.

[0016] [Explanation of Symbols] 100, 200, 300, 400, 600, 700: Semiconductor Components 100A: Closest to the corner 110, 410, 610, 710: Semiconductor dies 110A, 600A, 700A: Corner 120, 320, 320A, 320B, 420: First conductive pad 130, 430: Second conductive pad 140, 440: First connecting member structure 150, 450: Second connecting member structure 440E, 450E: Edge 442, 452: Layers 444: First columnar protrusion 454: Second columnar protrusion 460: First passivation layer 460A, 470A: First opening 460B, 470B: Second opening 470: Second passivation layer 480: Protective layer 480A: Third opening 480B: Fourth opening 492: First Solder Cover 494: Second Solder Cover 500: Semiconductor substrate 502: Fin Structure 504: Metal gate stack 504a: Gate dielectric layer 504b: Gate 506: Spacer wall assembly 508: Extensional Structure 510: Etching Stop Layer 512, 516: Dielectric layer 514, 518a, 518b: Contact 520, 630, 730, 732, 734, 736: Conductive wiring 522: Work Function Layer 620, 720: Conductive pads 640, 740: Connector structure BRC1: Boundary D1, D1A, D1B: First lateral dimension D2: Second lateral dimension D3: Third lateral dimension D4: Fourth lateral dimension D5: Lateral dimension F1, F2, F3, F5: Distance FA: Stress LC: Distribution range LS: Length RC1, RC2, RC3, RC4, RC5, RC6: Corner Area RM, RM1, RM3, RM4: Central Area S730A, S730B: Spacing SE: Sidewall Edge W630, W732, W734: Line width X1, X2: Intersection Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or examples to implement various features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or over a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout this disclosure. Such repetition is for the purpose of brevity and clarity and is not, in itself, indication of a relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, for ease of explanation, spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” are used herein to describe the relationship between one component or feature shown in the figures and another component or feature. In addition to the orientations illustrated in the figures, these spatially relative terms are also intended to encompass different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0019] Figure 1 A schematic plan view of a semiconductor assembly according to some embodiments of the present disclosure is shown. The semiconductor assembly 100 includes a semiconductor die 110, a first conductive pad 120, a second conductive pad 130, a first connector structure 140, and a second connector structure 150. Figure 1 The illustration shows the side of semiconductor component 100 intended to be bonded to other components via a semiconductor die bonding process, and some components of semiconductor component 100, such as wiring, dielectric layers, active components, passive components, or the like, are omitted. Additionally, the first conductive pad 120 and the second conductive pad 130 may not be exposed on the surface of semiconductor component 110, while... Figure 1 The text is merely used to illustrate the relationship between the conductive pads and the connector structure. For example, the first conductive pad 120 and the second conductive pad 130 are not shown in the text. Figure 1 The diagram shows at least one passivation layer covering the first conductive pad 120 and the second conductive pad 130, therefore the first conductive pad 120 and the second conductive pad 130 are used. Figure 1 It is drawn using dashed lines.

[0020] The first conductive pad 120 and the second conductive pad 130 are arranged in arrays along the X and Y directions. First connector structures 140 are arranged corresponding to the first conductive pads 120, and second connector structures 150 are arranged corresponding to the second conductive pads 130. In some embodiments, one first connector structure 140 overlaps with a corresponding first conductive pad 120, and one second connector structure 150 overlaps with a corresponding second conductive pad 130. In some embodiments, in a predetermined direction, the spacing between the first conductive pads 120 and the first connector structures 140 may be the same, and the spacing between the second conductive pads 130 and the second connector structures 150 may be the same. In some embodiments, the spacing between the first conductive pads 120 and the second conductive pads 130 may be the same or different. Alternatively, the spacing between the first connector structures 140 and the second connector structures 150 may be the same or different. In some embodiments, the first conductive pads 120 and the second conductive pads 130 may be arranged with non-fixed spacing. In some embodiments, the geometric center of the shape defined by the contour of the first conductive pad 120 may be aligned with the geometric center of the shape defined by the contour of the first connector structure 140, and the geometric center of the shape defined by the contour of the second conductive pad 130 may be aligned with the geometric center of the shape defined by the contour of the second connector structure 150.

[0021] Figure 2 and Figure 3 The arrangement of conductive pads and connector structures are illustrated using planar diagrams of semiconductor components. (Refer to...) Figures 1 to 3 The first conductive pad 120 has a first lateral dimension D1, the second conductive pad 130 has a second lateral dimension D2, the first connector structure 140 has a third lateral dimension D3, and the second connector structure 150 has a fourth lateral dimension D4. The first lateral dimension D1, the second lateral dimension D2, the third lateral dimension D3, and the fourth dimension D4 are dimensions of corresponding components measured in the same direction. In some embodiments, the dimensions of a component measured in different directions may be different or the same. The area of ​​the first connector structure 140 may be larger than the area of ​​the corresponding conductive pad 120, and the third lateral dimension D3 may be larger than the first lateral dimension D1. The area of ​​the second connector structure 150 may be smaller than the area of ​​the corresponding second conductive pad 130, and the fourth lateral dimension D4 may be smaller than the second lateral dimension D2. In some embodiments, such as Figure 3 As shown, the first connector structure 140 may have the same area as the second connector structure 150, that is, the third lateral dimension D3 and the fourth lateral dimension D4 are the same. In some embodiments, such as Figure 2As shown, the area of ​​the first conductive pad 120 may be smaller than the area of ​​the second conductive pad 130, that is, the first lateral dimension D1 is smaller than the second lateral dimension D2. In some alternative embodiments, the first connector structure 140 may have a different area than the second connector structure 150, and the third lateral dimension D3 may be different from the fourth lateral dimension D4. The first lateral dimension D1 may be the same as the second lateral dimension D2, but the first lateral dimension D1 is smaller than the third lateral dimension D3, and the second lateral dimension D2 is larger than the fourth lateral dimension D4.

[0022] like Figure 1 As shown, the semiconductor die 110 in the bottom view may have a rectangular or similar rectangular shape and includes four corners 110A. In some embodiments, the corners 110A may be rounded corners or sharp corners. Figure 1 In this design, semiconductor die 110 has four corner regions RC1 and a central region RM1 at its four corners 110A. A first conductive pad 120 is located in the corner region RC1. A second conductive pad 130 is located in the central region RM1. Similarly, a first connector structure 140 is located in the corner region RC1, and a second connector structure 150 is located in the central region RM1. Compared to the first conductive pad 110, the second conductive pad 120 is farther from the nearest corner 100A of semiconductor die 100. For example, the distance F1 between the first conductive pad 110 and the nearest corner 110A is less than the distance F2 between the second conductive pad 120 and the nearest corner 110A.

[0023] In an embodiment, the corner region RC1 can be multiple triangular regions. The distribution range LC measured from the boundary BRC1 of the corner region RC1 to the corner 110A of the semiconductor die 110 can be no greater than 0.04 times the length LS of the sidewall edge SE of the semiconductor die 110. Therefore, the distance F3 between the first conductive pad 120 of the semiconductor die 110 and the closest corner 110A can be less than or equal to 0.04 times the length LS of the sidewall edge SE of the semiconductor die 110. The second conductive pad 130 is spaced apart from the corner 110A of the semiconductor die 110 by a distance (e.g., F2), and this distance (e.g., F2) is 0.04 times greater than the length LS of the sidewall edge SE of the semiconductor die 110. In some embodiments, the second conductive pad 130 has the same size, and the boundary between the corner region RC1 and the center region RM1 can be defined between two adjacent conductive pads with different sizes.

[0024] Figure 4 A schematic plan view of a semiconductor assembly according to some embodiments of the present disclosure is shown. Semiconductor assembly 200 includes a semiconductor die 110, a first conductive pad 120, a second conductive pad 130, a first connector structure 140, and a second connector structure 150. Semiconductor assembly 200 and... Figure 1The semiconductor components 100 shown are similar, and similar or identical reference numerals in both embodiments represent similar or identical components. Specifically, in semiconductor component 200, semiconductor die 110 may have multiple non-triangular corner regions RC2. The corner regions RC2 of semiconductor die 110 may be fan-shaped, and the boundary between the corner region RC2 and the center region RM is a curved boundary. In the corner region RC2, the first conductive pad 120 farthest from corner 110A may be spaced from corner 110A by a distance F5, and the distance F5 may not be greater than 0.04 times the length of the sidewall edge of semiconductor die 110.

[0025] Figure 5 The semiconductor components according to some embodiments of the present disclosure are schematically illustrated, and Figure 5 A plan view of the semiconductor assembly is shown to illustrate one side of the semiconductor assembly that will be bonded to other components via a semiconductor die bonding process. The semiconductor assembly 300 may include a semiconductor die 110, a first conductive pad 320, a second conductive pad 130, a first connector structure 140, and a second connector structure 150. For ease of illustration, in... Figure 3 Some components in the semiconductor component 300 may be omitted. In some embodiments, the semiconductor component 300 may further include wiring, dielectrics, active components, passive components, or combinations thereof. The first conductive pad 320 and the second conductive pad 130 may not be exposed on the surface of the semiconductor component 300 and may be covered by at least one passivation layer (not shown). Figure 1 The text is merely used to illustrate the relationship between the conductive pads and the connector structure. For example, the first conductive pad 120 and the second conductive pad 130 are not shown in the text. Figure 1 The diagram shows at least one passivation layer covering the first conductive pad 120 and the second conductive pad 130, therefore the first conductive pad 120 and the second conductive pad 130 are used. Figure 1 The first conductive pad 320 and the second conductive pad 130 are drawn using dashed lines to illustrate the relationship between the conductive pads and the connector structure.

[0026] The first conductive pad 320 may include a first conductive pad 320A and a first conductive pad 320B with different dimensions. The second conductive pad 130 may have the same dimensions, the first connector structure 140 may have the same dimensions, and the second connector structure 150 may have the same dimensions. For example, the first conductive pad 320A has a first lateral dimension D1A, and this first lateral dimension D1A is different from the first lateral dimension D1B of the first conductive pad 320B. Furthermore, the second conductive pad 130 may have the same second lateral dimension D2, the first connector structure 140 may have the same third lateral dimension D3, and the second connector structure 150 may have the same fourth lateral dimension D4. The first lateral dimension D1A of the first conductive pad 320A is smaller than the third lateral dimension D3 of the corresponding first connector structure 140, and the first dimension D1B of the first conductive pad 320B is smaller than the third lateral dimension D3 of the corresponding first connector structure 140. The second lateral dimension D2 of each second conductive pad 130 is greater than the fourth lateral dimension D4 of the corresponding second connector structure 150.

[0027] Figure 6 The arrangement of conductive pads is schematically shown in a planar diagram of a semiconductor component. (Reference) Figure 5 and Figure 6 In this embodiment, the first conductive pad 320 located in the corner region RC3 has a smaller size than the second conductive pad 130 located in the central region RM1. The second conductive pads 130 have the same size in the top view. In other words, the lateral dimensions of the second conductive pads 130 are the same. The first conductive pads 320 arranged in the corner region RC3 of the semiconductor die 110 may have two or more size designs, but the invention is not limited thereto. For example, the first conductive pad 320A may have a larger size than the first conductive pad 320B. In this embodiment, the sizes of the first conductive pads 320A and 320 are smaller than the sizes of the corresponding second conductive pads 130. In some embodiments, the boundary between the corner region RC3 and the central region RM3 may be a straight boundary, such that the corner region RC3 may have a triangular shape. In some other embodiments, the boundary between the corner region RC3 and the central region RM3 may be a curved boundary, such that the corner region RC3 may have a fan-shaped shape.

[0028] Figure 7A schematic cross-sectional view of a semiconductor assembly according to some embodiments of the present disclosure is shown. The semiconductor assembly 400 includes a semiconductor die 410, a first conductive pad 420, a second conductive pad 430, a first connector structure 440, and a second connector structure 450. The first connector structure 440 and the second connector structure 450 are disposed on the semiconductor die 410 for bonding to another assembly via a die-bonding process. The first conductive pad 420 and the second conductive pad 430 are disposed on the semiconductor die 410. The first conductive pad 420 is located between the first connector structure 440 and the semiconductor die 410 to form an electrical connection between the first connector structure 440 and the semiconductor die 410. The second conductive pad 430 is located between the second connector structure 450 and the semiconductor die 410 to form an electrical connection between the second connector structure 450 and the semiconductor die 410. In addition, the semiconductor component 400 may further include a first passivation layer 460, a second passivation layer 470 and a protective layer 480, wherein the protective layer 480 is disposed between the metal layers / structures forming the first conductive pad 420, the second conductive pad 430, the first connector structure 440 and the second connector structure 450.

[0029] In some embodiments, the arrangement of the first conductive pad 420, the second conductive pad 430, the first connector structure 440, and the second connector structure 450 can be referenced. Figures 1 to 5 The arrangement of conductive pads and connector structures shown in any of them. That is, Figures 1 to 5 The arrangement of conductive pads and connector structures shown in any of them can be incorporated into Figure 7 The embodiments, or, Figure 7 The structure shown can be considered as Figures 1 to 5 An exemplary cross-sectional view of a semiconductor component is shown in either of the diagrams. Semiconductor component 400 may have a central region RM4 and a corner region RC4, with the corner region RC4 being closer to a corner of the semiconductor component 400 than the central region RM4, as shown in the diagram. Figures 1 to 5 As shown in either of the above. The first conductive pad 420 and the first connector structure 440 are located within the corner region RC4, and the second conductive pad 430 and the second connector structure 450 are located within the central region RM4. In some embodiments, the distance between the nearest corner of the first conductive pad 420 and the semiconductor component 440 is less than the distance between the nearest corner of the second conductive pad 430 and the semiconductor component 450.

[0030] like Figure 7As shown, the semiconductor die 410 may include circuitry formed therein. Specifically, the semiconductor die 410 may further include electrical components, contact structures, and wiring for electrically connecting the electrical components to form the desired circuitry. For example, the electrical components may include various interconnected N-type metal-oxide-semiconductor (NMOS) and / or P-type metal-oxide-semiconductor (PMOS) components, such as transistors, capacitors, resistors, diodes, photodiodes, fuses, and the like, to perform one or more functions. The aforementioned functions may include memory structures, processing structures, sensors, amplifiers, power distributions, input / output circuitry, or the like. The above examples are merely illustrative to further illustrate the application of some embodiments and are not intended to limit this disclosure. The contacts and wiring for electrically connecting the electrical components may include one or more inter-metal dielectric (IMD) layers and associated metallization layers formed on and interconnected with the electrical components.

[0031] The intermetallic dielectric layer can be formed from a low-dielectric-constant dielectric material, such as fluorinated silicate glass (FSG) formed by plasma-enhanced chemical vapor deposition (PECVD) or high-density plasma-enhanced chemical vapor deposition (HDPCVD) or similar processes, and may include intermediate etch stop layers. The metallization layer can be formed from copper or copper alloys, although it can also be formed from other metals. Furthermore, the metallization layer extends from the topmost IMD layer to the top metal layer that provides external electrical connections or is formed and patterned, and protects the underlying layers from various environmental contaminants. The topmost intermetallic dielectric layer can be formed from a dielectric material such as silicon nitride, silicon oxide, undoped silicon glass, or the like.

[0032] A first passivation layer 460 is disposed on the semiconductor die 410, a first conductive pad 420 and a second conductive pad 430 are disposed on the first passivation layer 460, a second passivation layer 470 is disposed on the first conductive pad 420 and the second conductive pad 430, a protective layer 480 is disposed on the second passivation layer 470, and a first connector structure 440 and a second connector structure 450 are disposed on the protective layer 480. In this embodiment, the first passivation layer 460, the second passivation layer 470, and the protective layer 480 may have one or more openings, allowing the metal layers in the conductive pads and connector structures to be electrically connected to the overlying metal layer and / or the underlying metal layer. Therefore, an electrical connection is formed between the first conductive pad 420, the second conductive pad 430, the first connector structure 440, and the second connector structure 450.

[0033] A first passivation layer 460 is formed to separate the first conductive pad 420 and the second conductive pad 430 from the semiconductor die 410. The first passivation layer 460 may be formed of a dielectric material, such as undoped silicate glass (USG), silicon nitride, silicon oxide, silicon oxynitride, or a non-porous material, by any suitable method, such as CVD, PVD, or similar. The first passivation layer 460 may be a monolayer or a laminate. Figure 7 The single-layer conductive pads and passivation layers illustrated are for illustrative purposes only. Therefore, other embodiments may use any number of conductive layers and / or passivation layers. The first passivation layer 460 may have one or more openings (not shown) such that the metal layers of the first conductive pad 420 and the second conductive pad 430 extend within the openings to contact the topmost metallization layer of the semiconductor die 410.

[0034] A first conductive pad 420 and a second conductive pad 430 are disposed on a semiconductor die 410, and the first conductive pad 420 and the second conductive pad 430 may be formed of aluminum, aluminum-copper, aluminum alloy, copper, copper alloy, or the like. The first conductive pad 420 has a first lateral dimension D1, and the second conductive pad 430 has a second lateral dimension D2. Figure 7 The lateral dimensions depicted are dimensions measured in a direction substantially parallel to the plane of the semiconductor die 410 and extending along the cutting direction of the cross-section. A first lateral dimension D1 differs from a second lateral dimension D2. In some embodiments, the first lateral dimension D1 is smaller than the second lateral dimension D2. In some embodiments, each of the first conductive pad 420 and the second conductive pad 430 may have a circular shape in the top view, such as... Figures 1 to 6 As shown. In some alternative embodiments, each of the first conductive pad 420 and the second conductive pad 430 may be non-circular in top view, such as rectangular, square, pentagonal, hexagonal or other polygonal, or elliptical, or other shapes.

[0035] A second passivation layer 470 is disposed on the first passivation layer 460, the first conductive pad 420, and the second conductive pad 430. The second passivation layer 470 may be formed of a dielectric material, such as undoped silicate glass (USG), silicon nitride, silicon oxide, silicon oxynitride, or a non-porous material, by any suitable method, such as CVD, PVD, or similar processes. The second passivation layer 470 may be a monolayer or a laminate. The second passivation layer 470 may be patterned using a masking method, photolithography, etching process, or a combination thereof, such that a first opening 460A is formed to expose a portion of the first conductive pad 420, and a second opening 460B is formed to expose a portion of the second conductive pad 430. The second passivation layer 470 is located between a portion of the first conductive pad 420 and a portion of the first connector structure 440, and between a portion of the second conductive pad 430 and a portion of the second connector structure 450. The second passivation layer 470 may cover the sidewalls of the first conductive pad 420 and the second conductive pad 430, and expose the central portion of the first conductive pad 420 and the central portion of the second conductive pad 430.

[0036] A protective layer 480 is disposed on the second passivation layer 470. The protective layer 480 has a third opening 480A and a fourth opening 480B. The third opening 480A exposes a portion of the first conductive pad 420, and the fourth opening 480B exposes a portion of the second conductive pad 430. The protective layer 480 may not only cover the surface of the second passivation layer 470 facing away from the semiconductor die 410, but may also cover the edge surfaces of the second passivation layer 470 located at the first opening 470A and the second opening 470B. The protective layer 480 does not cover the central portion of the first conductive pad 420 located at the third opening 480A and the central portion of the second conductive pad 430 located at the fourth opening 480B. For example, the protective layer 480 may be a polymer layer. The polymer layer may be formed from polymeric materials such as epoxy resin, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and the like, but may also be formed from other relatively soft materials, typically organic dielectric materials. The aforementioned formation methods include spin coating or other methods.

[0037] A first connector structure 440 is disposed on the protective layer 480 and is in physical contact with a first conductive pad 420 located at the third opening 480A. The first connector structure 440 includes a first bump base metal (UBM) layer 442 and a first columnar bump 444 disposed on the first UBM layer 442. The first UBM layer 442 is at least disposed on the exposed portion of the first conductive pad 420 located at the third opening 480A and extends over the protective layer 480 surrounding the third opening 480A. A second connector structure 450 is disposed on the protective layer 480 and is in physical contact with a second conductive pad 430 located at the fourth opening 480B. The second connector structure 450 includes a second bump base metal (UBM) layer 452 and a second columnar bump 454 disposed on the second UBM layer 452. The second UBM layer 452 is disposed on the exposed portion of the second conductive pad 430 located at the third opening 480B, and extends on the protective layer 480 surrounding the third opening 480B.

[0038] In some embodiments, each of the first UBM layer 442 and the second UBM layer 452 includes a first layer serving as a diffusion barrier layer or adhesive layer, wherein the first layer comprises titanium, tantalum, titanium nitride, tantalum nitride, or the like formed by physical vapor deposition (PVD) or sputtering. The deposition thickness of the first layer is between approximately 500 and 2000 angstroms. In some embodiments, each of the first UBM layer 442 and the second UBM layer 452 includes a second layer serving as a seed layer, wherein the second layer comprises copper or a copper alloy formed by physical vapor deposition (PVD) or sputtering. The deposition thickness of the second layer is between approximately 500 and 10000 angstroms.

[0039] A first columnar bump 444 is disposed on a first UBM layer 442, and a second columnar bump 454 is disposed on a second UBM layer 452. Each of the first columnar bump 444 and the second columnar bump 454 may be a copper layer containing substantially pure elemental copper, a copper layer containing unavoidable impurities, or a copper alloy layer containing trace amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum, or zirconium. Methods for forming the first columnar bump 444 and the second columnar bump 454 may include sputtering, printing, electroplating, electroless electroplating, or chemical vapor deposition (CVD) methods. For example, electrochemical electroplating (ECP) may be performed to form the first columnar bump 444 and the second columnar bump 454. In an exemplary embodiment, the thickness of each of the first columnar bump 444 and the second columnar bump 454 is greater than 30 μm. In another exemplary embodiment, the thickness of each of the first columnar bump 444 and the second columnar bump 454 is greater than 40 μm. For example, the thickness of each of the first columnar bump 444 and the second columnar bump 454 is between about 40 μm and 50 μm, or between about 40 μm and 70 μm, although the thickness may be greater or less.

[0040] In this embodiment, a first solder mask 492 is disposed on top of a first connector structure 440, and a second solder mask 494 is disposed on top of a second connector structure 450. Each of the first solder mask 492 and the second solder mask 494 may be made of Sn, SnAg, Sn-Pb, SnAgCu (Cu weight percentage less than 0.3%), SnAgZn, SnZn, SnBi-In, Sn-In, Sn-Au, SnPb, SnCu, SnZnIn, or SnAgSb, for example, formed by an electroplating process. In some embodiments, both the first solder mask 492 and the second solder mask 494 are lead-free solder masks. For example, the lead-free solder mask is SnAg, wherein the Ag content is controlled within 3.0 weight percentage (wt%). In some embodiments, the lead-free solder mask is SnAg, wherein the Ag content is controlled within approximately 2.5 weight percentage (wt%). For example, a reflow process can be performed by heating the wafer or by rapid thermal processing (RTP), making the first solder mask 492 and the second solder mask 494 hemispherical. In some embodiments, the first solder mask 492 may have the same lateral dimensions as the first connector structure 440, while the second solder mask 494 may have the same lateral dimensions as the second connector structure 450. In alternative embodiments, the first solder mask 492 and the second solder mask 494 may each have different lateral dimensions than the first connector structure 440 and the second connector structure 450, respectively.

[0041] The first UBM layer 442 of the first connector structure 440 has a third lateral dimension D3, which is measured in the same direction as the first lateral dimension D1 of the first conductive pad 420. The first columnar bump 444 has a lateral dimension that is substantially the same as the first UBM layer 442. Therefore, in a plan view of the semiconductor assembly 400, the third dimension D3 can represent the lateral dimension of the first connector structure 440. In some embodiments, the lateral dimension of the first columnar bump 444 may be different, for example, smaller than the third dimension D3 of the first UBM layer 442. The third dimension D3 is larger than the first dimension D1. In some embodiments, the first conductive pad 420 may be completely located under the first connector structure 440. Therefore, the virtual line extending from the edge 440E of the first connector structure 440 toward the semiconductor die 410 may not pass through the first conductive pad 420.

[0042] The second UBM layer 452 of the second connector structure 450 has a fourth lateral dimension D4, which is measured in the same direction as the second lateral dimension D2 of the second conductive pad 430. The second columnar bump 454 has a substantially the same lateral dimension as the second UBM layer 452. Therefore, in a plan view of the semiconductor assembly 400, the fourth dimension D4 can represent the lateral dimension of the second connector structure 450. In some embodiments, the lateral dimension of the second columnar bump 454 may be different from, for example, smaller than, the fourth dimension D4 of the second UBM layer 452. The fourth dimension D4 is not greater than, for example, equal to or smaller than, the second lateral dimension D2 of the second conductive pad 430. In some embodiments, the lateral dimension of the second conductive pad 430 may exceed the dimension of the second connector structure 440. Therefore, a virtual line extending from the edge 450E of the second connector structure 450 toward the semiconductor die 410 passes through the second conductive pad 430.

[0043] In some embodiments, the third lateral dimension D3 of the first connector structure 440 and the fourth lateral dimension D4 of the second connector structure 450 are the same. The first lateral dimension D1 of the first conductive pad 420 is smaller than the second lateral dimension D2 of the second conductive pad 430. Each of the first connector structure 440, the second connector structure 450, and the second conductive pad 430 has a larger lateral dimension than the first conductive pad 420. In some alternative embodiments, the first connector structure 440, the second connector structure 450, and the second conductive pad 430 may have the same lateral dimension, i.e., the second lateral dimension D2 may be the same as the third lateral dimension D3 and the fourth lateral dimension D4.

[0044] In some embodiments, to ensure the reliability of the semiconductor component 400, a thermal cycling test may be performed to cyclically heat and cool the semiconductor component 400. During the thermal cycling test, stresses are generated due to the different physical properties of various materials. For example, the materials of various layers / components have different coefficients of thermal expansion, so the different expansion during the thermal cycling test results in stresses in the semiconductor component 400. In some embodiments, the stresses generated during the thermal cycling test may be more concentrated in the corner region RC4 than in the central region RM4. In some embodiments, stress FA may be generated along the edge 440E of the first connector structure 440 and applied to the second passivation layer 470. In the corner region RC4, the first conductive pad 420 is smaller than the first connector structure 440, so the second passivation layer 470 is located on the first passivation layer 460 below the edge 440E of the first connector structure 440. The first passivation layer 460 located under the second passivation layer 470 can act as a buffer to reduce the stress FA applied to the second passivation layer 470. Therefore, during thermal cycling testing, the second passivation layer 470 will not crack or its cracking can be mitigated, thus preventing the semiconductor component 400 from failing and / or becoming undesirable. In other words, the reliability of the semiconductor component 400 is improved.

[0045] Figure 8 schematically shown Figure 7 The semiconductor die 410 is illustrated. The semiconductor die 410 includes a semiconductor substrate 500, a fin structure 502, a metal gate stack 504, a spacer assembly 506, an epitaxial structure 508, an etch stop layer 510, a dielectric layer 512, a contact 514, a dielectric layer 516, a contact 518a, a contact 518b, and conductive wiring 520. The metal gate stack 504 partially covers and surrounds the fin structure 502. The metal gate stack 504 may have substantially the same width. In some alternative embodiments, the metal gate stack 504 may have different widths. The metal gate stack 504 includes a gate dielectric layer 504a and a gate 504b.

[0046] In some embodiments, the semiconductor substrate 500 is a bulk semiconductor substrate, such as a semiconductor wafer. For example, the semiconductor substrate 500 comprises silicon or other elemental semiconductor materials, such as germanium. The semiconductor substrate 500 can be an undoped semiconductor substrate or a doped (e.g., p-type, n-type, or a combination thereof) semiconductor substrate. In some embodiments, the semiconductor substrate 500 includes an epitaxially grown semiconductor layer disposed on a dielectric layer. The epitaxially grown semiconductor layer may be made of silicon-germanium, silicon-germanium, one or more other suitable materials, or a combination thereof.

[0047] In some other embodiments, the semiconductor substrate 500 includes a compound semiconductor. For example, the compound semiconductor includes one or more semiconductors having the molecular formula Al.X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 The defined composition is a III-V compound semiconductor, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions. Each of X1, X2, X3, Y1, Y2, Y3, and Y4 is greater than or equal to zero, and their sum equals 1. The compound semiconductor may include silicon carbide, gallium arsenide, indium arsenide, indium phosphide, one or more other suitable compound semiconductors, or combinations thereof. Other suitable substrates, including II-VI compound semiconductors, may also be used.

[0048] In some embodiments, the semiconductor substrate 500 is an active layer of a semiconductor-on-insulator (SOI) substrate. The SOI substrate can be fabricated using a SIMOX (Implanted Oxygen Separation) process, a wafer bonding process, another suitable method, or a combination of the foregoing processes. In some other embodiments, the semiconductor substrate 500 comprises a multilayer structure. For example, the semiconductor substrate 500 includes a silicon-germanium layer formed on a bulk silicon layer.

[0049] In some embodiments, a plurality of recesses (or trenches) are formed in the semiconductor substrate 500. Therefore, fin structures 502 protruding from the surface of the semiconductor substrate 500 are formed or defined between the recesses (or trenches). In some embodiments, one or more photolithography and etching processes are used to form the recesses (or trenches). In some embodiments, the fin structures 502 are in direct contact with the semiconductor substrate 500. However, embodiments of this disclosure may have many variations and / or modifications. In some other embodiments, the fin structures 502 are not in direct contact with the semiconductor substrate 500. One or more other material layers may be formed between the semiconductor substrate 500 and the fin structures 502. Figure 5 (Not shown in the image). For example, a dielectric layer is formed between the semiconductor substrate 500 and the fin structure 502. In some embodiments, multiple fin structures may be formed on the semiconductor substrate 500, and the number of fin structures is not limited.

[0050] In some embodiments, an isolation feature (not shown) is formed in the recess to surround the lower portion of the fin structure 502. The isolation feature defines and electrically isolates various component assemblies formed in and / or on the semiconductor substrate 500. In some embodiments, the isolation feature includes a shallow trench isolation (STI) feature, a localized oxidation of silicon (LOCOS) feature, another suitable isolation feature, or a combination of the foregoing isolation features. In some embodiments, each isolation feature has a multilayer structure. In some embodiments, the isolation feature is composed of a dielectric material. The dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a low dielectric constant dielectric material, another suitable material, or a combination thereof. In some embodiments, an STI liner (not shown) is formed to reduce crystallization defects at the interface between the semiconductor substrate 500 and the isolation feature. Similarly, an STI liner may also be used to reduce crystallization defects at the interface between the fin structure and the isolation feature.

[0051] A metal gate stack 504, comprising gate dielectric layers 504a and gate 504b, can be disposed on the fin structure 502, and the metal gate stack 504 is formed by a gate replacement process. In some embodiments, the gate dielectric layer 504a is made of or comprises a dielectric material having a high dielectric constant. The gate dielectric layer 504a may be or comprises hafnium oxide, zirconium oxide, aluminum oxide, hafnium alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, one or more other suitable high dielectric constant materials, or combinations thereof. The gate dielectric layer 504a can be deposited using ALD, CVD, one or more other suitable processes, or combinations thereof. In some embodiments, the formation of the gate dielectric layer 504a involves thermal operation.

[0052] According to some embodiments, the gate 504b may include a work function layer and a conductive fill layer. The work function layer can be used to provide the desired work function to enhance the component performance of the transistor, including improvements in the threshold voltage. In some embodiments, the work function layer is used to form an NMOS component. The work function layer is an n-type work function layer. The n-type work function layer is capable of providing a work function value suitable for the component, for example, equal to or less than about 4.5 eV. The n-type work function layer may include a metal, a metal carbide, a metal nitride, or a combination thereof. For example, the n-type work function layer includes titanium nitride, tantalum, tantalum nitride, one or more other suitable materials, or combinations thereof. In some other embodiments, the n-type work function layer is an aluminum-containing layer. The aluminum-containing layer may be or include TiAlC, TiAlO, TiAlN, one or more other suitable materials, or combinations thereof.

[0053] In some embodiments, the work function layer is used to form a PMOS device. The work function layer is a p-type work function layer. The p-type work function layer can provide a work function value suitable for the device, for example, equal to or greater than about 4.8 eV. The p-type work function layer may include metals, metal carbides, metal nitrides, other suitable materials, or combinations thereof. For example, p-type metals include tantalum nitride, tungsten nitride, titanium, titanium nitride, other suitable materials, or combinations thereof.

[0054] The work function layer may also be or include hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, aluminum carbide), aluminides, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides, or combinations thereof. The thickness and / or composition of the work function layer 522 can be fine-tuned to adjust the work function level. For example, depending on the thickness and / or composition of the titanium nitride layer, the titanium nitride layer may be used as a p-type work function layer or an n-type work function layer. The work function layer may be deposited on the gate dielectric layer 504a using ALD, CVD, PVD, electroplating, electroless electroplating, one or more other suitable processes, or combinations thereof.

[0055] In some embodiments, a barrier layer may be formed prior to the formation of the work function layer to demarcate the gate dielectric layer 504a from the subsequently formed work function layer. The barrier layer may also be used to prevent diffusion between the barrier layers of the gate dielectric layer 504a and the gate 504b. The barrier layer may be made of or comprise a metal-containing material. Metal-containing materials may include titanium nitride, tantalum nitride, one or more other suitable materials, or combinations thereof. The barrier layer may be deposited using ALD, CVD, PVD, electroplating, electroless plating, one or more other suitable processes, or combinations thereof.

[0056] A spacer wall assembly 506 is disposed on the sidewall of the metal gate stack 504. In some embodiments, the spacer wall assembly 506 is made of or comprises a dielectric material. The dielectric material may include silicon nitride, silicon oxynitride, silicon oxide, silicon carbide, one or more other suitable materials, or combinations thereof.

[0057] Epitaxial structures 508 disposed on fin structures 502 can perform source / drain characteristics. In some embodiments, prior to forming the epitaxial structures 508, recesses may be formed in multiple portions of the fin structure 502 not covered by the metal gate stack 504 and spacer assembly 506. In some embodiments, the aforementioned recesses extend laterally into the channel region below the metal gate stack 504. For example, multiple portions of the recesses are located directly below the spacer assembly 506. Subsequently, one or more semiconductor materials are epitaxially grown on the sidewalls and bottom of the recesses to form the epitaxial structures 508. In some embodiments, the epitaxial structures 508 located on both opposite sides of the metal gate stack 504 are p-type semiconductor structures. In some other embodiments, the epitaxial structures 508 located on both opposite sides of the metal gate stack 504 are n-type semiconductor structures. In some other embodiments, one of the epitaxial structures 508 is a p-type semiconductor structure, and the other of the epitaxial structures 508 is an n-type semiconductor structure. p-type semiconductor structures may include epitaxially grown silicon germanium or boron-doped silicon germanium. n-type semiconductor structures may include epitaxially grown silicon, epitaxially grown silicon carbide (SiC), epitaxially grown silicon phosphide (SiP), or another suitable epitaxially grown semiconductor material. In some embodiments, the epitaxial structure 508 is formed by an epitaxial process. In some other embodiments, the epitaxial structure 508 is formed by multiple individual processes, such as multiple individual epitaxial growth processes. The epitaxial structure 508 may be formed using selective epitaxial growth (SEG), CVD processes (e.g., vapor phase epitaxy (VPE), low-pressure chemical vapor deposition (LPCVD), and / or ultra-high vacuum chemical vapor deposition (UHV-CVD)), molecular beam epitaxy, one or more other suitable processes, or combinations of the foregoing processes.

[0058] In some embodiments, one or both of the epitaxial structures 508 are doped with one or more suitable dopants. For example, the epitaxial structure 508 is a silicon germanide source / drain feature doped with boron (B), indium (In), or other suitable dopants. Alternatively, in some other embodiments, one or both of the epitaxial structures 508 are silicon source / drain features doped with phosphorus (P), antimony (Sb), or another suitable dopant. In some embodiments, the epitaxial structure 508 is doped in-situ during its epitaxial growth. In some other embodiments, the epitaxial structure 508 is not doped during its epitaxial growth. Instead, after the formation of the epitaxial structure 508, it is doped in a subsequent process. In some embodiments, doping is achieved using ion implantation, plasma immersion ion implantation, gas and / or solid source diffusion, one or more other suitable processes, or combinations thereof. In some embodiments, one or more annealing processes are performed to activate the dopants in the epitaxial structure 508. For example, a rapid thermal annealing process is used to activate the dopants in the epitaxial structure 508.

[0059] According to some embodiments, an etch stop layer 510 and a dielectric layer 512 are sequentially disposed on a semiconductor substrate 500 and an epitaxial structure 508. The etch stop layer 510 may conformally extend along the surfaces of the spacer assembly 506 and the epitaxial structure 508. The dielectric layer 512 covers the stop layer 510 and surrounds the spacer assembly 510 and the metal gate stack 504. The etch stop layer 510 may be made of or include silicon nitride, silicon oxynitride, silicon carbide, one or more other suitable materials, or combinations thereof. In some embodiments, the etch stop layer 510 is deposited on the semiconductor substrate 500 using a CVD process, an ALD process, a PVD process, one or more other suitable processes, or combinations thereof. The dielectric layer 512 may be or include silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphate silicate glass (PSG), borosilicate phosphosilicate glass (BPSG), fluoride silicate glass (FSG), a low dielectric constant material, a porous dielectric material, one or more other suitable materials, or a combination of the foregoing materials. In some embodiments, the dielectric layer 512 is deposited using a CVD process, an ALD process, an FCVD process, a PVD process, one or more other suitable processes, or a combination thereof. The top surfaces of the dielectric layer 512, the etch stop layer 510, the spacer assembly 506, and the metal gate stack 504 are substantially flush with each other.

[0060] The semiconductor substrate 500, fin structure 502, metal gate stack 504, spacer assembly 506, epitaxial structure 508, etch stop layer 510, and dielectric layer 512 are formed by front-end process (FEOL). After the front-end process, dielectric layer 516, contact 518a, contact 518b, and conductive wiring 520 are formed on the semiconductor substrate 500.

[0061] The contact 514 penetrates the dielectric layer 512 and the etch stop layer 510, and the contact 514 can serve as the bottom part of the source / drain contact and is electrically connected to the epitaxial structure 508 (i.e., the source / drain feature).

[0062] A dielectric layer 516 may be disposed above a dielectric layer 512. In some embodiments, the dielectric layer 516 is deposited on the dielectric layer 512 using a CVD process, an ALD process, an FCVD process, a PVD process, one or more other suitable processes, or a combination of the foregoing processes. The dielectric layer 516 may be or include silicon oxide, silicon oxynitride, BSG, PSG, BPSG, FSG, a low dielectric constant material, a porous dielectric material, one or more other suitable materials, or a combination thereof. The dielectric layer 516 may be patterned by any suitable method. For example, the dielectric layer 516 may be patterned by a photolithography process. After the dielectric layer 516 is patterned, vias are formed in the dielectric layer 516, exposing portions of the contact 514 and the gate 504b. A conductive material (e.g., copper or other suitable metal) may be deposited on the dielectric layer 516 and fill the vias defined in the dielectric layer 516. The conductive material may be deposited using a CVD process or other suitable processes. In some embodiments, a planarization process is performed to remove deposited conductive material until the top surface of dielectric layer 516 is exposed. The planarization process may include chemical mechanical polishing (CMP), polishing, etching, dry polishing, one or more other suitable processes, or a combination thereof. Figure 8 As shown, contacts 518a and 518b are formed to penetrate the dielectric layer 516. Contact 518a can serve as a gate contact electrically connected to the gate 504b, while contact 518b sits on contact 514 and can serve as the upper part of the source / drain contact.

[0063] Conductive wiring 520 may be disposed on dielectric layer 516 to electrically connect to contacts 518a and 518b. A conductive material (e.g., copper or other suitable metal) may be deposited on the top surface of dielectric layer 516, and the conductive material may be patterned by any suitable method to form conductive wiring 520. For example, CVD or other suitable processes may be used to deposit the conductive material, and photolithography may be used to pattern the conductive material. After the conductive wiring 520 is formed, a mid-stage process (MEOL) is completed, followed by a back-end process (BEOL) to fabricate on semiconductor die 410. Figure 7 The first conductive pad 420, the second conductive pad 430, the first connector structure 440, and the second connector structure 450 are illustrated.

[0064] Figure 9 A partial plan view schematically illustrates a conductive pad layer within a semiconductor assembly according to some embodiments of the present disclosure. The semiconductor assembly 600 includes a semiconductor die 610, a conductive pad 620, and conductive wiring 630. The semiconductor assembly 600 has a corner region RC5, and the corner region RC5 is adjacent to corner 600A. The conductive pad 620 and the conductive wiring 630 are disposed within the corner region RC5 and are on the same layer. The conductive wiring 630 is connected to the conductive pad 620. Figure 9 In the foreground, dashed lines are used to depict the connector structure 640 for clarity. The semiconductor assembly 600 may further include other components described in the above embodiments. Figure 9 The range and distribution of the corner area RC5 can be referenced from the corner areas RC1 to RC4 in the above embodiments.

[0065] The conductive pad 620 and connector structure 640 may have a similar design to the first conductive pads 120, 320, and 420 and the connector structures 140 and 440, and the aforementioned details of the first conductive pads 120, 320, and 420 and the connector structures 140 and 440 may be applied to the conductive pad 620 and the connector structure 640. The lateral dimension D5 of the conductive pad 620 is smaller than that of the connector structure 640. Figure 9 As shown, the area (distribution region) of the conductive pad 620 may be entirely within the area (distribution region) of the connector structure 640. Conductive wiring 630 connects to the conductive pad 620 and extends beyond the area of ​​the connector structure 640. In some embodiments, the conductive wiring 630 may be in the same layer as the conductive pad 620. In a plan view, the trace of the conductive wiring 630 may cross the outline of the area (distribution region) of the connector structure 640. In some embodiments, the linewidth W630 of the conductive wiring 630 is between 5 μm and 15 μm. In a plan view, the outline of the conductive wiring 630 and the outline of the connector structure 640 may intersect at intersection X1 and intersection X2. In some embodiments, the linewidth W630 may be substantially the same as the distance between intersection X1 and intersection X2. In some alternative embodiments, in a plan view, the conductive wiring 630 may not be connected to the conductive pad 620, but may partially overlap with the connector structure 640.

[0066] Figure 10A partial plan view of a conductive pad layer within a semiconductor component according to some other embodiments of the present disclosure is schematically shown. The semiconductor component 700 includes a semiconductor die 710, a conductive pad 720, and conductive wiring 730. The semiconductor component 700 has a corner region RC6, and the corner region RC6 is adjacent to a corner 700A. The conductive pad 720 and the conductive wiring 730 are disposed within the corner region RC6 and are in the same layer. The conductive wiring 730 may include conductive wiring 732, conductive wiring 734, and conductive wiring 736. In some embodiments, conductive wiring 732, conductive wiring 734, and conductive wiring 736 may be formed in the same layer as the conductive pad 720. Figure 10 In the diagram, dashed lines are used to illustrate the connector structure 740. The semiconductor assembly 700 may further include other components described in the above embodiments. Figure 10 The range and distribution of the corner area RC6 can be referenced from the corner areas RC1 to RC4 in the above embodiments.

[0067] The conductive pad 720 and the connector structure 740 may have a design similar to that of the first conductive pads 120, 320, and 420 and the connector structures 140 and 440, and the aforementioned details of the first conductive pads 120, 320, and 420 and the connector structures 140 and 440 may be applied to the conductive pad 720 and the connector structure 740. The lateral dimension of the conductive pad 720 is smaller than that of the connector structure 740. Figure 10 As shown, the area (distribution) of the conductive pad 720 can be completely located within the area (distribution) of the connector structure 740.

[0068] In the plan view, each of the conductive wirings 732, 734, and 736 extends through the outline of the area (distribution) of the connector structure 740. In some embodiments, the linewidths W732 of conductive wiring 732, W734 of conductive wiring 734, and W736 of conductive wiring 736 are each in the range of 5 μm to 15 μm. Furthermore, the spacing S730A between conductive wirings 732 and 734 and the spacing S730B between conductive wirings 732 and 736 may each be greater than 5 μm.

[0069] According to embodiments of this disclosure, a semiconductor component includes various designs of conductive pads that contact a connector structure in different regions. In corner regions of the semiconductor component or adjacent to corner regions, the conductive pads located below the connector structure are smaller than the connector structure. In central regions or regions with conductive pads of the same size, the conductive pads located below the connector structure are not smaller than the connector structure. In corner regions, a passivation layer is sandwiched between an underlying passivation layer and a connector structure that is larger than the conductive pads. This helps reduce the stress experienced by the passivation layer and improves the reliability of the passivation layer.

[0070] The embodiments disclosed herein relate to a semiconductor assembly including a semiconductor die, a first conductive pad, a second conductive pad, a first connector structure, and a second connector structure. The first conductive pad is disposed on the semiconductor die, wherein the first conductive pad has a first lateral dimension. The second conductive pad is disposed on the semiconductor die, wherein the second conductive pad has a second lateral dimension. The first connector structure is disposed on the first conductive pad, wherein the first connector structure has a third lateral dimension larger than the first lateral dimension. The second connector structure is disposed on the second conductive pad, wherein the second connector structure has a fourth lateral dimension smaller than the second lateral dimension. The fourth lateral dimension is the same as the third lateral dimension. The semiconductor assembly further includes a passivation layer disposed on the semiconductor die and covering the sidewalls of the first conductive pad and the sidewalls of the second conductive pad. The passivation layer is located between a portion of the first conductive pad and a portion of the first connector structure, and between a portion of the second conductive pad and a portion of the second connector structure. The semiconductor assembly further includes a protective layer disposed on the semiconductor die. The protective layer has a first opening above a first conductive pad and a second opening above a second conductive pad. A first connector structure is connected to the first conductive pad through the first opening, and a second connector structure is connected to the second conductive pad through the second opening. The first connector structure includes a first bump base metal (UBM) layer and a first columnar bump disposed on the first UBM layer. The second connector structure includes a second UBM layer and a second columnar bump disposed on the second UBM layer. The second conductive pad is located further from a corner of the semiconductor die than the first conductive pad. The distance between the first conductive pad and the corner of the semiconductor die is less than or equal to 0.04 times the length of the sidewall edge of the semiconductor die.

[0071] Another embodiment of this disclosure relates to a semiconductor assembly including a semiconductor die, a first conductive pad, a second conductive pad, a first connector structure, and a second connector structure. The first conductive pad is disposed on an upper first region of the semiconductor die. The second conductive pad is disposed on a second region of the semiconductor die, the second region being further away from a corner of the semiconductor die than the first region, wherein the first conductive pad has a first lateral dimension, and the second conductive pad has a second lateral dimension larger than the first lateral dimension. The first connector structure is disposed on the first conductive pad. The second connector structure is disposed on the second conductive pad. The first connector structure includes a first UBM layer and a first columnar bump disposed on the first UBM layer, and the second connector structure includes a second UBM layer and a second columnar bump disposed on the second UBM layer. The first connector structure and the second connector structure have the same lateral dimension. The distance between the first conductive pad and the corner of the semiconductor die is less than or equal to 0.04 times the length of the sidewall edge of the semiconductor die. The first connector structure has a third lateral dimension, and the second connector structure has a fourth lateral dimension identical to the third lateral dimension. The semiconductor assembly further includes a passivation layer disposed on the semiconductor die and covering the sidewalls of the first conductive pad and the second conductive pad. The passivation layer is located between a portion of the first conductive pad and a portion of the first connector structure, and between a portion of the second conductive pad and a portion of the second connector structure.

[0072] Another embodiment of this disclosure relates to a semiconductor assembly including a semiconductor die, a plurality of first conductive pads, a plurality of second conductive pads, a plurality of first connector structures, and a plurality of second connector structures. The first conductive pads are disposed on a first region of the semiconductor die, wherein two of the first conductive pads have different lateral dimensions. Second conductive pads are disposed on a second region of the semiconductor die, and the second region is farther from a corner of the semiconductor die than the first region. First connector structures are disposed on the first conductive pads, wherein the lateral dimension of each of the first connector structures is larger than that of the corresponding first conductive pad. Second connector structures are disposed on the second conductive pads. The semiconductor assembly further includes a passivation layer disposed on the semiconductor die and covering the sidewalls of the first and second conductive pads. The passivation layer is located between portions of the first conductive pads and portions of the first connector structures, and between portions of the second conductive pads and portions of the second connector structures. The lateral dimension of each of the second connector structures is smaller than that of the corresponding second conductive pad. The semiconductor assembly further includes a first solder mask and a second solder mask, the first solder mask being disposed on the first connector structure, and the second solder mask being disposed on the second connector structure.

[0073] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor component, comprising: Semiconductor die; A first conductive pad is disposed on the semiconductor die, wherein the first conductive pad has a first lateral dimension and a first planar profile; A second conductive pad is disposed on the semiconductor die, wherein the second conductive pad has a second lateral dimension; A first connector structure is disposed on the first conductive pad, wherein the first connector structure has a second planar profile and a third lateral dimension that is larger than the first lateral dimension, and the first planar profile is located within the second planar profile, and the second planar profile surrounds the first planar profile to maintain an annular space between the first planar profile and the second planar profile. as well as A second connector structure is disposed on the second conductive pad, wherein the second connector structure has a fourth lateral dimension smaller than the second lateral dimension.

2. The semiconductor assembly as claimed in claim 1, wherein the fourth lateral dimension is the same as the third lateral dimension.

3. The semiconductor component as claimed in claim 1, further comprising a passivation layer disposed on the semiconductor die and covering the sidewalls of the first conductive pad and the second conductive pad.

4. The semiconductor assembly of claim 3, wherein the passivation layer is located between a portion of the first conductive pad and a portion of the first connector structure, and between a portion of the second conductive pad and a portion of the second connector structure.

5. The semiconductor assembly of claim 1, wherein the semiconductor assembly further includes a protective layer disposed on the semiconductor die, wherein the protective layer has a first opening on the first conductive pad and a second opening on the second conductive pad, the first connector structure being connected to the first conductive pad through the first opening and the second connector structure being connected to the second conductive pad through the second opening.

6. The semiconductor assembly of claim 1, wherein the first connector structure includes a first bump base metal (UBM) layer and a first columnar bump disposed on the first bump base metal layer, and the second connector structure includes a second bump base metal layer and a second columnar bump disposed on the second bump base metal layer.

7. The semiconductor component as claimed in claim 1, wherein the second conductive pad is farther from a corner of the semiconductor die than the first conductive pad.

8. The semiconductor assembly of claim 1, wherein the distance between the first conductive pad and the corner of the semiconductor die is less than or equal to 0.04 times the length of the sidewall edge of the semiconductor die.

9. A semiconductor component, comprising: Semiconductor die; A first conductive pad is disposed on a first region of the semiconductor die, wherein the first conductive pad has a first planar profile; A second conductive pad is disposed on a second region of the semiconductor die, the second region being further away from the corner of the semiconductor die than the first region, wherein the first conductive pad has a first lateral dimension, and the second conductive pad has a second lateral dimension greater than the first lateral dimension; A first connector structure is disposed on the first conductive pad, wherein the first connector structure has a second planar profile, and the first planar profile is located within the second planar profile, and the second planar profile surrounds the first planar profile to maintain an annular space between the first planar profile and the second planar profile. as well as The second connector structure is disposed on the second conductive pad.

10. The semiconductor assembly of claim 9, wherein the first connector structure includes a first bump base metal layer and a first columnar bump disposed on the first bump base metal layer, and the second connector structure includes a second bump base metal layer and a second columnar bump disposed on the second bump base metal layer.

11. The semiconductor assembly of claim 10, wherein the first bump bottom metal layer and the second bump bottom metal layer have the same lateral dimensions.

12. The semiconductor assembly of claim 9, wherein the distance between the first conductive pad and the corner of the semiconductor die is less than or equal to 0.04 times the length of the sidewall edge of the semiconductor die.

13. The semiconductor assembly of claim 9, wherein the first connector structure has a third lateral dimension and the second connector structure has a fourth lateral dimension that is the same as the third lateral dimension.

14. The semiconductor assembly of claim 9, wherein the semiconductor assembly further includes a passivation layer disposed on the semiconductor die and covering the sidewalls of the first conductive pad and the second conductive pad.

15. The semiconductor assembly of claim 14, wherein the passivation layer is located between a portion of the first conductive pad and a portion of the first connector structure, and between a portion of the second conductive pad and a portion of the second connector structure.

16. A semiconductor component, comprising: Semiconductor die; A plurality of first conductive pads are disposed on the semiconductor die in a first region, wherein two of the first conductive pads have different lateral dimensions, and at least one of the first conductive pads has a first planar profile. Multiple second conductive pads are disposed on the semiconductor die in a second region, which is further away from the corner of the semiconductor die than the first region; A plurality of first connector structures are disposed on the first conductive pad, wherein the lateral dimension of each of the first connector structures is larger than that of the corresponding first conductive pad, at least one of the first connector structures has a second planar profile, and the corresponding first planar profile is located within the second planar profile, and the second planar profile surrounds the first planar profile to maintain an annular space between the first planar profile and the second planar profile. as well as Multiple second connector structures are disposed on the second conductive pad.

17. The semiconductor assembly of claim 16, further comprising a passivation layer disposed on the semiconductor die and covering the sidewalls of the first conductive pad and the second conductive pad.

18. The semiconductor assembly of claim 17, wherein the passivation layer is located between a portion of the first conductive pad and a portion of the corresponding first connector structure, and between a portion of the second conductive pad and a portion of the corresponding second connector structure.

19. The semiconductor assembly of claim 16, wherein the lateral dimension of each of the second connector structures is smaller than that of the corresponding second conductive pad.

20. The semiconductor assembly of claim 16, wherein the semiconductor assembly further includes a first solder mask and a second solder mask, the first solder mask being disposed on the first connector structure and the second solder mask being disposed on the second connector structure.

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