Semiconductor device and method of forming the same

Abstract

In some implementations, one or more semiconductor processing tools can form a via for a semiconductor device. One or more semiconductor processing tools can deposit a metal plug within the via. One or more semiconductor processing tools can deposit an oxide-based layer on the metal plug within the via. One or more semiconductor processing tools can deposit a resistor on the oxide-based layer within the via. One or more semiconductor processing tools can deposit a first landing pad and a second landing pad on the resistor within the via. One or more semiconductor processing tools can deposit a first metal plug on the first landing pad and a second metal plug on the second landing pad.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for forming a semiconductor device. Background Technology

[0002] Semiconductor devices may include resistors to apply resistance based on the voltage difference between electrodes coupled to the ends of the resistor. The resistor may be configured with a landing pad (e.g., to provide coupling to a metal plug) defined within an intermetallic dielectric material of the semiconductor device. Summary of the Invention

[0003] One embodiment of this disclosure provides a method for forming a semiconductor device, comprising: forming a via of the semiconductor device; depositing a metal plug within the via; depositing an oxide substrate on the metal plug within the via; depositing a resistive layer on the oxide substrate within the via; depositing a landing pad layer on the resistive layer within the via; forming a resistor formed from the resistive layer and a first landing pad and a second landing pad formed from the landing pad layer within the via; and depositing a first metal plug on the first landing pad and a second metal plug on the second landing pad.

[0004] Another aspect of this disclosure provides a semiconductor device, comprising: a metal plug located within a through-hole of the semiconductor device; an oxide substrate located on the metal plug within the through-hole; a resistor located on the oxide substrate within the through-hole; a first landing pad and a second landing pad located on the resistor within the through-hole; a first metal plug located on the first landing pad; and a second metal plug located on the second landing pad.

[0005] Another embodiment of this disclosure provides a semiconductor device comprising: a through-hole, the through-hole including: a metal plug; an insulating layer on the metal plug located within the through-hole; a resistor on the insulating layer located within the through-hole; a first landing pad and a second landing pad on the resistor located within the through-hole; a first metal plug located on the first landing pad; and a second metal plug located on the second landing pad. The semiconductor device includes a first top metal electrode located on the first metal plug; and a second top metal electrode located on the second metal plug. Attached Figure Description

[0006] The best understanding of all aspects of this disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1It is a diagram of an exemplary environment in which the systems and / or methods described herein can be implemented.

[0008] Figures 2A to 2F This is a diagram illustrating the sequence of operations used to manufacture semiconductor devices as described herein.

[0009] Figure 3 Based on such Figures 2A to 2F A diagram of an exemplary semiconductor device formed by the described exemplary technology.

[0010] Figure 4 yes Figure 1 A diagram of an exemplary component of one or more devices.

[0011] Figure 5 This is a flowchart of an exemplary process for manufacturing semiconductor devices as described herein. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are set forth below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout this disclosure. This repetition is for the purpose of brevity and clarity and is not intended to indicate any relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of explanation, spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” are used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0014] Semiconductor devices may include resistors to apply resistance based on the voltage difference between electrodes coupled to the ends of the resistor. The resistor may be configured with a landing pad (e.g., to provide coupling to a metal plug) defined within an intermetallic dielectric material of the semiconductor device.

[0015] The semiconductor device may also include vias defined within the semiconductor device. A via may include a recess formed from the upper surface of the semiconductor device. For example, a via may include a groove defined within an intermetallic dielectric material. Structures within the via may include multiple layers, such as metal plugs electrically coupled to another material within the semiconductor device or electrically coupled to another semiconductor device.

[0016] Resistors and vias can be formed in different layers of the intermetallic dielectric material in a semiconductor device. To enable the resistors and vias to function properly, one or more semiconductor manufacturing machines can fine-tune the inter-vias to simultaneously land on the resistor (e.g., on a landing pad) and the intermetallic dielectric material.

[0017] In some cases, manufacturing semiconductor devices that include vias and resistors can be a complex process with a relatively high error rate. For example, when attempting to fine-tune an internal via to simultaneously land on a resistor and an intermetallic dielectric material, one or more semiconductor manufacturing machines may have a relatively high error rate. Alternatively, the manufacturing process may include a relatively large number of masking and etching operations to form vias and resistors at different depths in the semiconductor device, which can reduce manufacturing efficiency and increase cycle time.

[0018] Some embodiments described herein provide techniques and apparatus for placing resistors within vias of semiconductor devices. In some embodiments, the semiconductor device may include a metal plug (e.g., a metal layer) within a via of the semiconductor device and an oxide-based layer on the metal plug within the via. The oxide-based layer may provide electrical insulation to the metal plug within the via. The semiconductor device may also include a resistor on the oxide-based layer within the via and a first landing pad and a second landing pad on the resistor. The semiconductor device may further include a first metal plug on the first landing pad and a second metal plug on the second landing pad to provide electrical connection to the landing pad and through the resistor. Because the resistor is disposed within the via, the process of manufacturing the semiconductor device may have fewer operations, reduced operational complexity (e.g., by increasing manufacturing tolerance), lower process costs, and / or shorter manufacturing time compared to a process of manufacturing a semiconductor device with the resistor disposed outside the via (e.g., in a different layer within an intermetallic dielectric material outside the via).

[0019] Figure 1 This is a diagram of an exemplary environment 100 in which the systems and / or methods described herein can be implemented. For example... Figure 1As shown, environment 100 may include multiple semiconductor processing equipment (deposition equipment 102, etching equipment 104, chemical-mechanical polishing (CMP) equipment 106) and wafer / die transport device 108. The multiple semiconductor processing equipment (deposition equipment 102, etching equipment 104, CMP equipment 106) may include deposition equipment 102, etching equipment 104, and / or CMP equipment 106, etc. The semiconductor processing equipment included in the exemplary environment 100 may be included in a semiconductor clean room, a semiconductor foundry, and / or a semiconductor processing and / or manufacturing facility, etc.

[0020] Deposition equipment 102 is a semiconductor processing equipment capable of depositing various types of materials onto a substrate. In some embodiments, deposition equipment 102 includes a spin coater capable of depositing a photoresist layer on a substrate such as a wafer. In some embodiments, deposition equipment 102 includes a chemical vapor deposition (CVD) equipment, such as a plasma-enhanced CVD (PECVD) equipment, a high-density plasma CVD (HDP-CVD) equipment, a sub-atmospheric CVD (SACVD) equipment, an atomic layer deposition (ALD) equipment, a plasma-enhanced atomic layer deposition (PEALD) equipment, or another type of CVD equipment. In some embodiments, deposition equipment 102 includes a physical vapor deposition (PVD) equipment, such as a sputtering equipment or another type of PVD equipment. In some implementations, exemplary environment 100 includes various types of deposition stations 102.

[0021] Etching station 104 is a semiconductor processing equipment capable of etching (e.g., removing) various types of materials, including substrates, wafers, or semiconductor devices. For example, etching station 104 may include wet etching stations, dry etching stations, laser etching stations, chemical etching stations, plasma etching stations, reactive ion etching stations, sputtering etching stations, and / or vapor phase etching stations. A wet etching station may include a chamber filled with an etchant, and a substrate may be placed in the chamber for a specific period of time to remove one or more portions of the substrate. A dry etching station may use plasma etching techniques (e.g., plasma sputtering) and / or plasma-assisted etching (which may involve using ionized gas to isotropically or directionally etch one or more portions) to remove one or more portions of the substrate. In some embodiments, etching station 104 may remove layers from a semiconductor device as described herein.

[0022] CMP machine 106 is a semiconductor processing machine comprising one or more devices capable of polishing or planarizing wafers or semiconductor devices of various layers. In some embodiments, CMP machine 106 can polish or planarize layers of deposited or plated material. CMP machine 106 can polish or planarize the surface of semiconductor devices by a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive polishing). The CMP machine can combine a polishing pad and a retaining ring (e.g., typically having a diameter larger than the semiconductor device) using a polishing and corrosive chemical polishing slurry. The polishing pad and semiconductor device can be pressed together by a dynamic polishing head and secured by the retaining ring. The dynamic polishing head can rotate on different axes of rotation to remove material and plan any irregularities in the topography of the semiconductor device, making the semiconductor device flat or planar.

[0023] The wafer / die transport device 108 includes mobile robots, robotic arms, trams, or railcars, and / or another type of device for transporting wafers and / or dies between semiconductor processing equipment (deposition equipment 102, etching equipment 104, CMP equipment 106), and / or to and from other locations (e.g., wafer racks, storage rooms, etc.). In some embodiments, the wafer / die transport device 108 may be a programmed device to travel along a specific path and / or be semi-autonomously or automatically operated.

[0024] Figure 1The number and arrangement of the devices shown are provided as one or more examples. In fact, with... Figure 1 Compared to the number and arrangement of the devices shown, there may be additional devices, fewer devices, different devices, or devices arranged in different ways. Furthermore, Figure 1 The two or more devices shown can be implemented within a single device, or Figure 1 The single device shown can be implemented as multiple distributed devices. Alternatively or additionally, a group of devices in environment 100 (e.g., one or more devices) can perform one or more functions described as being performed by another group of devices in environment 100.

[0025] Figures 2A to 2F This is an illustration of one or more exemplary embodiments described herein. As described herein, exemplary embodiments may include one or more exemplary embodiments of a process for manufacturing semiconductor device 200. In some embodiments, exemplary embodiments may include a process for manufacturing semiconductor device 200 in which resistors are formed within vias of semiconductor device 200.

[0026] like Figure 2A As shown, the semiconductor device 200 may include an intermetallic dielectric (IMD) material 202, and one or more metal electrodes 204 are disposed within the IMD material 202 (e.g., below the upper surface of the IMD material and / or above the lower surface of the IMD material). In some embodiments, a deposition apparatus (e.g., deposition apparatus 102) may deposit the IMD material 202 onto a substrate of the semiconductor device 200. In some embodiments, the deposition apparatus may use high-density plasma deposition, plasma-enhanced chemical vapor deposition, chemical vapor deposition, or physical vapor deposition, etc., to deposit the IMD material 202 onto the semiconductor device 200. In some aspects, the IMD material 202 may include a silicon-rich oxide material and / or fluorosilicate glass, etc.

[0027] In some embodiments, a deposition stage may deposit a layer of metallic material on the upper surface of a first portion of the IMD material 202, and an etching stage (e.g., etching stage 104) may etch (e.g., remove) a portion of the metallic material layer to form one or more metallic electrodes 204. Figure 2A As shown, the deposition equipment can deposit additional IMD material between and on one or more metal electrodes 204 to form a semiconductor device 200.

[0028] In some embodiments, a CMP apparatus (e.g., CMP apparatus 106) can planarize the upper surface of the IMD material 202. In some embodiments, a deposition apparatus can deposit a layer of antireflective coating material (e.g., undoped silicate glass) on the upper surface of the IMD material 202 (e.g., after planarization).

[0029] like Figure 2B As shown, an etching apparatus (e.g., etching apparatus 104) can etch portions of the IMD material 202 to form vias 206 (e.g., recesses in the IMD material 202). The etching apparatus can also etch one or more additional portions of the IMD material 202 to form additional vias between the upper surface of the IMD material 202 and one or more metal electrodes 204.

[0030] A deposition stage (e.g., deposition stage 102) can deposit one or more layers of material including a metal plug 208, an insulating layer 210, a resistive layer 212, a landing pad layer 214, and / or an oxide nitride layer 216. In some embodiments, the deposition stage may use high-density plasma deposition, plasma-enhanced chemical vapor deposition, chemical vapor deposition, or physical vapor deposition, etc., to deposit one or more layers of material on the semiconductor device 200 and / or within the via 206.

[0031] In some embodiments, a deposition apparatus may sequentially deposit one or more layers. For example, a metal plug 208 may be deposited on an IMD material 202 (e.g., in a via and / or within an additional via between the upper surface of the IMD material 202 and one or more metal electrodes 204). In some embodiments, the metal plug 208 may fill the additional via between the upper surface of the IMD material 202 and one or more metal electrodes 204. In some embodiments, the metal plug 208 may be deposited within a via 206 (e.g., on the sidewalls and bottom surface of the via 206). For example, a deposition apparatus may deposit the metal plug 208 to fill the additional via between the upper surface of the IMD material 202 and one or more metal electrodes 204 and to cover the surface of the via 206. A CMP apparatus (e.g., CMP apparatus 106) may planarize the upper surface of the metal plug 208 and / or an etching apparatus (e.g., etching apparatus 104) may etch portions of the metal plug 208 within the via 206.

[0032] The deposition apparatus can deposit an insulating layer 210 on the metal plug 208, a resistive layer 212 on the insulating layer 210, a landing pad layer 214 on the resistive layer 212, and / or a nitride layer 216 on the landing pad layer 214. The deposition apparatus can also deposit the insulating layer 210, the resistive layer 212, the landing pad layer 214, and / or the nitride layer 216 within and / or outside the via 206 (e.g., on the upper surface of the semiconductor device 200 and / or the upper surface of the metal plug 208). In some embodiments, the insulating layer 210, the resistive layer 212, the landing pad layer 214, and / or the nitride layer 216 may have a substantially uniform thickness within and outside the via 206.

[0033] In some embodiments, the layers may be arranged differently from the described arrangement, one or more described layers may be omitted, and / or additional layers (e.g., adhesive layers) may be added between the described layers. For example, the deposition equipment may deposit an adhesive layer (e.g., titanium nitride-based material) on the IMD material 202 before depositing the metal plug 208 to improve bonding and / or reduce peeling of the metal plug 208 within the via 206.

[0034] In some embodiments, the metal plug 208 may comprise a tungsten-based material. The metal plug 208 provides isolation (e.g., electrical insulation) between the resistive layer 212 and the IMD material 202. In some embodiments, the insulating layer 210 may comprise an oxide-based material (e.g., silicon-rich oxide). The insulating layer 210 (e.g., an oxide base layer) provides buffering and / or electrical insulation between the metal plug 208 and the resistive layer 212. In some embodiments, the resistive layer 212 may comprise a silicon-chromium-based material. In some embodiments, the landing pad layer 214 may comprise a metallic material, such as a titanium nitride-based material. The landing pad layer 214 provides a connection to the resistive layer 212. In this way, the metallic material may be disposed within the landing pad layer 214 to establish an electrical connection to the resistive layer 212 when the metallic material is not disposed within the resistive layer 212. In some embodiments, the oxide nitride layer 216 may comprise an oxide nitride-based material. The oxide nitride layer can provide a bottom anti-reflective coating for extreme ultraviolet lithography to reduce and / or eliminate substrate reflection during photoresist exposure operations (e.g., during etching operations).

[0035] like Figure 2CAs shown, an etching station (e.g., etching station 104) can etch portions of the landing pad layer 214 and the oxide nitride layer 216 at the etched portion 218 within the via 206 to form two separate portions of the landing pad layer 214 and the oxide nitride layer 216 within the via 206. As part of etching the etched portion 218, a deposition station (e.g., deposition station 102) can deposit photoresist on the upper surface of the semiconductor device (excluding the etched portion 218) before the etching station performs one or more etching operations. In this way, one or more etching operations can remove material from the etched portion 218 (e.g., and not outside the etched portion 218). In some embodiments, the etching station can perform additional etching operations to remove the photoresist.

[0036] In some embodiments, the two separate portions of the landing pad layer 214 and the oxide nitride layer 216 may include a first portion and a second portion generally parallel to the upper surface of the semiconductor device 200. In some embodiments, an etching apparatus may perform landing pad breakthrough (e.g., titanium nitride breakthrough), cleaning operations (e.g., post-etching residual polymer removal, post-etching residual photoresist removal, or EKC cleaning, etc.) to remove irregularities from the upper surfaces of the landing pad layer 214 and / or the oxide nitride layer 216, and / or wet etching processes of the landing pad to etch portions of the landing pad layer 214 and the oxide nitride layer 216. After etching, the first portion and the second portion of the landing pad layer 214 may be electrically isolated within the via 206.

[0037] like Figure 2D As shown, a deposition apparatus (e.g., deposition apparatus 102) can deposit an insulating layer 220 (e.g., an oxide base layer) and / or a dielectric material 222 (e.g., additional IMD material) on the upper surface of the semiconductor device 200 (including within via 206) and can deposit the dielectric material 222 on the insulating layer 220 (e.g., within and / or outside via 206). For example, the deposition apparatus can deposit the insulating layer 220 on an oxide nitride layer 216 (e.g., within and / or outside via 206) and on a resistive layer 212 at a portion 218 etched within via 206. In some embodiments, the insulating layer 220 may have a substantially uniform thickness within and outside via 206. In some embodiments, the dielectric material 222 may substantially fill via 206 until at least the upper surface of the dielectric material 222 is outside via 206.

[0038] In some embodiments, the deposition apparatus may use high-density plasma deposition, plasma-enhanced chemical vapor deposition, chemical vapor deposition, or physical vapor deposition to deposit the insulating layer 220 and / or dielectric material 222. The insulating layer 220 may provide buffering and / or electrical insulation between the resistive layer 212 and the dielectric material 222. In some embodiments, the insulating layer 220 may comprise an oxide-based material (e.g., silicon-rich oxide).

[0039] like Figure 2E As shown, a CMP machine (e.g., CMP machine 106) can planarize the upper surface of a semiconductor device 200 to remove one or more materials. In some embodiments, the CMP machine may use one or more CMP operations to planarize the upper surface of the semiconductor device 200. For example, the CMP machine may planarize the insulating layer 220 and dielectric material 222 in a first operation to remove a layer of material above a metal plug 208 on the upper surface of the semiconductor device 200. In some embodiments, the first operation may include removing all material above the metal plug 208 from the upper surface of the semiconductor device 200 so that only the metal plug 208 is disposed above the upper surface of the IMD material 202 (e.g., outside of vias 206 and additional vias between the upper surface of the IMD material 202 and one or more metal electrodes 204). Alternatively or additionally, the CMP machine may planarize the metal plug 208 in a second operation. In some embodiments, the second operation may include removing the metal plug 208 from the upper surface of the semiconductor device 200, such that no metal plug 208 is disposed above the upper surface of the IMD material 202 except for the via 206 and the additional via between the upper surface of the IMD material 202 and one or more metal electrodes 204. In some embodiments, the first and second operations are part of the same CMP operation (e.g., a single CMP operation planarizes the metal plug 208 and the layer of material above the metal plug 208 on the upper surface of the semiconductor device 200).

[0040] Similarly, Figure 2E As shown, the CMP equipment can form resistor 224 by removing a portion of the resistive layer 212 from outside the via 206. The CMP equipment can also form a first landing pad 226 and a second landing pad 228 within the via 206 by removing a portion of the landing pad layer 214 from outside the via 206. The first landing pad 226 and the second landing pad 228 can be electrically coupled through resistor 224.

[0041] As in Figure 2EAs further shown, the CMP equipment can form a separate metal plug 230 (e.g., from metal plug 208) in an additional via (e.g., outside via 206) based on removing a portion of the metal plug 208 from the upper surface of the IMD material 202. The additional via can connect the upper surface of the semiconductor device 200 to one or more metal electrodes 204 within the IMD material 202. The metal plug 230 in the additional via can provide isolated electrical connections to one or more metal electrodes 204.

[0042] like Figure 2F As shown, an etching apparatus (e.g., etching apparatus 104) can etch portions of the dielectric material 222, portions of the insulating layer 220, portions of the oxide nitride layer 216, portions of the first landing pad 226, and / or portions of the second landing pad 228, etc., to form a first resistor via and a second resistor via within the via 206. The first resistor via and the second resistor via can respectively connect the first landing pad 226 and the second landing pad 228 to the upper surface of the semiconductor device 200. A deposition apparatus (e.g., deposition apparatus 102) can deposit a first metal plug 232 within the first resistor via to provide an electrical connection from the upper surface of the semiconductor device 200 to the first landing pad 226 and a first portion of the resistor 224. Furthermore, the deposition apparatus can deposit a second metal plug 234 within the second resistor via to provide an electrical connection from the upper surface of the semiconductor device 200 to the second landing pad 228 and a second portion of the resistor 224. In some embodiments, the deposition equipment may use high-density plasma deposition, plasma-enhanced chemical vapor deposition, chemical vapor deposition or physical vapor deposition, etc., to deposit a first metal plug 232 in the first resistor via and / or deposit a second metal plug 234 in the second resistor via.

[0043] In some implementations, a CMP machine (e.g., CMP machine 106) may planarize the upper surface of the semiconductor device 200 after depositing the first metal plug 232 and the second metal plug 234, in order to planarize the upper surface of the first metal plug 232, the upper surface of the second metal plug 234, and the upper surface of the semiconductor device 200 (e.g., via structures within via 206 and / or additional vias and metal plugs in the IMD material 202 outside via 206).

[0044] The process of manufacturing semiconductor device 200 can have reduced process costs and / or shorter manufacturing time compared to the process of manufacturing semiconductor devices with resistors disposed inside via 206 (e.g., in a layer of the same IMD material 202 as the via) and outside via 206 (e.g., in an intermetallic dielectric material outside the via) and in different layers of IMD material 202 outside via 206.

[0045] Provide such as Figures 2A to 2F The structures and / or layers shown are examples. In practice, this includes additional structures and / or layers, fewer structures and / or layers, different structures and / or layers, or structures and / or layers similar to... Figures 2A to 2F Semiconductor devices with structures and / or layers arranged in different ways as shown can be manufactured according to, for example... Figures 2A to 2F The aforementioned techniques are used to handle this.

[0046] Figure 3 Based on such Figures 2A to 2F A diagram of a semiconductor device 200 formed by the exemplary technology described herein.

[0047] like Figure 3 As shown, the semiconductor device 200 may include an IMD material 202 and one or more metal electrodes 204. Within a via (e.g., disposed within the IMD material 202), the semiconductor device 200 may also include a metal plug 208 (e.g., comprising a metallic material, such as a tungsten-based material), a metal plug 208 on an insulating layer 210 (e.g., an oxide-based material), a resistor 224 on an insulating layer 220, a first landing pad 226 and a second landing pad 228 on the resistor 224, a first metal plug 232 on the first landing pad 226 and / or a second metal plug 234 on the second landing pad 228.

[0048] In some embodiments, the semiconductor device 200 may further include an oxide nitride layer 216 on portions of the first landing pad 226 and the second landing pad 228 within the via. In some embodiments, the semiconductor device 200 may further include an insulating layer 220 on portions of the resistor 224, portions of the first landing pad 226 and the second landing pad 228, and / or portions of the oxide nitride layer 216 within the via. Alternatively or additionally, the semiconductor device 200 may include a dielectric material 222 on portions of the insulating layer 220 within the via.

[0049] Furthermore, the semiconductor device 200 may include a first metal electrode 302 deposited on a first metal plug 232 and a second metal electrode 304 deposited on a second metal plug 234. In some aspects, the first metal plug 232 may provide electrical coupling of a first portion of the resistor 224 (e.g., through a first landing pad 226) to the first metal electrode 302 (e.g., a first top metal electrode), and the second metal plug 234 may provide electrical coupling of a second portion of the resistor 224 (e.g., through a second landing pad 228) to the second metal electrode 304 (e.g., a second top metal electrode). In this way, the resistor 224 may be configured to provide resistance based on the applied voltage difference between the first metal electrode 302 and the second metal electrode 304.

[0050] In some embodiments, the semiconductor device 200 may also include one or more metal plugs 230 in additional vias outside the vias and providing electrical connections between one or more metal electrodes 204 and one or more additional metal electrodes 306.

[0051] As mentioned above, providing Figure 3 As an example. Other instances may be similar. Figure 3 The descriptions are different.

[0052] Figure 4 These are icons representing exemplary components of device 400. In some embodiments, deposition stage 102, etching stage 104, CMP stage 106, and / or wafer / die transport device 108 may include one or more devices 400 and / or components of one or more devices 400. Figure 4 As shown, device 400 may include bus 410, processor 420, memory 430, storage component 440, input component 450, output component 460 and communication component 470.

[0053] Bus 410 includes components enabling wired / wireless communication between multiple components of device 400. Processor 420 includes a central processing unit (CPU), graphics processing unit (GPU), microprocessor, microcontroller, digital signal processor (DSP), field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), and / or another type of processing component. Processor 420 is implemented in hardware, firmware, and / or a combination of hardware and software. In some embodiments, processor 420 includes one or more processors programmable to perform functions. Memory 430 includes random access memory (RAM), read-only memory (ROM), and / or another type of memory (e.g., flash memory, magnetic memory, and / or optical memory).

[0054] Storage component 440 stores information and / or software related to the operation of device 400. For example, storage component 440 may include a hard disk drive, disk drive, optical disk drive, solid-state drive (SSD), compact disc (CD), digital versatile disc (DVD), and / or another type of non-transitory computer-readable storage medium. Input component 450 enables device 400 to receive input, such as user input and / or sensor input. For example, input component 450 may include a touchscreen display, keyboard, keypad, mouse, buttons, microphone, sensor, global positioning system (GPS), accelerometer, gyroscope, and / or actuator. Output component 460 enables device 400 to provide output, such as via a display, speaker, and / or one or more light-emitting diodes. Communication component 470 enables device 400 to communicate with other devices, such as via wired and / or wireless connections. For example, communication component 470 may include a receiver, transmitter, transceiver, modem, network interface card, and / or antenna.

[0055] Device 400 may perform one or more processes described herein. For example, a non-transitory computer-readable storage medium (e.g., memory 430 and / or storage component 440) may store a set of instructions (e.g., one or more instructions, code, software code, and / or program code, etc.) for execution by processor 420. Processor 420 may execute the set of instructions to perform one or more processes described herein. In some embodiments, the set of instructions is executed by one or more processors 420, causing one or more processors 420 and / or device 400 to perform one or more processes described herein. In some embodiments, hardware circuitry may be used in place of or in combination with software instructions to perform one or more processes described herein. Therefore, the embodiments described herein are not limited to any particular combination of hardware circuitry and software.

[0056] supply Figure 4 The number and arrangement of components shown are examples. Device 400 may include additional components, fewer components, different components, or components arranged in a different manner. Alternatively or additionally, a group of components of device 400 (e.g., one or more components) may perform one or more functions described as being performed by another group of components of device 400.

[0057] Figure 5 This is a flowchart of an exemplary process for manufacturing semiconductor devices. In some embodiments, Figure 5One or more process blocks can be performed by one or more semiconductor processing equipment (e.g., one or more of deposition equipment 102, etching equipment 104, CMP equipment 106, and / or wafer / die transport device 108). Alternatively or alternatively, Figure 5 One or more process blocks in the device 400 may be executed by one or more components of the device 400, such as processor 420, memory 430, storage component 440, input component 450, output component 460 and / or communication component 470.

[0058] like Figure 5 As shown, process 500 may include forming vias (block 510) of a semiconductor device. For example, as described above, one or more semiconductor processing equipment (e.g., deposition equipment 102, etching equipment 104, CMP equipment 106) may form vias 206 of the semiconductor device 200.

[0059] like Figure 5 As further shown, process 500 may include depositing a metal plug (block 520) within the via 206. For example, as described above, one or more semiconductor processing equipment (e.g., deposition equipment 102, etching equipment 104, CMP equipment 106) may deposit a metal plug 208 within the via 206.

[0060] like Figure 5 As further shown, process 500 may include depositing an oxide base layer (block 530) on a metal plug within a via. For example, as described above, one or more semiconductor processing equipment (e.g., deposition equipment 102, etching equipment 104, CMP equipment 106) may deposit an oxide base layer (e.g., insulating layer 210) on a metal plug 208 within a via 206.

[0061] like Figure 5 As further shown, process 500 may include depositing a resistive layer (block 540) on an oxide substrate within a via. For example, as described above, one or more semiconductor processing equipment (e.g., deposition equipment 102, etching equipment 104, CMP equipment 106) may deposit a resistive layer 212 on an oxide substrate (e.g., insulating layer 210) within the via 206.

[0062] like Figure 5 As further shown, process 500 may include depositing a landing pad layer on the resistive layer within the via (block 550). For example, as described above, one or more semiconductor processing equipment (e.g., deposition equipment 102, etching equipment 104, CMP equipment 106) may deposit a landing pad layer 214 on the resistive layer 212 within the via 206.

[0063] like Figure 5As further shown, process 500 may include forming a resistor formed from a resistive layer and a first landing pad and a second landing pad formed from a landing pad layer within the via 206 (block 560). For example, one or more semiconductor processing equipment (e.g., deposition equipment 102, etching equipment 104, CMP equipment 106) may form a resistor 224 formed from a resistive layer 212 and a first landing pad 226 and a second landing pad 228 formed from a landing pad layer 214 within the via 206.

[0064] like Figure 5 As further shown, process 500 may include depositing a first metal plug on a first landing pad and depositing a second metal plug on a second landing pad (block 570). For example, as described above, one or more semiconductor processing equipment may deposit a first metal plug 232 on a first landing pad 226 and a second metal plug 234 on a second landing pad 228.

[0065] Process 500 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or in combination with one or more other processes described elsewhere herein.

[0066] In the first embodiment, process 500 includes depositing an additional oxide substrate on the resistor, the first landing pad, and the second landing pad within a via after forming the resistor, the first landing pad, and the second landing pad.

[0067] In the second embodiment, alone or in combination with the first embodiment, process 500 includes depositing a nitrogen oxide base layer on the first landing pad and the second landing pad.

[0068] In the third embodiment, forming the first landing pad and the second landing pad, alone or in combination with one or more of the first and second embodiments, includes etching a portion of the landing pad layer to form the first landing pad and the second landing pad.

[0069] In the fourth embodiment, alone or in combination with one or more of the first to third embodiments, process 500 includes depositing an intermetallic dielectric material in a via prior to depositing the first metal plug and the second metal plug, and etching a first portion of the intermetallic dielectric material to form a first resistor via for the first metal plug, and etching a second portion of the intermetallic dielectric material to form a second resistor via for the second metal plug.

[0070] In the fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, process 500 includes depositing a first metal electrode on a first metal plug and depositing a second metal electrode on a second metal plug.

[0071] In the sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, the resistor is configured to provide resistance based on the application of a voltage difference across the first metal electrode and the second metal electrode.

[0072] In the seventh embodiment, alone or in combination with one or more of the first to sixth embodiments, process 500 includes performing one or more CMP operations prior to depositing the first metal plug and the second metal plug.

[0073] although Figure 5 The illustration shows an exemplary block in process 500, but in some embodiments, process 500 may include additional blocks, fewer blocks, different blocks, or blocks with... Figure 5 The blocks shown are arranged in different ways. Alternatively, two or more blocks in process 500 can be executed in parallel.

[0074] In this way, based on the resistor being disposed in the via (e.g., at a layer of the same IMD material 202 as the via), the process of manufacturing the semiconductor device can have reduced process costs and / or shorter manufacturing time compared to the process of manufacturing a semiconductor device with the resistor disposed outside the via 206 (e.g., in an intermetallic dielectric material outside the via) and at different layers of the IMD material 202 outside the via 206.

[0075] As described in more detail above, some embodiments described herein provide a method for forming a semiconductor device. The method includes forming a through-hole of the semiconductor device. The method includes depositing a metal plug in the through-hole. The method includes depositing an oxide substrate on the metal plug within the through-hole. The method includes depositing a resistor on the oxide substrate within the through-hole. The method includes depositing a first landing pad and a second landing pad on the resistor within the through-hole. The method includes depositing a first metal plug on the first landing pad and a second metal plug on the second landing pad.

[0076] An embodiment of this disclosure of a method for forming a semiconductor device further includes: after forming the resistor, the first landing pad and the second landing pad, depositing an additional oxide substrate on the resistor, the first landing pad and the second landing pad within the via.

[0077] A method for forming a semiconductor device according to an embodiment of the present disclosure further includes: depositing a nitrogen oxide substrate on the first landing pad and the second landing pad.

[0078] An embodiment of this disclosure provides a method for forming a semiconductor device, wherein forming the first landing pad and the second landing pad includes: etching a portion of the landing pad layer to form the first landing pad and the second landing pad.

[0079] An embodiment of the present disclosure of a method for forming a semiconductor device further includes: depositing an intermetallic dielectric material in the via before depositing the first metal plug and the second metal plug; and etching a first portion of the intermetallic dielectric material to form a first resistor via for the first metal plug and etching a second portion of the intermetallic dielectric material to form a second resistor via for the second metal plug.

[0080] An embodiment of this disclosure provides a method for forming a semiconductor device, which further includes: depositing a first metal electrode on a first metal plug and depositing a second metal electrode on a second metal plug.

[0081] An embodiment of this disclosure provides a method for forming a semiconductor device, wherein the resistor is configured to provide resistance based on the application of a voltage difference across a first metal electrode and a second metal electrode.

[0082] A method for forming a semiconductor device according to an embodiment of the present disclosure further includes: performing one or more chemical mechanical polishing operations before depositing the first metal plug and the second metal plug.

[0083] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a metal plug located within a through-hole of the semiconductor device. The semiconductor device includes an oxide substrate on the metal plug located within the through-hole. The semiconductor device includes a resistor on the oxide substrate located within the through-hole. The semiconductor device includes a first landing pad and a second landing pad on the resistor located within the through-hole. The semiconductor device includes a first metal plug on the first landing pad and a second metal plug on the second landing pad.

[0084] A semiconductor device according to an embodiment of the present disclosure, wherein the via is disposed within an intermetallic dielectric material.

[0085] A semiconductor device according to an embodiment of this disclosure further includes: one or more additional vias connecting the upper surface of the semiconductor device to one or more metal electrodes within the intermetallic dielectric material, wherein the one or more metal electrodes are located outside the vias.

[0086] A semiconductor device according to an embodiment of the present disclosure, wherein the metal plug provides isolation between the resistor and the intermetallic dielectric material.

[0087] A semiconductor device according to an embodiment of the present disclosure, wherein a first metal plug provides electrical coupling of a first portion of the resistor to a first top metal electrode, and wherein a second metal plug provides electrical coupling of a second portion of the resistor to a second top metal electrode.

[0088] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a through-hole comprising a metal plug; an insulating layer on the metal plug within the through-hole; a resistor on the insulating layer within the through-hole; a first landing pad and a second landing pad on the resistor within the through-hole; a first metal plug on the first landing pad; and a second metal plug on the second landing pad. The semiconductor device includes a first top metal electrode on the first metal plug. The semiconductor device includes a second top metal electrode on the second metal plug.

[0089] According to an embodiment of the present disclosure, a semiconductor device is provided in which one or more of the metal plugs, the first metal plug or the second metal plug, comprise a tungsten-based material.

[0090] A semiconductor device according to an embodiment of the present disclosure, wherein the first landing pad and the second landing pad comprise a titanium nitride-based material.

[0091] A semiconductor device according to an embodiment of the present disclosure, wherein the resistor comprises a silicon-chromium based material.

[0092] A semiconductor device according to an embodiment of this disclosure further includes: an additional oxide substrate located on a portion of the resistor between the first landing pad and the second landing pad within the via.

[0093] A semiconductor device according to an embodiment of this disclosure further includes a dielectric material located on the additional oxide substrate within the via.

[0094] A semiconductor device according to an embodiment of the present disclosure, wherein the metal plug provides isolation between the resistor and the intermetallic dielectric material of the semiconductor device.

[0095] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or attain the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor device, comprising: Forming through-holes in semiconductor devices; A metal plug is deposited within the through-hole; An oxide base layer is deposited on the metal plug within the through-hole; A resistive layer is deposited on the oxide substrate within the through-hole; A landing pad layer is deposited on the resistive layer within the through-hole; A resistor formed from the resistive layer and a first landing pad and a second landing pad formed from the landing pad layer are formed within the through hole; as well as A first metal plug is deposited on the first landing pad and a second metal plug is deposited on the second landing pad.

2. The method for forming a semiconductor device according to claim 1, further comprising: After the resistor, the first landing pad and the second landing pad are formed, an additional oxide base layer is deposited on the resistor, the first landing pad and the second landing pad within the through hole.

3. The method for forming a semiconductor device according to claim 1, further comprising: Nitrogen oxide base layers are deposited on the first landing pad and the second landing pad.

4. The method of forming a semiconductor device according to claim 1, wherein forming the first landing pad and the second landing pad comprises: A portion of the landing pad layer is etched to form the first landing pad and the second landing pad.

5. The method for forming a semiconductor device according to claim 1, further comprising: Before depositing the first metal plug and the second metal plug, an intermetallic dielectric material is deposited in the through-hole; as well as The first portion of the intermetallic dielectric material is etched to form a first resistor via for the first metal plug, and the second portion of the intermetallic dielectric material is etched to form a second resistor via for the second metal plug.

6. The method for forming a semiconductor device according to claim 1, further comprising: A first metal electrode is deposited on the first metal plug and a second metal electrode is deposited on the second metal plug.

7. The method of forming a semiconductor device according to claim 6, wherein the resistor is configured to provide resistance based on the application of a voltage difference across the first metal electrode and the second metal electrode.

8. The method for forming a semiconductor device according to claim 1, further comprising: One or more chemical mechanical polishing operations are performed before depositing the first metal plug and the second metal plug.

9. A semiconductor device, comprising: A metal plug is located inside the through-hole of the semiconductor device; An oxide substrate is located on the metal plug within the through hole; A resistor is located on the oxide substrate within the through-hole; The first landing pad and the second landing pad are located on the resistor within the through hole; A first metal plug is located on the first landing pad, wherein the first metal plug provides electrical coupling of a first portion of the resistor to a first top metal electrode; as well as A second metal plug, located on the second landing pad, wherein the second metal plug provides electrical coupling of a second portion of the resistor to a second top metal electrode.

10. The semiconductor device of claim 9, wherein the via is disposed within the intermetallic dielectric material.

11. The semiconductor device of claim 10, further comprising: One or more additional vias connect the upper surface of the semiconductor device to one or more metal electrodes within the intermetallic dielectric material, wherein the one or more metal electrodes are located outside the vias.

12. The semiconductor device of claim 10, wherein the metal plug provides isolation between the resistor and the intermetallic dielectric material.

13. A semiconductor device, comprising: Through holes, including: Metal plug; An insulating layer is located on the metal plug within the through hole; A resistor is located on the insulating layer within the through-hole; The first landing pad and the second landing pad are located on the resistor within the through hole; A first metal plug is located on the first landing pad; and The second metal plug is located on the second landing pad; A first top metal electrode is located on the first metal plug; and The second top metal electrode is located on the second metal plug.

14. The semiconductor device of claim 13, wherein one or more of the metal plugs, the first metal plug or the second metal plug comprises a tungsten-based material.

15. The semiconductor device of claim 13, wherein the first landing pad and the second landing pad comprise a titanium nitride-based material.

16. The semiconductor device of claim 13, wherein the resistor comprises a silicon-chromium based material.

17. The semiconductor device of claim 13, further comprising: An additional oxide base layer is located on a portion of the resistor between the first landing pad and the second landing pad within the through-hole.

18. The semiconductor device of claim 17, further comprising: Dielectric material is located on the additional oxide substrate within the through-hole.

19. The semiconductor device of claim 13, wherein the metal plug provides isolation between the resistor and the intermetallic dielectric material of the semiconductor device.

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