Pixel sensor and method of manufacturing the same

Abstract

A pixel sensor and a method of fabricating the same are provided. The method deposits a contact etch stop layer on a substrate. The contact etch stop layer includes less than about 12% hydrogen. Depositing the contact etch stop layer includes depositing a contact etch stop layer material at a temperature greater than about 600 °C, a pressure greater than about 150 Torr, and / or at a ratio of NH3 and SiH4 of at least greater than about 70:1. A silicon-based layer is deposited over the contact etch stop layer. An etching operation is performed into the silicon-based layer until the contact etch stop layer is reached to form a trench isolation structure. The present invention can reduce (or eliminate) ghosting effects.

Description

Technical Field

[0001] This invention relates to a pixel sensor and a method for manufacturing it. Background Technology

[0002] Complementary metal-oxide-semiconductor (CMOS) image sensors use photosensitive CMOS circuits (called pixel sensors) to convert light energy into electrical energy. Pixel sensors typically include photodiodes formed on a silicon substrate. When a photodiode is exposed to light, a charge is induced within it. Sampling of this charge within the photodiode is used to generate a digital image. Summary of the Invention

[0003] A pixel sensor according to an embodiment of this disclosure includes: a substrate; a contact etch stop layer disposed on the substrate, wherein the contact etch stop layer includes less than about 12% hydrogen; a silicon substrate disposed above the contact etch stop layer, wherein the silicon substrate includes a photodiode; and one or more trench isolation structures disposed through the silicon substrate to the contact etch stop layer.

[0004] An embodiment of this disclosure provides a method for manufacturing a pixel sensor, comprising: depositing a contact etch stop layer on a substrate, wherein depositing the contact etch stop layer includes depositing a contact etch stop layer material at a temperature above about 600°C and a pressure above about 150 Torr; depositing a silicon substrate over the contact etch stop layer; and performing an etching operation into the silicon substrate until reaching the contact etch stop layer to form a trench isolation structure.

[0005] An embodiment of this disclosure discloses a method for manufacturing a pixel sensor, comprising: depositing a contact etch stop layer on a substrate, wherein depositing the contact etch stop layer comprises depositing a contact etch stop layer material at a temperature above about 600°C, and wherein depositing the contact etch stop layer material comprises depositing NH3 and SiH4 in a ratio above about 70:1; depositing a silicon substrate over the contact etch stop layer; and performing an etching operation to etch trenches for trench isolation structures into the silicon substrate until reaching the contact etch stop layer. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 A diagram is a sample environment in which the systems and / or methods described herein can be implemented.

[0008] Figure 2A and Figure 2B This is a diagram of the example semiconductor structure described in this article.

[0009] Figures 3A-3F This is a diagram of an example implementation described in this article.

[0010] Figure 4 yes Figure 1 A diagram of example components of one or more devices.

[0011] Figure 5 and Figure 6 This is a flowchart of an example process related to an etch stop layer with a low hydrogen concentration. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these components and arrangements are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Additionally, for ease of description, spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” are used herein to describe the relationship between one component or feature and another component or feature(s) as shown in the figures. Besides the orientations depicted in the figures, spatially relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein shall be interpreted accordingly.

[0014] Pixel sensors in complementary metal-oxide-semiconductor (CMOS) image sensors may include trench isolation structures (e.g., deep trench isolation (DTI) structures) around photodiodes. To facilitate the etching operation in forming the trench isolation structure, a pixel sensor with a contact etch stop layer (CESL) can be formed beneath the photodiode. The etching operation may include etching through a silicon substrate (e.g., the pixel sensor substrate) until the CESL is detected. In this way, the etching tool can control the depth of the etching process and / or can control how many layers of material are removed during the etching operation.

[0015] However, the etch stop layer (e.g., silicon nitride material) can have a relatively high concentration of hydrogen (>15% atoms). When light enters the pixel sensor (e.g., during image capture operations), some electrons may be trapped in the relatively high hydrogen concentration of the CESL. The CESL can release the trapped electrons, which can induce charge within the pixel sensor and cause a ghost image effect (e.g., residual images caused by the release of trapped electrons from the CESL induce charge in the pixel sensor). This can lead to imaging distortion in CMOS image sensors.

[0016] Some embodiments described herein provide techniques and devices for a low-hydrogen-concentration CESL disposed beneath a silicon substrate (e.g., including a photodiode) of a pixel sensor. A low-hydrogen-concentration CESL may comprise less than about 12% hydrogen (e.g., based on the atomic percentage of hydrogen atoms within a contact etch stop layer). In some embodiments, a low-hydrogen-concentration CESL may comprise at least about 70% silicon and nitrogen.

[0017] When light enters the photodiode of a pixel sensor, the low hydrogen concentration CESL reduces the amount of trapped electrons, thus reducing (or eliminating) the ghosting effect when capturing images using the pixel sensor. This improves the digital image generated based on the sampling of the charge of the photodiode in the pixel sensor.

[0018] To further reduce ghosting, a portion of the photodiode in the pixel sensor may have an upper surface with an angle ranging from approximately 80 degrees to approximately 100 degrees. In some embodiments, the angle may be approximately 90 degrees and / or the upper surface may be generally rectangular in shape. In this way, the likelihood of photons escaping the photodiode increases, based on the reduced probability of forming an incident angle with the diode's surface (causing total internal reflection within the diode). Furthermore, or alternatively, the amount of charge induced within the pixel sensor can be reduced when the trapped electrons are released. Thus, when using the pixel sensor to capture images, the pixel sensor can reduce (or eliminate) ghosting effects.

[0019] Figure 1 This is a diagram of example environment 100, in which the systems and / or methods described in this article can be implemented. (See diagram for example.) Figure 1 As shown, environment 100 may include a plurality of semiconductor process tools (symbols 102 to 108) and a chip / die transport tool 110. The plurality of semiconductor process tools (symbols 102 to 108) may include deposition tool 102, etching tool 104, planarization tool 106, ion implantation tool 108, and / or other tools. The semiconductor tools included in example environment 100 may be located in a semiconductor cleanroom, semiconductor foundry, semiconductor processing and / or manufacturing facility, or other location.

[0020] Deposition tool 102 is a semiconductor process tool capable of depositing various types of materials onto a substrate. In some embodiments, deposition tool 102 includes a spin coater capable of depositing a photoresist layer on a substrate such as a chip. In some embodiments, deposition tool 102 includes chemical vapor deposition (CVD) tools, such as plasma-enhanced CVD (PECVD) tools, high-density plasma CVD (HDP-CVD) tools, sub-atmospheric CVD (SACVD) tools, atomic layer deposition (ALD) tools, plasma-enhanced atomic layer deposition (PEALD) tools, or other types of CVD tools. In some embodiments, deposition tool 102 includes physical vapor deposition (PVD) tools, such as sputtering tools or other types of PVD tools. In some embodiments, example environment 100 includes multiple types of deposition tools 102.

[0021] The deposition tool 102 may include a deposition chamber with temperature and / or pressure, which can be modified for deposition operations. In some embodiments, the deposition tool 102 may heat and / or pressurize the deposition chamber to prepare for depositing a layer of material on a chip. As described herein, for example, the deposition tool 102 may heat the deposition chamber to at least about 600°C and / or pressurize the deposition chamber to at least about 150 Torr to prepare for depositing a CESL on a substrate.

[0022] Etching tool 104 is a semiconductor process tool capable of etching materials on various types of substrates, chips, or semiconductor devices. For example, etching tool 104 may include wet etching tools, dry etching tools, and / or another type of etching tool. Wet etching tools may include chemical etching tools or another type of wet etching tool, which includes a chamber filled with an etchant. The substrate may be placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. Dry etching tools may include plasma etching tools, laser etching tools, reactive ion etching tools, or vapor phase etching tools, etc. Dry etching tools may use sputtering techniques, plasma-assisted etching techniques (e.g., plasma sputtering techniques or another type of technique including using ionized gases to etch one or more portions isotopically or directionally), or other types of dry etching techniques.

[0023] Etching tool 104 (e.g., dry etching tool) can perform etching operations until the CESL of the chip or semiconductor device is detected. The detection result of the CESL can indicate that the etching operation is complete. Etching tool 104 can perform subsequent etching operations and / or chip / die transport tool 110 can transfer the chip or semiconductor device from etching tool 104 to another semiconductor process tool after the etching operation is completed.

[0024] Planarization tool 106 is a semiconductor process tool capable of grinding or planarizing various layers of a chip or semiconductor device. For example, the grinding device may include a chemical mechanical polishing (CMP) device and / or another type of grinding device. In some embodiments, the grinding device can grind or planarize layers of deposited or electroplated material.

[0025] Ion implantation tool 108 is a semiconductor process tool used to implant ions into substrates such as chips or semiconductor devices. For example, ion implantation tool 108 can implant ions into the silicon substrate of a CMOS image sensor to form a diode. Ion implantation tool 108 generates ions from a source material, such as a gas or solid, in an arc chamber. The source material is supplied to the arc chamber, and an arc voltage is released between the cathode and electrodes to generate a plasma containing ions of the source material. One or more extraction electrodes are used to extract ions from the plasma within the arc chamber and accelerate the ions to form an ion beam. The ion beam can be directed towards the substrate, such that ions are implanted below the surface of the substrate to dope the substrate.

[0026] Chip / die transport vehicle 110 includes mobile robots, robotic arms, trams or railcars, overhead hoist transfer (OHT) vehicles, automated material handling systems (AMHS), and / or other tools for transporting chips and / or dies between semiconductor process tools 102 to 108 and / or to other locations, such as chip racks, storage rooms, or other locations. In some embodiments, chip / die transport vehicle 110 may be a programmed tool for traveling along a specific path and / or may operate semi-autonomously or autonomously.

[0027] Figure 1 One or more examples are provided to illustrate the number and arrangement of the tools. In fact, with... Figure 1 Compared to the tools shown, there can be more tools, fewer tools, different tools, or different arrangements of tools. Furthermore, Figure 1 The two or more tools shown can be implemented within a single tool, or Figure 1 The single tool shown can be implemented as multiple distributed tools. Additionally or alternatively, the tool set (e.g., one or more tools) of environment 100 can perform one or more functions described as being performed by another set of tools of environment 100.

[0028] Figure 2A and 2B This is a diagram of the example semiconductor structure 200 described in this article. Figure 2A A cross-section of the side of the semiconductor structure 200 is shown. Figure 2B A top view of a portion AA of the semiconductor structure 200 is shown. The semiconductor structure 200 may include, or may include in, a pixel sensor and / or an image sensor. The image sensor may be a CMOS image sensor, a backside illumination (BSI) CMOS image sensor, or other types of image sensors.

[0029] like Figure 2AAs shown, the semiconductor structure 200 may include a substrate 202 and a CESL 204 disposed on the substrate 202. The semiconductor structure 200 may also include a silicon substrate 208 disposed on a dielectric layer 206 of the CESL 204 and / or disposed above the CESL (e.g., in other embodiments, the silicon substrate 208 is on the dielectric layer 206 or on the CESL 204). The silicon substrate 208 may include one or more photodiodes 210, and the one or more photodiodes 210 are separated by one or more trench isolation structures 212 disposed through the silicon substrate 208 to the CESL 204.

[0030] Substrate 202 may include a dielectric material. For example, substrate 202 may include an inter-metal dielectric layer. The inter-metal dielectric layer may include bonding pads and / or other metal interconnect structures that connect the semiconductor structure 200 to an encapsulation, external electrical connections, and / or other external devices. Substrate 202 may include a low-k dielectric material, such as silicon dioxide, fluorinated silicate glass, hydrogen silsesquioxane or methyl silsesquioxane, organosilicon glass, and / or organic aromatic polymers.

[0031] Similar to substrate 202, dielectric layer 206 may include low-k materials, such as silicon dioxide, fluorinated silicate glass, hydrosiloxanes, methylsiloxanes, organosilicon glasses, and / or organic aromatic polymers. Dielectric layer 206 may provide electrical and / or optical isolation between substrate 202 and silicon base layer 208. Dielectric layer 206 may include interlayer dielectrics.

[0032] In some embodiments, CESL 204 may be disposed between substrate 202 and dielectric layer 206. In some embodiments, CESL 204 may be disposed between dielectric layer 206 and silicon base layer 208. CESL 204 may have a thickness in the range of about 10 nanometers to about 100 nanometers. In this way, CESL 204 can be thick enough to be used as CESL (e.g., not so thin that CESL cannot be detected during etching) and thin enough to reduce the amount of hydrogen atoms that diffuse into CESL 204 during its deposition.

[0033] CESL 204 may comprise materials based on nitrogen, silicon, hydrogen, and / or oxygen. CESL 204 may comprise less than about 12% (e.g., 0% to 12%) of hydrogen. For example, based on the atomic percentage of hydrogen atoms within CESL 204, CESL 204 may comprise less than about 12% hydrogen. CESL 204 may comprise at least about 65% nitrogen and silicon. In some embodiments, CESL 204 may comprise at least 65% nitrogen-14 isotope and silicon-28 isotope. Nitrogen and silicon may form silicon nitride-based materials. In some embodiments, a portion of the nitrogen may form bonds with hydrogen atoms, which may result in hydrogen being retained in CESL 204.

[0034] Based on the fact that CESL 204 contains less than about 12% hydrogen, it can reduce the amount of electrons trapped when light enters photodiode 210. This can reduce (or eliminate) ghosting when images are captured using semiconductor structure 200. The reduction of ghosting improves the digital image generated by sampling the charge of photodiode 210 based on semiconductor structure 200.

[0035] The silicon substrate 208 may include a silicon substrate, a substrate formed of a material including silicon, a III-V compound semiconductor substrate such as a gallium arsenide (GaAs) substrate, a silicon-on-insulator (SOI) substrate, or another substrate capable of generating charge from photons of incident light.

[0036] Photodiode 210 can be formed within silicon substrate 208. For example, photodiode 210 can be a portion of silicon substrate 208 that has been doped to form a photodiode 210 for one or more pixel sensors. The silicon-based material can be doped with multiple ions to form a PN junction for each photodiode 210. For example, silicon substrate 208 can be a first portion (e.g., an n-type portion) of photodiode 210 doped with an n-type dopant and a second portion (e.g., a p-type portion) of photodiode 210 doped with a p-type dopant. In some embodiments, another technique, such as diffusion, is used to form photodiode 210.

[0037] A trench isolation structure 212 (e.g., a DTI structure) may be formed in the silicon substrate 208 and / or the dielectric layer 206. In other embodiments, the trench isolation structure 212 may be formed between adjacent photodiodes 210 and / or (e.g., completely or partially) around each photodiode 210. In some embodiments, the trench isolation structure 212 may be a back trench isolation structure (e.g., a back DTI structure) formed in the back side of the silicon substrate 208. The trench isolation structure 212 may be filled with an oxide-based material. For example, the trench isolation structure 212 may be filled with silicon oxide (SiO2).x The material may be an oxide or other similar material to provide electrical and / or optical isolation between photodiodes 210. The trench isolation structure 212 may include trenches (e.g., deep trenches) extending downwards from the photodiodes 210 into the silicon substrate 208. The trench isolation structure 212 can provide optical isolation between the photodiodes 210 of the semiconductor structure 200 to reduce the amount of optical crosstalk between adjacent photodiodes 210 and / or pixel sensors. In particular, the trench isolation structure 212 can absorb, refract, and / or reflect incident light, thus reducing the amount of incident light that passes through the photodiodes 210 into adjacent photodiodes and is absorbed by the adjacent photodiodes 210.

[0038] like Figure 2B As shown, the upper surface of one or more photodiodes 210 may include an angle 214. Angle 214 may have an angle in the range of about 80 degrees to about 100 degrees. In some embodiments, angle 214 may have an angle of about 90 degrees. In some embodiments, the upper surface of the photodiode 210 may be generally (substantially) rectangular. Based on the upper surface having an angle 214 in the range of about 80 degrees to about 100 degrees (e.g., about 90 degrees) and / or having a generally rectangular upper surface, the probability of forming an angle of incidence with the surface of the diode is reduced (resulting in total internal reflection within the diode), and photons may have an increased probability of leaving the photodiode. In this way, a reduced amount of charge can be induced within the pixel sensor upon release of trapped electrons.

[0039] As mentioned above, providing Figure 2A and 2B As an example. Other examples can be related to... Figure 2A and 2B The descriptions are different.

[0040] Figures 3A-3F This is a diagram of the exemplary embodiment 300 described herein. Exemplary embodiment 300 may be an example process for forming semiconductor structure 200. Semiconductor structure 200 may include a CMOS image sensor, a BSI CMOS image sensor, or other types of image sensors.

[0041] like Figure 3AAs shown, the semiconductor structure 200 may include a substrate 202 and a CESL 204 disposed on the substrate 202. In some embodiments, a deposition tool (e.g., deposition tool 102) may deposit CESL on the substrate 202. In some embodiments, the deposition tool may use chemical vapor deposition or physical vapor deposition, including depositing CESL on the substrate 202. In some embodiments, the deposition tool may deposit CESL material at temperatures above about 600°C and / or at pressures above about 150 Torr. In some embodiments, temperatures below 600°C may be used in combination with pressures above 150 Torr. Similarly, temperatures above 600°C may be used in combination with pressures below 150 Torr. One or more of these deposition techniques may be used to achieve a low-hydrogen-concentration CESL 204.

[0042] Based on the use of a temperature of at least about 600°C and / or a pressure of at least about 150 Torr during deposition, atoms within the deposition tool (e.g., within the deposition tool cavity) can possess sufficient energy to move, allowing hydrogen to be released or expelled from the deposited layer of the CESL (e.g., a material comprising silicon nitride). Alternatively, by using a temperature of at least 600°C and / or a pressure of at least 150 Torr during deposition, nitrogen atoms can increase the likelihood of bonding with silicon atoms rather than with hydrogen atoms. This can allow hydrogen atoms to form hydrogen gas and escape from the surface of the CESL 204.

[0043] Alternatively, the deposition tool can be based on providing an NH3:SiH4 gas flow rate greater than approximately 70:1 to deposit CESL 204. Based on using NH3 and SiH4 at a ratio of at least approximately 70:1, a sufficiently high nitrogen-silicon (nitrogen / silicon) ratio can be present to form bonds between nitrogen and silicon atoms, excluding hydrogen atoms within the CESL. Hydrogen atoms can be prevented from penetrating the CESL and / or can be released as hydrogen gas. Hydrogen gas can be vented from the deposition tool.

[0044] In some embodiments, based on the deposition technique described above, CESL 204 may include less than about 12% hydrogen. For example, CESL 204 may include less than 15% hydrogen, about 10% hydrogen, or less than 12% hydrogen. Based on the atomic percentage of hydrogen atoms within CESL 204, CESL 204 may include less than about 12% hydrogen. In some embodiments, CESL 204 may include materials based on silicon, nitrogen, hydrogen, and / or oxygen.

[0045] In some embodiments, based on the deposition techniques described above, CESL 204 may comprise at least (e.g., based on the atomic percentage of nitrogen or silicon atoms in CESL 204) about 70% nitrogen and silicon.

[0046] In some embodiments, a planarization tool (e.g., planarization tool 106) can planarize the upper surfaces of substrate 202 and / or CESL 204. Thus, within the pixel region, the upper surfaces of substrate 202 and / or CESL 204 can be substantially flat and / or the thickness of CESL 204 can be substantially uniform.

[0047] like Figure 3B As shown, the semiconductor structure 200 may include a dielectric layer 206 disposed on the CESL 204. In some embodiments, a deposition tool (e.g., deposition tool 102) may deposit the dielectric layer 206 on the CESL 204. In some embodiments, the deposition tool may use chemical vapor deposition or physical vapor deposition, etc., to deposit the dielectric layer 206 on the CESL 204. In some embodiments, the deposition tool may deposit the dielectric layer 206 to completely cover the CESL 204 within the pixel sensor region of the semiconductor structure 200.

[0048] In some embodiments, the planarization tool (e.g., planarization tool 106) may planarize the upper surface of the dielectric layer 206. In this way, the upper surface of the dielectric layer 206 may be substantially flat within the pixel region and / or the thickness of the dielectric layer 206 may be substantially uniform.

[0049] like Figure 3C As shown, the semiconductor structure 200 may include a silicon substrate 208 disposed on the dielectric layer 206 and / or above the CESL 204 (e.g., in an upper layer, but not necessarily directly above or directly on it). In some embodiments, a deposition tool (e.g., deposition tool 102) may deposit the silicon substrate 208 on the dielectric layer 206 and / or above the CESL 204. In some embodiments, the deposition tool may use chemical vapor deposition or physical vapor deposition, etc., to deposit the silicon substrate 208 on the dielectric layer 206 and / or above the CESL 204. In some embodiments, the deposition tool may deposit the silicon substrate 208 to completely cover the dielectric layer 206 and / or the CESL 204 within the pixel sensor region of the semiconductor structure 200.

[0050] In some embodiments, a planarization tool (e.g., planarization tool 106) can planarize the upper surface of the silicon substrate 208. In this way, the upper surface of the silicon substrate 208 can be substantially flat within the pixel region and / or the thickness of the silicon substrate 208 can be substantially uniform. Thus, one or more photodiodes formed within the silicon substrate 208 can have approximately equal thicknesses, and the sampling of one or more photodiodes in the semiconductor structure 200 can be consistent.

[0051] In some embodiments, the semiconductor structure 200 may omit the dielectric layer 206, such that the silicon substrate 208 is disposed (e.g., directly disposed) on the CESL 204. In some embodiments, a deposition tool may deposit the CESL 204 between the dielectric layer 206 and the silicon substrate 208.

[0052] like Figure 3D As shown, the semiconductor structure 200 may include a photodiode 210 within a silicon substrate 208. In some embodiments, an ion implantation tool (e.g., ion implantation tool 108) may use ion implantation technology to dope a portion of the silicon substrate 208 302 to form photodiodes 210 for a plurality of pixel sensors. The silicon substrate 208 may be doped with multiple ions to form a PN junction for each photodiode 210. For example, the silicon substrate 208 may be a first portion (e.g., an n-type portion) doped with an n-type dopant to form a second portion (e.g., a p-type portion) doped with a p-type dopant to form a second portion (e.g., a p-type portion) of the photodiode 210. In some embodiments, another technical implementation is, for example, diffusion for forming the photodiode 210.

[0053] like Figure 3E As shown, the semiconductor structure 200 may include one or more trenches 304 formed between photodiodes 210. In some embodiments, an etching tool (e.g., etching tool 104) may etch portions of the silicon substrate 208 and / or dielectric layer 206 to form one or more trenches 304. In some embodiments, the etching tool may use a CESL-type etching process, wherein the etching tool performs etching operations until CESL 204 is detected. For example, the etching tool may begin etching from multiple portions of the silicon substrate 208 (e.g., between photodiodes 210). The etching tool may continue etching until CESL 204 is detected. Thus, the etching tool may remove material from the silicon substrate 208 and / or dielectric layer 206, but may stop material removal before reaching the substrate 202.

[0054] In some embodiments, Figure 3D and Figure 3E The operations shown can be reversed. For example, the etching tool can etch portions of the silicon substrate 208 and / or dielectric layer 206 to form one or more trenches 304 before the ion implantation tool dopes portions of the silicon substrate 208.

[0055] like Figure 3FAs shown, the semiconductor structure 200 may include one or more trench isolation structures 212 (e.g., DTI structures) within one or more trenches 304 (e.g., formed between photodiodes 210). In some embodiments, a deposition tool (e.g., deposition tool 102) may deposit trench isolation material into one or more trenches 304 to provide deep trench isolation (DTI) for isolating adjacent photodiodes 210. In some embodiments, the deposition tool may use chemical vapor deposition or physical vapor deposition; in other examples, trench isolation material is deposited into one or more deep trenches of the substrate 202. In some embodiments, a planarization tool (e.g., planarization tool 106) may planarize the upper surface of the trench isolation structures 212 and / or the photodiodes 210.

[0056] As mentioned above, providing Figures 3A-3F As an example. Other examples can be related to... Figures 3A-3F The descriptions are different. Figures 3A-3F The number and arrangement of devices, layers, and / or materials shown are provided as examples. In practice, there may be additional devices, layers, and / or materials, fewer devices, layers, and / or materials, different devices, layers, and / or materials, or combinations thereof. Figures 3A-3F The examples shown depict different arrangements of devices, layers, and / or materials. For example, one or more additional operations may be performed to form one or more additional portions of the semiconductor structure 200. For example, one or more semiconductor tools may perform one or more additional operations to form metal shielding regions, bonding pad regions, and / or measurement regions, etc., of the semiconductor structure 200.

[0057] Figure 4 This is a diagram of an example CESL device 400, which features a low hydrogen concentration for a pixel sensor, as described herein. The CESL can be formed using one or more of the techniques described herein to reduce its hydrogen concentration. Figure 4 As shown, CESL may include nitrogen atoms (e.g., nitrogen 14), silicon atoms (e.g., silicon 28), hydrogen atoms and / or oxygen atoms, as well as other example materials. Figure 4 As further shown, nitrogen atoms can constitute about 40% of the CESL up to a depth of about 40 nanometers, silicon can constitute about 30% of the CESL up to a depth of about 40 nanometers, hydrogen can account for about 11% of the CESL at a depth of about 30 nanometers, and / or oxygen can account for less than about 5% of the CESL at a depth of about 30 nanometers.

[0058] Based on this, CESL has a low hydrogen concentration (e.g., less than 12% of the atoms in CESL). When light enters the photodiode of the pixel sensor, CESL can capture a reduced number of electrons, which reduces the ghosting effect when capturing images using the pixel sensor. This improves the charge of the photodiode in the upsampled pixel sensor for digital image generation.

[0059] As mentioned above, providing Figure 4 As an example. Other examples can be related to... Figure 4 The descriptions differ. In the example diagram, with... Figure 4 The different materials shown and / or materials different from those shown Figure 4 The concentrations shown and / or other concentrations in the material can form CESL.

[0060] Figure 4 This is a diagram of example components of device 400, which may correspond to deposition tool 102, etching tool 104, planarization tool 106, ion implantation tool 108, and / or chip / die transport tool 110. In some embodiments, deposition tool 102, etching tool 104, planarization tool 106, ion implantation tool 108, and / or chip / die transport tool 110 may include one or more devices 400 and / or components of one or more devices 400. Figure 4 As shown, device 400 may include bus 410, processor 420, memory 430, storage component 440, input component 450, output component 460 and communication component 470.

[0061] Bus 410 includes components capable of wired and / or wireless communication between components of device 400. Processor 420 includes a central processing unit, graphics processing unit, microprocessor, controller, microcontroller, digital signal processor, field-programmable gate array, application-specific integrated circuits, and / or another type of processing component. Processor 420 is implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 420 includes one or more processors capable of being programmed to perform functions. Memory 430 includes random access memory, read-only memory, and / or another type of memory (e.g., flash memory, magnetic memory, and / or optical memory).

[0062] Storage component 440 stores information and / or software related to the operation of device 400. For example, storage component 440 may include a hard disk drive, disk drive, optical disk drive, solid-state drive, optical disk, digital multifunction optical disk, and / or another type of non-transitory calculator-readable media. Input component 450 enables device 400 to receive input signals such as user input and / or sensor input. For example, input component 450 may include a touchscreen, keyboard, keypad, mouse, button, microphone, switch, sensor, GPS component, accelerometer, gyroscope, and / or actuator. Output component 46 enables device 400 to provide output signals, such as through a display, speaker, and / or one or more light-emitting diodes. Communication component 470 enables device 400 to communicate with other devices, such as via wired and / or wireless connections. For example, communication component 470 may include a receiver, transmitter, transceiver, modem, network adapter, and / or antenna.

[0063] Device 400 may perform one or more of the processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 430 and / or storage component 440) may store a set of instructions (e.g., one or more instructions, code, software code, and / or coded code) for processor 420 to execute. Processor 420 may execute a set of instructions to perform one or more of the processes described herein. In some embodiments, one or more processors 420 may execute a set of instructions to cause one or more processors 420 and / or device 400 to perform one or more of the processes described herein. In some embodiments, hard-wired circuitry may be used in place of or in combination with instructions to perform one or more of the processes described herein. Therefore, the embodiments described herein are not limited to any particular combination of hardware circuitry and software.

[0064] by Figure 4 The number and arrangement of components shown are for example. Figure 4 Compared to the components shown, device 400 may include additional components, fewer components, different components, or components arranged differently. Additionally or alternatively, the component group of device 400 (e.g., one or more components) may perform one or more functions of another group of components described as components of device 400.

[0065] Figure 5 This is a flowchart of an example process 600 associated with a CESL having a low hydrogen concentration, wherein the low-hydrogen-concentration CESL is used for a pixel sensor. In some embodiments, Figure 5One or more process blocks can be performed by one or more semiconductor process tools (e.g., deposition tool 102, etching tool 104, planarization tool 106, ion implantation tool 108, and / or chip / die transport tool 110). Alternatively or alternatively, Figure 5 One or more process blocks in the device 400 may be performed by one or more components in the device 400, such as processor 420, memory 430, storage component 440, input component 450, output component 460 and / or communication component 470.

[0066] like Figure 5 As shown, process 600 may include depositing CESL on a substrate, wherein depositing CESL includes depositing CESL material at a temperature above about 600°C and a pressure above about 150 Torr (block 510). For example, one or more semiconductor process tools may deposit CESL 204 on substrate 202 as described above. In some embodiments, depositing CESL 204 includes depositing CESL material at a temperature above about 600°C and a pressure above about 150 Torr.

[0067] like Figure 5 As further shown, process 600 may include depositing a silicon substrate (block 520) over the CESL. For example, as described above, one or more semiconductor process tools may deposit a silicon substrate 208 over the CESL 204.

[0068] As in Figure 5 As further shown, process 600 may include etching operations on the silicon substrate up to CESL to form a trench isolation structure (block 530). For example, as described above, one or more semiconductor process tools may perform etching operations on the silicon substrate up to CESL 204 to form trench isolation structure 212.

[0069] Process 600 may include additional implementations, such as any single implementation or any combination of implementations of one or more other processes described below and / or elsewhere herein.

[0070] In a first embodiment, process 600 includes forming a photodiode between one or more trench isolation structures within a silicon substrate.

[0071] In the second embodiment, the etching operation, alone or in combination with the first embodiment, includes forming a trench isolation structure around a portion of the silicon substrate, wherein the upper surface of the portion of the silicon substrate includes a plurality of angles, wherein the angles are in the range of about 80 degrees and about 100 degrees.

[0072] In the third embodiment, the etching operation, alone or in combination with one or more of the first and second embodiments, includes forming a trench isolation structure around a portion of the silicon substrate, wherein the portion of the silicon substrate has an upper surface that is generally rectangular in shape.

[0073] In the fourth embodiment, alone or in combination with one or more of the first to third embodiments, the deposition of CESL includes providing an airflow with an NH3 to SiH4 ratio greater than about 70:1.

[0074] In the fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, the CESL comprises less than about 12% hydrogen based on the atomic percentage of hydrogen atoms within the CESL 204.

[0075] In the sixth embodiment, CESL comprises a silicon nitride-based material, either alone or in combination with one or more of the first to fifth embodiments.

[0076] although Figure 5 Example blocks from process 500 are shown, but in some embodiments, process 500 may include additional blocks, fewer blocks, different blocks, or blocks similar to those in process 500. Figure 5 The different blocks depicted. In addition, or alternatively, two or more of the blocks and processes in 500 can be performed in parallel.

[0077] Figure 6 This is a flowchart of an example process 600 associated with CESL, where a low hydrogen concentration is used for the pixel sensor. In some embodiments, Figure 6 One or more process blocks can be performed by one or more semiconductor process tools (e.g., deposition tool 102, etching tool 104, planarization tool 106, ion implantation tool 108, and / or chip / die transport tool 110). Alternatively or alternatively, Figure 6 One or more process blocks in the device 400 may be performed by one or more components in the device 400, such as processor 420, memory 430, storage component 440, input component 450, output component 460 and / or communication component 470.

[0078] like Figure 6As shown, process 600 may include depositing CESL on a substrate, wherein depositing CESL includes depositing CESL material at a temperature above approximately 600°C, and wherein depositing CESL material includes depositing NH3 and SiH4 in a ratio above approximately 70:1 (block 610). For example, as described above, one or more semiconductor process tools may deposit CESL 204 on substrate 202. In some embodiments, depositing CESL 204 includes depositing CESL material at a temperature above approximately 600°C. In some embodiments, the CESL material comprises NH3 and SiH4 in a ratio above approximately 70:1.

[0079] like Figure 6 As further shown, process 600 may include depositing a silicon substrate (block 620) over the CESL. For example, as described above, one or more semiconductor process tools may deposit a silicon substrate 208 over the CESL 204.

[0080] As in Figure 6 As further shown, process 600 may include performing an etching operation to etch trenches for trench isolation structures into the silicon substrate until CESL (block 630) is reached. For example, as described above, one or more semiconductor process tools may perform an etching operation to etch trench 304 into the silicon substrate 208 until CESL 204 is reached.

[0081] Process 600 may include additional implementations, such as any single implementation or any combination of implementations of one or more other processes described below and / or elsewhere herein.

[0082] In the first embodiment, CESL comprises less than about 12% hydrogen.

[0083] In the second embodiment, the etching operation, alone or in combination with the first embodiment, includes forming trenches around a portion of the silicon substrate, wherein the upper surface of the portion of the silicon substrate includes a plurality of corners, wherein the corners are between about 80 degrees and about 100 degrees.

[0084] In a third embodiment, alone or in combination with one or more of the first and second embodiments, process 600 includes ionizing a portion of a silicon substrate to form a silicon-doped material, wherein the silicon-doped material includes a photodiode at least partially surrounded by a trench isolation structure.

[0085] although Figure 6 Example blocks from process 600 are shown, but in some embodiments, process 600 may include additional blocks, fewer blocks, different blocks, or blocks similar to those in process 600. Figure 6The different blocks depicted. In addition, or alternatively, two or more of the blocks and processes in 600 can be performed in parallel.

[0086] In this way, the CESL can include less than about 12% hydrogen. Based on the fact that the CESL includes less than about 12% hydrogen (e.g., less than 15%, about 10%, etc.), the CESL can reduce the amount of electrons trapped when light enters the photodiode. This can reduce ghosting effects when using a semiconductor structure to capture images. Reduced ghosting can improve the digital image generated by sampling the charge of a semiconductor-based photodiode.

[0087] As described in more detail above, some embodiments described herein provide a pixel sensor. The pixel sensor includes a substrate. The pixel sensor includes a contact etch stop layer disposed on the substrate, wherein the contact etch stop layer comprises less than about 12% hydrogen. The pixel sensor includes a silicon substrate disposed above the substrate, wherein the silicon substrate includes a photodiode. The pixel sensor includes one or more trench isolation structures disposed through the silicon substrate to the contact etch stop layer.

[0088] According to some embodiments of the present disclosure, the upper surface of the photodiode includes a plurality of corners, wherein the plurality of corners have angles in the range of about 80 degrees to about 100 degrees. According to some embodiments of the present disclosure, the plurality of corners have angles of about 90 degrees. According to some embodiments of the present disclosure, the upper surface of the photodiode is rectangular. According to some embodiments of the present disclosure, the contact etch stop layer comprises less than about 12% hydrogen based on the atomic percentage of hydrogen atoms within the contact etch stop layer. According to some embodiments of the present disclosure, the contact etch stop layer comprises a silicon nitride-based material. According to some embodiments of the present disclosure, the contact etch stop layer has a thickness in the range of about 10 nanometers to about 100 nanometers. According to some embodiments of the present disclosure, the pixel sensor comprises a complementary metal-oxide-semiconductor image sensor. According to some embodiments of the present disclosure, the photodiode comprises a silicon-doped material.

[0089] As described in more detail above, some embodiments described herein provide methods. The methods include depositing a contact etch stop layer on a substrate, wherein depositing the contact etch stop layer includes depositing a contact etch stop layer material at a temperature above about 600°C and a pressure above about 150 Torr. The methods include depositing a silicon substrate over the contact etch stop layer. The methods include performing an etching operation into the silicon substrate until reaching the contact etch stop layer to form a trench isolation structure.

[0090] According to some embodiments of the present disclosure, a photodiode is further formed between one or more of the trench isolation structures within the silicon substrate. According to some embodiments of the present disclosure, performing the etching operation includes forming the trench isolation structure around a portion of the silicon substrate, wherein the upper surface of the portion of the silicon substrate includes a plurality of angles having angles in the range of about 80 degrees and about 100 degrees. According to some embodiments of the present disclosure, performing the etching operation includes forming the trench isolation structure around a portion of the silicon substrate, wherein the portion of the silicon substrate has a rectangular upper surface. According to some embodiments of the present disclosure, depositing the contact etch stop layer includes providing an airflow with an NH3:SiH4 ratio greater than about 70:1. According to some embodiments of the present disclosure, the contact etch stop layer comprises less than about 12% hydrogen based on the atomic percentage of hydrogen atoms within the contact etch stop layer. According to some embodiments of the present disclosure, the contact etch stop layer comprises a silicon nitride-based material.

[0091] As described in more detail above, some embodiments described herein provide methods. The methods include depositing a contact etch stop layer on a substrate, wherein depositing the contact etch stop layer includes depositing a contact etch stop layer material at a temperature above about 600°C, and wherein depositing the contact etch stop layer material comprises depositing NH3 and SiH4 in a ratio greater than about 70:1. The methods include depositing a silicon substrate over the contact etch stop layer. The methods include performing an etching operation to etch trenches for trench isolation structures into the silicon substrate until the contact etch stop layer is reached.

[0092] According to some embodiments of this disclosure, the contact etch stop layer comprises less than about 12% hydrogen. According to some embodiments of this disclosure, performing the etching operation includes forming the trench around a portion of the silicon substrate, and the upper surface of said portion of the silicon substrate includes a plurality of angles having angles in the range of about 80 degrees and about 100 degrees. According to some embodiments of this disclosure, the method further includes ionizing a portion of the silicon substrate to form a doped silicon-like material, wherein the doped silicon-like material includes a photodiode at least partially surrounded by the trench isolation structure.

[0093] The foregoing summary outlines the features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other methods and structures to achieve the same purposes and / or advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A pixel sensor, comprising: Substrate; A contact etch stop layer is disposed on the substrate. The contact etch stop layer comprises less than 12% hydrogen, based on the atomic percentage of hydrogen atoms within the contact etch stop layer. A silicon substrate is disposed above the contact etch stop layer. The silicon substrate includes a photodiode; as well as One or more trench isolation structures are disposed through the silicon substrate to the contact etch stop layer, wherein the upper surface of the photodiode includes a plurality of angles, wherein the plurality of angles have an angle in the range of 80 degrees to 100 degrees.

2. The pixel sensor of claim 1, wherein the plurality of said angles have an angle of 90 degrees.

3. The pixel sensor according to claim 1, wherein the upper surface of the photodiode is rectangular.

4. The pixel sensor of claim 1, wherein the contact etch stop layer comprises a silicon nitride-based material.

5. The pixel sensor of claim 1, wherein the contact etch stop layer has a thickness in the range of 10 nanometers to 100 nanometers.

6. The pixel sensor of claim 1, wherein the pixel sensor comprises a complementary metal-oxide-semiconductor image sensor.

7. The pixel sensor according to claim 1, wherein the photodiode comprises a silicon-doped material.

8. A method for manufacturing a pixel sensor, comprising: Based on an airflow providing an NH3:SiH4 ratio greater than 70:1, a contact etch stop layer is deposited on the substrate. The deposition of the contact etch stop layer includes depositing the contact etch stop layer material at a temperature above 600°C and a pressure above 150 Torr. A silicon substrate is deposited above the contact etch stop layer; A photodiode is formed within the silicon substrate, the photodiode having an upper surface with an angle ranging from 80 degrees to 100 degrees; as well as The etching process is performed into the silicon substrate until the contact etch stop layer is reached to form a trench isolation structure. The contact etch stop layer comprises less than 12% hydrogen, based on the atomic percentage of hydrogen atoms within the contact etch stop layer.

9. The method of claim 8, wherein performing the etching operation includes forming the trench isolation structure around a portion of the silicon substrate. The upper surface of the portion of the silicon substrate includes a plurality of angles having angles in the range of 80 degrees and 100 degrees.

10. The method of claim 8, wherein performing the etching operation includes forming the trench isolation structure around a portion of the silicon substrate. The portion of the silicon substrate has a rectangular upper surface.

11. The method of claim 8, wherein the contact etch stop layer comprises a silicon nitride-based material.

12. A method for manufacturing a pixel sensor, comprising: Deposit a contact etch stop layer on the substrate. The deposition of the contact etch stop layer includes depositing the contact etch stop layer material at a temperature above 600°C, and The material used to deposit the contact etch stop layer comprises NH3 and SiH4 in a ratio greater than 70:1; A silicon substrate is deposited above the contact etch stop layer; A photodiode is formed within the silicon substrate, the photodiode having an upper surface with an angle ranging from 80 degrees to 100 degrees; as well as An etching operation is performed to etch trenches for the trench isolation structure into the silicon substrate until the contact etch stop layer is reached. The contact etch stop layer comprises less than 12% hydrogen, based on the atomic percentage of hydrogen atoms within the contact etch stop layer.

13. The method of claim 12, wherein performing the etching operation comprises forming the trench around a portion of the silicon substrate, and The upper surface of the portion of the silicon substrate includes a plurality of angles having angles in the range of 80 degrees and 100 degrees.

14. The method of claim 12, further comprising: A portion of the silicon substrate is ionized to form a silicon-doped material.

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