Semiconductor device and method for manufacturing the same

Abstract

The present disclosure relates to a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: a substrate; a semiconductor layer disposed on the substrate and comprising a first semiconductor stack and a second semiconductor layer disposed on the first semiconductor stack, wherein a two-dimensional electron gas is formed at the interface between the first semiconductor stack and the second semiconductor layer; a source electrode, a drain electrode, and a gate electrode disposed on the second semiconductor layer and spaced apart; a metal layer disposed within the semiconductor layer and located between the substrate and the two-dimensional electron gas; an electrical connection structure extending from the gate electrode into the semiconductor layer and connected to the metal layer; a first blocking structure at least partially disposed between the metal layer and the two-dimensional electron gas and between the electrical connection structure and the two-dimensional electron gas; and a second blocking structure connected to the first blocking structure and covering the side of the metal layer. The semiconductor device can effectively reduce the electric field strength of the gate of a HEMT device under high voltage, thereby increasing the device's breakdown voltage.

Description

Technical Field

[0001] The present disclosure generally relates to the field of semiconductor devices. More specifically, the present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] Semiconductor devices, also known as high electron mobility transistors (HEMTs), are widely used in high frequency, high voltage, high temperature and high power density fields due to their high electron mobility, high two-dimensional electron gas concentration and high breakdown voltage.

[0003] A desirable property of semiconductor devices is a higher breakdown voltage. Gate field plates are widely used in semiconductor devices because they can increase the device's breakdown voltage. Gate field plates are typically located on the passivation layer atop a semiconductor device and connected to the gate or source. While they can increase the device's breakdown voltage, new technologies are still being developed to increase this voltage. Ideally, this new technology could be combined with the gate field plate to significantly increase the device's breakdown voltage. Summary of the Invention

[0004] In order to solve some or all of the above problems, the present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device has a higher breakdown voltage without using a gate field plate, and has an even higher breakdown voltage when using a gate field plate.

[0005] According to a first aspect of the present disclosure, a semiconductor device is provided, comprising: a substrate; a semiconductor layer disposed on the substrate, the semiconductor layer comprising: a first semiconductor stack and a second semiconductor layer disposed on the first semiconductor stack; a two-dimensional electron gas formed at an interface between the first semiconductor stack and the second semiconductor layer; a source electrode, a drain electrode, and a gate electrode disposed on the second semiconductor layer and arranged at intervals; a metal layer disposed in the semiconductor layer and located between the substrate and the two-dimensional electron gas; an electrical connection structure extending from the gate electrode into the semiconductor layer and connected to the metal layer, for electrically connecting the metal layer to the gate electrode; a first blocking structure disposed on a side of the metal layer away from the substrate, for insulating and isolating the metal layer and the electrical connection structure from the two-dimensional electron gas; a second blocking structure connected to the first blocking structure and covering a side surface of the metal layer, wherein the side surface is adjacent to a side surface of the metal layer away from the substrate.

[0006] According to a second aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, which includes the following steps: providing a substrate; forming a semiconductor layer on the substrate, the semiconductor layer including a first semiconductor stack and a second semiconductor layer arranged on the first semiconductor stack; forming a two-dimensional electron gas at the interface between the first semiconductor stack and the second semiconductor layer; forming a metal layer in the semiconductor layer, the metal layer being located between the substrate and the two-dimensional electron gas; forming a source, a drain and a gate on the second semiconductor layer; extending from the gate into the semiconductor layer and electrically connected to the metal layer to form an electrical connection structure; arranging a first barrier structure on a side of the metal layer away from the substrate, wherein the first barrier is used to insulate and isolate the metal layer and the electrical connection structure from the two-dimensional electron gas; and arranging a second barrier structure on a side of the metal layer, wherein the side is adjacent to a side of the metal layer away from the substrate.

[0007] In the semiconductor device and method for manufacturing the same provided in embodiments of the present disclosure, a metal layer electrically connected to a gate is disposed within the device, and a first barrier structure is used to isolate the metal layer from the two-dimensional electron gas (2DEG), as well as the electrical connection structure from the 2DEG. This allows the metal layer connected to the gate to effectively reduce the electric field strength of the gate under high voltage conditions in the HEMT device, thereby increasing the device's breakdown voltage. Furthermore, because the metal layer is susceptible to reacting with ammonia during the subsequent epitaxial growth process, the embodiments of the present disclosure further isolate the metal layer within the first and second barrier structures using the first and second barrier structures. This reduces the risk of the metal layer reacting with ammonia used in the epitaxial growth process during subsequent device manufacturing, particularly during epitaxial growth, thereby ensuring the successful realization of the aforementioned benefits. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The preferred embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings:

[0009] Figure 1 Schematic diagram of a top view of the semiconductor device according to the first embodiment of the present disclosure;

[0010] Figure 2 for Figure 1 Cross-sectional view along line AA;

[0011] Figure 3 for Figure 1 Cross-sectional view along the midline BB;

[0012] Figure 4 Shows Figure 1 The metal layer and electrical connection structure of the semiconductor device shown;

[0013] Figures 5a to 5iA diagram showing the manufacturing process of the semiconductor device according to the first embodiment of the present disclosure is shown;

[0014] Figure 6 A schematic cross-sectional structural diagram of a semiconductor device according to a second embodiment of the present disclosure;

[0015] Figure 7 Shows Figure 6 The metal layer and electrical connection structure of the semiconductor device are shown.

[0016] In the drawings, like parts are given like reference numerals, but the drawings are not necessarily drawn to scale. DETAILED DESCRIPTION

[0017] The present disclosure will be further described below with reference to the accompanying drawings.

[0018] In the description of this application, "epitaxial growth" refers to the growth of a desired layer structure on a material to be processed. Technologies related to "epitaxial growth" may include metal-organic chemical vapor deposition (MOCVD), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), atomic layer deposition (ALD), etc. Those skilled in the art can select an appropriate epitaxial growth technology based on actual conditions.

[0019] In the description of this application, "etching" should be understood in a broad sense, that is, growing a layer of photoresist on the surface of the material to be processed, selectively exposing and developing the photoresist through a mask to leave a photoresist layer identical to the mask pattern on the surface of the material to be processed, and then selectively corroding the material to be processed by chemical or physical methods, and finally stripping off the photoresist layer to form a structure corresponding to the mask pattern on the material to be processed.

[0020] In the description of this application, the orientation or position relationship indicated by "up" or "down" is based on the orientation or position relationship shown in the accompanying drawings, and is only for the convenience of describing the present disclosure and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0021] In the description of this application, except for Example 1, the other examples are written in a way that avoids duplication as much as possible, that is, the key points are recorded that are different from other examples. In these examples, if any technical features are not clearly recorded, please refer to the corresponding description of Example 1.

[0022] The various embodiments of the present disclosure provide a semiconductor device that can be a HEMT device, or a high electron mobility transistor (HEMT), which has advantages such as high breakdown voltage and high conductivity. It can be used as a semiconductor power device or a semiconductor radio frequency device and has been widely used in base station communications, the Internet of Things, aerospace, radar systems and other fields.

[0023] like Figure 1 、 Figure 2 、 Figure 3 、 Figure 6 As shown, the semiconductor device includes a substrate 1 and a semiconductor layer 2 provided on the substrate 1 .

[0024] For example, Figure 1 and Figure 2 As shown, the substrate 1 can be formed of silicon (Si), silicon carbide (SiC) or sapphire. The semiconductor layer 2 includes a first semiconductor stack and a second semiconductor layer disposed on the first semiconductor stack. In some embodiments, the second semiconductor layer includes a barrier layer 204, the main manufacturing material of which can be an alloy nitride, in particular aluminum gallium nitride (AlGaN), with a thickness of 5nm-50nm ("nm" means nanometer). The first semiconductor stack includes a buffer layer 202 and a channel layer 203 disposed on the buffer layer 202, wherein the main manufacturing material of the channel layer 203 can be a III-V nitride, in particular gallium nitride (GaN), with a thickness of generally 100nm-1000nm. When the channel layer 203 comprises a III-V nitride and the barrier layer 204 comprises an alloy nitride, the channel layer 203 and the barrier layer 204 form a heterostructure. Due to the large difference in polarization strength and bandgap width between the two, a two-dimensional electron gas (2DEG) is formed at the interface between the two. The channel layer 203 and the barrier layer 204 can both be a single layer or multiple layers. In some embodiments, the channel layer 203 comprises a 300nm high-resistance gallium nitride layer and a 200nm high-temperature gallium nitride layer arranged in a direction away from the substrate 1, while the barrier layer 204 comprises a 1nm aluminum nitride layer, a 20nm aluminum gallium nitride layer, and a 2nm gallium nitride layer arranged in a direction away from the channel layer 203.

[0025] For example, the semiconductor layer 2 may further include a nucleation layer 201 disposed on the substrate 1, and a buffer layer 202 disposed on the nucleation layer 201. The nucleation layer 201 is formed of aluminum carbide (AlN) or gallium nitride (GaN) with a thickness of 10 nm to 500 nm, and is used to improve the growth quality of the buffer layer 202 and provide an isolation function. The buffer layer 202 is formed of iron-doped gallium nitride, carbon-doped gallium nitride, gallium nitride (GaN), or aluminum gallium nitride (AlGaN), and is formed of a thickness of 100 nm to 10 μm, and is used to improve the growth quality of the III-V nitride. The buffer layer 202 may be a single layer or a multilayer structure. When the substrate 1 is selected as silicon material, the buffer layer 202 is preferably a three-layer structure, the first layer is aluminum gallium nitride with an aluminum content of 75% and a total thickness of 400nm, the second layer is aluminum gallium nitride with an aluminum content of 50% and a total thickness of 900nm, and the third layer is aluminum gallium nitride with an aluminum content of 25% and a total thickness of 1500nm.

[0026] like Figure 1 、 Figure 2 、 Figure 3 and Figure 6 As shown, the semiconductor device further includes a gate 5 , a drain 4 and a source 6 which are arranged on the second semiconductor layer and spaced apart from each other.

[0027] For example, Figure 1 and Figure 2 The semiconductor device further includes a gate 5, a drain 4, and a source 6 disposed on the barrier layer 204 and spaced apart. The source 6 and the drain 4 can both be a single-layer structure or a multi-layer structure. For example, the drain 4 and the source 6 can respectively include a titanium (Ti) layer, an aluminum (Al) layer, a nickel (Ni) layer, and a gold (Au) layer connected in sequence. The source 6 makes ohmic contact with the barrier layer 204 and is electrically connected to the two-dimensional electron gas. The drain 4 also makes ohmic contact with the barrier layer 204 and is electrically connected to the two-dimensional electron gas. The gate 5 mainly includes one or two of a nickel (Ni) layer and a gold (Au) layer, and makes Schottky contact with the barrier layer 204. When using the semiconductor device, changing the electric field of the gate 5 can regulate the two-dimensional electron gas and control the conduction and shutdown of the source 6 and the drain 4.

[0028] Exemplarily, the semiconductor device further includes a passivation layer 9. The passivation layer 9 is disposed on the barrier layer 204 and provides a clearance for the gate 5, drain 4, and source 6. Specifically, the passivation layer 9 has a plurality of clearance holes through which the gate 5, drain 4, and source 6 respectively pass. This allows the passivation layer 9 to insulate the gate 5, drain 4, and source 6, thereby preventing malfunctions of the semiconductor device due to erroneous connection between the electrodes. The passivation layer 9 is made of a material selected from insulating compounds such as silicon dioxide, silicon nitride, aluminum nitride, and aluminum oxide.

[0029] like Figure 1 、 Figure 2 、 Figure 3 and Figure 6 As shown, the semiconductor device also includes: a metal layer 7, which is arranged in the semiconductor layer 2 and located between the substrate 1 and the two-dimensional electron gas; and an electrical connection structure 57, which extends from the gate 5 into the semiconductor layer 2 and is connected to the metal layer 7, for electrically connecting the metal layer 7 to the gate 5.

[0030] For example, Figure 3 As shown, the electrical connection structure 57 may be a rod-shaped structure.

[0031] Based on this, in some embodiments, such as Figure 3 As shown, the passivation layer 9 is provided on the second semiconductor layer, and the passivation layer 9 is located between the electrical connection structure 57 and the source electrode 6, and between the gate electrode 5 and the drain electrode 4. In other words, the passivation layer may have an avoidance hole through which the power supply connection structure 57 passes, so that one end of the electrical connection structure 57 is located inside the semiconductor layer 2 and connected to the connection area of the metal layer 7, while the other end of the electrical connection structure 57 is located outside the semiconductor layer 2 and connected to the side of the gate electrode 5 facing the drain electrode 4. The electrical connection structure 57 having a rod-shaped structure can not only realize the electrical connection between the metal layer 7 and the gate electrode 5, but also the structure used is very simple. For example, the electrical connection structure 57 is preferably perpendicular to the metal layer 7 and is formed of metal so as to be suitable for formation by epitaxial growth and etching. Among them, the metal layer 7 is preferably one or more high-temperature resistant materials such as tungsten, molybdenum, tantalum and nickel.

[0032] In some embodiments, the metal layer 7 includes a first surface distal from the substrate 1, a second surface opposite thereto and proximal to the substrate 1, and side surfaces adjoining the first and second surfaces. A single metal layer 7 may be provided, and the metal layer 7 intersects with the orthographic projection of the gate 5 on the substrate 1. When an electric potential is applied to the gate 5 of the semiconductor device, the source 6 and drain 4 can be connected via a two-dimensional electron gas. The metal layer 7 can regulate the electric field distribution between the channel layer 203 and the barrier layer 204, reducing the peak electric field intensity near the gate 5 and increasing the device's breakdown voltage, thereby improving the device's operating characteristics at high voltage, high power, and / or high frequency conditions.

[0033] In other embodiments, since the electric field intensity peak occurs between the gate 5 and the drain 4 and is close to the gate 5, the orthographic projection of the metal layer 7 on the substrate 1 is closer to the orthographic projection of the drain 4 on the substrate 1 than the orthographic projection of the gate 5 on the substrate 1. Thus, the metal layer 7 can further reduce the electric field intensity peak near the gate 5 and further increase the breakdown voltage of the device.

[0034] In some embodiments, the metal layer 7 is disposed in the channel layer 203 .

[0035] In some embodiments, the first surface of the metal layer 7 and the second surface of the metal layer 7 are both located within the channel layer 203. Thus, the channel layer 203 includes at least two layers to ensure that the metal layer 7 is suitable for being formed between the at least two layers by epitaxial growth and etching.

[0036] In other embodiments, the first surface of the metal layer 7 is located in the channel layer 203, and the second surface of the metal layer 7 is connected to the interface between the buffer layer 202 and the channel layer 203. In this way, while ensuring that the metal layer 7 is suitable for formation by epitaxial growth and etching methods, a metal layer can be prepared before growing the channel layer 203, thereby simplifying the device manufacturing process.

[0037] In other embodiments, the metal layer 7 is disposed within the buffer layer, so that the insulation properties of the buffer layer can be utilized to enhance the insulation between the metal layer 7 and the two-dimensional electron gas. In this way, the buffer layer 202 includes at least two layers to ensure that the metal layer 7 is suitable for being formed between at least two layers by epitaxial growth and etching. In some embodiments, in order to simplify the manufacturing process of the metal layer, the first surface of the metal layer 7 is in contact with the side of the buffer layer 202 away from the substrate 1, and the second surface of the metal layer 7 is located within the buffer layer 202. In this way, the buffer layer 202 includes a first layer structure and a second layer structure. A conductive material layer is grown on the first layer structure, the conductive material layer is etched to obtain the metal layer 7, and then a second layer structure is grown on the first layer structure to wrap the metal layer 7. When the thickness of the second layer structure is the same as that of the metal layer 7, the first surface of the metal layer 7 is in contact with the side of the buffer layer 202 away from the substrate 1.

[0038] In some embodiments, the metal layer 7 may be a rectangular body that is easy to shape. Figure 4 . The thickness of the metal layer 7 is 10nm-1000nm, preferably 100nm. Exemplarily, the metal layer 7 may be a structure formed by a metal, suitable for formation by epitaxial growth and etching. Among them, the metal is preferably one or more high-temperature resistant materials such as tungsten, molybdenum, tantalum and nickel. The size of the metal layer 7 along the first direction (i.e., the arrangement direction from the source 6 to the drain 4) is larger than the size of the metal layer 7 along the second direction (i.e., the arrangement direction from the substrate 1 to the semiconductor layer 2), so that its structure is flattened, thereby reducing the occupancy ratio of the metal layer 7 to the semiconductor layer 2, such as the occupancy ratio of the channel layer 203, effectively avoiding the significant decrease in the two-dimensional electron gas concentration due to the excessive volume of the metal layer 7, and ensuring that the switching characteristics of the semiconductor device are still useful and efficient.

[0039] like Figure 1 、 Figure 2 、 Figure 3 and Figure 6As shown, to prevent the metal layer 7 from reacting with ammonia used in epitaxial growth during subsequent device manufacturing processes, in particular, the semiconductor device further includes a first barrier structure 8 and a second barrier structure 803. The first barrier structure 8 is at least partially disposed between the metal layer 7 and the two-dimensional electron gas, and between the electrical connection structure 57 and the two-dimensional electron gas. The second barrier structure 803 is connected to the first barrier structure 8 and covers the side surfaces of the metal layer 7.

[0040] It should be noted that the first barrier structure 8 and the second barrier structure 803 are both made of high-resistance materials, which is beneficial to the insulation between the metal layer 7 and the semiconductor layer 2 .

[0041] In some embodiments, as Figure 2 As shown, the first blocking structure 8 includes a first blocking portion 801, which is arranged above the metal layer 7 and is used to insulate the metal layer 7 from the two-dimensional electron gas, thereby intercepting the leakage current generated by the two-dimensional electron gas flowing toward the metal layer 7, thereby effectively reducing the risk of failure or damage of the semiconductor device during high-voltage operation.

[0042] In some embodiments, as shown in Figure 5 , a first barrier 801 is disposed above the metal layer 7 to electrically isolate the metal layer 7 from the two-dimensional electron gas. For example, referring again to Figure 5 , it should be noted that the first surface of the metal layer 7 includes a connection region for connection to the electrical connection structure 57 , and the first barrier 801 is disposed on the first surface of the metal layer 7 excluding the connection region. The first barrier 801 is made of one of silicon dioxide, silicon nitride, aluminum nitride, and aluminum oxide, and has a thickness of 5 nm to 1000 nm to ensure its suitability for formation via epitaxial growth and etching.

[0043] In some embodiments, the first barrier structure 8 further includes a second barrier portion 802 that encases the electrical connection structure 57. This serves to insulate the electrical connection structure 57 from the two-dimensional electron gas (2DEG), intercepting leakage current generated by the 2DEG and flowing toward the electrical connection structure 57. This effectively reduces the risk of failure or damage to the semiconductor device during high-voltage operation. Second barrier portion 802 resembles a sleeve-like structure and is made of one of silicon dioxide, silicon nitride, aluminum nitride, and aluminum oxide. Its thickness can be selected from 5 nm to 1000 nm to ensure its suitability for formation via epitaxial growth and etching.

[0044] In some embodiments, the first barrier structure 8 covers the first surface of the metal layer 7 and the side of the buffer layer 202 away from the substrate, and is located on the side of the channel layer 203 close to the substrate 1. In this way, the first barrier structure 8 can be directly constructed as a layer structure between the channel layer 203 and the buffer layer 202.

[0045] In some embodiments, the manufacturing steps and materials used for the second barrier structure 803 and the first barrier portion 801 of the first barrier structure 8 may be the same or different.

[0046] In other embodiments, Figure 6 As shown, there are multiple metal layers 7 , and the multiple metal layers 7 are spaced apart along the first direction (ie, the arrangement direction from the source 6 to the drain 4 ).

[0047] In some embodiments, see Figure 6 Each metal layer 7 has equal dimensions, and the total dimension of the multiple metal layers 7 along the first direction is smaller than the dimension of a single metal layer 7 along the second direction, where the second direction is the arrangement direction from the substrate 1 to the semiconductor layer 2. Based on this, there are also multiple electrical connection structures 57, each of which is a rod-shaped body perpendicular to the corresponding metal layer 7, with one end of each electrical connection structure 57 connected to the connection area of the metal layer 7 and the other end connected to the gate 5.

[0048] In other embodiments, in order to reduce the number of electrical connection structures, such as Figure 7 As shown, metal layer 7 includes: first metal layers 701 spaced apart and a second metal layer 702 connecting the spaced apart first metal layers 701. Exemplarily, second metal layer 702 is perpendicular to first metal layer 701. Thus, because the spaced apart first metal layers 701 are connected by second metal layer 702, only one electrical connection structure 57 electrically connected to gate 5 is required to achieve electrical connection between metal layer 702 and gate 5.

[0049] In some other embodiments, the first metal layers 701 are arranged at intervals along a first direction, wherein the first direction is an arrangement direction of the source 6 to the drain 4 .

[0050] In some embodiments, as Figure 7 As shown, the connection area of the metal layer 7 is located on one of the multiple first metal layers 701; there is one electrical connection structure 57, and one end of the electrical connection structure 57 is connected to the first metal layer 701 with the connection area, and the other end is connected to the gate 5.

[0051] In some embodiments, as Figure 7 As shown, the connection region is located on an extension area of the first metal layer 701 having the connection region that extends away from the second metal layer 702 .

[0052] In the above embodiment, a metal layer 7 electrically connected to the gate 5 is provided inside the semiconductor device, and the metal layer 7 and the two-dimensional electron gas, as well as the electrical connection structure 57 and the two-dimensional electron gas, are isolated by the first barrier structure 8. Thus, the electric field strength of the gate 5 under high voltage of the semiconductor device can be effectively reduced by the metal layer 7 to which the gate 5 is connected, thereby improving the breakdown voltage of the device.

[0053] It should be noted that the metal layer 7 is made primarily of a metal material. When the metal layer 7 is primarily made of metal, the metal is susceptible to reacting with ammonia gas during the subsequent epitaxial growth process of the device. Isolating the metal layer within the first and second barrier structures 803 reduces corrosion of the metal layer 7 by ammonia gas during epitaxial growth, thereby ensuring that the metal layer 7 can be electrically connected to the gate 5 and helping to reduce the electric field near the gate 5. Thus, the first and second barrier structures 803 of the disclosed embodiments further prevent the metal layer 7 from reacting with ammonia gas used in subsequent device manufacturing processes, particularly during epitaxial growth, ensuring that the aforementioned effects can be successfully achieved.

[0054] In some embodiments, as Figure 2 As shown, the semiconductor device may further include a gate field plate 11, which is located on the passivation layer 9 between the gate 5 and the drain 4. The gate field plate 11 can assist the metal layer 7 in adjusting the electric field distribution between the channel layer 203 and the barrier layer 204, further reducing the peak electric field intensity near the gate 5, thereby significantly improving the breakdown voltage of the device.

[0055] In the above embodiment, by providing a metal layer 7 similar to a gate field plate within the device and utilizing the metal layer 7 to increase the breakdown voltage of the device, the semiconductor device has a higher breakdown voltage when no gate field plate is used, and an even higher breakdown voltage when a gate field plate is used. In fact, the metal layer 7 can be connected to the gate 5 or the source 6. However, since the potential of the source 6 is not as strong as that of the gate 5, and the peak value of the electric field intensity near the gate 5 is synchronized with the potential of the gate 5 rather than the potential of the source 6, the metal layer 7 connected to the gate 5 must have a stronger and more accurate electric field regulation capability near the gate, which is beneficial to ensuring a lower peak value of the electric field intensity near the gate 5 and a higher breakdown voltage of the device. When the metal layer 7 needs to be connected to the source electrode 6, since the source electrode 6 can be directly extended to and connected to the metal layer 7, the metal layer connected to the source electrode 6 is easy to realize during the manufacturing process. However, when the metal layer 7 needs to be connected to the gate 5, since the gate 5 may damage the two-dimensional electron gas and cannot be directly extended to the metal layer 7, the metal layer 7 connected to the gate 5 is difficult to realize during the manufacturing process. After diligent research, the applicant discovered that it is possible to add an electrical connection structure 57 in the device that passes through the barrier layer 204 and the channel layer 203 and connects the metal layer 7 and the gate 5 therethrough. At the same time, a first blocking structure 8 is added between the metal layer 7 and the two-dimensional electron gas and between the electrical connection structure 57 and the two-dimensional electron gas. The first blocking structure 8 can help to insulate the metal layer 7 from the two-dimensional electron gas, and then insulate the electrical connection structure 57 from the two-dimensional electron gas. This can intercept the leakage current generated by the two-dimensional electron gas and flowing toward the metal layer 7 and the electrical connection structure 57, effectively improving the breakdown voltage of the device, allowing the semiconductor device to operate normally at a higher operating voltage.

[0056] Please combine again Figure 1 、 Figure 2 、 Figure 3 and Figure 6 , the embodiment of the present disclosure also discloses a method for manufacturing a semiconductor device, the method comprising the following steps: providing a substrate 1; forming a semiconductor layer 2 on the substrate 1, the semiconductor layer 2 comprising a first semiconductor stack and a second semiconductor layer arranged on the first semiconductor stack; forming a two-dimensional electron gas at the interface between the first semiconductor stack and the second semiconductor layer; forming a metal layer 7 in the semiconductor layer 2 and positioning it between the substrate 1 and the two-dimensional electron gas; forming a source 6, a drain 4 and a gate 5 on the second semiconductor layer; extending from the gate 5 into the semiconductor layer 2 and electrically connecting to the metal layer 7 to form an electrical connection structure 57; providing a first barrier structure 8 on a side of the metal layer 7 away from the substrate 1, wherein the first barrier structure 8 is used to insulate and isolate the metal layer 7 and the electrical connection structure 50 from the two-dimensional electron gas; providing a second barrier structure 803 on a side of the metal layer 7, wherein the side is adjacent to a side of the metal layer away from the substrate 1.

[0057] In this way, the semiconductor device prepared by the above method, by providing a metal layer 7 that can be electrically connected to the gate 5 inside the device, and isolating the metal layer 7 from the two-dimensional electron gas, and the electrical connection structure 57 from the two-dimensional electron gas, by the first barrier structure 8, can effectively reduce the electric field strength of the gate 5 of the HEMT device under high voltage through the metal layer 7 connected to the gate 5, thereby improving the breakdown voltage of the device.

[0058] In some embodiments, the first semiconductor stack includes: a buffer layer 202 close to the substrate 1, and a channel layer 203 disposed on the buffer layer 202, and forming the metal layer 7 in the semiconductor layer 2 includes:

[0059] A metal layer 7 is formed in the channel layer 203 .

[0060] In this way, the metal layer 7 is disposed in the channel layer 203 , which can ensure that the metal layer 7 is located below the two-dimensional electron gas while reducing the distance between the metal layer 7 and the gate 5 .

[0061] In some embodiments, forming a metal layer in a channel layer includes:

[0062] A conductive material layer formed of a metal material is grown on the buffer layer 202, and the conductive material layer is etched to obtain a metal layer 7 formed of the remaining conductive material layer;

[0063] Of course, for the method of setting the metal layer 7 in the channel layer 203, after the first epitaxial growth of the channel layer 203 reaches a certain height, the conductive material layer can be grown by the same sampling growth method and then etched to form the metal layer 7, and then the remaining channel layer 203 can be grown by secondary epitaxial growth.

[0064] In some other embodiments, a first barrier structure 8 is provided on a side of the metal layer 7 away from the substrate 1, and a second barrier structure 803 is provided on a side of the metal layer 7, including:

[0065] A high-resistance material layer formed of an insulating compound is grown on the metal layer 7, and the high-resistance material layer is etched to obtain a first barrier portion 801 of the first barrier structure 8 formed by the remaining high-resistance material layer and located above the metal layer 7, and a second barrier structure 803 located on the side of the metal layer 7.

[0066] Regarding the methods in the above embodiments, the specific manner of executing the steps of each method has been described in detail in the embodiments of the device, and will not be elaborated here.

[0067] In order to further understand the semiconductor device and the method for manufacturing the semiconductor device provided by the embodiments of the present disclosure, the above disclosure is further described below through the following specific embodiments.

[0068] Example 1

[0069] This embodiment provides a semiconductor device, also known as a high electron mobility transistor (HEMT), which has advantages such as high breakdown voltage and high conductivity. It can be used as a semiconductor power device or a semiconductor radio frequency device and has been widely used in base station communications, the Internet of Things, aerospace, radar systems and other fields.

[0070] like Figure 1 and Figure 2 As shown, the semiconductor device includes a substrate 1 and a semiconductor layer 2 provided on the substrate 1. The substrate 1 can be formed of silicon (Si), silicon carbide (SiC) or sapphire. The semiconductor layer 2 includes a first semiconductor stack and a second semiconductor layer provided on the first semiconductor stack. The second semiconductor layer includes a barrier layer 204, the main manufacturing material of which can be alloy nitride, in particular aluminum gallium nitride (AlGaN), with a thickness of 5nm-50nm ("nm" means nanometer). The first semiconductor stack includes a buffer layer 202 and a channel layer 203 provided on the buffer layer 202, wherein the main manufacturing material of the channel layer 203 can be III-V nitride, in particular gallium nitride (GaN), and the thickness is generally 100nm-1000nm. When the channel layer 203 comprises a III-V nitride and the barrier layer 204 comprises an alloy nitride, the channel layer 203 and the barrier layer 204 form a heterostructure. Due to the large difference in polarization strength and bandgap between the two, a two-dimensional electron gas (2DEG) forms at their interface. Both the channel layer 203 and the barrier layer 204 can be a single or multilayer structure. Preferably, the channel layer 203 comprises a 300nm high-resistance gallium nitride layer and a 200nm high-temperature gallium nitride layer arranged in a direction away from the substrate 1, while the barrier layer 204 comprises a 1nm aluminum nitride layer, a 20nm aluminum gallium nitride layer, and a 2nm gallium nitride layer arranged in a direction away from the channel layer 203.

[0071] The semiconductor layer 2 may further include a nucleation layer 201 disposed on the substrate 1, and a buffer layer 202 disposed on the nucleation layer 201. The nucleation layer 201 is formed of aluminum carbide (AlN) or gallium nitride (GaN) with a thickness of 10 nm to 500 nm, and is used to improve the growth quality of the buffer layer 202 and provide an isolation function. The buffer layer 202 is formed of iron-doped gallium nitride, carbon-doped gallium nitride, gallium nitride (GaN), or aluminum gallium nitride (AlGaN), and has a thickness of 100 nm to 10 μm, and is used to improve the growth quality of the III-V nitride. The buffer layer 202 may have a single layer or multiple layers. When the substrate 1 is selected as silicon material, the buffer layer 202 is preferably a three-layer structure, the first layer is aluminum gallium nitride with an aluminum content of 75% and a total thickness of 400nm, the second layer is aluminum gallium nitride with an aluminum content of 50% and a total thickness of 900nm, and the third layer is aluminum gallium nitride with an aluminum content of 25% and a total thickness of 1500nm.

[0072] The semiconductor device also includes a gate 5, a drain 4, and a source 6, which are mainly arranged on the barrier layer 204. The source 6 and the drain 4 can both be a single-layer structure or a multi-layer structure, preferably including a titanium (Ti) layer, an aluminum (Al) layer, a nickel (Ni) layer, and a gold (Au) layer connected in sequence. The source 6 makes ohmic contact with the barrier layer 204 and is electrically connected to the two-dimensional electron gas. The drain 4 also makes ohmic contact with the barrier layer 204 and is electrically connected to the two-dimensional electron gas. The gate 5 mainly includes one or two of a nickel (Ni) layer and a gold (Au) layer, and makes Schottky contact with the barrier layer 204. When using the semiconductor device, changing the electric field of the gate 5 can regulate the two-dimensional electron gas and control the conduction and shutdown of the source 6 and the drain 4.

[0073] The semiconductor device also includes a passivation layer 9. Passivation layer 9 is disposed on barrier layer 204 and provides clearance for gate 5, drain 4, and source 6. Specifically, passivation layer 9 has multiple clearance holes through which gate 5, drain 4, and source 6 pass, respectively. This allows passivation layer 9 to insulate gate 5, drain 4, and source 6, thereby preventing semiconductor device failures due to erroneous connection between electrodes. Passivation layer 9 is made of an insulating compound such as silicon dioxide, silicon nitride, aluminum nitride, and aluminum oxide.

[0074] like Figure 2 and Figure 3As shown, the semiconductor device further includes a metal layer 7 disposed within the channel layer 203, and an electrical connection structure 57 for electrically connecting the metal layer 7 to the gate 5. The metal layer 7 includes a first surface away from the substrate 1, a second surface opposite thereto and close to the substrate 1, and a side surface connected to the first surface and the second surface. There can be only one metal layer 7, and the metal layer 7 intersects with the orthographic projection of the gate 5 on the substrate 1. When an electric potential is applied to the gate 5 of the semiconductor device, the source 6 and the drain 4 can be connected via the two-dimensional electron gas. The metal layer 7 can adjust the electric field distribution between the channel layer 203 and the barrier layer 204, reduce the peak electric field intensity near the gate 5, and increase the breakdown voltage of the device, thereby improving the operating characteristics of the device under high voltage, high power and / or high frequency. However, since the peak electric field strength occurs between the gate 5 and the drain 4 and is close to the gate 5, it is recommended to set it up so that the orthographic projection of the metal layer 7 on the substrate 1 is closer to the orthographic projection of the drain 4 on the substrate 1 than the orthographic projection of the gate 5 on the substrate 1. In this way, the metal layer 7 can further reduce the peak electric field strength near the gate 5 and further increase the breakdown voltage of the device.

[0075] The first surface of the metal layer 7 is located in the channel layer 203, and the second surface of the metal layer 7 is connected to the interface between the buffer layer 202 and the channel layer 203, so as to ensure that the metal layer 7 is suitable for forming by epitaxial growth and etching. The metal layer 7 is preferably a rectangular body that is easy to shape. Figure 4 . The thickness of the metal layer 7 is 10nm-1000nm, preferably 100nm, and can be a structure formed by metal, suitable for formation by epitaxial growth and etching methods. Among them, the metal layer 7 is preferably one or more high-temperature resistant materials such as tungsten, molybdenum, titanium and nickel. The size of the metal layer 7 along the first direction (i.e., the arrangement direction from the source 6 to the drain 4) is larger than the size of the metal layer 7 along the second direction (i.e., the arrangement direction from the substrate 1 to the semiconductor layer 2), so that its structure is flattened, thereby reducing the occupancy ratio of the metal layer 7 to the communication layer 3, effectively avoiding the significant decrease in the two-dimensional electron gas concentration due to the excessive volume of the metal layer 7, and ensuring that the switching characteristics of the semiconductor device are still useful and efficient.

[0076] The electrical connection structure 57 is a rod-shaped structure. The passivation layer 9 also has avoidance holes through which the power supply connection structure 57 passes. This allows one end of the electrical connection structure 57 to be located within the semiconductor layer 2 and connected to the connection area of the metal layer 7, while the other end of the electrical connection structure 57 is located outside the semiconductor layer 2 and connected to the side of the gate 5 facing the drain electrode 4. The rod-shaped electrical connection structure 57 not only achieves electrical connection between the metal layer 7 and the gate 5, but also uses a very simple structure. Preferably, the electrical connection structure 57 is perpendicular to the metal layer 7 and formed of metal, making it suitable for formation through epitaxial growth and etching methods. The electrical connection structure 57 is preferably one or more high-temperature resistant materials such as tungsten, molybdenum, tantalum, and nickel.

[0077] The first barrier structure 8 includes a first barrier portion 801, which is arranged above the metal layer 7 and is used to insulate the metal layer 7 from the two-dimensional electron gas, intercepting the leakage current generated by the two-dimensional electron gas flowing into the metal layer 7, thereby effectively reducing the risk of failure or damage of the semiconductor device during high-voltage operation. In addition, the first barrier structure 8 can also prevent the metal layer 7 from reacting with the ammonia used in the subsequent device manufacturing process, especially with the epitaxial growth, to ensure that it can smoothly achieve the above-mentioned effect. Preferably, the first barrier portion 801 is arranged on the first surface of the metal layer 7 except for the connection area. The manufacturing material of the first barrier portion 801 is one of silicon dioxide, silicon nitride, aluminum nitride and aluminum oxide, and the thickness can be selected from 5nm to 1000nm to ensure that it is suitable for formation by epitaxial growth and etching.

[0078] First barrier structure 8 also includes a second barrier portion 802 encasing electrical connection structure 57. This serves to insulate electrical connection structure 57 from the two-dimensional electron gas (2DEG), intercepting leakage current generated by the 2DEG and flowing toward electrical connection structure 57. This effectively reduces the risk of failure or damage to the semiconductor device during high-voltage operation. Second barrier portion 802 resembles a sleeve-like structure and is made of one of silicon dioxide, silicon nitride, aluminum nitride, and aluminum oxide. Its thickness can be selected from 5 nm to 1000 nm to ensure its suitability for formation via epitaxial growth and etching.

[0079] To further prevent the metal layer 7 from reacting during subsequent device manufacturing processes, the semiconductor device further includes a second barrier structure 803, which is connected to the first barrier structure 8 and covers the side surfaces of the metal layer 7. The second barrier structure 803 and the first barrier portion 801 of the first barrier structure 8 may be manufactured using the same or different manufacturing steps and materials.

[0080] The semiconductor device may further include a gate field plate 11 disposed on the passivation layer 9 and connected to the gate 5. The gate field plate 11 can assist the metal layer 7 in regulating the electric field distribution between the channel layer 203 and the barrier layer 204, further reducing the peak electric field intensity near the gate 5, thereby significantly improving the breakdown voltage of the device.

[0081] Next, a method for manufacturing a semiconductor device is described. The steps of the method include: providing a substrate 1, as shown in FIG. Figure 5a ; A nucleation layer 201 is grown on the substrate 1; a buffer layer 202 is grown on the nucleation layer 201, see Figure 5b; A conductive material layer formed of a metal material is grown on the buffer layer 202; the conductive material layer is etched to obtain a metal layer 7 formed of the remaining conductive material layer; a high-resistance material layer formed of an insulating compound is grown on the buffer layer 202 and the metal layer 7; the high-resistance material layer is etched to obtain a first barrier portion 801 of a first barrier structure 8 formed of the remaining high-resistance material layer and located above the metal layer 7, and a second barrier structure 803 covering the side of the metal layer 7, see Figure 5c ; A channel layer 203 is grown on the buffer layer 202 to cover the first barrier portion 801 and the second barrier structure 803 of the first barrier structure 8; a barrier layer 204 is grown on the channel layer 203, see Figure 5d .

[0082] Next, the barrier layer 204, the channel layer 203 and the first barrier portion 801 of the first barrier structure 8 are opened by etching to obtain a first slot 57a leaking out of the metal layer 7. Figure 5e ; Insulating material 9a is grown on the barrier layer 204 and in the first slot 57a, see Figure 5f ; The insulating material 9a on the barrier layer 204 is opened by etching to obtain a source hole region, a gate hole region and a drain hole region; a source electrode 6, a gate electrode 5 and a drain electrode 4 are formed in the source hole region, the gate hole region and the drain hole region respectively by growth, etching and tempering, and a gate field plate 11 connected to the gate electrode 5 is formed on the insulating material 9a. Figure 5g By etching the insulating material 9a inside and outside the first slot 57a, a second slot 57b is obtained which is thinner than the first slot 57a and can leak out the metal layer 7. Figure 5h A conductive material is grown in the second slot 57b, and then the conductive material is etched to obtain an electrical connection structure 57 formed of the conductive material and connecting the metal layer 7 to the gate 5, a passivation layer 9 formed of the remaining insulating material 9a and located on the barrier layer 204, and a second barrier portion 802 of the first barrier structure 8 for covering the electrical connection structure 57, see Figure 5i .

[0083] Example 2

[0084] like Figure 6As shown, the semiconductor device includes a substrate 1, a semiconductor layer 2 provided on the substrate 1, and a gate 5, a drain 4, and a source 6 provided on the semiconductor layer 2. The semiconductor layer 2 includes a nucleation layer 201 provided on the substrate 1, a buffer layer 202 provided on the nucleation layer 201, a channel layer 203 provided on the buffer layer 202, and a barrier layer 204 provided on the channel layer 203. The gate 5 makes a Schottky contact with the barrier layer 204, the source 6 makes an ohmic contact with the barrier layer 204, and the drain 4 makes an ohmic contact with the barrier layer 204. The semiconductor device may further include a passivation layer 9 provided on the barrier layer 204, and the passivation layer 9 has a plurality of avoidance holes for the gate 5, the drain 4, and the source 6 to pass through, respectively.

[0085] like Figure 6 and Figure 7 As shown, the semiconductor device also includes a metal layer 7 provided in the channel layer 203, and an electrical connection structure 57 for electrically connecting the metal layer 7 to the gate 5. The metal layer 7 includes a first surface away from the substrate 1, and a second surface opposite thereto and close to the substrate 1. The metal layer 7 includes first metal layers 701 spaced apart along a first direction (i.e., the arrangement direction from the source 6 to the drain 4) and a second metal layer 702 connecting the spaced apart first metal layers 701. A connection region in contact with the electrical connection structure 57 is provided on one of the plurality of first metal layers 701. Preferably, the connection region is located on an extended region of the first metal layer 701 having the connection region extending away from the second metal layer 702. More preferably, the second metal layer 702 is perpendicular to the first metal layer 701 to reduce the difficulty of manufacturing. The orthographic projection of at least one first metal layer 701 on the substrate 1 intersects with the orthographic projection of the gate 5 on the substrate 1. When an electric potential is applied to the gate 5 of the semiconductor device, the source 6 and drain 4 can be connected via the two-dimensional electron gas. The metal layer 7, primarily through the multiple first metal layers 701, uniformly regulates the electric field distribution between the channel layer 203 and the barrier layer 204. Compared to the semiconductor device of Example 1, the semiconductor device having the first metal layer 701 and the second metal layer 702 can more effectively reduce the peak electric field intensity near the gate 5, further improve the device's breakdown voltage, and improve the device's operating characteristics under high voltage, high power, and / or high frequency conditions. However, since the electric field intensity peak occurs between the gate 5 and the drain 4 and is immediately adjacent to the gate 5, it is recommended that the orthographic projection of the first metal layer 701 closest to the drain 4 on the substrate 1 among the multiple first metal layers 701 is closer to the orthographic projection of the drain 4 on the substrate 1 than the orthographic projection of the gate 5 on the substrate 1. As a result, the first metal layer 701 closest to the drain 4 can better reduce the peak electric field intensity near the gate 5 and more effectively improve the device's breakdown voltage.

[0086] The first surface of the metal layer 7 is located in the channel layer 203, and the second surface of the metal layer 7 is in contact with the surface of the buffer layer 202 away from the substrate 1 to ensure that the metal layer 7 is suitable for being formed by epitaxial growth and etching. Each first metal layer 701 is preferably a rectangular body that is easy to form. The thickness of the metal layer 7 is 10nm-1000nm, preferably 100nm, and can be optionally a structure formed by metal, suitable for being formed by epitaxial growth and etching. Among them, the metal layer 7 is preferably one or more high-temperature resistant materials such as tungsten, molybdenum, tantalum and nickel. The size of each first metal layer 701 along the first direction is larger than the size of the first metal layer 7 along the second direction (i.e., the arrangement direction from the substrate 1 to the semiconductor layer 2), thereby reducing the proportion of the metal layer 7 occupying the communication layer 3, effectively avoiding a significant decrease in the concentration of the two-dimensional electron gas, and ensuring that the switching characteristics of the semiconductor device are still useful and efficient.

[0087] The electrical connection structure 57 is a rod-shaped structure, and the passivation layer 9 also has an avoidance hole through which the power supply connection structure 57 passes. This allows one end of the electrical connection structure 57 to be located within the semiconductor layer 2 and connected to the connection area of the first metal layer 701, while the other end of the electrical connection structure 57 is located outside the semiconductor layer 2 and connected to the side of the gate 5 facing the drain 4. The rod-shaped electrical connection structure 57 not only achieves electrical connection between the metal layer 7 and the gate 5, but also uses a very simple structure. Preferably, the electrical connection structure 57 is perpendicular to the metal layer 7 and is formed of metal, making it suitable for formation through epitaxial growth and etching methods. The metal is preferably one or more high-temperature resistant materials such as tungsten, molybdenum, titanium, and nickel.

[0088] The first barrier structure 8 includes a first barrier portion 801, which is arranged above the metal layer 7 and is used to insulate the metal layer 7 from the two-dimensional electron gas, intercepting the leakage current generated by the two-dimensional electron gas and flowing toward the metal layer 7, thereby effectively reducing the risk of failure or damage of the semiconductor device during high-voltage operation. In addition, the first barrier structure 8 can also prevent the metal layer 7 from reacting with ammonia used in subsequent device manufacturing processes, especially with epitaxial growth, to ensure that it can smoothly achieve the aforementioned effects. Preferably, the first barrier portion 801 is arranged on the first surface of the metal layer 7 except for the connection area. The number of first barrier portions 801 can be one or more. When the number of first barrier portions 801 is selected as one, the first barrier portion 801 covers the first surface (i.e., the upper surface) of all first metal layers 701 and leaves only the connection area for connecting to the electrical connection structure 57. When the number of the first barrier parts 801 is selected as plural, one first barrier part 801 covers the first surface of the first metal layer 701 having the connection area and leaves only the connection area for connecting the electrical connection structure 57, and each of the remaining first barrier parts 801 can independently cover the first surface of the first metal layer 701. The manufacturing material of the first barrier part 801 is one of silicon dioxide, silicon nitride, aluminum nitride and aluminum oxide, and the thickness can be selected from 5nm to 1000nm, which is suitable for formation by epitaxial growth and etching. The first barrier structure 8 also includes a second barrier part 802 (see Figure 3 ) is used to electrically isolate the electrical connection structure 57 from the two-dimensional electron gas, intercepting leakage current generated by the two-dimensional electron gas and flowing toward the electrical connection structure 57, thereby effectively reducing the risk of failure or damage to the semiconductor device during high-voltage operation. The second barrier portion 802 is made of one of silicon dioxide, silicon nitride, aluminum nitride, and aluminum oxide, with a thickness of 5 nm to 1000 nm, and is suitable for formation via epitaxial growth and etching.

[0089] To further prevent metal layer 7 from reacting during subsequent device manufacturing processes, the semiconductor device further includes a second barrier structure 803 connected to the first barrier structure 8 and covering the side surfaces of metal layer 7. The second barrier structure 803 and the first barrier portion 801 of the first barrier structure 8 may be manufactured using the same or different manufacturing steps and materials.

[0090] Preferably, the semiconductor device may further include a gate field plate 11 disposed on the passivation layer 9 and connected to the gate 5. The gate field plate 11 can assist the metal layer 7 in adjusting the electric field distribution between the channel layer 203 and the barrier layer 204, further reducing the peak electric field intensity near the gate 5, thereby significantly improving the breakdown voltage of the device.

[0091] Next, a method for manufacturing a semiconductor device is introduced, and the steps of the manufacturing method include: providing a substrate 1; growing a nucleation layer 201 on the substrate 1; growing a buffer layer 202 on the nucleation layer 201; growing a conductive material layer formed of a metal material on the buffer layer 202; etching the conductive material layer to obtain a metal layer 7 formed of a remaining conductive material layer; growing a high-resistance material layer formed of an insulating compound on the buffer layer 202 and the metal layer 7; etching the high-resistance material layer to obtain a first barrier portion 801 of a first barrier structure 8 formed by the remaining high-resistance material layer and located above the metal layer 7, and a second barrier structure 803 covering the side of the metal layer 7; growing a channel layer 203 on the buffer layer 202 that can cover the first barrier portion 801 and the second barrier structure 803 of the first barrier structure 8; and growing a barrier layer 204 on the channel layer 203.

[0092] Then, the barrier layer 204, the channel layer 203 and the first barrier portion 801 of the first barrier structure 8 are opened by etching to obtain a first slot 57a leaking out of the metal layer 7 (see Figure 5e ); growing insulating material on the barrier layer 204 and in the first slot 57a; opening holes in the insulating material on the barrier layer 204 by etching to obtain a source hole region, a gate hole region, and a drain hole region; forming a source 6, a gate 5, and a drain 4 in the source hole region, the gate hole region, and the drain hole region respectively by growing, etching, and tempering, and forming a gate field plate 11 connected to the gate 5 on the insulating material; opening holes in the insulating material inside and outside the first slot 57a by etching to obtain a second slot 57b (see FIG. 5 ) that can leak out the metal layer 7 and is thinner than the first slot 57a. Figure 5h ); a conductive material is grown in the second slot 57b, and then the conductive material is etched to obtain an electrical connection structure 57 formed by the conductive material and connecting the metal layer 7 to the gate 5, as well as a passivation layer 9 formed by the remaining insulating material and located on the barrier layer 204, and a second barrier portion 802 of the first barrier structure 8 for covering the electrical connection structure 57.

[0093] The above description is only a preferred embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any person skilled in the art can easily make changes or variations within the technical scope of the present disclosure, and such changes or variations should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims. As long as there is no structural conflict, the various technical features mentioned in the various embodiments can be combined in any way. The present disclosure is not limited to the specific embodiments disclosed herein, but includes all technical solutions that fall within the scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; A semiconductor layer is provided on a substrate, the semiconductor layer comprising: a first semiconductor stack and a second semiconductor layer provided on the first semiconductor stack; a two-dimensional electron gas is formed at an interface between the first semiconductor stack and the second semiconductor layer; A source electrode, a drain electrode, and a gate electrode are provided on the second semiconductor layer and arranged at intervals; a metal layer disposed in the semiconductor layer and between the substrate and the two-dimensional electron gas; an electrical connection structure, extending from the gate into the semiconductor layer and connected to the metal layer, for electrically connecting the metal layer to the gate; a first blocking structure, disposed on a side of the metal layer away from the substrate, for insulating and isolating the metal layer and the electrical connection structure from the two-dimensional electron gas; The second barrier structure is connected to the first barrier structure and covers a side surface of the metal layer, wherein the side surface is adjacent to a side of the metal layer away from the substrate.

2. The semiconductor device according to claim 1, wherein The first barrier structure comprises: a first blocking portion, disposed above the metal layer, for insulating and isolating the metal layer from the two-dimensional electron gas; The second blocking portion wraps the electrical connection structure and is used to insulate and isolate the electrical connection structure from the two-dimensional electron gas.

3. The semiconductor device according to claim 2, wherein The metal layer includes: a first surface away from the substrate and a second surface close to the substrate, wherein the first surface includes a connection area for connecting to the electrical connection structure, and the first barrier portion is arranged on the first surface of the metal layer except the connection area.

4. The semiconductor device according to claim 3, wherein The first semiconductor stack includes: a buffer layer close to the substrate, and a channel layer disposed on the buffer layer; The metal layer is disposed in the channel layer.

5. The semiconductor device according to claim 4, wherein The first surface of the metal layer and the second surface of the metal layer are both located in the channel layer; or, A first surface of the metal layer is located in the channel layer, and a second surface of the metal layer is connected to an interface between the buffer layer and the channel layer.

6. The semiconductor device according to claim 3, wherein The first semiconductor stack includes: a buffer layer close to the substrate, and a channel layer disposed on the buffer layer; The metal layer is disposed in the buffer layer.

7. The semiconductor device according to claim 6, wherein: The first surface of the metal layer is in contact with a side of the buffer layer away from the substrate, and the second surface of the metal layer is located in the buffer layer.

8. The semiconductor device according to claim 7, wherein: The first barrier portion covers the first surface of the metal layer and the side of the buffer layer away from the substrate, and is located on the side of the channel layer close to the substrate.

9. The semiconductor device according to any one of claims 1 to 8, wherein The metal layer is in the shape of a rectangular body.

10. The semiconductor device according to claim 9, wherein There is one metal layer, and a size of the metal layer along a first direction is larger than a size of the metal layer along a second direction, wherein the first direction is an arrangement direction from the source to the drain, and the second direction is an arrangement direction from the substrate to the semiconductor layer.

11. The semiconductor device according to claim 10, wherein: The electrical connection structure is a rod-shaped structure perpendicular to the metal layer, one end of the electrical connection structure is connected to the connection area, and the other end of the electrical connection structure is connected to the gate.

12. The semiconductor device according to claim 9, wherein There are a plurality of metal layers, and the plurality of metal layers are spaced apart along a first direction, where the first direction is an arrangement direction from the source electrode to the drain electrode; There are multiple electrical connection structures, each of which is a rod-shaped body perpendicular to the corresponding metal layer. One end of each electrical connection structure is connected to the connection area of the corresponding metal layer, and the other end is connected to the gate.

13. The semiconductor device according to any one of claims 1 to 8, wherein: The metal layer includes: first metal layers arranged at intervals and a second metal layer connecting the first metal layers arranged at intervals.

14. The semiconductor device according to claim 13, wherein: The second metal layer and the first metal layer are perpendicular to each other, and the first metal layers are arranged at intervals along a first direction, wherein the first direction is an arrangement direction from the source to the drain.

15. The semiconductor device according to claim 14, wherein: The connection area of the metal layer is located on one of the first metal layers; there is one electrical connection structure, one end of which is connected to the first metal layer having the connection area, and the other end is connected to the gate.

16. The semiconductor device according to claim 15, wherein: The connection region is located on an extension area of the first metal layer having the connection region that extends away from the second metal layer.

17. The semiconductor device according to claim 1, wherein The first barrier structure and the second barrier structure are formed of an insulating compound.

18. The semiconductor device according to claim 3, wherein An orthographic projection of the metal layer on the substrate intersects an orthographic projection of the gate on the substrate.

19. The semiconductor device according to claim 1, wherein: The semiconductor device further includes: A passivation layer is provided on the second semiconductor layer, and the passivation layer is located between the electrical connection structure and the source electrode, and between the gate electrode and the drain electrode.

20. The semiconductor device according to claim 19, wherein The semiconductor device further includes: A gate field plate is located on the passivation layer between the gate and the drain, connected to the gate and disposed on the second semiconductor layer; one end of the electrical connection structure is connected to a side of the gate facing the drain.

21. The semiconductor device according to claim 1, wherein The metal layer is made of one or more of tungsten, molybdenum, tantalum and nickel.

22. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: providing a substrate; forming a semiconductor layer on the substrate, wherein the semiconductor layer comprises a first semiconductor stack and a second semiconductor layer disposed on the first semiconductor stack; A two-dimensional electron gas is formed at the interface between the first semiconductor stack and the second semiconductor layer; forming a metal layer in the semiconductor layer, wherein the metal layer is located between the substrate and the two-dimensional electron gas; forming a source electrode, a drain electrode and a gate electrode on the second semiconductor layer; extending from the gate into the semiconductor layer and electrically connected to the metal layer to form an electrical connection structure; A first barrier structure is provided on a side of the metal layer away from the substrate, wherein the first barrier is used to insulate the metal layer and the electrical connection structure from the two-dimensional electron gas; A second barrier structure is provided on a side surface of the metal layer, wherein the side surface is adjacent to a side of the metal layer away from the substrate.

23. The manufacturing method according to claim 22, wherein: forming a metal layer within the semiconductor layer, comprising: growing a conductive material layer formed of a metal material on the buffer layer in the semiconductor layer, and etching the conductive material layer to obtain the metal layer formed of the remaining conductive material layer; or Growing a conductive material layer formed of a metal material in a buffer layer within the semiconductor layer, wherein the buffer layer includes a first layer structure and a second layer structure, and growing the conductive material layer formed of a metal material in the buffer layer within the semiconductor layer is growing the conductive material layer on the first layer structure; Etching the conductive material layer to obtain the metal layer; growing the second layer structure wrapping the metal layer on the first layer structure; The step of providing a first barrier structure on a side of the metal layer away from the substrate, and providing a second barrier structure on a side of the metal layer, comprises: A high-resistance material layer formed of an insulating compound is grown on the metal layer, and the high-resistance material layer is etched to obtain a first barrier portion of a first barrier structure formed by the remaining high-resistance material layer and located above the metal layer, and a second barrier structure located on the side of the metal layer.

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