A controllable dual-gate tunneling field-effect transistor based on silicon

Abstract

The present invention relates to a dual-gate tunneling field effect transistor, and in particular to a silicon-based adjustable dual-gate tunneling field effect transistor, which is used to solve the problem that the existing tunneling field effect transistor cannot avoid the increase of bipolar current while enhancing the on-state current. The silicon-based adjustable dual-gate tunneling field effect transistor includes a first channel region, a second channel region, a source region, a drain region, a gate oxide layer, and an auxiliary tunneling barrier layer; wherein the gate oxide layer includes a first gate oxide layer close to the drain region and a second gate oxide layer close to the source region, and the dielectric constant of the first gate oxide layer is relatively low, so as to increase the reverse tunneling barrier width to reduce the bipolar effect; the present invention can increase the on-state current of the device by reducing the width of the second gate oxide layer, and increase the width of the first gate oxide layer to suppress the bipolar current, thereby solving the shortcomings of the traditional TFET with low on-state current, obvious bipolar effect, and failure to meet the rapid development needs of TFET devices.

Description

Technical Field

[0001] The invention relates to a dual-gate tunneling field effect transistor, in particular to a silicon-based adjustable dual-gate tunneling field effect transistor. Background Art

[0002] With the rapid development of the Internet of Things and neural network computers, the requirements for ultra-low power consumption and ultra-low voltage of integrated circuits will continue to increase in the future. MOSFET-based chips will run faster and save more power than before. However, due to the physical limitations of the thermally excited conduction mechanism of MOSFET, its subthreshold swing (SS: Subthreshold Swing) can only reach a minimum of 60mV / dec at room temperature. The contradiction between static power consumption and device performance caused by off-state leakage current has become an important concern. In order to solve this problem, researchers have proposed a low-power device that changes the conduction mechanism of the device, namely the tunneling field effect transistor (TFET). The on-current of TFET is affected by band-to-band tunneling (BTBT), breaking the shackles of its subthreshold swing that cannot be lower than 60mV / dec, thereby greatly reducing the power consumption of the device, becoming one of the most promising devices to replace MOSFET in the post-Moore era in the field of high-performance and low-power integrated circuits.

[0003] To exploit the potential of TFET, researchers have proposed various novel TFET structures to enhance the on-state current. Dual-gate TFET exhibits twice the gate control capability of the channel, so it can provide a smaller leakage current while enhancing the on-state current of the device. However, because the tunneling rate improvement is also activated in the bipolar state, the bipolar current of the dual-gate TFET will also increase. Summary of the invention

[0004] The purpose of the present invention is to solve the problem that the existing tunneling field effect transistor cannot avoid the increase of bipolar current while enhancing the on-state current, and to provide a silicon-based adjustable dual-gate tunneling field effect transistor.

[0005] In order to solve the deficiencies of the above-mentioned prior art, the present invention provides the following technical solutions:

[0006] A silicon-based adjustable dual-gate tunneling field effect transistor includes a channel region, a source region, a drain region, and a gate oxide layer, and is special in that it also includes an auxiliary tunneling barrier layer;

[0007] The channel region includes a first channel region and a second channel region; the drain region, the first channel region, the second channel region, the auxiliary tunneling barrier layer, and the source region are arranged in sequence from top to bottom;

[0008] The source region is P-type doped or N-type doped, and the doping type of the drain region is opposite to that of the source region;

[0009] The first channel region width is smaller than the second channel region width;

[0010] The gate oxide layer includes a first gate oxide layer symmetrically arranged on both sides of the first channel region, and a second gate oxide layer symmetrically arranged on both sides of the second channel region and the auxiliary tunnel barrier layer; the width L of the first gate oxide layer on both sides of the first channel region is ox1 Greater than the width L of the second gate oxide layer on both sides of the second channel region and the auxiliary tunnel barrier layer ox2 , the dielectric constant of the second gate oxide layer is greater than the dielectric constant of the first gate oxide layer, and the width of the second gate oxide layer L ox2 The width of the first gate oxide layer L ox1 Not equal;

[0011] The auxiliary tunneling barrier layer has a thickness of 2-5 nm and a width of 5-60 nm, and the width of the auxiliary tunneling barrier layer is less than or equal to the width of the second channel region.

[0012] Furthermore, the L ox1 is 5nm, the L ox2 is 2nm.

[0013] Furthermore, the material of the second gate oxide layer is at least one of HfO2, TiO2, ZrO2 and other high-k materials, and the high-k material satisfies k>20; the material of the first gate oxide layer is at least one of SiO2, SiON, Al2O3 and other low-k materials, and the low-k material satisfies k≤3.9.

[0014] Furthermore, the auxiliary tunneling barrier layer is made of at least one of Si, Ge, and SiGe semiconductor materials, and the doping concentration of the auxiliary tunneling barrier layer is 1×10 17～19 cm -3 .

[0015] Furthermore, the width of the second channel region is not greater than 60 nm.

[0016] Furthermore, the material of the source region is Si 1-x Ge x , and the source region doping concentration is 1×10 20 ~2×10 20 cm -3 , the drain region doping concentration is 1×10 18 c~5×10 18 cm -3 .

[0017] Furthermore, the drain region and the first channel region have the same width, the width of the portion of the second channel region protruding from the first channel region is equal, and the second channel region and the source region have the same width.

[0018] Furthermore, the widths of the drain region and the first channel region are both 50 nm, the widths of the second channel region, the auxiliary tunneling barrier layer, and the source region are all 60 nm; and the thickness of the auxiliary tunneling barrier layer is 5 nm.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] (1) The present invention discloses a silicon-based controllable dual-gate tunneling field effect transistor, comprising a first channel region, a second channel region, a source region, a drain region, a gate oxide layer, and an auxiliary tunneling barrier layer; wherein the gate oxide layer comprises a first gate oxide layer close to the drain region and a second gate oxide layer close to the source region, and the dielectric constant of the first gate oxide layer is relatively low, so as to increase the reverse tunneling barrier width to reduce the bipolar effect; a heterojunction contact interface is formed between the source region and the auxiliary tunneling barrier layer, and the auxiliary tunneling barrier layer is used to reduce the tunneling barrier width; the present invention can increase the on-state current of the device by reducing the width of the second gate oxide layer and increase the width of the first gate oxide layer to suppress the bipolar current, thereby solving the shortcomings of the traditional TFET, such as low on-state current, obvious bipolar effect, and failure to meet the rapid development needs of TFET devices.

[0021] (2) The present invention is a silicon-based controllable dual-gate tunneling field effect transistor. Taking the source region as a P-type doping example, under the on-state condition (Vg = Vd = 1V), the on-state current of the present invention is significantly greater than that of the silicon-based dual-gate TFET, and the bipolar current is also reduced. The on-state current of the present invention can reach 10 -4 A / μm, the off-state current is only 10 -19 A / μm, which is about 4 orders of magnitude smaller than ordinary silicon-based TFET. In addition, the average subthreshold swing of the present invention is only 21mV / dec, which is 60% lower than that of traditional TFET, ensuring that the device has good working characteristics and meets the requirements of the new generation of devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a schematic structural diagram of an embodiment 1 of a silicon-based controllable dual-gate tunneling field-effect transistor of the present invention;

[0023] Figure 2 A schematic diagram of the structure of a conventional double-gate tunneling field effect transistor for comparative example;

[0024] Figure 3 It is a comparison diagram of the energy bands of Example 1 of the present invention and the comparative example under the on-state condition along the horizontal distance between the second gate oxide layer 42 and 1 nm;

[0025] Figure 4 It is a comparison diagram of the transfer characteristic curves of Example 1 of the present invention and the comparative example under open state conditions;

[0026] Figure 5 Based on Embodiment 1 of the present invention, different first gate oxide layer widths L under the on-state condition are ox1 Comparison of transfer characteristic curves;

[0027] Figure 6 Based on Embodiment 1 of the present invention, different second gate oxide layer widths L under the on-state condition are ox2 Comparison of transfer characteristic curves;

[0028] The reference numerals are explained as follows: 1 - channel region, 11 - first channel region, 12 - second channel region; 2 - source region; 3 - drain region; 4 - gate oxide layer, 41 - first gate oxide layer, 42 - second gate oxide layer; 5 - auxiliary tunneling barrier layer. DETAILED DESCRIPTION

[0029] The present invention will be further described below in conjunction with the accompanying drawings and exemplary embodiments.

[0030] Define the horizontal length as width and the vertical length as thickness.

[0031] Example

[0032] Reference Figure 1 , a silicon-based controllable double-gate tunneling field effect transistor, including a channel region 1, a source region 2, a drain region 3, a gate oxide layer 4 and an auxiliary tunneling barrier layer 5.

[0033] The channel region 1 includes a first channel region 11 and a second channel region 12; the drain region 3, the first channel region 11, the second channel region 12, the auxiliary tunneling barrier layer 5, and the source region 2 are arranged in sequence from top to bottom.

[0034] The source region 2 may be P-type doped or N-type doped. The auxiliary tunneling barrier layer 5 and the drain region 3 have opposite doping types to the source region 2. The doping concentration of the source region 2 needs to meet 1×10 20 ~2×10 20 cm -3 , the doping concentration of drain region 3 needs to meet 1×10 18 c~5×10 18 cm -3 The auxiliary tunneling barrier layer 5 has a thickness of 2 to 5 nm and a width of 5 to 60 nm. The auxiliary tunneling barrier layer 5 can be made of at least one of Si, Ge, and SiGe semiconductor materials. The doping concentration of the auxiliary tunneling barrier layer 5 must meet 1×10 17 ～19 cm -3 .

[0035] The gate oxide layer 4 includes a first gate oxide layer 41 symmetrically arranged on both sides of the first channel region 11, and a second gate oxide layer 42 symmetrically arranged on both sides of the second channel region 12 and the auxiliary tunneling barrier layer 5; the dielectric constant of the second gate oxide layer 42 is greater than the dielectric constant of the first gate oxide layer 41, and the width L of the second gate oxide layer 42 is ox2 Greater than the width L of the first gate oxide layer 41 ox1 .

[0036] The present invention adopts a bilaterally symmetrical structure, the drain region 3 and the first channel region 11 have the same width, the second channel region 12 protruding from the first channel region 11 has the same width, and the second channel region 12 and the source region 2 have the same width and are greater than the first channel region 11.

[0037] In this embodiment, the source region 2 is P-type doped, and the source region material is Si 0.1 Ge 0.9 , the doping concentration of source region 2 is 1×10 20 cm -3 ; The drain region 3 is N-type doped, and the doping concentration of the drain region 3 is 1×10 18 cm -3 The width L of the first gate oxide layer 41 on both sides of the first channel region ox1 The second gate oxide layer 42 has a width L of 5 nm on both sides of the second channel region and the auxiliary tunnel barrier layer. ox2 The widths of the drain region 3 and the first channel region 11 are 50 nm, and the widths of the second channel region 12, the auxiliary tunneling barrier layer 5, and the source region 2 are 60 nm. The thickness of the auxiliary tunneling barrier layer 5 is 5 nm, and the doping concentration of the auxiliary tunneling barrier layer 5 is 5×10 18 cm -3 .

[0038] Comparative Example

[0039] Reference Figure 2 , an existing double-gate tunneling field effect transistor, which has a channel region 1, a source region 2, a drain region 3, and a gate oxide layer 4. The materials of the channel region 1, the source region 2, and the drain region 3 are all silicon, the channel and the source region 2 are doped with P-type phosphorus (Boron), the gate oxide layer 4 at the top and bottom of the channel region 1 is made of SiO2, the width is 2nm, and the other structural parameters are the same as those of Example 1.

[0040] Figure 3 In the embodiment of the present invention and the comparative example, under the on-state condition, along the horizontal distance between the second gate oxide layer 42 and 1 nm ( Figure 1It can be seen from the figure that the difference in device structure will affect the internal energy band distribution during operation. When the device is in the on state, compared with the comparative example, the tunneling distance of the embodiment of the present invention is smaller than the tunneling distance formed by the comparative example. Therefore, the dual-gate tunneling field effect transistor structure of the embodiment of the present invention effectively improves the on-state current of the device.

[0041] Figure 4 The figure is a comparison of the transfer characteristic curves of the embodiment of the present invention and the comparative example under the on-state condition. When the gate voltage Vg=0V, the embodiment of the present invention is reduced by 4 orders of magnitude compared with the comparative example, and the off-state current of the device is effectively suppressed. Figure 4 The transfer characteristic curve shows that the embodiment of the present invention effectively improves the on-state current of the device, suppresses the bipolar current and off-state current of the device, and the tunneling of the embodiment of the present invention is turned on early.

[0042] Figure 5 Based on the first embodiment of the present invention, different widths L of the first gate oxide layer 41 are obtained under the open state. ox1 As the width L of the first gate oxide layer 41 increases, ox1 The bipolar current of the device decreases with the increase of the gate voltage. When the gate voltage is reverse biased, the thickened first gate oxide layer 41 reduces the electric field at the tunnel junction of the channel region 1 and the drain region 3, thereby weakening the band bending around the tunnel junction of the channel region 1 and the drain region 3. Therefore, the tunneling probability of the carrier is reduced, and the bipolar current is also weakened. The embodiment of the present invention achieves the effective reduction of the bipolar current without affecting the on-state current of the tunnel field effect transistor.

[0043] Figure 6 Based on the first embodiment of the present invention, different widths L of the second gate oxide layer 42 are obtained under the on-state condition. ox2 As the width L of the second gate oxide layer 42 increases, ox2 The decrease of , the device on-state current increases. Figure 6 It can be seen that when the gate voltage Vgs=1V, its on-state current increases by 3 orders of magnitude, indicating that the on-state current of the device can be effectively increased by adjusting the width of the second gate oxide layer 42, and the device can start tunneling in advance by reducing the width of the second gate oxide layer 42.

[0044] Example 2

[0045] In this embodiment, the source region 2 is P-type doped, and the source region material is Si 0.1 Ge 0.9 , the doping concentration of source region 2 is 2×10 20 cm -3 ; The drain region 3 is N-type doped, and the doping concentration of the drain region 3 is 5×10 18The width L of the first gate oxide layer 41 on both sides of the first channel region ox1 The width L of the second gate oxide layer 42 on both sides of the second channel region and the auxiliary tunnel barrier layer is 5 nm. ox2 The widths of the drain region 3 and the first channel region 11 are 50 nm, and the widths of the second channel region 12, the auxiliary tunneling barrier layer 5, and the source region 2 are 60 nm; the thickness of the auxiliary tunneling barrier layer 5 is 2 nm, and the doping concentration of the auxiliary tunneling barrier layer 5 is 5×10 18 cm -3 .

[0046] The remaining structural parameters of this embodiment are the same as those of embodiment 1. In this embodiment, under the on-state condition, the horizontal distance between the second gate oxide layer 42 and the second gate oxide layer 42 is 1 nm ( Figure 1 The energy band curve of Figure 3 The energy band curves corresponding to the embodiments in the embodiment have the same trend.

[0047] The above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit them. For ordinary professional and technical personnel in the field, the specific technical solutions recorded in the aforementioned embodiments can be modified, or some of the technical features therein can be replaced by equivalents, and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions protected by the present invention.

Claims

1. A silicon-based controllable dual-gate tunneling field effect transistor, comprising a channel region (1), a source region (2), a drain region (3), and a gate oxide layer (4), characterized in that: It also includes an auxiliary tunneling barrier layer (5); The channel region (1) comprises a first channel region (11) and a second channel region (12); the drain region (3), the first channel region (11), the second channel region (12), the auxiliary tunneling barrier layer (5), and the source region (2) are arranged in sequence from top to bottom; The source region (2) is P-type doped or N-type doped, and the doping type of the drain region (3) is opposite to that of the source region (2); The width of the first channel region (11) is smaller than the width of the second channel region (12); The gate oxide layer (4) comprises a first gate oxide layer (41) symmetrically arranged on both sides of the first channel region (11), and a second gate oxide layer (42) symmetrically arranged on both sides of the second channel region (12) and the auxiliary tunneling barrier layer (5); the width L of the first gate oxide layer (41) on both sides of the first channel region (11) is ox1 Greater than the width L of the second gate oxide layer (42) on both sides of the second channel region (12) and the auxiliary tunneling barrier layer (5) ox2 , the dielectric constant of the second gate oxide layer (42) is greater than the dielectric constant of the first gate oxide layer (41); The auxiliary tunneling barrier layer (5) has a thickness of 2 to 5 nm and a width of 5 to 60 nm, and the width of the auxiliary tunneling barrier layer (5) is less than or equal to the width of the second channel region (12).

2. The silicon-based controllable dual-gate tunneling field effect transistor according to claim 1, characterized in that: The L ox1 is 5nm, the L ox2 is 2nm.

3. A silicon-based controllable dual-gate tunneling field effect transistor according to claim 1 or 2, characterized in that: The material of the second gate oxide layer (42) is at least one of HfO2, TiO2, ZrO2 and other high-k materials, and the high-k material satisfies k>20; the material of the first gate oxide layer (41) is at least one of SiO2, SiON, Al2O3 and other low-k materials, and the low-k material satisfies k≤3.

9.

4. The silicon-based controllable dual-gate tunneling field effect transistor according to claim 3, characterized in that: The auxiliary tunneling barrier layer (5) is made of at least one of Si, Ge, and SiGe semiconductor materials, and the doping concentration of the auxiliary tunneling barrier layer (5) is 1×10 17～19 cm -3 .

5. The silicon-based controllable dual-gate tunneling field effect transistor according to claim 4, characterized in that: The width of the second channel region (12) is no greater than 60 nm.

6. The silicon-based controllable dual-gate tunneling field effect transistor according to claim 5, characterized in that: The material of the source region (2) is Si 1-x Ge x , and the doping concentration of the source region (2) is 1×10 20 ~2×10 20 cm -3 , the doping concentration of the drain region (3) is 1×10 18 ~5×10 18 cm -3 .

7. The silicon-based controllable dual-gate tunneling field effect transistor according to claim 6, characterized in that: The drain region (3) and the first channel region (11) have the same width, the portion of the second channel region (12) protruding from the first channel region (11) has the same width, and the second channel region (12) and the source region (2) have the same width.

8. The silicon-based controllable dual-gate tunneling field effect transistor according to claim 7, characterized in that: The widths of the drain region (3) and the first channel region (11) are both 50 nm, and the widths of the second channel region (12), the auxiliary tunneling barrier layer (5) and the source region (2) are all 60 nm; the thickness of the auxiliary tunneling barrier layer (5) is 5 nm.

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