Method for forming a semiconductor element structure

Abstract

A semiconductor element structure and a method of forming the same are described. In one embodiment, a method for forming a semiconductor element structure is provided. The method includes forming a sacrificial gate structure over a portion of a semiconductor fin; forming gate spacers on opposite sides of the sacrificial gate structure; forming an amorphized region in the semiconductor fin not covered by the sacrificial gate structure and the gate spacers, wherein the amorphized region has an amorphous-crystalline interface of a first roughness; forming a stressor layer over the amorphized region, wherein the formation of the stressor layer recrystallizes the amorphous-crystalline interface from the first roughness to a second roughness that is less than the first roughness; and subjecting the amorphized region to an annealing process to recrystallize the amorphized region into a crystalline region that includes dislocations.

Description

Technical Field

[0001] This disclosure relates to a method for forming a semiconductor device structure. Background Technology

[0002] In recent years, strain engineering has become a widely used method for improving the performance of transistor devices. Strain engineering introduces stress into the channel region and / or source and drain regions of a transistor device. The stress stretches the lattice of the regions (multiple), causing the interatomic distances to exceed their normal interatomic distances. By stretching the lattice, strain engineering increases the charge carrier mobility, thereby improving device performance. Although existing strain engineering methods are generally sufficient to achieve their intended purpose, they are not entirely satisfactory in all aspects. Summary of the Invention

[0003] In some embodiments, a method of forming a semiconductor element structure includes: forming a sacrificial gate structure over a portion of a semiconductor fin; forming a gate spacer on an opposite side of the sacrificial gate structure; forming an amorphous region in the semiconductor fin not covered by the sacrificial gate structure and the gate spacer, wherein the amorphous region has an amorphous-crystalline interface with a first roughness; forming a stress source layer over the amorphous region, wherein the formation of the stress source layer recrystallizes the amorphous-crystalline interface from the first roughness to a second roughness less than the first roughness; subjecting the amorphous region to an annealing process to recrystallize the amorphous region into a crystalline region, wherein the crystalline region includes a first dislocation.

[0004] In some embodiments, a method for forming a semiconductor device structure includes: forming a semiconductor fin from a substrate having a first region and a second region; forming a first sacrificial gate structure and a second sacrificial gate structure over a portion of the semiconductor fin at the first region and the second region, respectively; forming a plurality of amorphous regions on opposite sides of the first sacrificial gate structure in the semiconductor fin, wherein the amorphous regions have a substantially circular outline; forming a stress source layer over the first sacrificial gate structure, the second sacrificial gate structure, and the amorphous regions, wherein the stress source layer is formed by an atomic layer deposition process for a period of time, causing the amorphous regions to transform from a substantially circular outline to a substantially square outline; annealing the substrate to recrystallize the amorphous regions to form a plurality of crystalline regions having a first dislocation; forming grooves in the crystalline regions; forming source / drain epitaxial features in the grooves, wherein the source / drain epitaxial features form a second dislocation extending from the first dislocation.

[0005] In some embodiments, a method of forming a semiconductor device structure includes: forming a sacrificial gate structure over a portion of a semiconductor fin; forming a gate spacer on an opposite side of the sacrificial gate structure; forming an amorphous region in the semiconductor fin not covered by the sacrificial gate structure and the gate spacer, wherein the amorphous region has an amorphous-crystalline interface with a first roughness; forming an oxide layer on the sacrificial gate structure and the amorphous region; forming a stress source layer on the oxide layer in a reaction chamber by subjecting the oxide layer to a deposition cycle, the deposition cycle including exposing the oxide layer to a silicon-containing precursor to form a silicon monolayer, removing the silicon-containing precursor from the reaction chamber, exposing the silicon monolayer to a plurality of nitrogen free radicals, and removing the nitrogen free radicals from the reaction chamber, wherein the deposition cycle recrystallizes the amorphous-crystalline interface from the first roughness to a second roughness less than the first roughness; subjecting the amorphous region to an annealing process to recrystallize the amorphous region into a crystalline region, wherein the crystalline region includes a dislocation. Attached Figure Description

[0006] The state of this disclosure is in relation to the accompanying documents. Figure 1 The best way to understand this text is by referring to the detailed description below. Note that, according to industry standards, the features are not drawn to scale. In practice, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0007] Figures 1 to 3 This is a perspective view of an intermediate stage in the manufacturing of a semiconductor device structure according to some embodiments;

[0008] Figures 4 to 17 It is taken along line AA according to some embodiments. Figure 3 Cross-sectional side views of the various stages of manufacturing semiconductor device structures.

[0009] [Symbol Explanation]

[0010] 100: Semiconductor Component Structure

[0011] 101A: Area

[0012] 101B: Area

[0013] 102: Substrate

[0014] 108a: Fin

[0015] 108b: Fin

[0016] 112: Insulating materials

[0017] 120: STI area

[0018] 121: Area

[0019] 123: Area

[0020] 128: Sacrificial Gate Stack

[0021] 130: Sacrificial gate dielectric layer

[0022] 131: Quarantine Zone

[0023] 132: Sacrificial gate electrode layer

[0024] 134: Masking Structure

[0025] 135: Patterned mask layer

[0026] 137: Patterned mask layer

[0027] 139: PAI process

[0028] 140: Gate spacer

[0029] 141: Amorphous region

[0030] 143: Centerline

[0031] 145: Oxide layer

[0032] 147: Stress source layer

[0033] 149: Annealing process

[0034] 151: Crystallization Zone

[0035] 152: S / D epitaxial characteristics

[0036] 153a: Misalignment

[0037] 153a': Misalignment

[0038] 153b: Misalignment

[0039] 153b': Misalignment

[0040] 154: S / D epitaxial characteristics

[0041] 155: Pinch Stop Point

[0042] 157: Trench

[0043] 158h: Horizontal buffer zone

[0044] 158v: Vertical buffer

[0045] 159: Patterned mask layer

[0046] 160:CESL

[0047] 162: ILD layer

[0048] 166: Gate dielectric layer

[0049] 168: Gate electrode layer

[0050] 172: Electrical conductivity characteristics

[0051] 170: Silicide layer

[0052] 174: Interconnection Structure

[0053] 177: Replacement of gate structure

[0054] 179: SAC layer

[0055] AA: Line

[0056] D1: Distance

[0057] D2: Amorphization depth

[0058] D3: Depth

[0059] D4: Distance

[0060] X, Y: Direction Detailed Implementation

[0061] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0062] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower part," "above," "above," "on," "top," "upper part," and similar terms are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of elements during use or operation, other than those depicted in the figures. Elements may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted similarly accordingly.

[0063] Figures 1 to 17 Various stages of manufacturing a semiconductor device structure 100 according to various embodiments of this disclosure are illustrated. Of course, for additional embodiments of the method, [further details may be needed]. Figures 1 to 17Additional operations are provided before, during, and after the processes shown, and some of the operations described below can be replaced or eliminated. The order of operations / processes is interchangeable.

[0064] Figures 1 to 3 This is a perspective view of an intermediate stage in the fabrication of a semiconductor device structure 100 according to some embodiments. Figure 1 The invention provides a semiconductor substrate 102. Substrate 102 may be or may include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (using p-type or n-type dopants) or undoped. Substrate 102 may include silicon or another basic semiconductor material such as germanium. In some embodiments, substrate 102 includes a compound semiconductor. The compound semiconductor may include gallium arsenide, silicon carbide, indium arsenide, indium phosphide, another suitable semiconductor material, or a combination thereof.

[0065] Substrate 102 includes a first portion in region 101A and a second portion in region 101B. The first and second portions are continuous substrate 102. Regions 101A and 101B can be separated from each other by a region having a distance D1, which can be any suitable distance depending on the application. For example, isolation region 131 ( Figures 4 to 17An isolation region (not shown) may be formed in the region between region 101A and region 101B. Although region 101A is shown as adjacent to region 101B along the X direction, region 101A may be located in a different region of substrate 102 along the Y direction. Regions 101A and 101B may be of different types and are referred to according to the type of element formed therein. In some embodiments, region 101A is a logic element region for forming logic transistors therein. The logic element region may not include any memory array therein and may or may not be in the peripheral region of an SRAM array. In some embodiments, region 101B is a Static Random Access Memory (SRAM) region in which SRAM cells and transistors are formed. Regions 101A and 101B may include both p-type metal-oxide-semiconductor (PMOS) elements and n-type metal-oxide-semiconductor (NMOS) elements therein. In some embodiments, region 101A includes an NMOS element and region 101B includes a PMOS element. In some embodiments, region 101A may be a multi-fin FinFET region and region 101B may be a single-fin FinFET region, or vice versa. In some embodiments, regions 101A and 101B may be planar element regions including planar transistors. Although the embodiments described in this disclosure are described in the context of FinFET, some implementations of this disclosure can be used in other processes and / or other devices, such as planar FETs, nanostructured channel FETs, horizontal gate all around (HGAA) FETs, vertical gate all around (VGAA) FETs, and other suitable devices.

[0066] Multiple fins 108a, 108b are formed from a substrate 102. The fins 108a, 108b can be formed by patterning a hard mask layer (not shown) on top of the fins 108a, 108b using one or more optical lithography processes (including dual patterning or multi-patterning processes). Typically, dual patterning or multi-patterning processes combine optical lithography and self-alignment processes, allowing for patterns with smaller pitches, for example, than those achievable using a single, direct optical lithography process. For example, in one embodiment, a sacrificial layer (not shown) is formed over the substrate and patterned using an optical lithography process. Spacers (not shown) are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the substrate and form fins. Portions of the fins 108a, 108b can be used as channels in subsequently formed NMOS and PMOS elements in regions 101A, 101B, respectively. Although not shown, a hard masking layer may be formed on top of fins 108a and 108b.

[0067] exist Figure 2In this process, an insulating material 112 is formed between adjacent fins 108a and 108b. The insulating material 112 can be formed first between and above adjacent fins 108a and 108b, so that the fins 108a and 108b are embedded in the insulating material 112. A planarization process, such as chemical-mechanical polishing (CMP), can be performed to expose the tops of the fins 108a and 108b. In some embodiments, the planarization process exposes the top of a hard mask layer (not shown) disposed on the fins 108a and 108b. The insulating material 112 is then recessed such that the top surface of the insulating material 112 is lower than the top surface of the fins 108a and 108b, thereby forming a shallow trench isolation (STI) region 120. The insulating material 112 can be recessed by any suitable removal process, such as dry etching or wet etching, which selectively removes the insulating material 112 without substantially affecting the fins 108a, 108b. The insulating material 112 may include oxygen-containing materials, such as silicon oxide, carbon or nitrogen-doped oxides, or fluorosilicate glass (FSG); nitrogen-containing materials, such as silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN; low-k dielectric materials (e.g., materials with a k-value lower than that of silicon dioxide); or any suitable dielectric material. The insulating material 112 can be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD).

[0068] exist Figure 3In this configuration, one or more sacrificial gate stacks 128 are formed on a portion of fins 108a and 108b. Each sacrificial gate stack 128 may include a sacrificial gate dielectric layer 130, a sacrificial gate electrode layer 132, and a masking structure 134. The sacrificial gate dielectric layer 130 may include one or more dielectric material layers, such as SiO2, SiN, high-k dielectric materials, and / or other suitable dielectric materials. In some embodiments, the sacrificial gate dielectric layer 130 includes a material different from the insulating material 112. The sacrificial gate dielectric layer 130 may be deposited using CVD processes, sub-atmospheric CVD (SACVD) processes, FCVD processes, atomic layer deposition (ALD) processes, PVD processes, or other suitable processes. The sacrificial gate electrode layer 132 may include polysilicon (polysilicon). The masking structure 134 may include an oxygen-containing layer and a nitrogen-containing layer. In some embodiments, the sacrificial gate electrode layer 132 and the mask structure 134 are formed by various processes such as layer deposition, for example, CVD (including LPCVD and PECVD), PVD, ALD, thermal oxidation, electron beam evaporation, or other suitable deposition techniques, or combinations thereof.

[0069] The sacrificial gate stack 128 can be formed by first depositing a sacrificial gate dielectric layer 130, a sacrificial gate electrode layer 132, and a blanket layer of a mask structure 134, followed by patterning and etching processes. For example, the patterning process includes lithography processes (e.g., optical lithography or electron beam lithography), which may further include a photoresist coating layer (e.g., spin-on coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE), wet etching, other etching methods, and / or combinations thereof. By patterning the sacrificial gate stack 128, fins 108a and 108b are partially exposed on opposite sides of the sacrificial gate stack 128. Although Figure 3 Two sacrificial gate stacks 128 are shown, but it should be understood that they are for illustrative purposes only and any number of sacrificial gate stacks 128 can be formed.

[0070] Figures 4 to 17 It is cut along line AA according to some embodiments. Figure 3Cross-sectional side views of various stages of fabricating the semiconductor device structure 100. In various embodiments, one or more isolation regions 131 (only one is shown) are formed in the region between region 101A and region 101B. The isolation region 131 may extend from the top surface of fins 108a, 108b into the fins 108a, 108b. In some embodiments, the isolation region 131 is an STI region, which is formed by etching the substrate 102 during the formation of fins 108a, 108b to form trenches in the fins 108a, 108b along the X direction, and filling the trenches with a dielectric material (e.g., insulating material 112).

[0071] exist Figure 4 In this process, after forming the sacrificial gate structure 128, a gate spacer 140 is conformally formed on the exposed portions of the sacrificial gate structure 128, the fins 108a and 108b, the isolation region 131, and the insulating material 112. The gate spacer 140 can be formed by ALD or any suitable process. The gate spacer 140 can be made of a dielectric material such as silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon carbonitride oxynitride (SiOCN), an air gap, or any combination thereof. The gate spacer 140 can be a two-layer or three-layer structure, including the multilayer dielectric materials discussed herein. The gate spacer 140 can have a total thickness of about 2 nm to about 20 nm, for example, about 4 nm to about 10 nm.

[0072] exist Figure 5 In this process, a portion of the gate spacer 140 at region 101B is removed. A patterned masking layer 135 may first be formed on the sacrificial gate stack 128 and fins 108a, 108b at region 101A, and the sacrificial gate stack 128 and fins 108a, 108b at region 101B may be exposed. The patterned masking layer 135 may be a photoresist or the like. Removal processes, such as anisotropic etching, may be performed on the exposed gate spacer 140 at region 101B. During the anisotropic etching process, most of the gate spacer 140 is removed from multiple horizontal surfaces (such as the top of the sacrificial gate stack 128 at region 101B, the top of the fins 108a, 108b, and the top of the isolation region 131), leaving the gate spacer 140 on vertical surfaces, such as the opposing sidewalls of the sacrificial gate stack 128. The order of processes discussed herein is intended to be illustrative. Depending on the application, a patterned masking layer 135 (i.e., the PMOS region is covered) may first be formed in region 101B, and a removal process may be performed on the exposed gate spacer layer 140 in region 101A.

[0073] exist Figure 6In region 101B, the portions of fins 108a and 108b not covered by the sacrificial gate stack 128 and gate spacer 140 are recessed. These recesses in the fins 108a and 108b can be achieved through an etching process (isotropic or anisotropic etching). The etching process substantially does not affect the masking layer and sacrificial gate stack 128 in region 101A. The etching process can be dry etching, such as RIE, NBE, or similar, or wet etching, such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant. The fins 108a and 108b are recessed such that the tops of the fins 108a and 108b are positioned below the top surface of the insulating material 112. Due to the recesses in the portions of the fins 108a and 108b, trenches are formed in the fins 108a and 108b.

[0074] Next, source / drain (S / D) epitaxial features 152 are formed in the trench. In the case that region 101B is a PMOS region, each S / D epitaxial feature 152 may comprise one or more layers of Si, SiGe, SiGeB, Ge, or III-V group materials (InSb, GaSb, InGaSb). In some embodiments, the S / D epitaxial feature 152 in region 101B is Si. In some embodiments, the S / D epitaxial feature 152 in region 101B is SiGe. Each S / D epitaxial feature 152 may include a P-type dopant, such as boron (B) or other suitable P-type dopant. The S / D epitaxial feature 152 may be formed by any suitable method, such as CVD, CVD epitaxy, MBE, or other suitable methods. The S / D epitaxial feature 152 may be grown vertically and horizontally to form facets that may correspond to the crystal planes of the material used for the substrate 102. S / D epitaxial feature 152 may each have a top surface at a level higher than the top of fins 108a, 108b.

[0075] exist Figure 7 In this process, a patterned masking layer 137, such as a photoresist or the like, is formed on the sacrificial gate stack 128, S / D epitaxial feature 152, and fins 108a and 108b in region 101B, and the sacrificial gate stack 128 and fins 108a and 108b in region 101A are exposed. The patterned masking layer 137 is used to define the subsequent amorphization region 141. Figure 8The exposed gate spacer 140 is then positioned at the location of the exposure and protected from implantation damage. A removal process, such as an anisotropic etching process, is then performed on the exposed gate spacer 140 at region 101A. During the anisotropic etching process, most of the gate spacer 140 is removed from horizontal surfaces, such as the top of the sacrificial gate stack 128, the top of fins 108a and 108b, and the top of the isolation region 131 at region 101A, leaving the gate spacer 140 on vertical surfaces, such as on the opposite sidewalls of the sacrificial gate stack 128.

[0076] exist Figure 8 In this process, a pre-amorphous implantation (PAI) process 139 is performed on the exposed fins 108a and 108b at region 101A that are not covered by the sacrificial gate stack 128 and the gate spacer 140. The PAI process 139 implants ionic species into the fins 108a and 108b, which damages the lattice structure of the fins 108a and 108b and forms an amorphous region 141. The amorphous region 141 is located at positions corresponding to the source and drain regions of a transistor element. In some embodiments, the implanted ionic species may be dispersed within the fins 108a and 108b. The implanted ionic species result in lateral amorphization, which causes the amorphous region 141 to extend into the region shielded by the gate spacer 140. Amorphous region 141 is formed in the source and drain regions (i.e., the regions on opposite sides of the sacrificial gate stack 128 at region 101A) and does not extend beyond the centerline 143 of the sacrificial gate stack 128. Amorphous region 141 has an amorphous depth D2 measured from the top surface of fins 108a, 108b to the bottom of amorphous region 141. The amorphous depth D2 is formed according to design specifications and can be adjusted by controlling the implantation energy, implantation dose, and implantation species. The amorphous depth D2 can also be controlled by the thickness of the gate spacer 140. This is because the gate spacer 140 is used to concentrate the implantation energy of the PAI process 139 away from the centerline 143 of the sacrificial gate stack 128, thereby allowing for a deeper amorphous depth D2. In various embodiments, the depth D2 is in the range of about 10 nm to about 100 nm, for example, about 15 nm to about 35 nm.

[0077] In some embodiments, the PAI process 139 implants exposed fins 108a, 108b with silicon (Si) or germanium (Ge). Other implanted ions heavier than silicon can also be used. For example, in some embodiments, the PAI process 139 utilizes implanted species such as Ar, Xe, BF2, As, In, or the like, or combinations thereof. The PAI process 139 can implant ion species at kinetic energies in the range of about 10 keV to about 60 keV (such as about 20 keV to about 45 keV), and at about 1E10 14 atoms / cm 2approximately 2E10 15 atoms / cm 2 The implantation dosage of ion species is within a range that can vary depending on the implantation temperature. Lower implantation temperatures improve the efficiency of amorphization. In some embodiments, the implantation temperature is in the range of about 10 degrees Celsius to about 85 degrees Celsius. In one exemplary embodiment, a PAI process 139 is performed to implant Ge ion species at a kinetic energy of about 30 keV and an implantation temperature of about 60 degrees Celsius.

[0078] exist Figure 9 In the process, after the amorphous region 141 is formed, the patterned mask layer 137 is removed. The patterned mask layer 137 can be removed using any suitable process such as ashing or etching. An oxide layer 145 is conformally formed on the exposed surface of the semiconductor device structure 100. The oxide layer 145 is deposited on the exposed surfaces of fins 108a, 108b, S / D epitaxial feature 152, and sacrificial gate stack 128 and isolation region 131 at region 101B, and on the amorphous region 141 and sacrificial gate stack 128 at region 101A. The oxide layer 145 serves to provide etch selectivity with respect to the subsequent stress source layer 147, such that the underlying layers (e.g., sacrificial gate stack 128 and S / D epitaxial feature 152) are not damaged during the removal of the stress source layer 147. The oxide layer 145 may include or be made of silicon oxide, silicon oxynitride, or the like, and can be formed by CVD, PECVD, ALD, or any suitable deposition technique. The oxide layer 145 may have a thickness of about 1 angstrom to about 20 angstroms (e.g., about 10 angstroms).

[0079] Next, a stress source layer 147 is formed on the oxide layer 145. The stress source layer 147 is used to provide stress in the amorphous region 141. The stress source layer 147 may include or be composed of silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, oxynitride, oxide, titanium nitride, silicon germanium, boron carbide, and / or any combination thereof. In one embodiment, the stress source layer 147 is silicon nitride, which may or may not contain carbon. In another embodiment, the stress source layer 147 is silicon carbide. In yet another embodiment, the stress source layer 147 is boron carbide. In some embodiments, the stress source layer 147 is a bilayer stack comprising silicon nitride and silicon carbide. In some embodiments, the stress source layer 147 is a bilayer stack comprising silicon carbide and boron carbide. In some embodiments, the stress source layer 147 is a bilayer stack comprising silicon nitride and boron carbide. The stress source layer 147 is formed by inherent tensile stress. Tensile stress affects subsequent recrystallization processes. As will be discussed in more detail below, the tensile stress of the stress source layer 147 imparts stress to the amorphous region 141 during the subsequent annealing process, resulting in a substantially uniform regrowth rate across different crystal planes. Therefore, crystallization defects such as dislocations can form symmetrically and uniformly in both the source and drain regions. This uniform dislocation introduces lattice strain into the subsequently formed S / D epitaxial features at region 101A. Consequently, uniform channel stress is achieved, and the carrier mobility of the NMOS device is improved.

[0080] The stress source layer 147 is a highly conformal layer (e.g., total thickness variation less than about 5%) formed by thermal ALD, PEALD, CVD, PVD, HDPCVD, electroplating, or any suitable deposition technique. The stress source layer 147 has a thickness ranging from about 80 angstroms to about 400 angstroms, for example, from about 100 angstroms to about 200 angstroms. In some embodiments, the oxide layer 145 has a thickness T1, and the stress source layer 147 has a thickness T2, and the ratio of thickness T1 to T2 is about 1:8 to about 1:20, for example, about 1:13. In one embodiment, the deposited stress source layer 147 is a dielectric film having Si-N bonds formed by a plasma-enhanced atomic layer deposition process. An exemplary plasma-enhanced atomic layer deposition process for forming silicon nitride may include the following operations: (a) providing a semiconductor device structure 100 in a reaction chamber; (b) introducing a silicon-containing precursor into the reaction chamber such that a monolayer of silicon or silicon-containing material is adsorbed onto the surface of an oxide layer 145; (c) removing excess silicon-containing precursor and reaction byproducts from the reaction chamber; (d) introducing a nitrogen-containing precursor into the reaction chamber; (e) generating a reactive material from the nitrogen-containing precursor and exposing the adsorbed silicon or silicon-containing material to the reactive material to convert the adsorbed silicon or silicon-containing material into silicon nitride; and (f) removing nitrogen atoms, plasma, or free radicals and reaction byproducts from the reaction chamber. A deposition cycle may include operations (b) through (f) and may be repeated until a silicon nitride layer of a predetermined thickness is formed. A carrier gas (e.g., helium or the like) flow rate may be provided along with the silicon-containing precursor. Removal of precursors and reaction byproducts can be performed by stopping the flow of precursors while allowing the carrier gas or purge gas (e.g., nitrogen or argon) to continue flowing. In some embodiments, excess precursors can be purged by an inert gas (e.g., nitrogen) flowing throughout the deposition cycle. The order of the silicon-containing and nitrogen-containing precursors is expected to be variable, and the deposition cycle can begin with any precursor. Furthermore, silicon-containing and nitrogen-containing precursors can overlap or be combined. For example, silicon-containing and nitrogen-containing precursors can be provided simultaneously in partially or completely overlapping time cycles. The term "time cycle" can be understood to include a predetermined amount of time for introducing reactants into the reaction chamber, and therefore can be of any length.

[0081] Suitable gases for silicon-containing precursors may include, but are not limited to, silanes (SiH4), dichlorosilanes (SiH2Cl2, DCS), trichlorosilanes (SiHCl3, TCS), tetrachlorosilanes (SiCl4, STC), hexachlorosilanes (Si2Cl6), or combinations thereof. Other gases containing Si, N, H, and optionally C in their molecules may also be used. In some embodiments, a nitrogen-containing precursor is introduced into the reaction chamber in an excited state. In some embodiments, the nitrogen-containing precursor may be or may include nitrogen radicals, nitrogen atoms, and / or nitrogen plasma. Suitable gases for nitrogen-containing precursors may include, but are not limited to, nitrogen (N2), ammonia (NH3), hydrazine (N2H4), nitrous oxide (N2O), or similar substances, or combinations thereof. In some embodiments, the nitrogen-containing precursor may continue to flow throughout the deposition process and be activated only intermittently. The reactants may be generated in situ in the reaction chamber by a rare gas (e.g., Ar or He) or upstream of the reaction chamber (e.g., from a remote plasma generator). In some embodiments, the reactants are or include hydrogen plasma, hydrogen radicals, or atomic hydrogen.

[0082] In various embodiments, the flow rate of the silicon-containing precursor to the flow rate of the nitrogen-containing precursor can be in a ratio of about 1:1 to about 1:20, such as about 1:2 to about 1:4, for example, about 1:3. The flow rate of the nitrogen-containing precursor to the flow rate of the purge gas (or inert gas) can be in a ratio of about 1:20 to about 1:400, such as about 1:40 to about 1:200, for example, about 1:50. The flow rate of the silicon-containing precursor can be in the range of about 0.5 to 5 standard liters per minute (SLM). The flow rate of the nitrogen-containing precursor can be in the range of about 2 to 10 SLM. The flow rate of the purge gas can be in the range of about 100 to 400 SLM. During the deposition process, the temperature of the substrate can be maintained in the range of about 350 to 550 degrees Celsius. The pressure in the reaction chamber can be maintained at 1 to 20 Torr. The duration of each deposition cycle can be about 60 seconds to about 120 seconds, for example, about 90 seconds. The cleanup time can be from about 5 seconds to about 15 seconds, for example, about 10 seconds. The supply time of the silicon-containing precursor can be from about 15 seconds to about 40 seconds, for example, about 30 seconds. The supply time of the nitrogen-containing precursor can be from about 10 seconds to about 30 seconds, for example, about 20 seconds. If RF power is applied during the deposition process, the RF power can be from about 50 W to about 300 W, operating at a frequency of 13.56 MHz. The deposited stress source layer 147 has a hydrogen content of about 10 atomic percent or less, such as about 5% or less, for example, from about 1% to about 4%.

[0083] In some embodiments, the stress source layer 147 is formed by an ALD-based process (e.g., PEALD) performed at a temperature of about 550 degrees Celsius or below, such as about 450 degrees Celsius or below, like about 350 degrees Celsius to about 400 degrees Celsius. The lower temperature prevents hydrogen loss from the stress source layer 147, which would otherwise affect the stress to be applied to the crystallization region 151 during subsequent annealing processes. Figure 10 The tensile stress. Specifically, the entire ALD-based process is performed for at least 3 hours or more, for example, at least about 4 hours or more. In one embodiment, the stress source layer 147 is formed by a plasma-enhanced atomic layer deposition process at a temperature of about 400 degrees Celsius for about 4.5 hours. It has been observed that after the PAI process 139, the amorphous region 141 may have a rough, generally circular profile, and the amorphous-crystalline interface is irregular due to the damage caused by the PAI process 139. Figure 8 In one example shown, the amorphous-crystalline interface, such as the interface at region 121, has a first roughness after the PAI process 139. The roughness caused by PAI can lead to inhomogeneous dislocations during subsequent recrystallization processes. Compared to CVD-based processes (e.g., PECVD or CVD), it is advantageous to use an ALD-based process to form the stress source layer 147 for a duration of 4 hours or longer because the stress source layer deposited using a CVD-based deposition process has a faster deposition rate, allowing the deposited stress source layer to form under unstable film stress, and the amorphous-crystalline interface may not have sufficient time to recover to a smooth profile, resulting in the non-desirable silicon being regrown from the rough and inhomogeneous amorphous-crystalline interface in an inhomogeneous manner. Therefore, crystallization defects (e.g., dislocations) form with uneven depths, and in some cases, are even absent. In contrast, the low temperature and long processing time of the ALD-based process ensure that the rough and inhomogeneous amorphous-crystalline interface of the amorphized region 141 is recrystallized or recovered by thermal energy during the formation of the stress source layer 147. Therefore, a smooth amorphous-crystalline interface can be obtained before the subsequent recrystallization process. In some embodiments, after the stress source layer 147 is formed, the amorphized region 141 is transformed into a region with a substantially square profile. Figure 9 In one example shown, the amorphous-crystalline interface (such as the interface at region 123) has a second roughness less than the first roughness. In some embodiments, the second roughness is in a ratio of about 1:8 to about 1:50 to the first roughness, such as about 1:10 to about 1:30, for example, about 1:20. The term “roughness” discussed herein refers to the arithmetic mean of the absolute values ​​of the profile height deviating from the centerline, recorded over the evaluation length. A smooth amorphous-crystalline interface improves the uniformity of dislocations formed in the amorphized region 141.

[0084] Example

[0085] In one exemplary embodiment, the stress source layer 147 is formed on the oxide layer 145 in the reaction chamber using the plasma-enhanced atomic layer deposition process described above. Examples of process conditions are shown below.

[0086] DCS (Standard Liters per Minute, SLM) 3 <![CDATA[NH3(SLM)]]> 6 <![CDATA[N2(SLM)]]> 250 Substrate temperature (°C) 450 RF power (W) 150 (at a frequency of 13.56MHz) Pressure (tug) 10 Duration of each cycle (in seconds) 90 Processing time (hours) 3 Purification time (minutes) 10 DCS supply time (seconds) 30 NH3 supply time (seconds) 20

[0087] exist Figure 10 In this process, after forming a stress source layer 147 on the oxide layer 145, an annealing process 149 is performed on the semiconductor device structure 100. The annealing process 149 causes the amorphous region 141 to recrystallize. The annealing process 149 can be any suitable thermal process, such as rapid thermal annealing (RTA), millisecond thermal annealing (MSA), microsecond thermal annealing (μSA), laser annealing, or other annealing processes. In some embodiments, the annealing process 149 is performed using spike RTA, which heats the semiconductor device structure 100 to an annealing temperature between approximately 900 degrees Celsius and approximately 1100 degrees Celsius for approximately 1 second to approximately 10 seconds. The annealing process 149 may include a preheating phase, which heats the semiconductor device structure 100 at a temperature ranging from approximately 400 degrees Celsius to approximately 620 degrees Celsius for a duration of approximately 20 seconds to approximately 80 seconds. Following annealing process 149, the semiconductor device structure 100 is cooled. As a result of annealing process 151, the amorphous region 141 is recrystallized to form a crystalline region 151 with memory stress obtained from the stress source layer 147. The growth rate on the surface with the (100) plane is generally higher than the growth rate on the surface with the (110) plane. During recrystallization, the stabilizing film stress from the stress source layer 147 slows down the recrystallization rate of the amorphous region with the (100) plane, allowing for a uniform recrystallization rate of the amorphous region 141 on different crystal planes (i.e., the growth rates on the (100) plane and the (110) plane are substantially the same).

[0088] During annealing process 149, dislocations 153a and 153b are formed in crystallized region 151 as amorphous region 141 recrystallizes. Recrystallization begins at the interface between amorphous region 141 and silicon substrate 102. Dislocations 153a and 153b are formed when the recrystallized bottom portion (having crystal face (100)) of amorphous region 141 merges with the recrystallized side portion (having crystal face (110)) of amorphous region 141. Therefore, dislocations 153a and 153b extend along dislocation surfaces inclined in opposite directions. Dislocations 153a and 153b are substantially symmetrical, and the angle between the dislocation planes can be in the range of about 20 degrees to about 65 degrees, for example, about 40 degrees to about 50 degrees. In some embodiments, misalignments 153a, 153b begin to form at a clamping point 155, which is at a depth D3 measured from the top surface of fins 108a, 108b in the crystal region 151. Depth D3 can range from about 5 nm to about 80 nm, for example, from about 20 nm to about 30 nm. The deeper the depth D3, the lower the stress to be generated in the channel region. In some embodiments, misalignments 153a, 153b are formed at a consistent depth D3 in all elements in region 101A. The distance D4 between misalignments 153a, 153b and the adjacent sacrificial gate stack 128 also affects the channel stress. The larger the distance D4, the lower the stress to be generated in the channel region. In some embodiments, distance D4 is less than about 10 nm, such as about 7 nm or below, for example, from about -2 nm to about 5 nm.

[0089] The clamp stop 155 is formed according to design specifications and is a function of the annealing process 149. In some embodiments, the annealing process 149 is performed (e.g., by controlling the temperature of the preheating stage) such that the clamp stop 155 is not formed within the channel region (e.g., the fins 108a, 108b below the sacrificial gate stack 128). In some embodiments, the clamp stop 155 has a horizontal buffer 158h of about 1 nm to about 10 nm (e.g., about 2 nm to about 5 nm) and a vertical buffer 158v of about 1 nm to about 20 nm (e.g., about 3 nm to about 10 nm). In some cases where the isolation region 131 is too close to or in contact with a portion of the crystal region 151, a single dislocation (e.g., 153a) may be formed in the crystal region 151 in contact with the isolation region 131. Figure 10 As shown in the image.

[0090] exist Figure 11 In this process, the stress source layer 147 and the oxide layer 145 are removed. The stress source layer 147 and the oxide layer 145 can be removed by one or more etching processes, which can be dry etching, wet etching, or a combination thereof. Since the crystal region 151 remembers the stress caused by the stress source layer 147, the crystal region 151 retains its stress lattice configuration when the stress source layer 147 is removed.

[0091] exist Figure 12 In this process, a portion of the crystallized region 151 is removed to form a trench 157. A patterned masking layer 159, such as a patterned masking layer 137, can be deposited on the sacrificial gate stack 128, S / D epitaxial feature 152, and fins 108a and 108b at region 101B, while the sacrificial gate stack 128 and the crystallized region 151 at region 101A are exposed. The removal of a portion of the crystallized region 151 can be performed by an etching process, which can be dry etching, wet etching, or a combination thereof. The etching process selectively removes portions of recrystallized silicon in the crystallized region 151, but does not remove the sacrificial gate stack 128 and the gate spacer 140. The trench 157 may have a depth less than D2 ( Figure 8 The depth D5 is in the range of about 2 nm to about 60 nm, for example, about 5 nm to about 20 nm. An etching process can remove portions of the dislocations 153a and 153b. In some embodiments, the removal of a portion of the crystalline region 151 is performed such that a portion of the dislocations 153a and 153b remains in the crystalline region 151. The remaining dislocations 153a and 153b serve as seed crystals for subsequent S / D epitaxial features to be formed in the trench 157. Figure 13 Dislocations are formed in the S / D epitaxial features (154) of the crystal.

[0092] exist Figure 13 In the middle, remove the patterned mask layer 159, and in the groove 157 ( Figure 12Source / drain (S / D) epitaxial features 154 are formed in the trench 157. Alternatively, the S / D epitaxial features 154 may be formed in the trench 157 before the patterned masking layer 159 is removed. The patterned masking layer 159 may be removed using any suitable process such as ashing or etching. In the case that region 101A is an NMOS region, each S / D epitaxial feature 154 may comprise one or more layers of Si, SiP, SiC, SiCP, SiAs, or III-V materials (InP, GaAs, AlAs, InAs, InAlAs, InGaAs). In some embodiments, each S / D epitaxial feature 152 comprises two or more layers of Si, SiP, SiC, SiCP, or III-V materials, and each layer may have a different silicon concentration. Each S / D epitaxial feature 152 may include an N-type dopant, such as phosphorus (P), arsenic (As), or other suitable N-type dopant. The S / D epitaxial feature 152 can be formed by any suitable method, such as CVD, CVD epitaxy, MBE, or other suitable methods. The S / D epitaxial feature 154 may each have a top surface at a quasi-position above the top of the fins 108a, 108b. In some embodiments, the S / D epitaxial feature 154 may have dislocations 153a', 153b' formed, which develop from dislocations 153a', 153b' in the crystal region 151 and extend into the S / D epitaxial feature 154. The dislocations 153a', 153b' apply tensile stress in the S / D epitaxial feature 152, which increases the carrier mobility in the channel region, thereby improving the device performance of the NMOS device at region 101A.

[0093] exist Figure 14In this process, a contact etch stop layer (CESL) 160 is conformally formed on the exposed surface of the semiconductor device structure 100. CESL 160 covers the sidewalls of the sacrificial gate stack 128, the insulating material 112, the S / D epitaxial features 152 and 154, and the isolation region 131. In some embodiments, CESL 160 also contacts a portion of the crystallization region 151. CESL 160 may comprise an oxygen-containing or nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbide, or similar materials or combinations thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, a first interlayer dielectric (ILD) 162 is formed on CESL 160. The material used for the ILD layer 162 may include compounds comprising Si, O, C, and / or H, such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, silicon oxide, or doped silicon oxide such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric materials. The ILD layer 162 may be deposited using a PECVD process or other suitable deposition techniques. In some embodiments, after the formation of the ILD layer 162, the semiconductor device structure 100 may undergo a heat treatment to anneal the ILD layer 162.

[0094] exist Figure 15 In the process, after forming ILD 162, a planarization process such as CMP is performed to expose the sacrificial gate electrode layer 132. Figure 14 The planarization process removes portions of the ILD layer 162 and CESL 160 disposed on the sacrificial gate stack 128. The planarization process may also remove the mask structure 134. Next, the mask structure 134 (if not removed during the CMP process), the sacrificial gate electrode layer 132 ( Figure 14 ), and sacrificial gate dielectric layer 130 ( Figure 14 The sacrificial gate electrode layer 132 and the sacrificial gate dielectric layer 130 are removed. They can be removed by one or more etching processes (such as dry etching, wet etching, or a combination thereof). One or more etching processes selectively remove the sacrificial gate electrode layer 132 and the sacrificial gate dielectric layer 130 without substantially affecting the spacer 140, CESL 160, and ILD layer 162. The removal of the sacrificial gate electrode layer 132 and the sacrificial gate dielectric layer 130 exposes the top portions of the fins 108a and 108b in the channel region.

[0095] exist Figure 16In this process, a replacement gate structure 177 is formed. The replacement gate structure 177 may include a gate dielectric layer 166 and a gate electrode layer 168 formed on a gate dielectric layer 166. The gate dielectric layer 166 is formed and contacts the exposed fins 108a, 108b and the gate spacer 140. The gate dielectric layer 166 may include one or more dielectric layers and may include the same material (multiple types) as the sacrificial gate dielectric layer 130. In some embodiments, the gate dielectric layer 166 may be deposited by one or more ALD processes or other suitable processes. The gate electrode layer 168 may include one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, AlTi, AlTiO, AlTiC, AlTiN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. For the NMOS device in region 101A, the gate electrode layer 168 may be AlTiO, AlTiC, or a combination thereof. For the PMOS device in region 101B, the gate electrode layer 168 may be AlTiO, AlTiC, AlTiN, or a combination thereof. The gate electrode layer 168 may be formed by PVD, CVD, ALD, electroplating, or other suitable methods.

[0096] Optionally, a metal gate etching back (MGEB) process is performed to remove portions of the gate dielectric layer 166 and the gate electrode layer 168. The MGEB process may be a plasma etching process using one or more etchants, such as chlorine-containing gases, bromine-containing gases, and / or fluorine-containing gases. After the MGEB process, the top surface of the gate electrode layer 168 may be lower than the top surface of the gate dielectric layer 166. In some embodiments, portions of the gate spacer 140 are etched back such that the top surface of the gate spacer 140 is higher than the top surfaces of the gate dielectric layer 166 and the gate electrode layer 168. The trenches formed on the gate dielectric layer 166 and the gate electrode layer 168 due to the MGEB process are then filled with a self-aligned contact (SAC) layer 179. The SAC layer 179 may be formed of any dielectric material having an etch selectivity different from that of CESL 160 and serves as an etch stop layer during subsequent trench and via patterning of the metal contacts. Next, a CMP process is performed to remove excess deposits in the SAC layer 179 until the top surface of the ILD layer 162 is exposed.

[0097] exist Figure 17In this process, portions of the ILD layer 162 and CESL 160 disposed on both sides of the replacement gate structure 177 are removed. The removal of portions of the ILD layer 162 and CESL 160 forms contact openings for the exposed S / D epitaxial features 152 and 154, respectively. In some embodiments, the upper portions of the exposed S / D epitaxial features 152 and 154 are removed. Conductive features 172 (i.e., S / D contacts) are then formed in the contact openings above the S / D epitaxial features 152 and 154. Conductive features 172 may include conductive materials such as one or more of Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, and TaN. Conductive features 172 can be formed by any suitable process, such as PVD, CVD, ALD, electroplating, or other suitable methods. A silicide layer 170 may be formed between the respective S / D epitaxial features 152 and 154 and the conductive features 172, such as... Figure 17 As shown in the diagram, silicide layer 170 conductively couples S / D epitaxial features 152 and 154 to conductive feature 172. Silicide layer 170 is a metal or metal alloy silicide, and the metal includes noble metals, refractory metals, rare earth metals, alloys thereof, or combinations thereof. For an n-channel FET, silicide layer 170 may include one or more of TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, YbSi, or combinations thereof. For a p-channel FET, silicide layer 170 may include one or more of NiSi, CoSi, MnSi, WSi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, or combinations thereof. Once the conductive feature 172 is formed, a planarization process such as CMP is performed on the semiconductor device structure 100 until the top surface of the SAC layer 179 (if used) is exposed.

[0098] Interconnect structure 174 is formed above semiconductor element structure 100. Interconnect structure 174 may include one or more interlayer dielectrics and multiple interconnect features (not shown, such as conductive vias and wiring) formed in the respective interlayer dielectrics. Interconnect features may include W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, or combinations thereof or formed therefrom. The interlayer dielectric may be formed of the same material as ILD layer 162. Power rails (not shown) may be electrically connected to S / D epitaxial features 152, 154 via S / D contacts (e.g., conductive feature 172) and interconnect features. Depending on the application and / or conductivity type of the elements in regions 101A, 101B, a positive voltage (VDD) or a negative voltage (VSS) (i.e., ground or zero voltage) may be fed to the power rails.

[0099] The embodiments disclosed herein provide a mechanism for forming dislocations in the source and drain regions between the gate structures of a FinFET device to improve carrier mobility. The dislocations are formed by first amorphizing the source and drain regions, forming a stress source layer over the amorphized source and drain regions, and then recrystallizing the source and drain regions. Specifically, the stress source layer is formed using an ALD-based process, with a process duration sufficient to smooth the rough and non-uniform amorphous / crystalline interface of the amorphized source and drain regions. The smooth amorphous / crystalline interface improves the uniformity of the dislocations to be formed in the amorphized source and drain regions 141 during subsequent annealing processes. The uniform dislocations apply tensile stress in the source and drain regions (and the S / D epitaxial features to be formed therein), which increases carrier mobility in the channel regions, thereby improving device performance.

[0100] In one embodiment, a method for forming a semiconductor device structure is provided. The method includes forming a sacrificial gate structure over a portion of a semiconductor fin; forming a gate spacer on an opposite side of the sacrificial gate structure; forming an amorphous region in the semiconductor fin not covered by the sacrificial gate structure and the gate spacer, wherein the amorphous region has an amorphous-crystalline interface with a first roughness; forming a stress source layer over the amorphous region, wherein the formation of the stress source layer recrystallizes the amorphous-crystalline interface from the first roughness to a second roughness less than the first roughness; and subjecting the amorphous region to an annealing process to recrystallize the amorphous region into a crystalline region, wherein the crystalline region includes a first dislocation. In some embodiments, the second roughness is in a ratio of about 1:10 to 1:30 to the first roughness. In some embodiments, the stress source layer is formed by a plasma-enhanced atomic layer deposition process. In some embodiments, the plasma-enhanced atomic layer deposition process is performed at a temperature of about 400 degrees Celsius for at least 4 hours. In some embodiments, the method further includes forming an oxide layer between the sacrificial gate structure and the stress source layer. In some embodiments, the annealing process includes a preheating stage, heating the amorphous region to a temperature of approximately 400 degrees Celsius to approximately 620 degrees Celsius. In some embodiments, the annealing process is a peak annealing process, heating the amorphous region to a temperature between approximately 900 degrees Celsius and approximately 1100 degrees Celsius. In some embodiments, the method of forming a semiconductor device structure further includes, after subjecting the amorphous region to an annealing process, removing multiple portions of dislocations and crystalline regions to form a trench; and epitaxially forming a source / drain epitaxial feature in the trench, the source / drain epitaxial feature having a second dislocation extending from the first dislocation.

[0101] In another embodiment, a method for forming a semiconductor device structure is provided. The method includes forming semiconductor fins from a substrate having a first region and a second region; forming a first sacrificial gate structure and a second sacrificial gate structure over portions of the semiconductor fins in the first and second regions, respectively; forming an amorphous region in the semiconductor fins on opposite sides of the first sacrificial gate structure, wherein the amorphous region has a substantially circular outline; forming a stress source layer over the first and second sacrificial gate structures and the amorphous region, wherein the stress source layer is formed by an ALD-based process for a period of time, causing the amorphous region to transform from a substantially circular outline to a substantially square outline; annealing the substrate to recrystallize the amorphous region to form a crystalline region with a first dislocation; forming a groove in the crystalline region, and forming source / drain epitaxial features in the groove, wherein the source / drain epitaxial features form a second dislocation extending from the first dislocation. In some embodiments, the atomic layer deposition process is a plasma-enhanced atomic layer deposition process. In some embodiments, the plasma-enhanced atomic layer deposition process is performed for at least 4 hours or longer within a temperature range of about 350 degrees Celsius to about 400 degrees Celsius. In some embodiments, the method of forming the semiconductor device structure further includes removing the stress source layer before forming a trench in the crystallization region. In some embodiments, the method of forming the semiconductor device structure further includes forming a contact etch-stop layer on the source / drain epitaxial feature after forming a source / drain epitaxial feature in the trench, wherein the contact etch-stop layer contacts a portion of the crystallization region. In some embodiments, the method of forming the semiconductor device structure further includes forming an oxide layer between the sacrificial gate structure and the stress source layer. In some embodiments, the oxide layer has a first thickness and the stress source layer has a second thickness, and the first thickness to the second thickness is in a ratio of about 1:8 to about 1:20. In some embodiments, the stress source layer is made of silicon carbide. In some embodiments, the stress source layer is made of boron carbide.

[0102] In yet another embodiment, a method for forming a semiconductor device structure is provided. The method includes forming a sacrificial gate structure over a portion of a semiconductor fin; forming a gate spacer on an opposite side of the sacrificial gate structure; forming an amorphous region in the semiconductor fin not covered by the sacrificial gate structure and the gate spacer, wherein the amorphous region has an amorphous-crystalline interface with a first roughness; forming an oxide layer on the sacrificial gate structure and the amorphous region; forming a stress source layer on the oxide layer in a reaction chamber by subjecting the oxide layer to a deposition cycle, the deposition cycle including exposing the oxide layer to a silicon-containing precursor to form a silicon monolayer, removing the silicon-containing precursor from the reaction chamber, exposing the silicon monolayer to nitrogen radicals, and removing nitrogen radicals from the reaction chamber, wherein the deposition cycle recrystallizes the amorphous-crystalline interface from the first roughness to a second roughness less than the first roughness; and subjecting the amorphous region to an annealing process to recrystallize the amorphous region into a crystalline region, wherein the crystalline region includes dislocations. In some embodiments, the second roughness is in a ratio of about 1:10 to about 1:30 to the first roughness. In some implementations, the deposition cycle is performed at a temperature of about 400 degrees Celsius for at least 4 hours or longer.

[0103] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor device structure, characterized in that, Include: A sacrificial gate structure is formed over a portion of a semiconductor fin; A gate spacer is formed on the opposite side of the sacrificial gate structure; An amorphized region is formed in the semiconductor fin not covered by the sacrificial gate structure and the gate spacer, wherein the amorphized region has an amorphous-crystalline interface with a first roughness; A stress source layer is formed over the amorphous region by an atomic layer deposition process, wherein the formation of the stress source layer recrystallizes the amorphous-crystalline interface from the first roughness to a second roughness that is smaller than the first roughness. as well as The amorphous region is subjected to an annealing process to recrystallize the amorphous region into a crystalline region, and the crystalline region includes a first dislocation.

2. The method according to claim 1, characterized in that, The second roughness is in a ratio of 1:10 to 1:30 to the first roughness.

3. The method according to claim 2, characterized in that, The stress source layer is formed using a plasma-enhanced atomic layer deposition process.

4. The method according to claim 3, characterized in that, The plasma-enhanced atomic layer deposition process is performed at a temperature of 400 degrees Celsius for at least 4 hours.

5. The method according to claim 1, characterized in that, Further includes: An oxide layer is formed between the sacrificial gate structure and the stress source layer.

6. The method according to claim 1, characterized in that, The annealing process includes a preheating stage, in which the amorphized region is heated to a temperature of 400 to 620 degrees Celsius.

7. The method according to claim 6, characterized in that, The annealing process involves heating the amorphized region to a peak temperature between 900°C and 1100°C for annealing.

8. The method according to claim 1, characterized in that, Further includes: After subjecting the amorphous region to an annealing process, the dislocation and multiple portions of the crystalline region are removed to form a trench; and A source / drain epitaxial feature is formed in the trench, and the source / drain epitaxial feature has a second dislocation extending from the first dislocation.

9. A method for forming a semiconductor device structure, characterized in that, Include: A semiconductor fin is formed from a substrate having a first region and a second region; A first sacrificial gate structure and a second sacrificial gate structure are respectively formed above a portion of the semiconductor fin in the first region and the second region; In the semiconductor fin, a plurality of amorphous regions are formed on opposite sides of the first sacrificial gate structure, wherein the plurality of amorphous regions have a generally circular outline; A stress source layer is formed above the first sacrificial gate structure, the second sacrificial gate structure, and the amorphous region. The stress source layer is formed by an atomic layer deposition process that lasts for a period of time, causing the amorphous region to change from a basic circular profile to a basic square profile, and the roughness of the basic square profile is less than the roughness of the basic circular profile. Annealing the substrate causes the amorphous region to recrystallize, thereby forming a plurality of crystalline regions with a first dislocation; A groove is formed in the plurality of crystallization regions; and A source / drain epitaxial feature is formed in the groove, wherein the source / drain epitaxial feature has a second dislocation extending from the first dislocation.

10. The method according to claim 9, characterized in that, This atomic layer deposition process is a plasma-enhanced atomic layer deposition process.

11. The method according to claim 10, characterized in that, The plasma-enhanced atomic layer deposition process is performed for at least 4 hours or longer within a temperature range of 350°C to 400°C.

12. The method according to claim 9, characterized in that, Further includes: The stress source layer is removed before a groove is formed in the plurality of crystallization regions.

13. The method according to claim 12, characterized in that, Further includes: After a source / drain epitaxial feature is formed in the groove, a contact etch stop layer is formed on the source / drain epitaxial feature, wherein the contact etch stop layer contacts a portion of the plurality of crystal regions.

14. The method according to claim 9, characterized in that, Further includes: An oxide layer is formed between the sacrificial gate structure and the stress source layer.

15. The method according to claim 14, characterized in that, The oxide layer has a first thickness and the stress source layer has a second thickness, and the first thickness and the second thickness are in a ratio of 1:8 to 1:

20.

16. The method according to claim 9, characterized in that, The stress source layer is made of silicon carbide.

17. The method according to claim 9, characterized in that, The stress source layer is made of boron carbide.

18. A method for forming a semiconductor device structure, characterized in that, Include: A sacrificial gate structure is formed over a portion of a semiconductor fin; A gate spacer is formed on the opposite side of the sacrificial gate structure; An amorphized region is formed in the semiconductor fin not covered by the sacrificial gate structure and the gate spacer, wherein the amorphized region has an amorphous-crystalline interface with a first roughness; An oxide layer is formed on the sacrificial gate structure and the amorphous region; By subjecting the oxide layer to a deposition cycle based on atomic layer deposition, a stress source layer is formed on the oxide layer in a reaction chamber. The deposition cycle includes exposing the oxide layer to a silicon-containing precursor to form a silicon monolayer, removing the silicon-containing precursor from the reaction chamber, exposing the silicon monolayer to a plurality of nitrogen free radicals, and removing the plurality of nitrogen free radicals from the reaction chamber. The deposition cycle recrystallizes the amorphous-crystalline interface from the first roughness to a second roughness smaller than the first roughness. as well as The amorphous region is subjected to an annealing process to recrystallize the amorphous region into a crystalline region, and the crystalline region contains a dislocation.

19. The method according to claim 18, characterized in that, The second roughness is in a ratio of 1:10 to 1:30 to the first roughness.

20. The method according to claim 18, characterized in that, The deposition cycle is performed at a temperature of 400 degrees Celsius for at least 4 hours or longer.

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