Variable capacitance diode and method of manufacturing the same

Abstract

The present disclosure provides a varactor tube and a preparation method thereof. In some embodiments of the present disclosure, the varactor tube comprises a substrate, a channel layer, a shorted source-drain electrode, a gate dielectric layer and a gate electrode, the channel layer is a carbon nanotube film, the gate dielectric layer is made of a ferroelectric material, and the substrate, the channel layer, the source-drain electrode, the gate dielectric layer and the gate electrode form a metal-ferroelectric-semiconductor (MFS) structure. The varactor tube provided by the present disclosure can realize bidirectional voltage operation, obtain a varactor ratio greater than 5, maintain a high Q value and operating frequency, and meet the requirements of high integration and large bandwidth radio frequency circuits.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a varactor transistor and its fabrication method. Background Technology

[0002] The MOS varactor, implemented using a metal-oxide-semiconductor (MOS) structure, is a commonly used adjustable passive component in analog integrated circuits. By changing the voltage applied to it, it can exhibit different capacitance values ​​to adapt to the needs of circuit parameter adjustment. It can be widely used in frequency modulation and tuning circuits such as voltage-controlled oscillators (VCOs) and is key to realizing radio frequency CMOS integrated transceivers.

[0003] The performance indicators of a varactor diode mainly include the capacitance adjustment range, i.e., the capacitance ratio (C-ratio), the quality factor (Q value), and the voltage operating range.

[0004] The varactor ratio is determined by the gate dielectric capacitance, semiconductor capacitance, and parasitic capacitance. Traditional varactors have the maximum capacitance (approximately the gate dielectric capacitance) in the channel material accumulation region and strong inversion region, and the minimum capacitance (approximately the parallel sum of the semiconductor depletion layer capacitance, quantum capacitance, and parasitic capacitance) in the depletion region, exhibiting bidirectional voltage operation. However, they suffer from low varactor ratios and asymmetrical capacitance changes. While improved inversion and accumulation varactors can achieve larger varactor ratios, they cannot achieve bidirectional voltage operation. Therefore, minimizing the semiconductor capacitance and increasing the gate dielectric capacitance is beneficial for improving the varactor's varactor ratio.

[0005] The quality factor of a varactor mainly reflects circuit losses. The higher the quality factor, the lower the resistance loss. Maximizing channel mobility and reducing channel contact resistance are beneficial to improving the quality factor of the varactor.

[0006] Currently, there is a need for a varactor diode with a high varactor ratio, a high quality factor, and the ability to operate under bidirectional voltage to meet the requirements of radio frequency CMOS integrated circuits. Summary of the Invention

[0007] To solve at least one of the above-mentioned technical problems, this disclosure provides a variable capacity tube and a method for preparing the same.

[0008] The first aspect of this disclosure provides a varactor comprising: a substrate, a channel layer, shorted source / drain electrodes, a gate dielectric layer, and a gate, wherein the channel layer is a carbon nanotube thin film, the gate dielectric layer is made of a ferroelectric material, and the substrate, channel layer, source / drain electrodes, gate dielectric layer, and gate form a metal-ferroelectric-semiconductor (MFS) structure.

[0009] In some possible implementations of the first aspect of this disclosure, the carbon nanotube film is a semiconductor carbon nanotube array film with a density greater than or equal to a first predetermined density.

[0010] In some possible implementations of the first aspect of this disclosure, the first predetermined density is 200 roots per micrometer.

[0011] In some possible implementations of the first aspect of this disclosure, the carbon nanotube film is a parallel-arranged carbon nanotube array film or a disordered carbon nanotube network film.

[0012] In some possible implementations of the first aspect of this disclosure, the gate dielectric layer is made of a ferroelectric material with a high dielectric constant.

[0013] In some possible implementations of the first aspect of this disclosure, the source and drain electrodes are made of a metallic material whose work function is located near the center of the carbon nanotube band gap.

[0014] In some possible implementations of the first aspect of this disclosure, the gate is a planar gate structure, a fin gate structure, or a T-gate structure.

[0015] In some possible implementations of the first aspect of this disclosure, the MFS structure is a top-gate structure or a bottom-gate structure.

[0016] A second aspect of this disclosure provides a method for preparing a variable capacitance tube, comprising:

[0017] Provide substrate;

[0018] A carbon nanotube array thin film is prepared and patterned on the substrate to form a channel layer;

[0019] Short-circuited source and drain electrodes are formed on the channel layer;

[0020] A ferroelectric material is used to form a gate dielectric layer on the channel layer;

[0021] A gate electrode is formed on the gate dielectric layer.

[0022] A third aspect of this disclosure provides a method for preparing a variable capacitance tube, comprising:

[0023] Provide substrate;

[0024] A gate is formed on the substrate;

[0025] A ferroelectric material is used to form a gate dielectric layer on the substrate, and the gate dielectric layer covers the gate.

[0026] A carbon nanotube array thin film is fabricated and patterned on the gate dielectric layer to form a channel layer;

[0027] Short-circuited source and drain electrodes are formed on the channel layer.

[0028] The varactor provided in this disclosure adopts an MFS structure with carbon nanotubes as the channel material and ferroelectric materials as the gate dielectric. It can achieve a capacitance adjustment range of more than 5 under both positive and negative voltages. That is, the varactor provided in this disclosure can achieve a varactor ratio of more than 5 while achieving bidirectional voltage operation, and maintain a high Q value and operating frequency, thereby meeting the requirements of high-integration and high-bandwidth RF circuits and effectively improving the operating bandwidth and integration of RF CMOS integrated circuits. Attached Figure Description

[0029] The accompanying drawings illustrate exemplary embodiments of the present disclosure and, together with the description thereof, serve to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification.

[0030] Figure 1A and Figure 1B This is a schematic diagram of the variable capacity tube structure of the top grid structure according to some embodiments of this disclosure.

[0031] Figure 2 This is a schematic diagram of a variable capacity tube structure with a bottom grid structure according to some embodiments of the present disclosure.

[0032] Figure 3 This is a device scanning schematic diagram of a varactor according to some embodiments of the present disclosure.

[0033] Figure 4 This is a schematic diagram of the simulated CV curve of a variable capacitance tube according to some embodiments of this disclosure.

[0034] Figure 5 This is a schematic flowchart of a method for preparing a variable capacitance tube according to some embodiments of the present disclosure.

[0035] Figure 6A and Figure 6B This is a schematic diagram of the device structure after a carbon nanoarray thin film is prepared during the fabrication process of the variable container according to some embodiments of this disclosure.

[0036] Figure 7A and Figure 7B This is a schematic diagram of the structure after the channel layer is formed during the fabrication process of the variable container according to some embodiments of this disclosure.

[0037] Figure 8A and Figure 8B This is a schematic diagram of the structure after the source and drain electrodes are formed during the fabrication process of the varactor tube according to some embodiments of this disclosure.

[0038] Figure 9A and Figure 9BThis is a schematic diagram of the structure after the gate dielectric layer is formed during the fabrication process of the variable capacitance tube according to some embodiments of this disclosure.

[0039] Figure 10 This is a schematic flowchart of a method for preparing a variable capacitance tube according to other embodiments of the present disclosure.

[0040] Figure 11A and Figure 11B This is a schematic diagram of the structure after the bottom gate electrode is formed during the fabrication process of the varactor tube according to some embodiments of this disclosure.

[0041] Figure 12A and Figure 12B This is a schematic diagram of the structure after the gate dielectric layer is formed during the fabrication process of the variable capacitance tube according to some embodiments of this disclosure.

[0042] Figure 13A and Figure 13B This is a schematic diagram of the structure after the channel layer is formed during the fabrication process of the variable capacity tube according to some embodiments of this disclosure.

[0043] Figure 14A and Figure 14B This is a schematic diagram of the structure of a varactor obtained after forming short-circuited source and drain electrodes during the fabrication process according to some embodiments of this disclosure.

[0044] Explanation of reference numerals in the attached figures

[0045] 100 Varactor tube with top grid structure

[0046] 200 Varactor tube with bottom grid structure

[0047] 101 substrate

[0048] 102 Channel Layer

[0049] 103 Source / Drain Electrodes

[0050] 104 Gate dielectric layer

[0051] 105 gate Detailed Implementation

[0052] The present disclosure will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the present disclosure are shown in the accompanying drawings.

[0053] It should be noted that, where there is no conflict, the embodiments and features described in this disclosure can be combined with each other. The technical solutions of this disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0054] Unless otherwise stated, the exemplary implementations / embodiments shown are to be understood as providing exemplary features of various details that provide ways in which the technical concepts of this disclosure can be implemented in practice. Therefore, unless otherwise stated, the features of various implementations / embodiments may be additionally combined, separated, interchanged and / or rearranged without departing from the technical concepts of this disclosure.

[0055] The use of crosshairs and / or shading in the accompanying drawings is generally used to clarify the boundaries between adjacent components. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, proportions, commonalities between the illustrated components, or any other characteristics, properties, etc., of the components. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of components may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, a specific process sequence may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Furthermore, the same reference numerals denote the same components.

[0056] When a component is referred to as being "on" or "above" another component, "connected to," or "joined to" another component, the component may be directly on, directly connected to, or directly joined to the other component, or there may be intermediate components. However, when a component is referred to as being "directly on" another component, "directly connected to," or "directly joined to" another component, there are no intermediate components. Therefore, the term "connection" can refer to a physical connection, an electrical connection, etc., and may or may not have intermediate components.

[0057] For descriptive purposes, this disclosure may use spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side (e.g., in a “sidewall”)” to describe the relationship between one component and another component as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are also intended to encompass different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, a component described as “below” or “under” another component or feature would subsequently be positioned “above” said other component or feature. Thus, the exemplary term “below” can encompass both “above” and “below” orientations. Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), thus interpreting the spatial relative descriptive terms used herein accordingly.

[0058] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “the” are intended to include the plural forms as well. Furthermore, when the terms “comprising” and / or “including” and variations thereof are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, parts, components, and / or groups thereof, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, parts, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than as terms of degree, thus explaining the inherent biases in measurements, calculated values, and / or provided values ​​that would be recognized by one of ordinary skill in the art.

[0059] Table 1 below illustrates the characteristics and problems of varactor diodes in related technologies. As can be seen from Table 1, traditional silicon-based varactor diodes are currently limited by the depletion layer capacitance, making it difficult to achieve a varactor ratio greater than 2. Even by reducing the channel layer thickness and using silicon-on-insulator (SOI) technology, it is difficult to achieve a varactor ratio greater than 5. Furthermore, their unidirectional operating voltage range is insufficient to meet the demands of subsequent higher bandwidth and higher integration RF circuits. In other words, varactor diodes in related technologies not only suffer from low varactor ratios and low quality factors, but also cannot achieve bidirectional operation.

[0060] Table 1

[0061]

[0062] Considering the quasi-one-dimensional structure of carbon nanotubes, their depletion region capacitance is negligible, while their quantum capacitance is close to zero in the depletion region and relatively large in the accumulation region. Ferroelectric materials, compared to traditional oxide gate dielectrics, possess higher dielectric constants (up to 40 or higher) and symmetrical dielectric constant characteristics under both positive and negative voltages. Therefore, this disclosure combines the characteristics of these two materials to address the difficulty in improving the capacitance ratio and quality factor of varactor tubes.

[0063] The specific embodiments of this disclosure will be described in detail below.

[0064] In some embodiments of this disclosure, a varactor is provided, which includes a substrate, a channel layer, source / drain electrodes, a gate dielectric layer, and a gate. The channel layer is a carbon nanotube thin film, and the gate dielectric layer is made of a ferroelectric material. The substrate, channel layer, source / drain electrodes, gate dielectric layer, and gate form a metal-ferroelectric-semiconductor (MFS) structure.

[0065] In some embodiments of this disclosure, the MFS structure of the variable capacitance tube can be a top grid structure or a bottom grid structure. Figure 1A and Figure 1B A schematic diagram of the structure of the variable capacity tube 100 with top grid structure is shown. Figure 2 A schematic diagram of the structure of the variable capacitance tube 200 with a bottom grid structure is shown. Figure 3 A device scan schematic of a top-gate structured varactor 100 is shown.

[0066] like Figure 1A and Figure 1B As shown, in the varactor 100, the channel layer 102 is formed on the substrate 101, the source and drain electrodes 103 are formed on the channel layer 102, the gate dielectric layer 104 is formed on the channel layer 102 and located in the channel region surrounded by the source and drain electrodes 103, and the gate 105 is formed on the gate dielectric layer 104.

[0067] like Figure 2 As shown, in the varactor 200, the gate 105 is formed on the substrate 101, the gate dielectric layer 104 is formed on the substrate 101 and covers the gate 105, the channel layer 102 is formed on the gate dielectric layer 104, and the source drain electrode 103 is formed on the channel layer 102. The source drain electrode 103 partially covers the surface of the channel layer 120 and partially covers the surface of the gate dielectric layer 104.

[0068] In some embodiments, the carbon nanotube film used in the channel layer 102 can be a semiconducting carbon nanotube array film. Preferably, the carbon nanotube film used in the channel layer 102 can be a high-density carbon nanotube array film. For example, the density of the carbon nanotube film used in the channel layer 102 can be greater than or equal to a first predetermined density, which can be 200 nanotubes per micrometer or other values. The value of the first predetermined density can be flexibly selected as needed in specific applications. Because bipolar contacts have a certain height of Schottky barrier, the contact resistance of a single carbon nanotube is relatively large, resulting in a decrease in the quality factor of the varactor. Therefore, embodiments of this disclosure preferably use a high-density array carbon nanotube film as the channel material, reducing the total contact resistance through the parallel connection of multiple carbon nanotubes to ensure that the varactor has a high quality factor and operating speed.

[0069] Carbon nanotubes exhibit high carrier mobility, ranging from 1000 to 10000 cm⁻¹. -2 V -1 s -1Therefore, its channel resistance is extremely low. In some embodiments of this disclosure, the carbon nanotube array density of the channel layer 102 can be adjusted to 200-400 nanotubes per micrometer. This reduces the bipolar contact resistance, enabling the varactor to achieve a total parasitic resistance of less than 200 ohms per micrometer. Therefore, the varactor can achieve a quality factor of 1@500GHz (equivalent to 5@100GHz) in multi-finger structure RF devices, thus meeting the operating requirements of the terahertz band.

[0070] In practical applications, by adjusting the array density of carbon nanotubes in the channel layer 102, the voltage operating range of the varactor can be freely adjusted within ±10V. In some embodiments, the carbon nanotube film used in the channel layer 102 can be a high-density parallel-arranged carbon nanotube array film or a high-density disordered carbon nanotube network film. Because these carbon nanotube films possess high mobility and a wide range of quantum capacitance variations, they are more conducive to improving the voltage operating range of the varactor.

[0071] Considering that varactors are usually two-terminal devices, the embodiments of this disclosure adopt a short-circuited source-drain electrode 103, which forms a single electrode by short-circuiting the source-drain electrode. In this way, a two-terminal structure of gate, gate dielectric, and source-drain electrode can be formed.

[0072] In some embodiments, the source / drain electrodes 103 can be made of a metal material, such as titanium, whose work function is located near the center of the carbon nanotube band gap. Since carbon nanotubes with bipolar contact have a symmetrical bipolar capacitance-voltage response when titanium or other metals with work functions located around the center of the carbon nanotube band gap are used as source / drain electrodes, combined with the bidirectional operating characteristics described above, the varactor transistor of this disclosure embodiment can achieve a perfectly symmetrical bidirectional operating voltage range based on a zero-voltage point.

[0073] In some embodiments, the gate dielectric layer 104 can be made of a ferroelectric material with a high dielectric constant. For example, the ferroelectric material used in the gate dielectric layer can be, but is not limited to, barium titanate, potassium dihydrogen phosphate, etc. Since the dielectric constant of the gate dielectric is symmetrical about the zero voltage point and increases with the increase of voltage, the varactor ratio of the varactor tube can be further improved when operating under bidirectional voltage.

[0074] Considering that ferroelectric materials undergo polarization reversal and dynamic polarization response under an external electric field, their capacitance-voltage response is symmetrical and has a certain hysteresis. Therefore, in some embodiments, the gate dielectric layer 104 can preferably be made of a ferroelectric material with small hysteresis to avoid capacitance stability problems that may be caused by ferroelectric hysteresis.

[0075] In addition, when the operating voltage changes direction (from positive voltage to negative voltage or from negative voltage to positive voltage), the voltage can be pre-applied to the maximum operating voltage (e.g., +10V or -10V) to achieve polarization reversal of the ferroelectric material, and then the voltage can be applied to the actual operating voltage. This avoids the capacitance stability problem that may be caused by ferroelectric hysteresis and achieves stable operation of the device.

[0076] In some implementations, gate 105 can employ a gate structure commonly used in digital metal-oxide-semiconductor field-effect transistors (MOSFETs) and / or radio frequency MOSFETs. For example, the gate can be, but is not limited to, a planar gate structure, a fin gate structure, or a T-gate structure. For instance, in the example of Figure 1, gate 105 employs a T-gate structure. This further reduces the gate resistance of the varactor, thereby improving the varactor's capacitance ratio and quality factor.

[0077] The varactor provided in this embodiment uses a semiconducting carbon nanotube array thin film as the channel material. The quantum capacitance of the carbon nanotubes is modulated by the gate voltage. Applying a positive or negative voltage to the gate 105 can adjust the quantum capacitance to a larger value, while applying zero voltage can adjust it to a minimum value. Simultaneously, a ferroelectric material is used as the gate dielectric material. The electric field applied by the gate voltage to the ferroelectric material causes polarization reversal and a strong polarization response. The dielectric constant of the ferroelectric material is small at zero voltage and increases directionally to a larger value with increasing voltage. Since the quantum capacitance of the carbon nanotubes is close to zero in the depletion region and far exceeds the gate dielectric capacitance in the accumulation region, the varactor ratio is almost entirely determined by the ferroelectric material capacitance (i.e., the maximum capacitance value) and the parasitic capacitance (i.e., the minimum capacitance value). Therefore, by combining the bidirectional capacitance modulation characteristics of the carbon nanotube channel and the ferroelectric material gate dielectric, as well as the large capacitance modulation range, the varactor of this embodiment can achieve bidirectional operation while possessing an ultra-high varactor ratio.

[0078] Figure 4 A schematic diagram of the simulated capacitance variation curve (simulated CV curve) of the varactor diode according to an embodiment of this disclosure is shown. Figure 4 As can be seen, the variable capacitance tube in this embodiment satisfies the following relationship:

[0079] C max =2.7857uF / cm 2 C min_V＝0 =0.0425uF / cm 2

[0080] C-ratio = C max / C min ≈69

[0081] Among them, C max C represents the maximum capacitance of the varactor diode. min_V＝0 C represents the minimum capacitance of the varactor tube, and C-ratio represents the varactor tube's capacitance ratio.

[0082] pass Figure 4 As can be seen, the variable capacitance tube provided in this embodiment has a variable capacitance ratio much greater than 5, and the Q value of the variable capacitance tube is positively correlated with the variable capacitance ratio. Therefore, Figure 4 The CV curve also demonstrates that the varactor tube provided in this embodiment has an extremely high quality factor.

[0083] In summary, the varactor tube of this embodiment can not only operate under bidirectional voltage, but also has an ultra-high varactor ratio of greater than 5 and a high Q value.

[0084] Figure 5 Exemplary methods for preparing the variable capacitance tube 100 in some embodiments of this disclosure are shown. For example... Figure 5 As shown, the preparation method of the variable capacitance tube may include the following steps:

[0085] Step S52, provide substrate 102;

[0086] For example, the substrate size can be a standard 4-inch, 8-inch, or 12-inch wafer. For example, the substrate can be a silicon wafer covered with silicon dioxide or other surface-insulating materials.

[0087] Step S54: A carbon nanotube array thin film is prepared and patterned on the substrate 102 to form a channel layer 104;

[0088] like Figure 6A and Figure 6B As shown, a semiconductor high-density carbon nanotube array film can be prepared on substrate 102. The carbon nanotube array film uniformly covers the entire substrate surface to form a semiconductor active region. The purity of the semiconductor carbon nanotubes in the carbon nanotube array film is preferably greater than 99.9999%, and the density can be greater than 200 nanotubes / μm.

[0089] like Figure 7A and 7B As shown, photolithography and etching techniques can be used to pattern the active region covering the semiconductor to form the channel layer 104.

[0090] In practical applications, the width of the channel region of the channel layer 102 can be 5μm to 10μm. Depending on the operating requirements of the varactor, the length of the channel layer 102 can be around 100nm to 10μm.

[0091] Step S56: Short-circuited source / drain electrodes 103 are formed on the channel layer 102;

[0092] In some implementations, the shorted source / drain electrodes 103 can be formed by thin film growth, photolithography, and etching.

[0093] A portion of the source / drain electrode 103 covers the channel layer 102, and another portion covers the substrate 101, with the portions of the source / drain electrode 103 connected together to form a shorted structure. For example, as... Figure 8A and Figure 8B As shown, the source / drain electrode 103 may include three parts, the upper ends of which are connected together to form a short-circuited structure. The upper and lower ends of the part located in the central region of the channel layer 102 extend to the substrate 101, while the middle section covers the channel layer 102. The upper and lower ends of the two parts located at the edge of the channel layer 103 also extend to the substrate 101, while the middle section partially covers the channel layer 102 and partially covers the substrate 101.

[0094] In specific applications, the width of the source / drain electrode 103 can be 5μm to 10μm, matching the size of its corresponding channel region.

[0095] Step S58: A gate dielectric layer 104 is formed on the channel layer 102 using a ferroelectric material;

[0096] In some implementations, the ferroelectric material gate dielectric layer can be prepared by atomic layer deposition or other methods.

[0097] like Figure 9A and Figure 9B As shown, the gate dielectric layer 104 is formed on the channel layer 102 and located in the channel region between the source and drain electrodes 103. Both ends of the gate dielectric layer 104 can extend out of the channel layer 102 and cover the substrate 101.

[0098] In specific applications, the thickness of the gate dielectric layer 104 can be set according to the operating requirements of the varactor. For example, the thickness of the gate dielectric layer 104 can be between a few nanometers and tens of nanometers.

[0099] In step S510, a gate 105 is formed on the gate dielectric layer 104, thereby obtaining... Figure 1A and Figure 1B The variable capacity tube 100 is shown.

[0100] In some implementations, the gate 105 can be formed by thin film growth, photolithography, and etching.

[0101] Taking Figure 1 as an example, the gate can adopt a T-gate structure. The size of the gate 105 varies with the channel length and the source / drain electrode width. Taking a variable capacitor with a channel length of 100 nm as an example, the gate pin length of the gate 105 can be 50 nm, the gate cap length can be 300 nm, the gate height can be 300 nm, and the gate width is the same as the width of the source / drain electrode.

[0102] Figure 10 Exemplary methods for preparing the variable capacitance tube 200 in some embodiments of this disclosure are shown, such as Figure 10 As shown, the method for preparing the variable capacitance tube 200 may include:

[0103] Step S120, providing substrate 101;

[0104] Step S140: Form a gate 105 on the substrate 101;

[0105] For example, a bottom gate electrode (i.e., gate 105) can be formed on a substrate using thin film growth, photolithography, and etching, resulting in a device structure as follows: Figure 11A Figure 11B As shown.

[0106] Step S160: A gate dielectric layer 104 is formed on the substrate 101 using a ferroelectric material, and the gate dielectric layer 104 covers the gate.

[0107] For example, the gate dielectric layer 104 of the ferroelectric material can be prepared by atomic layer deposition or other methods, and the gate dielectric layer 104 can completely cover the gate 105. The device structure at this time is as follows: Figure 12A and Figure 12B As shown.

[0108] Step S180: A carbon nanotube array film is prepared and patterned on the gate dielectric layer 104 to form the channel layer 102;

[0109] The specific implementation details of step S180 are the same as those of step S54 above, and will not be repeated here. The device structure obtained in step S180 is as follows: Figure 13A and Figure 13B As shown.

[0110] In step S110, short-circuited source and drain electrodes 103 are formed on the channel layer 102 to obtain the varactor 200.

[0111] For example, the shorted source / drain electrodes 103 can be formed using thin film growth, photolithography, and etching. The specific implementation is the same as in step S56 above, and will not be repeated here. The device structure of the varactor 200 obtained in step S110 is as follows... Figure 14A and Figure 14B As shown.

[0112] Step S130: A connection through-hole for a local bottom grid is formed on the variable capacitance tube 200.

[0113] For example, photolithography, etching, and thin film growth can be used to form the interconnect vias of the local bottom gate.

[0114] It should be noted that the preparation method of the variable capacitance tube in this embodiment is not limited to the two methods described above, and the specific steps in the preparation process of the variable capacitance tube are not limited to the above implementation methods.

[0115] In the description of this specification, the references to terms such as "one embodiment / mode," "some embodiments / modes," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment / mode or example is included in at least one embodiment / mode or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments / modes or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments / modes or examples described in this specification, as well as the features of different embodiments / modes or examples.

[0116] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0117] Those skilled in the art should understand that the above embodiments are merely for illustrating the present disclosure and are not intended to limit the scope of the disclosure. Those skilled in the art can make other changes or modifications based on the above disclosure, and these changes or modifications still fall within the scope of the present disclosure.

Claims

1. A variable capacity tube, characterized in that, The varactor includes: a substrate, a channel layer, short-circuited source and drain electrodes, a gate dielectric layer, and a gate. The channel layer is a carbon nanotube thin film, and the gate dielectric layer is made of ferroelectric material. The substrate, channel layer, source and drain electrodes, gate dielectric layer, and gate form a metal-ferroelectric-semiconductor (MFS) structure. The gate dielectric layer is made of a ferroelectric material with a high dielectric constant, whose dielectric constant is symmetrical about the zero voltage point and increases with increasing voltage. Specifically, when the working voltage of the varactor tube changes direction, it is pre-pressurized to the maximum working voltage to realize the polarization reversal of the ferroelectric material, and then pressurized to the actual working voltage to avoid the capacitance stability problem caused by ferroelectric hysteresis. The source and drain electrodes are made of a metallic material whose work function is located near the center of the carbon nanotube band gap. The density of the carbon nanotube array in the channel layer is 200–400 nanotubes per micrometer.

2. The variable capacitance tube according to claim 1, characterized in that, The carbon nanotube film is either a parallel array of carbon nanotubes or a disordered network of carbon nanotubes.

3. The variable capacitance tube according to claim 1, characterized in that, The gate can be a planar gate structure, a fin gate structure, or a T-type gate structure.

4. The variable capacitance tube according to claim 1, characterized in that, The MFS structure can be a top-gate structure or a bottom-gate structure.

5. A method for preparing a variable capacitance tube according to any one of claims 1 to 4, characterized in that, include: Provide substrate; A carbon nanotube array thin film is prepared and patterned on the substrate to form a channel layer; Short-circuited source and drain electrodes are formed on the channel layer; A ferroelectric material is used to form a gate dielectric layer on the channel layer; A gate electrode is formed on the gate dielectric layer.

6. A method for preparing a variable capacitance tube according to any one of claims 1 to 4, characterized in that, include: Provide substrate; A gate is formed on the substrate; A ferroelectric material is used to form a gate dielectric layer on the substrate, and the gate dielectric layer covers the gate. A carbon nanotube array thin film is fabricated and patterned on the gate dielectric layer to form a channel layer; Short-circuited source and drain electrodes are formed on the channel layer.

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