A DC-DC converter
By introducing a minimum off-time control unit into the DC-DC converter, the minimum off-time is dynamically adjusted according to the duty cycle, which solves the problems of abnormal frequency rise and poor noise immunity of the DC-DC converter, and achieves voltage and frequency stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENGBANG MICROELECTRONICS (SUZHOU) CO LTD
- Filing Date
- 2022-09-15
- Publication Date
- 2026-07-17
AI Technical Summary
The minimum off-time in existing DC-DC converters is constant, which leads to abnormal frequency increases and poor noise immunity when the duty cycle changes.
The minimum off-time control unit is adopted, and the minimum off-time is dynamically adjusted based on the duty cycle of the DC-DC converter. The output voltage is stabilized through a feedback unit, a conduction time control unit, and a logic module, including feedback voltage generation, conduction time timing, and minimum off-time control.
It achieves dynamic adjustment of the minimum off time based on the duty cycle, preventing abnormal power increases in the DC-DC converter and improving frequency stability and noise immunity.
Smart Images
Figure CN115498878B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuits, and more specifically, to a DC-DC converter. Background Technology
[0002] DC-DC (Direct Current-Direct Current) converters are widely used in integrated circuits as voltage converters capable of transforming input voltage and effectively outputting a fixed voltage. Currently, many DC-DC converters employ constant on-time (COT) control mode to control the switching state of the power transistors.
[0003] In existing technologies, a minimum off-time circuit is usually required in such DC-DC converters to prevent the high-side power transistor from turning on prematurely due to various interferences or noises during the period when the inductor current signal decreases in each cycle, thereby causing the DC-DC converter to operate at too high a frequency.
[0004] In existing technologies, the minimum off time is usually set to a constant. However, this has certain problems. Since the power consumption of the downstream load connected to the DC-DC converter cannot be completely determined, and the state of the downstream load may change at any time, the actual operating duty cycle of the DC-DC converter will vary greatly within the range of 0 to 1.
[0005] When the duty cycle is small, the minimum turn-off time needs to be designed to be small to ensure that the setting of the minimum turn-off time does not affect the voltage stability of the DC-DC converter. However, when the duty cycle is large, the turn-off time of the DC-DC converter in each cycle is long. A minimum turn-off time that is too small is not enough to prevent the decreasing inductor current from rising sufficiently due to noise or interference, causing the DC-DC converter to enter the next cycle prematurely. This will result in poor noise immunity of the DC-DC converter and abnormal frequency rise.
[0006] To address this problem, this invention proposes a novel DC-DC converter. Summary of the Invention
[0007] To address the shortcomings of existing technologies, the present invention aims to provide a DC-DC converter that dynamically adjusts the minimum off-time based on the duty cycle, thereby preventing abnormal power increases in the DC-DC converter.
[0008] The present invention adopts the following technical solution.
[0009] A DC-DC converter operates in COT mode; and the DC-DC converter includes a minimum off-time control unit, wherein the minimum off-time generated by the minimum off-time control unit is adjustable based on the duty cycle of the DC-DC converter.
[0010] Preferably, the DC-DC converter includes a feedback unit, an on-time control unit, a minimum off-time control unit, a logic module, a power transistor, an inductor, and a capacitor. The feedback unit receives the feedback voltage Vfb generated by the output voltage under the action of the voltage divider resistor and compares it with a reference voltage to generate a first control signal OUT1. The on-time control unit receives the input voltage and output voltage of the DC-DC converter and generates an on-time control signal OUT2. The minimum off-time control unit receives the input voltage and output voltage of the DC-DC converter, the on-time control signal OUT2, and generates a minimum off-time control signal OUT3. The logic unit controls the power transistor to turn on or off based on the first control signal OUT1, the on-time control signal OUT2, and the minimum off-time control signal OUT3, thereby stabilizing the output voltage under the action of the inductor and capacitor.
[0011] Preferably, the minimum turn-off time control unit includes a first receiving unit, a second receiving unit, a current mirror, a reference voltage generation unit, a timing voltage generation unit, and a first comparator; wherein, the first receiving unit and the second receiving unit are respectively connected to the mirror unit, and are used to convert the input voltage and the output voltage into a first current and a second current, respectively; the reference voltage generation unit is connected to the current mirror, and realizes the reception of the difference current between the first current and the second current, and generates a reference voltage based on the difference current; the timing voltage generation unit is connected to the current mirror, and realizes the reception of the first current, and generates a timing voltage according to the charging and discharging rate of the timing capacitor; the first comparator is connected to the reference voltage generation unit and the timing voltage generation unit respectively, and compares the magnitude of the reference voltage and the timing voltage to generate a minimum turn-off time control signal.
[0012] Preferably, the first receiving unit and the second receiving unit have the same structure, both including an operational amplifier, a resistor, and an NMOS transistor; wherein, the non-inverting input terminal of the operational amplifier serves as the signal receiving terminal, the negative input terminal is connected to one end of the resistor and the source of the NMOS transistor respectively, and the output terminal is connected to the gate of the NMOS transistor; the other end of the resistor is grounded, and the drain of the NMOS transistor serves as the signal transmitting terminal.
[0013] Preferably, the current mirror includes a first mirror PMOS transistor, a second mirror PMOS transistor, and a third mirror PMOS transistor; wherein the sources of the first mirror PMOS transistor, the second mirror PMOS transistor, and the third mirror PMOS transistor are all connected to the power supply voltage, and their gates are interconnected and connected to the signal transmitting terminal of the first receiving unit; the drain of the first mirror PMOS transistor is also connected to the signal transmitting terminal of the first receiving unit, the drain of the second mirror PMOS transistor is connected to the signal transmitting terminal of the second receiving unit and connected to the reference voltage generating unit, and the drain of the third mirror PMOS transistor is connected to the timing voltage generating unit and the second comparator, respectively.
[0014] Preferably, the reference voltage generation unit includes a bias transistor and a voltage divider resistor; wherein, the source of the bias transistor is connected to the drain of the second mirror PMOS transistor, the gate is connected to a bias voltage, and the drain is grounded after passing through the voltage divider resistor; wherein, the voltage divider resistor generates a reference voltage and inputs it to the negative input terminal of the second comparator.
[0015] Preferably, the timing voltage generation unit includes a timing capacitor, a switching transistor, and an inverter; wherein, the source and drain of the switching transistor are connected in parallel with the upper and lower plates of the timing capacitor, and are connected between the drain of the third mirror PMOS transistor, the positive phase input terminal of the second comparator, and the low level; the conduction time control signal OUT2 is input to the gate of the switching transistor after passing through the inverter.
[0016] Preferably, when the first control signal OUT1 switches to a high level, the logic module controls the high-side power transistor to turn on, and the on-time control unit starts timing; when the second control signal OUT2 switches to a high level, the logic module controls the high-side power transistor to turn off, and the minimum off-time control unit starts timing; during the timing process of the minimum off-time control unit, the minimum off-time control signal OUT3 is always in a low level to ensure that the high-side power transistor is always off.
[0017] Preferably, the minimum turn-off time varies with the actual turn-off time of the DC-DC converter; wherein, T min =k·T off , R1 is the resistance value of the voltage divider resistor, C1 is the capacitance value of the timing capacitor, and T is the switching cycle of the power transistor in the DC-DC converter.
[0018] Preferably, the minimum shutdown time is T. min = (1-D)·R1·C1, where D is the duty cycle of the DC-DC converter.
[0019] The beneficial effect of this invention is that, compared with the prior art, the DC-DC converter of this invention can dynamically adjust the minimum off-time according to the duty cycle, thereby preventing abnormal power increases in the DC-DC converter. The method of this invention is simple, only improving the minimum off-time unit in COT control mode, so that the value of the minimum off-time is no longer constant, but can be adjusted according to the duty cycle. When the duty cycle is large, the minimum off-time is automatically reduced to prevent damage to the original control logic of the feedback voltage; while when the duty cycle is small, the minimum off-time is automatically extended to prevent noise or interference from causing insufficient frequency stability of the DC-DC converter. Attached Figure Description
[0020] Figure 1 This is a schematic diagram of the circuit structure of the COT control circuit in a DC-DC converter in the prior art;
[0021] Figure 2 This is a timing diagram of the inductor current during one cycle of a DC-DC converter in the prior art when the duty cycle is large.
[0022] Figure 3 This is a timing diagram of the inductor current during one cycle of a DC-DC converter in the prior art when the duty cycle is small.
[0023] Figure 4 This is a schematic diagram of the circuit structure of the minimum off-time control unit in a DC-DC converter according to the present invention. Detailed Implementation
[0024] The present application will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention, and should not be construed as limiting the scope of protection of the present application.
[0025] Figure 1 This is a schematic diagram of the circuit structure of a COT (Constant On-Time) control circuit in a DC-DC converter in the prior art. Figure 1 As shown, the DC-DC converter in this invention also uses the same circuit structure, but the only modification is made in the minimum off-time control unit.
[0026] Specifically, the present invention provides a DC-DC converter that operates in COT mode; and the DC-DC converter includes a minimum off-time control unit, wherein the minimum off-time generated by the minimum off-time control unit is adjustable, and the adjustment is based on the duty cycle of the DC-DC converter.
[0027] Preferably, the DC-DC converter includes a feedback unit, an on-time control unit, a minimum off-time control unit, a logic module, a power transistor, an inductor, and a capacitor. The feedback unit receives the feedback voltage Vfb generated by the output voltage under the action of the voltage divider resistor and compares it with a reference voltage to generate a first control signal OUT1. The on-time control unit receives the input voltage and output voltage of the DC-DC converter and generates an on-time control signal OUT2. The minimum off-time control unit receives the input voltage and output voltage of the DC-DC converter, the on-time control signal OUT2, and generates a minimum off-time control signal OUT3. The logic unit controls the power transistor to turn on or off based on the first control signal OUT1, the on-time control signal OUT2, and the minimum off-time control signal OUT3, thereby stabilizing the output voltage under the action of the inductor and capacitor.
[0028] It is understood that the circuit structure in this invention is similar to that of commonly used DC-DC converters in the prior art, both including logic units, high-side power transistor Mp0, low-side power transistor Mn0, inductor current L, and output capacitor Cout. Furthermore, in the COT mode of this invention, the on / off state of the power transistors can be implemented based on the feedback voltage Vfb and the first comparator COMP. The feedback voltage Vfb is the output voltage divided between resistors R1 and R2. After comparing the feedback voltage Vfb with the reference voltage Vref, a first control signal OUT1 is generated. This control signal OUT1 can control the logic module, turning on Mp0 and turning off Mn0 when Vfb is small, and performing the opposite operation when Vfb is large.
[0029] Preferably, when the first control signal OUT1 switches to a high level, the logic module controls the high-side power transistor to turn on, and the on-time control unit starts timing; when the second control signal OUT2 switches to a high level, the logic module controls the high-side power transistor to turn off, and the minimum off-time control unit starts timing; during the timing process of the minimum off-time control unit, the minimum off-time control signal OUT3 is always in a low level to ensure that the high-side power transistor is always off.
[0030] In this invention, the additional logic includes an on-time control signal OUT2. This unit can be implemented using various existing on-time control unit circuit structures. This unit can time the on-time. Specifically, when OUT1 flips to a high level, the unit starts timing. During the timing process, the OUT2 signal remains at a low level. When the timing ends, OUT2 flips to a high level, thereby turning off the high-side power transistor Mp0 and turning on Mn0.
[0031] When OUT2 flips to a high level, it signals the start of the minimum off-time control unit. This circuit begins timing and constrains the logic module to prevent the high-side power transistor Mp0 from turning on until the timing ends. After the timing of this unit ends, if the output signal of the first comparator COMP flips, the transistor can be restarted for the next cycle, causing the power transistor in the circuit to cycle through turning on and off repeatedly.
[0032] Figure 2 This is a timing diagram of the inductor current during one cycle in a DC-DC converter with a large duty cycle in the prior art. Figure 2 As shown, it should be noted that when the duty cycle of the DC-DC converter is large, in order to ensure that the downstream load can receive sufficient power, this invention should ensure that the minimum turn-off time of the DC-DC converter is less than [a certain value]. Figure 2 Toff in the middle.
[0033] Figure 3 This is a timing diagram of the inductor current during one cycle in a DC-DC converter with a low duty cycle in the prior art. Figure 3 As shown, when the duty cycle of the DC-DC converter is small, the high-side power transistor turns on for a relatively short time and turns off for a relatively long time. At this time, if the circuit uses the same minimum turn-off time, that is... Figure 3 If t1 is too short, then the minimum turn-off time constraint on Toff is too short. When the inductor current is affected by various noises, the inductor current may suddenly rise or fall. Once the inductor current drops rapidly, the first comparator may flip, causing the circuit to be unable to continue the normal turn-off operation after the minimum turn-off time ends and to enter the next cycle prematurely.
[0034] Figure 4 This is a schematic diagram of the circuit structure of the minimum off-time control unit in a DC-DC converter according to the present invention. Figure 4 As shown, preferably, the minimum turn-off time control unit includes a first receiving unit, a second receiving unit, a current mirror, a reference voltage generation unit, a timing voltage generation unit, and a second comparator; wherein, the first receiving unit and the second receiving unit are respectively connected to the mirror unit, and are used to convert the input voltage and the output voltage into a first current and a second current, respectively; the reference voltage generation unit is connected to the current mirror, and realizes the reception of the difference current between the first current and the second current, and generates a reference voltage based on the difference current; the timing voltage generation unit is connected to the current mirror, and realizes the reception of the first current, and generates a timing voltage according to the charging and discharging rate of the timing capacitor; the second comparator is connected to the reference voltage generation unit and the timing voltage generation unit respectively, and compares the magnitude of the reference voltage and the timing voltage to generate a minimum turn-off time control signal.
[0035] It is understood that, in this invention, by improving the minimum turn-off time control unit, the minimum turn-off time can be changed, thereby generating the output voltage more accurately.
[0036] The main idea of the minimum turn-off time control unit in this invention is to convert the input voltage Vin and the output voltage Vout into corresponding currents, respectively. The difference between these currents is then used to establish a reference voltage for the differential current through a resistor. The current converted from the input voltage Vin passes through capacitor C1, enabling a slow charging and discharging process. Timing is then based on this slow charging and discharging process. When the voltage on the upper plate of the capacitor slowly rises to the reference voltage, the output of the second comparator flips, thus completing the timing of the minimum turn-off time control unit.
[0037] Preferably, the first receiving unit and the second receiving unit have the same structure, both including an operational amplifier, a resistor, and an NMOS transistor; wherein, the non-inverting input terminal of the operational amplifier serves as the signal receiving terminal, the negative input terminal is connected to one end of the resistor and the source of the NMOS transistor respectively, and the output terminal is connected to the gate of the NMOS transistor; the other end of the resistor is grounded, and the drain of the NMOS transistor serves as the signal transmitting terminal.
[0038] It is understandable that when the NMOS transistor is in the ON state, ignoring its own resistance, the operational amplifier is in a negative feedback state, and the output current of the receiving unit is the ratio of the voltage at the signal receiving end to the resistance. Therefore, the output current of the first receiving unit is V. in / R0, the output current of the second receiving unit is V out / R0.
[0039] Preferably, the current mirror includes a first mirror PMOS transistor, a second mirror PMOS transistor, and a third mirror PMOS transistor; wherein the sources of the first mirror PMOS transistor, the second mirror PMOS transistor, and the third mirror PMOS transistor are all connected to the power supply voltage, and their gates are interconnected and connected to the signal transmitting terminal of the first receiving unit; the drain of the first mirror PMOS transistor is also connected to the signal transmitting terminal of the first receiving unit, the drain of the second mirror PMOS transistor is connected to the signal transmitting terminal of the second receiving unit and connected to the reference voltage generating unit, and the drain of the third mirror PMOS transistor is connected to the timing voltage generating unit and the second comparator, respectively.
[0040] Understandably, in the current mirror, the current output by the second mirror PMOS transistor should be V. in / R0-V out / R0, while the output current of the third mirror PMOS transistor is still V. in / R0.
[0041] Preferably, the reference voltage generation unit includes a bias transistor and a voltage divider resistor; wherein, the source of the bias transistor is connected to the drain of the second mirror PMOS transistor, the gate is connected to a bias voltage, and the drain is grounded after passing through the voltage divider resistor; wherein, the voltage divider resistor generates a reference voltage and inputs it to the negative input terminal of the second comparator.
[0042] Under the influence of the bias transistor, the gate voltage of Mp4 is controlled by the bias voltage Vb, thus allowing the output current of the second mirror PMOS transistor to be smoothly input into resistor R1. Therefore, the voltage across R1 remains relatively constant, which is (Vb / Vb). in -V out )·R1 / R0. In this case, the voltage at the negative input terminal of the comparator is also (V in -V out )·R1 / R0.
[0043] Preferably, the timing voltage generation unit includes a timing capacitor, a switching transistor, and an inverter; wherein, the source and drain of the switching transistor are connected in parallel with the upper and lower plates of the timing capacitor, and are connected between the drain of the third mirror PMOS transistor, the positive phase input terminal of the second comparator, and the low level; the conduction time control signal OUT2 is input to the gate of the switching transistor after passing through the inverter.
[0044] It is understood that in this invention, the timing voltage generation unit is controlled by the OUT2 signal. When the OUT2 signal is high, the Mns0 transistor is turned off, and C1 enters the charging state. The charging duration of C1 is related to the V4 voltage as follows: In this formula, t1 is the duration of capacitor charging from when OUT2 switches to high level, C1 is the capacitance value, and I1 is V. in / R0.
[0045] When the voltage at the positive input terminal and the voltage at the negative input terminal of the second comparator are equal, the output signal OUT3 flips.
[0046] Preferably, the minimum turn-off time varies with the actual turn-off time of the DC-DC converter; wherein, T min =k·T off , R1 is the resistance value of the voltage divider resistor, C1 is the capacitance value of the timing capacitor, and T is the switching cycle of the power transistor in the DC-DC converter.
[0047] In this invention, the minimum turn-off time is related to the actual turn-off time T of the high-side power transistor in each cycle. off There is always a proportionality coefficient between them, which ensures that a reasonable design of the values of R1 and C1 can guarantee T. min Always less than T offTo a certain extent, this prevents the minimum shutdown time from affecting T. off This is normal logic.
[0048] Preferably, the minimum shutdown time is T. min = (1-D)·R1·C1, where D is the duty cycle of the DC-DC converter.
[0049] In this invention, the minimum turn-off time actually decreases gradually as the duty cycle increases, thereby ensuring that the minimum turn-off time can be reasonably controlled regardless of the duty cycle value. This ensures that the minimum turn-off time will not affect the normal logic of Vfb, and can also reduce the abnormal switching of control signals caused by noise signals to a sufficient extent.
[0050] The beneficial effect of this invention is that, compared with the prior art, the DC-DC converter of this invention can dynamically adjust the minimum off-time according to the duty cycle, thereby preventing abnormal power increases in the DC-DC converter. The method of this invention is simple, only improving the minimum off-time unit in COT control mode, so that the value of the minimum off-time is no longer constant, but can be adjusted according to the duty cycle. When the duty cycle is large, the minimum off-time is automatically reduced to prevent damage to the original control logic of the feedback voltage; while when the duty cycle is small, the minimum off-time is automatically extended to prevent noise or interference from causing insufficient frequency stability of the DC-DC converter.
[0051] The applicant of this invention has provided a detailed description of the embodiments of the invention in conjunction with the accompanying drawings. However, those skilled in the art should understand that the above embodiments are merely preferred embodiments of the invention. The detailed description is only intended to help readers better understand the spirit of the invention and is not intended to limit the scope of protection of the invention. On the contrary, any improvements or modifications made based on the inventive spirit of the invention should fall within the scope of protection of the invention.
Claims
1. A DC-DC converter, characterized in that: The DC-DC converter operates in COT mode; and... The DC-DC converter includes a minimum off-time control unit. The minimum off-time generated by the minimum off-time control unit is adjustable and is adjusted based on the duty cycle of the DC-DC converter. The minimum off-time gradually decreases as the duty cycle increases. The minimum turn-off time control unit is used to receive the input voltage and output voltage of the DC-DC converter, the on-time control signal OUT2, and generate the minimum turn-off time control signal OUT3. The minimum turn-off time control unit includes a first receiving unit, a second receiving unit, a current mirror, a reference voltage generation unit, a timing voltage generation unit, and a first comparator; wherein... The first receiving unit and the second receiving unit are respectively connected to the mirror unit, and are used to convert the input voltage and the output voltage into a first current and a second current, respectively. The reference voltage generation unit is connected to the current mirror to receive the difference current between the first current and the second current, and to generate a reference voltage based on the difference current. The timing voltage generation unit is connected to the current mirror to receive the first current and generate the timing voltage according to the charging and discharging rate of the timing capacitor. The first comparator is connected to the reference voltage generation unit and the timing voltage generation unit respectively, and compares the magnitude of the reference voltage and the timing voltage to generate a minimum turn-off time control signal.
2. A DC-DC converter according to claim 1, characterized in that: The DC-DC converter includes a feedback unit, an on-time control unit, a minimum off-time control unit, a logic module, a power transistor, an inductor, and a capacitor; wherein... The feedback unit is used to receive the feedback voltage Vfb generated by the output voltage under the action of the voltage divider resistor, and compare it with the reference voltage to generate the first control signal OUT1. The on-time control unit is used to receive the input voltage and output voltage of the DC-DC converter and generate an on-time control signal OUT2; The logic module controls the power transistor to turn on or off based on the first control signal OUT1, the on-time control signal OUT2, and the minimum off-time control signal OUT3, so as to achieve stable output voltage under the action of inductor and capacitor.
3. A DC-DC converter according to claim 2, characterized in that: The first receiving unit and the second receiving unit have the same structure, both including an operational amplifier, resistors, and NMOS transistors; wherein, The non-inverting input terminal of the operational amplifier serves as the signal receiving terminal, the negative input terminal is connected to one end of a resistor and the source of an NMOS transistor, and the output terminal is connected to the gate of the NMOS transistor. The other end of the resistor is grounded, and the drain of the NMOS transistor serves as the signal transmitting end.
4. A DC-DC converter according to claim 3, characterized in that: The current mirror includes a first mirror PMOS transistor, a second mirror PMOS transistor, and a third mirror PMOS transistor; wherein... The sources of the first mirror PMOS transistor, the second mirror PMOS transistor, and the third mirror PMOS transistor are all connected to the power supply voltage, and their gates are connected to each other and connected to the signal transmitting terminal of the first receiving unit. The drain of the first mirror PMOS transistor is also connected to the signal transmitting terminal of the first receiving unit, the drain of the second mirror PMOS transistor is connected to the signal transmitting terminal of the second receiving unit and connected to the reference voltage generating unit, and the drain of the third mirror PMOS transistor is connected to the timing voltage generating unit and the second comparator respectively.
5. A DC-DC converter according to claim 4, characterized in that: The reference voltage generation unit includes a bias transistor and a voltage divider resistor; wherein... The source of the bias transistor is connected to the drain of the second mirror PMOS transistor, the gate is connected to the bias voltage, and the drain is grounded after passing through a voltage divider resistor. The voltage divider resistor generates a reference voltage and inputs it to the negative phase input of the second comparator.
6. A DC-DC converter according to claim 5, characterized in that: The timing voltage generation unit includes a timing capacitor, a switching transistor, and an inverter; The source and drain of the switching transistor are connected in parallel with the upper and lower plates of the timing capacitor, and connected between the drain of the third mirror PMOS transistor, the positive phase input of the second comparator, and the low level. The on-time control signal OUT2 is input to the gate of the switching transistor after passing through an inverter.
7. A DC-DC converter according to claim 6, characterized in that: When the first control signal OUT1 switches to a high level, the logic module controls the high-side power transistor to turn on, and the turn-on time control unit starts timing; When the on-time control signal OUT2 switches to a high level, the logic module controls the high-side power transistor to turn off, and the minimum off-time control unit starts timing. During the timing process of the minimum turn-off time control unit, the minimum turn-off time control signal OUT3 is always in a low level state to ensure that the high-side power transistor is always turned off.
8. A DC-DC converter according to claim 7, characterized in that: The minimum shutdown time varies with the actual shutdown time of the DC-DC converter; in, , , This is the resistance value of the voltage divider resistor. The capacitance value of the timing capacitor. The switching cycle of the power transistor in the DC-DC converter.
9. A DC-DC converter according to claim 8, characterized in that: The minimum shutdown time is ,in The duty cycle of the DC-DC converter.