A fixed power dissipation relaxation oscillator circuit

Abstract

A fixed power consumption relaxation oscillator circuit, characterized in that: the circuit comprises a first source follower unit and a second source follower unit; wherein the first source follower unit and the second source follower unit are connected with the drain of the amplifying tube in the relaxation oscillator respectively to limit the drain voltage of the amplifying tube; wherein the first source follower unit is used to limit the value of the drain voltage when the drain voltage is in a high level state; and the second source follower unit is used to limit the time when the drain voltage is output to the RS flip-flop when the drain voltage is in an intermediate state. The present application has a clever concept and a simple method, greatly improves the accuracy of the clock signal, ensures the stability of the clock signal output frequency, reduces the invalid power loss of the clock signal, and has a more extensive application value.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more specifically, to a fixed-power relaxation oscillator circuit. Background Technology

[0002] Currently, a relaxation oscillator circuit is a self-excited oscillation circuit composed of a unijunction transistor, resistors, and capacitors, which utilizes the negative resistance characteristic of the unijunction transistor. Relaxation oscillator circuits are widely used due to their advantages such as pulse repetition, a wide and easy frequency selection range, and relatively stable operating temperature.

[0003] Typically, a relaxation oscillator receives sawtooth wave signals generated by capacitor charging and discharging, and outputs a clock signal through an amplification circuit. Normally, the clock signal remains high until the capacitor charging / discharging voltage reaches the power supply voltage. When the capacitor charging / discharging voltage reaches its peak value, approaching or equaling the threshold voltage of the amplification circuit, the amplification circuit turns on, momentarily lowering the clock signal to a low level. Subsequently, after a short recovery period, the clock signal returns to a high level. In this way, the relaxation oscillator of this invention can achieve continuous oscillation and output of the clock signal.

[0004] In existing technologies, Class A amplifiers are typically used in the amplification circuits described above, for example, using MOSFETs connected in a common-emitter configuration. In this case, the pull-up state of the output signal is achieved solely through a current mirror element in the amplifier, and the charging time is inversely proportional to the magnitude of the current provided by the current mirror element. In this situation, the current mirror charges the output voltage of the Class A amplifier to the supply voltage, and changes in the supply voltage directly affect the charging time and the power supply rejection ratio (PSR). Therefore, when the supply voltage in the circuit is not stable enough, the output frequency of the clock signal will also change, making the output of the relaxation oscillator inaccurate.

[0005] On the other hand, when the clock signal generated by the relaxation oscillator is used as the input of the digital module, the clock signal will be in the intermediate state between high and low levels for a long time during the oscillation process, which will also lead to unnecessary power consumption, the recognition error of the clock signal by the digital module, and may even cause logic errors in the digital module.

[0006] To address the above problems, the present invention provides a relaxation oscillator with fixed power consumption. Summary of the Invention

[0007] To address the shortcomings of existing technologies, this invention provides a fixed-power relaxation oscillator circuit. This circuit uses a first source follower unit and a second source follower unit to adjust the amplifier transistors in the circuit, thereby limiting the high and low level states of the clock signal and minimizing the time the clock signal is in the intermediate state.

[0008] The present invention adopts the following technical solution.

[0009] In a first aspect, the present invention relates to a relaxation oscillator circuit with fixed power consumption, the circuit including a first source follower unit and a second source follower unit; wherein the first source follower unit and the second source follower unit are respectively connected to the drain of an amplifying transistor in the relaxation oscillator to limit the drain voltage of the amplifying transistor; wherein the first source follower unit is used to limit the value of the drain voltage when the drain voltage is in a high-level state; and the second source follower unit is used to limit the time for the drain voltage to be output to the RS flip-flop when the drain voltage is in an intermediate state.

[0010] Preferably, the first source follower unit includes a first mirror current source and a first source follower transistor Msf; wherein the source of the first source follower transistor Msf is connected to the drain of the amplifier transistor, and is connected to the power supply voltage through the first mirror current source, its drain is grounded, and its gate is connected to the first control voltage Vbp.

[0011] Preferably, the second source follower unit includes a second mirror current source and a second source follower transistor Mnb; wherein, the source of the second source follower transistor is connected to the drain of the amplifier transistor, its drain is connected to the power supply voltage through the second mirror current source, and its gate is connected to the second control voltage Vbn; the drain of the second source follower transistor serves as an output port for providing a clock amplification signal to the RS flip-flop.

[0012] Preferably, the second control voltage Vbn is higher than the first control voltage Vbp; and the difference between the second control voltage Vbn and the first control voltage Vbp is less than the threshold turn-on voltage of the first source follower transistor Msf.

[0013] Preferably, the current ratio of the first mirror current source to the second mirror current source is between 2 and 10.

[0014] Preferably, the width-to-length ratio of the second source follower tube is 5:0.6.

[0015] The beneficial effects of this invention are that, compared with the prior art, the fixed-power relaxation oscillator circuit of this invention adjusts the amplifying transistor in the circuit through a first source follower unit and a second source follower unit, thereby limiting the high and low level states of the clock signal and minimizing the time the clock signal is in the intermediate state. This invention is ingeniously conceived and simple in method, significantly improving the accuracy of the clock signal, ensuring the stability of the clock signal output frequency, reducing the ineffective power loss of the clock signal, and has wider application value. Attached Figure Description

[0016] Figure 1 A schematic diagram of the circuit structure of a high-speed relaxation oscillator in the prior art;

[0017] Figure 2 This is a schematic diagram illustrating the principle of generating a single clock signal in a high-speed relaxation oscillator, as described in the prior art.

[0018] Figure 3 This is a schematic diagram illustrating the principle of generating a single clock signal in one embodiment of an improved high-speed relaxation oscillator according to the present invention.

[0019] Figure 4 This is a schematic diagram of the control voltage generation circuit in an improved high-speed relaxation oscillator according to the present invention.

[0020] Figure 5 This is a schematic diagram illustrating the principle of generating a single clock signal in a fixed-power relaxation oscillator circuit according to the present invention.

[0021] Figure 6 This is a schematic diagram of the control voltage generation circuit in a fixed power consumption relaxation oscillator circuit according to the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this invention. The embodiments described in this application are merely some embodiments of this invention, and not all embodiments. Based on the spirit of this invention, other embodiments obtained by those skilled in the art without creative effort are all within the protection scope of this invention.

[0023] Figure 1 This is a schematic diagram of the circuit structure of a high-speed relaxation oscillator in the prior art. Figure 1 As shown, in order to generate clock signals and provide accurate logic clocks for subsequent circuits in the chip, existing technologies typically employ relaxation oscillators. A high-speed relaxation oscillator usually includes circuit elements such as a current mirror array, a capacitor array, a Class A amplifier array, and corresponding logic circuits.

[0024] Specifically, the current mirror array receives voltage from the power supply and generates mirror currents that are substantially equal or proportionally proportional in each branch. These mirror currents are then input to the capacitor array and the Class A amplifier array, respectively. The capacitors are charged by the mirror currents in the current mirrors. When the capacitor charging voltage reaches a level high enough to turn on the MOSFET in the Class A amplifier, the MOSFET releases the stored charge to ground, thus lowering the capacitor voltage. Once the capacitor voltage decreases, the MOSFET stops conducting. Therefore, in this way, the Class A amplifier and the capacitors form an oscillation module, achieving a continuous cyclical change in capacitor voltage. This oscillation is amplified by the Class A amplifier to output a clock signal. Simultaneously, multiple clock signals are generated in the capacitor array and the Class A amplifier array. These clock signals are processed through logic circuit structures similar to RS flip-flops to generate clock signals with the appropriate frequency and duty cycle that conform to the logic of the subsequent load.

[0025] However, this circuit has certain problems. Figure 2 This is a schematic diagram illustrating the principle of generating a single clock signal in a high-speed relaxation oscillator, as described in the prior art. Figure 2 As shown, specifically, the level of the clock signal output by a Class A amplifier is entirely determined by the magnitude of the power supply voltage. Therefore, if the power supply voltage is stable, the charging and discharging time of the capacitors is relatively predictable, resulting in an accurate clock signal frequency. However, if the power supply voltage is unstable, it will negatively impact the clock signal frequency, potentially causing fatal problems for the output logic of subsequent circuits. Therefore, this type of high-speed relaxation oscillator has relatively high requirements for power supply voltage accuracy.

[0026] On the other hand, since the voltage of the clock signal is directly controlled by the power supply voltage, the output power of the clock signal is relatively high, which also results in a large amount of ineffective power consumption in the entire chip.

[0027] To address the aforementioned problems, improvements typically made in existing technologies include... Figure 3 As shown. Figure 3 This is a schematic diagram illustrating the principle of generating a single clock signal in one embodiment of an improved high-speed relaxation oscillator according to the present invention. Figure 3 In this configuration, due to the addition of a source follower Msf, when the gate voltage Vbp of the MOSFET is fixed at a suitable voltage divider of the power supply voltage, Msf will generate a relatively fixed voltage at its source, such as Vbp + Vth - msf. Here, Vth - msf is the threshold turn-on voltage of the MOSFET Msf, which is the source-gate voltage difference when it is turned on. Figure 3The CLK signal is no longer directly controlled by the power supply voltage, but is instead limited to a potential of Vbp + Vth - msf under the influence of Vbp. In other words, if the Mn transistor used as a Class A op-amp is not conducting, the high-level state of the CLK signal is Vbp + Vth - msf. However, if the Mn transistor is conducting, the CLK signal level will be pulled low during the instantaneous turn-on and subsequent turn-off of Mn, and then slowly rise again. Therefore, as... Figure 3 As shown, the rising edge of the CLK signal is not an instantaneous impulse signal, but rather exhibits a relatively slow ramp-up state as the Mn transistor is gradually turned off.

[0028] Figure 4 This is a schematic diagram of the control voltage generation circuit in an improved high-speed relaxation oscillator according to the present invention. Figure 4 As shown, it should be noted that various methods can be used in the prior art to provide a suitable gate voltage for the Msf transistor. In one embodiment of the present invention, only a simple voltage divider of the power supply voltage is used. Therefore, a problem that this circuit still cannot overcome is that when Vbp fluctuates with an unstable power supply voltage, the high level of the clock signal CLK is also unstable. In other words, the frequency of the clock signal CLK may still be affected by the power supply voltage. In addition, although this circuit slightly reduces the output power consumption of the CLK signal, the CLK signal is not accurate because the intermediate state time is relatively long, that is, the intermediate period between the high and low levels is difficult to identify definitively. When the chip is affected by factors such as temperature, the logic identification of the clock signal by the subsequent circuit may be incorrect.

[0029] Based on this, the present invention provides a relaxation oscillator circuit with fixed power consumption.

[0030] Figure 5 This is a schematic diagram illustrating the principle of generating a single clock signal in a fixed-power relaxation oscillator circuit according to the present invention. Figure 5 As shown, a fixed-power relaxation oscillator circuit includes a first source follower unit and a second source follower unit. The first and second source follower units are respectively connected to the drain of the amplifier transistor in the relaxation oscillator to limit the drain voltage of the amplifier transistor. The first source follower unit is used to limit the value of the drain voltage when the drain voltage is in a high-level state; the second source follower unit is used to limit the time for the drain voltage to be output to the RS flip-flop when the drain voltage is in an intermediate state.

[0031] It is understood that in this invention, not only is the voltage range of the high-level state of the CLK signal limited by the first source follower, but the intermediate state of the CLK signal is also limited by the second source follower.

[0032] Preferably, the first source follower unit includes a first mirror current source and a first source follower transistor Msf; wherein the source of the first source follower transistor Msf is connected to the drain of the amplifier transistor, and is connected to the power supply voltage through the first mirror current source, its drain is grounded, and its gate is connected to the first control voltage Vbp.

[0033] It is understood that the first mirror current source in this invention can be a part of the structure of a prior art relaxation oscillator. By using this element in conjunction with the first source follower transistor Msf and connecting it to the drain of the amplifying transistor Mn, which is a Class A operational amplifier, it can function as a source follower to control the drain voltage of Mn. As mentioned earlier, if the transistor Mn is turned on, the voltage at point Vc will be rapidly pulled down and will no longer be affected by Msf. However, if the transistor Mn is turned off, the Msf transistor will fix Vc at an appropriate voltage according to the magnitude of Vbp.

[0034] Preferably, the second source follower unit includes a second mirror current source and a second source follower transistor Mnb; wherein, the source of the second source follower transistor is connected to the drain of the amplifier transistor, its drain is connected to the power supply voltage through the second mirror current source, and its gate is connected to the second control voltage Vbn; the drain of the second source follower transistor serves as an output port for providing a clock amplification signal to the RS flip-flop.

[0035] It is understood that a second source follower unit is also added in this invention, which also includes a current source and a source follower transistor. The source follower transistor is controlled by another control voltage, and during the conduction process, it receives the magnitude of the drain voltage transmitted from the Mn transistor and outputs it as the CLK signal.

[0036] It should be noted that, in order to control the output time of the drain voltage of the Mn transistor, the second source follower unit has a certain correlation between the magnitude of its gate voltage Vbn and the magnitude of the control voltage Vbp in the first source follower unit.

[0037] Figure 6 This is a schematic diagram of the control voltage generation circuit in a fixed-power relaxation oscillator circuit according to the present invention. Figure 6 As shown, preferably, the second control voltage Vbn is higher than the first control voltage Vbp; and the difference between the second control voltage Vbn and the first control voltage Vbp is less than the threshold turn-on voltage of the first source follower transistor Msf.

[0038] Understandably, the difference between the two voltages should be less than the threshold turn-on voltage Vth-msf when the Msf transistor is operating normally. In this way, the actual on-time of Mnb can be controlled. Specifically, when the Mn transistor is off, the voltage at point Vc is controlled by Msf and remains at Vbp+Vth-msf. If Vbn is less than the voltage at point Vc, the Mnb transistor cannot turn on. Due to the off state of the Mnb transistor, the CLK signal will remain at a high level, such as the output power supply voltage VDD.

[0039] On the other hand, if the charging of the capacitor causes Mn to conduct, the voltage of Vc will also drop instantaneously. At this time, the voltage at point Vc is lower than the gate control voltage Vbn of Mnb. Under this condition, Mnb also conducts along with Mn, and the CLK signal is pulled down to about 0V.

[0040] It's important to note that due to the discharge effect of Mn on the capacitor, the voltage of Vin decreases. At this point, the Mn transistor slowly turns off. During this process, because the source voltage Vc of Mnb has not yet fully recovered to be equal to or close to Vbn, the Mnb transistor remains on, keeping the CLK signal at a low level. In this way, the second-order follower unit limits the time it takes for the drain voltage of Mn to be output to the RS flip-flop. In other words, this method effectively extends the low-level time of the CLK output signal.

[0041] Furthermore, since the Mnb transistor will only turn off when the difference between Vbn and Vc is less than the threshold turn-on voltage of Mnb, although Mn turns off at a relatively slow speed, Mnb will only respond to the increase in Vc voltage at the moment Mn is completely turned off and turn off at a faster speed, thus making the rising edge of the CLK signal exhibit better instantaneity.

[0042] Preferably, the current ratio of the first mirror current source to the second mirror current source is between 2 and 10.

[0043] It is understandable that the current magnitude between the first and second mirror current sources can be reasonably considered in this invention. If the current ratio between the two is too low, the current magnitude of I2 will be closer to that of I1, which may result in a slower response speed of Mnb during voltage Vc oscillation, making it difficult for the CLK signal to maintain a good high-low level switching speed. On the other hand, if the current ratio between the two is too high, the current of I2 will be extremely small, causing Mnb transistor to fail and resulting in unnecessary power loss.

[0044] After extensive testing, this invention limits the ratio of the two currents to between 2 and 10. In one embodiment of this invention, the first mirror current is set to 15 μA and the second mirror current to 5 μA, resulting in an optimal CLK signal output by the circuit.

[0045] Preferably, the width-to-length ratio of the second source follower transistor is 5:0.6. In order to enable Mnb to respond quickly to changes in Vc and achieve rapid turn-on and turn-off, and to ensure that its drain current during turn-on is large enough to meet the corresponding requirements in the circuit of this invention, the width-to-length ratio of the MOS transistor is reasonably set, thereby achieving the best effect.

[0046] The beneficial effects of this invention are that, compared with the prior art, the fixed-power relaxation oscillator circuit of this invention adjusts the amplifying transistor in the circuit through a first source follower unit and a second source follower unit, thereby limiting the high and low level states of the clock signal and minimizing the time the clock signal is in the intermediate state. This invention is ingeniously conceived and simple in method, significantly improving the accuracy of the clock signal, ensuring the stability of the clock signal output frequency, reducing the ineffective power loss of the clock signal, and has wider application value.

[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. A relaxation oscillator circuit with fixed power consumption, characterized in that: The circuit includes a first source follower unit and a second source follower unit; wherein... The first source follower unit and the second source follower unit are respectively connected to the drain of the amplifier tube in the relaxation oscillator to limit the drain voltage of the amplifier tube; The first source follower unit includes a first mirror current source and a first source follower transistor Msf; the source of the first source follower transistor Msf is connected to the drain of the amplifier transistor, and is connected to the power supply voltage through the first mirror current source. Its drain is grounded, and its gate is connected to a first control voltage Vbp; the first source follower unit is used to limit the value of the drain voltage when the drain voltage is in a high-level state. The second source follower unit includes a second mirror current source and a second source follower transistor Mnb; the source of the second source follower transistor is connected to the drain of the amplifying transistor, its drain is connected to the power supply voltage through the second mirror current source, and its gate is connected to the second control voltage Vbn; the drain of the second source follower transistor serves as an output port for providing a clock amplification signal to the RS flip-flop; the second source follower unit is used to limit the time when the drain voltage is in the intermediate state to output the drain voltage to the RS flip-flop; The second control voltage Vbn is higher than the first control voltage Vbp; and the difference between the second control voltage Vbn and the first control voltage Vbp is less than the threshold turn-on voltage of the first source follower transistor Msf.

2. The fixed-power relaxation oscillator circuit according to claim 1, characterized in that: The current ratio between the first mirror current source and the second mirror current source is in the range of 2 to 10.

3. A fixed-power relaxation oscillator circuit according to claim 2, characterized in that: The width-to-length ratio of the second source follower is 5:0.6.

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