Clock data recovery circuit, control method, display panel, device and medium

Abstract

The embodiment of the application discloses a clock data recovery circuit, wherein: the first end of the voltage generation module is connected with an input signal, and the second end of the voltage generation module is connected with the first end of the voltage detection module and the third end of the recovery module respectively; the second end of the voltage detection module is connected with the first end of the recovery module, and the second end of the recovery module is connected with the third end of the voltage generation module; the voltage generation module is used for generating a control voltage based on the input signal and the recovery clock signal fed back by the recovery module; the voltage detection module is used for detecting whether the control voltage is in a preset voltage range matched by the voltage generation module, and generating a current branch selection signal in the case that the control voltage is not in the preset voltage range; the recovery module is used for adjusting the control voltage based on the current branch selection signal, and feeding back the obtained recovery clock signal to the voltage generation module until the control voltage is adjusted to be in the preset voltage range, and the clock data recovery circuit is locked.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of display technology, and in particular to a clock data recovery circuit, control method, display panel, device, and medium. Background Technology

[0002] To support a variety of application products, an increasing number of display interface protocols cover a wide range of data rates. Receivers supporting a wide range of data rates need to support these display interface protocols. Clock Data Recovery (CDR) circuits operate over a relatively wide range of operating frequencies, with the control voltage (Vctrl) varying over a relatively wide range. The performance of the CDR deteriorates when the control voltage is too high or too low. Summary of the Invention

[0003] In view of this, embodiments of this application provide at least one clock data recovery circuit, control method, display panel, device, and medium.

[0004] The technical solution of this application embodiment is implemented as follows:

[0005] On one hand, embodiments of this application provide a clock data recovery circuit, which includes: a voltage generation module, a voltage detection module, and a recovery module;

[0006] The first terminal of the voltage generation module is connected to an input signal, and the second terminal of the voltage generation module is connected to the first terminal of the voltage detection module and the third terminal of the recovery module, respectively; the second terminal of the voltage detection module is connected to the first terminal of the recovery module, and the second terminal of the recovery module is connected to the third terminal of the voltage generation module.

[0007] The voltage generation module is used to generate a control voltage based on the input signal and the recovery clock signal fed back by the recovery module;

[0008] The voltage detection module is used to detect whether the control voltage is within the preset voltage range matched by the voltage generation module, and to generate a current branch selection signal when the control voltage is not within the preset voltage range.

[0009] The recovery module is used to adjust the control voltage based on the current branch selection signal to obtain a recovery clock signal, and feed the recovery clock signal back to the voltage generation module until the control voltage is adjusted to the preset voltage range, at which point the clock data recovery circuit is locked.

[0010] On the other hand, embodiments of this application provide a control method for a clock data recovery circuit, the method being applied to the aforementioned clock data recovery circuit, the method comprising:

[0011] The voltage generation module in the clock data recovery circuit generates a control voltage based on the input signal and the recovered clock signal fed back by the recovery module in the clock data recovery circuit.

[0012] The voltage detection module in the clock data recovery circuit is used to detect whether the control voltage is within the preset voltage range matched by the voltage generation module. If the control voltage is not within the preset voltage range, a current branch selection signal is generated.

[0013] The recovery module adjusts the control voltage based on the current branch selection signal to obtain the recovery clock signal until the control voltage is within the preset voltage range, thereby locking the clock data recovery circuit.

[0014] In another aspect, embodiments of this application provide a control device for a clock data recovery circuit, the device comprising:

[0015] The first generation module 1201 is used to generate a control voltage based on the input signal and the recovery clock signal fed back by the recovery module in the clock data recovery circuit, using the voltage generation module in the clock data recovery circuit.

[0016] The second generation module 1202 is used to use the voltage detection module in the clock data recovery circuit to detect whether the control voltage is within the preset voltage range matched by the voltage generation module, and generate a current branch selection signal when the control voltage is not within the preset voltage range.

[0017] The first optical module 1203 is used to adjust the control voltage based on the current branch selection signal by the recovery module to obtain the recovery clock signal until the control voltage is within the preset voltage range, thereby locking the clock data recovery circuit.

[0018] In another aspect, embodiments of this application provide a computer device, including a memory and a processor, wherein the memory stores a computer program that can run on the processor, and the processor executes the program to implement some or all of the steps in the above-described method.

[0019] In another aspect, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements some or all of the steps in the above-described method.

[0020] In another aspect, embodiments of this application provide a computer program including computer-readable code, wherein when the computer-readable code is run in a computer device, a processor in the computer device performs some or all of the steps for implementing the above-described method.

[0021] In another aspect, embodiments of this application provide a computer program product, the computer program product including a non-transitory computer-readable storage medium storing a computer program, wherein when the computer program is read and executed by a computer, it implements some or all of the steps in the above method.

[0022] In this embodiment, a clock data recovery circuit is provided, comprising: a voltage generation module, a voltage detection module, and a recovery module; wherein, a first terminal of the voltage generation module is connected to an input signal, and a second terminal of the voltage generation module is connected to both the first terminal of the voltage detection module and the third terminal of the recovery module; the second terminal of the voltage detection module is connected to the first terminal of the recovery module, and the second terminal of the recovery module is connected to the third terminal of the voltage generation module; the voltage generation module is used to generate a control voltage based on the input signal and a recovery clock signal fed back by the recovery module; the voltage detection module is used to determine whether the control voltage is within a preset voltage range matched by the voltage generation module; if the control voltage is not within the preset voltage range, a current branch selection signal is generated based on the relationship between the control voltage and the preset voltage range; the recovery module is used to adjust the control voltage based on the current branch selection signal and feed back the recovery clock signal obtained during the adjustment process to the voltage generation module until the control voltage is within the preset voltage range, at which point the clock data recovery circuit is locked. By introducing a voltage detection module into the clock data recovery circuit, it is possible to determine whether the control voltage is within the preset voltage range matched by the voltage generation module. Since this preset voltage range is matched with the voltage generation module, meaning the voltage generation module performs well within this preset voltage range, it is possible to determine whether the control voltage is within the region that allows the voltage generation module to perform well. Subsequently, the voltage detection module generates a current branch selection signal according to the control voltage and the preset voltage range. This current branch selection signal controls the current in the recovery module, enabling the recovery module to recover the clock data from the input signal using the current and control voltage, obtaining the recovered clock signal, which is then fed back to the voltage generation module. Because the voltage detection module can determine whether the control voltage is within the preset voltage range, it can automatically adjust the control voltage to the preset voltage range when it is too high or too low, ensuring that the voltage generation module continuously operates within an optimal range, thus improving the performance of the clock data recovery circuit.

[0023] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of this disclosure. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the technical solutions of this application.

[0025] Figure 1 This is a schematic diagram of the composition structure of the clock data recovery circuit in some embodiments;

[0026] Figure 2 This is a schematic diagram of the charging and discharging current of the charge pump in the clock data recovery circuit in some embodiments;

[0027] Figure 3 A schematic diagram of the composition structure of the clock data recovery circuit provided in the embodiments of this application;

[0028] Figure 4A This is a schematic diagram of another component structure of the clock data recovery circuit provided in the embodiments of this application;

[0029] Figure 4B A schematic diagram of another component structure of the clock data recovery circuit provided in the embodiments of this application;

[0030] Figure 4C This is another schematic diagram of the clock data recovery circuit provided in the embodiments of this application;

[0031] Figure 5 A schematic diagram illustrating the implementation flow of a control method for a clock data recovery circuit provided in an embodiment of this application;

[0032] Figure 6 A schematic diagram of the composition structure of the clock data recovery circuit provided in the embodiments of this application;

[0033] Figure 7 A schematic diagram of the composition structure of the voltage-current converter in the clock data recovery circuit provided in the embodiments of this application;

[0034] Figure 8 This is a schematic diagram of another component structure of the clock data recovery circuit provided in the embodiments of this application;

[0035] Figure 9 This is a schematic diagram of another component structure of the voltage-current converter in the clock data recovery circuit provided in the embodiments of this application;

[0036] Figure 10 This is a schematic diagram illustrating the correspondence between the counter and the control voltage provided in an embodiment of this application;

[0037] Figure 11 A schematic diagram illustrating the implementation flow of the control method for the clock data recovery circuit provided in an embodiment of this application;

[0038] Figure 12 This is a schematic diagram of the hardware entity of a computer device provided in an embodiment of this application. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0040] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0041] The terms “first / second / third” are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that “first / second / third” may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of this application.

[0043] Before providing a further detailed description of the embodiments of this application, the nouns and terms involved in the embodiments of this application will be explained, and the nouns and terms involved in the embodiments of this application shall be interpreted as follows.

[0044] 1) A phase frequency detector (PFD) operates by triggering the transition edge of the input signal and is an edge-controlled digital phase frequency detector. A PFD can detect both phase and frequency. Since a PFD only compares the transition edges of two input signals, it does not have a fixed requirement for the duty cycle of the input signals.

[0045] 2) The integrated circuit (IC) industry continues to drive the development of the smartphone industry. Touch and display driver integration (TDDI) brings a unified system architecture. The original system architecture, because the display and touch chips were separate, could lead to some display noise. TDDI, however, achieves unified control, resulting in better noise management. TDDI uses a "time-division scanning" method, dividing one frame of display time into two parts: one part for touch scanning and the other for display scanning, without interference, fundamentally reducing the risk of signal interference.

[0046] To better understand the clock data recovery circuit provided in the embodiments of this application, the circuit structure of the clock data recovery circuit will be described below.

[0047] Figure 1 This is a schematic diagram of the clock data recovery circuit structure in some embodiments, combined with... Figure 1 The clock data recovery circuit comprises modules including: PFD 11, Phase Detector (PD) 12, Charge Pump (CP) 13, Voltage to Current Converter (V2I) 14, Current Controlled Oscillator (ICO) 15, and Divider 16. Upon system power-on or reset, it enters the clock training period. Data input (DIN) 17 transmits the clock signal, FLOCK 18 is 0, PFD 11 operates, and compares the feedback clock signal CLK. FB The frequency and phase error between the clock signal 19 and the reference clock signal DIN is converted into a charging / discharging current via CP 13. This changes the magnitude of the control voltage Vctrl, which in turn changes the magnitude of the current Ictrl, thereby adjusting the oscillation frequency of ICO and making CLK... FB The frequencies of DIN 19 and DIN 17 are in phase. The clock data recovery circuit is frequency locked; FLOCK 18 becomes 1, PD 12 operates, and DIN 17 transmits normal data signals. When the operating frequency of the clock data recovery circuit increases, the voltage Vctrl increases; when the operating frequency decreases, the voltage Vctrl decreases. When the clock data recovery circuit operates over a relatively wide frequency range, the control voltage Vctrl varies within a relatively wide range as the operating frequency of the clock data recovery circuit changes. Figure 2This is a schematic diagram of the charge pump charging and discharging current in the clock data recovery circuit of some embodiments, from... Figure 2 It can be seen that when the control voltage Vctrl is too large (e.g., greater than Vref1) or too small (e.g., less than Vref0), the charge pump operates in a region with poor linearity (i.e., ...). Figure 2 In regions 21 and 22 (within the original text), the performance of the clock data recovery circuit will deteriorate. Figure 2 In the diagram, curve 23 represents the charging current I. UP The relationship between the control voltage and the discharge current I is shown in curve 24. DN The correspondence between the current and the control voltage; in regions 21 and 22, the charging current and the discharging current are not equal, that is, the charging current and the discharging current are mismatched. In region 25, the charging current and the discharging current are equal, that is, the charging current and the discharging current are matched; in regions 21 and 22, due to the mismatch between the charging current and the discharging current, the function of the phase-locked loop is reduced, which in turn reduces the performance of the CDR.

[0048] This application provides a clock data recovery circuit. By introducing a control voltage Vctrl detection circuit for the CDR, it can determine whether Vctrl is in a working region with good CP linearity, and automatically adjust Vctrl to a working region with good CP linearity when Vctrl is too large or too small. The clock data recovery circuit provided in this application can be integrated into the driver chip of a display panel. The display panel can be the screen of an electronic device, such as a laptop, tablet, desktop computer, set-top box, mobile device (e.g., mobile phone, portable music player, personal digital assistant, dedicated messaging device, portable gaming device), or a server. The server can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDN), and big data and artificial intelligence platforms.

[0049] Figure 3 This is a schematic diagram of the composition structure of the clock data recovery circuit provided in the embodiments of this application, combined with... Figure 3 The following description is provided: The clock data recovery circuit includes: a voltage generation module 301, a voltage detection module 302, and a recovery module 303;

[0050] The first terminal of the voltage generation module 301 is connected to the input signal, and the second terminal of the voltage generation module 301 is connected to the first terminal of the voltage detection module 302 and the third terminal of the recovery module 303 respectively; the second terminal of the voltage detection module 302 is connected to the first terminal of the recovery module 303, and the second terminal of the recovery module 303 is connected to the third terminal of the voltage generation module 301.

[0051] The voltage generation module 301 is used to generate a control voltage based on the input signal and the recovery clock signal fed back by the recovery module 303.

[0052] Here, the first terminal of the voltage generation module 301 is connected to the output terminal of the input signal. This input signal can be a signal output from an analog front-end, which amplifies the input signal and outputs the amplified signal, which is the input signal to the voltage generation module. In some possible implementations, the voltage generation module 301 may include a frequency and phase detector and a charge pump. The frequency and phase detector determines the frequency and phase differences between the input signal and the recovered clock signal. Based on these differences, the charge pump is controlled to charge or discharge the current source using a charging or discharging signal, thereby generating a control voltage during the charging and discharging process. This control voltage controls the voltage-to-current converter in the recovery module, adjusting the magnitude of the converted current by adjusting the control voltage. This adjustment of the current magnitude changes the frequency and phase of the recovered clock signal output by the recovery module. The control voltage generated by the voltage generation module 301 is transmitted to the recovery module 303 through the second terminal of the voltage generation module 301 and the third terminal of the recovery module.

[0053] The voltage detection module 302 is used to detect whether the control voltage is within the preset voltage range matched by the voltage generation module, and to generate a current branch selection signal when the control voltage is not within the preset voltage range.

[0054] Here, the preset voltage range matched by the voltage generation module is obtained based on the simulation results of the charge pump's charging and discharging within the module. For example, if the difference between the charge current and discharge current of the charge pump is set to be less than 3%, then the minimum and maximum voltage values ​​that achieve this difference constitute the preset voltage range. Thus, this preset voltage range corresponds to the voltage range under the condition of charge pump charge and discharge current matching, meaning that the charge pump operates in a region with good linearity within this preset voltage range.

[0055] In some possible implementations, the voltage detection module includes a comparator and logic circuitry. The comparator compares the control voltage with a preset voltage range to obtain a comparison result. This comparison result determines whether the control voltage falls within the preset voltage range matched by the voltage generation module. The comparison result is then sent to the logic circuitry, which generates a current branch selection signal. The output of this logic circuitry serves as the second terminal of the voltage detection module.

[0056] The recovery module 303 is used to adjust the control voltage based on the current branch selection signal to obtain a recovery clock signal, and feed the recovery clock signal back to the voltage generation module until the control voltage is adjusted to the preset voltage range, at which point the clock data recovery circuit is locked.

[0057] Here, after receiving the current branch selection signal output by the voltage detection module, the recovery module 303 converts the control voltage into a current and outputs the current on each branch according to the current branch corresponding to the current branch selection signal. The currents on each branch are then combined to obtain a combined current. Based on this combined current, the frequency of the current-controlled oscillator in the recovery module 303 is adjusted to recover the clock data of the input signal, resulting in the recovered clock signal. This recovered clock signal is then fed back to the voltage generation module 301 through a closed-loop path. Thus, the recovered clock signal and the input signal are used to continue adjusting the control voltage to bring it within a preset voltage range, thereby locking the clock data recovery circuit. After the clock data recovery circuit is locked, it enters the normal data transmission stage, i.e., receiving data packets and display data.

[0058] In this embodiment, a voltage detection module is introduced into the clock data recovery circuit. This module can determine whether the control voltage is within a preset voltage range matched by the voltage generation module. Since this preset voltage range is matched with the voltage generation module, meaning the voltage generation module performs well within this range, it can be determined whether the control voltage is within a region that allows the voltage generation module to perform well. Then, when the control voltage is outside the preset voltage range, the voltage detection module generates a current branch selection signal based on the control voltage and the preset voltage range. This signal controls the current in the recovery module, adjusting the control voltage so that the recovery module can recover the clock data from the input signal using the current and control voltage, obtaining the recovered clock signal, which is then fed back to the voltage generation module. Because the voltage detection module can determine whether the control voltage is within the preset voltage range, it can automatically adjust the control voltage to the preset voltage range when it is too high or too low, ensuring the voltage generation module continuously operates within an optimal range and improving the performance of the clock data recovery circuit.

[0059] In some embodiments, a voltage detection module is formed by two comparators and a logic submodule to achieve automatic adjustment of the control voltage, such as... Figure 4A As shown, the voltage detection module 302 includes: a first comparator 401, a second comparator 402, and a logic submodule 403; wherein:

[0060] The positive terminal of the first comparator 401 is connected to the second terminal of the voltage generation module 301, and the negative terminal is connected to the output terminal of the minimum threshold Vref0 of the preset voltage range; the positive terminal of the second comparator 402 is connected to the second terminal of the voltage generation module 301, and the negative terminal is connected to the output terminal of the maximum threshold Vref1 of the preset voltage range; the first terminal of the logic submodule 403 is connected to the output terminal of the first comparator, the second terminal of the logic submodule 403 is connected to the output terminal of the second comparator; and the third terminal of the logic submodule 403 is connected to the first terminal of the recovery module 303.

[0061] The first comparator 401 is used to generate a first comparison value based on the control voltage and the minimum threshold.

[0062] Here, the minimum threshold of the preset voltage range is the minimum voltage value at which the charge pump of the voltage generation module operates in a region with good linearity. That is, if the control voltage is less than this minimum voltage value, the difference between the charging and discharging currents of the charge pump will be large, i.e., the charging current and discharging current of the charge pump will be mismatched. The first comparator can be a binary logic comparator. In the first comparator, if the input value at the positive terminal is greater than the input value at the negative terminal, the comparator outputs a high level 1, i.e., the first comparison value is a high level 1; if the input value at the positive terminal is less than the input value at the negative terminal, the comparator outputs a low level 0, i.e., the first comparison value is a low level 0.

[0063] The second comparator 402 is used to generate a second comparison value based on the control voltage and the maximum threshold.

[0064] Here, the positive terminals of the first and second comparators are connected together, both serving as the first terminal of the voltage detection module for inputting the control voltage. The maximum threshold of the preset voltage range is the maximum voltage value at which the charge pump of the voltage generation module operates in a region with good linearity. That is, if the control voltage is greater than this maximum voltage value, the difference between the charging and discharging currents of the charge pump will be large, i.e., the charging current and discharging current of the charge pump will be mismatched. The second comparator can also be a binary logic comparator. In the second comparator, if the input value at the positive terminal is greater than the input value at the negative terminal, i.e., the control voltage is greater than the maximum voltage value, then the comparator outputs a low level 0, i.e., the second comparison value is low level 0; if the input value at the positive terminal is less than the input value at the negative terminal, i.e., the control voltage is less than the maximum voltage value, then the comparator outputs a high level 1, i.e., the second comparison value is high level 1.

[0065] The logic submodule 403 is used to detect whether the control voltage is within the preset voltage range matched by the voltage generation module based on the first comparison value and the second comparison value, and to generate the current branch selection signal when the control voltage is not within the preset voltage range.

[0066] In some possible implementations, the logic submodule 403 is further configured to determine that the control voltage is not within the preset voltage range when the first comparison value indicates that the control voltage is less than the minimum threshold, or the second comparison value indicates that the control voltage is greater than the maximum threshold, and generate the current branch selection signal based on the first comparison value and the second comparison value.

[0067] Here, logic submodule 403 outputs a current branch selection signal through its third terminal and inputs this signal to the recovery module through its first terminal. Logic submodule 403 can be implemented using a logic circuit with a two-character output format: (first comparison value and second comparison value). If both the first and second comparison values ​​are 1, the output of the logic submodule is (1, 1). The first and second comparison values ​​correspond to different current branches in the voltage-to-current conversion circuit. If the first comparison value is 0 and the second comparison value is 1, the current branch selection signal controls the current branch corresponding to the first comparison value to disconnect and the current branch corresponding to the second comparison value to connect. This current branch selection signal controls the current value in the voltage-to-current conversion circuit connected to the output of the logic submodule. The output of the logic submodule serves as the second terminal of the voltage detection module, outputting the current branch selection signal to the recovery module.

[0068] In this embodiment, a comparator is used to compare a threshold within a preset voltage range with a control voltage, thereby controlling the current branch in the recovery module through a logic submodule. In this way, by changing the magnitude of the current in the recovery module, the control voltage can be automatically adjusted.

[0069] In some embodiments, the recovery of the input signal is achieved through a voltage-to-current converter, a current-controlled oscillator, and a frequency divider in the recovery module, such as... Figure 4B As shown, the recovery module 303 includes: a voltage-to-current converter 411, a current-controlled oscillator 412, and a frequency divider 413; wherein:

[0070] The first terminal of the voltage-current converter 411 is connected to the second terminal of the voltage detection module 302, the second terminal of the voltage-current converter 411 is connected to the first terminal of the current-controlled oscillator 412, and the third terminal of the voltage-current converter 411 is connected to the second terminal of the voltage generation module 301 for receiving the control voltage generated by the voltage generation module; the second terminal of the current-controlled oscillator 412 is connected to the first terminal of the frequency divider 413, and the second terminal of the frequency divider 413 is connected to the third terminal of the voltage generation module to transmit the recovery clock signal fed back by the frequency divider.

[0071] The voltage-to-current converter 411 is used to convert the control voltage into a current based on the current branch selection signal to obtain a control current.

[0072] Here, the voltage-to-current converter 411 may include multiple transistors, which are used to convert control voltage into current and maintain that current. The voltage-to-current converter 411 may have at least three current branches. Taking three current branches as an example, one current branch is a continuous branch, and the other two current branches may be equipped with switches. The current branch selection signal controls the closing and opening of the switches, thereby controlling the connection or disconnection of the branch. When the current branch selection signal is high, the switch in the corresponding branch is closed; when the current branch selection signal is low, the switch in the corresponding branch is open. The control current is the sum of the currents of all connected branches. The first terminal of the voltage-to-current converter 411 serves as the first terminal of the recovery module, receiving the current branch selection signal input from the logic submodule; the third terminal of the voltage-to-current converter 411 serves as the third terminal of the recovery module, receiving the control voltage generated by the voltage generation module.

[0073] In some possible implementations, the conversion from control voltage to control current is achieved by incorporating a first current conversion unit, a first current holding branch, and multiple current selection branches in the voltage-to-current converter. The voltage-to-current converter 411 includes: a first current conversion unit, a first current holding branch, and a first current selection branch comprising at least two branches with identical structures.

[0074] The input terminal of the first current conversion unit is connected to the second terminal of the voltage generation module 301 for receiving the control voltage; the output terminal of the first current conversion unit is connected to the input terminal of the first current holding branch and the first input terminal of the first current selection branch respectively; the second input terminal of the first current selection branch is connected to the second terminal of the voltage detection module for receiving the current branch selection signal; the output terminal of the first current selection branch is connected to the output terminal of the first current holding branch.

[0075] The first current conversion unit is used to convert the control voltage into current to obtain the initial current.

[0076] Here, the first current conversion unit can be implemented using a transistor. This transistor converts the applied control voltage into an initial current. For example... Figure 7 As shown, the first current conversion unit may include Figure 7The circuit includes transistor 71 and transistor MPA, which serves as the root current source. The transistors in the first current holding branch and the first current selection branch both replicate the circuitry of transistor MPA. The input terminal of the first current conversion unit is the gate of transistor 71, which can be used as the third terminal of the recovery module to receive the control voltage. The second input terminal of the first current selection branch is connected to the second terminal of the voltage detection module to receive the current branch selection signal; the second input terminal of the first current selection branch can also serve as the first terminal of the piezo-current converter 411, i.e., the first terminal of the recovery module. In the first current conversion unit, transistor 71 and transistor MPA convert the control voltage to obtain the initial current.

[0077] The transistors in the first current conversion unit, the first current holding branch, and the first current selection branch have the same aspect ratio. Here, the aspect ratio of the transistor is the ratio of the channel width to the channel length. Because the transistors in each of the first current conversion unit, the first current holding branch, and the first current selection branch have the same aspect ratio, the current flowing through each branch is the same. The output terminal of the first current conversion unit is the port where the gate of transistor MPA and one end of transistor 71 are connected. The converted current is output through this output terminal. The gate of transistor MPA and one end of transistor 71 are connected to the input terminals of the first current holding branch and the first current selection branch, respectively. This allows the first current holding circuit, in conjunction with transistor 71 in the first current conversion unit, to convert the control voltage to obtain the initial current. Furthermore, when the switch in the first current selection branch is closed, the first current selection branch, in conjunction with transistor 71 in the first current conversion unit, converts the control voltage to obtain the initial current.

[0078] The first current holding branch is used to hold and output the initial current.

[0079] Here, the first current holding branch can use a transistor to hold the initial current obtained from the first current conversion unit. For example... Figure 7 As shown, the first current holding branch may include transistor MP0, which holds the initial current and is connected to the output terminal of the control current.

[0080] The first current selection branch is used to determine a target branch that is in a conducting state among the at least two branches based on the current branch selection signal, and to output the initial current through the target branch.

[0081] Here, the control current includes the initial current output by each branch. Each branch in the first current selection branch can maintain the initial current obtained from the first current conversion unit through a transistor and a switch. For example... Figure 7As shown, one branch may include transistor MP1 and switch SW0; the other branch may include transistor MP2 and switch SW1. The high or low level of the current branch selection signal determines whether the switches in at least two branches are closed. If the current branch selection signal is high, the switch in the corresponding branch is closed, i.e., this branch is the target branch, so that the target branch transmits the initial current to the output terminal of the control current. Since multiple branches in the first current selection branch have the same structure, for example, ... Figure 7 As shown, the transistors in each branch have the same aspect ratio, so the current flowing through each branch is the same when it is conducting—the initial current. Therefore, by connecting each branch in the target branch to the same output terminal, the output control current is the sum of the initial current and the current output by the target branch. Thus, by using a current branch selection signal, the current branches conducting in the voltage-to-current converter can be automatically adjusted, thereby adjusting the control current output by the converter, and ultimately achieving automatic adjustment of the oscillation frequency of the oscillator.

[0082] The current-controlled oscillator 412 is used to adjust the oscillation frequency based on the control current and generate a feedback clock signal based on the adjusted oscillation frequency.

[0083] Here, the current-controlled oscillator (ICO) is typically a ring oscillator. The input terminal, or first terminal, of the ICO is used to connect a control current. This control current generates an oscillation frequency within the ICO. The frequency of the input clock signal is adjusted to this oscillation frequency, and the clock signal with this oscillation frequency is used as the feedback clock signal.

[0084] The frequency divider 413 is used to divide the feedback clock signal to obtain the recovered clock signal.

[0085] Here, the frequency divider 413 divides the input signal by N to obtain the divided signal, i.e., the restored clock signal; the restored clock signal is sent to the frequency and phase detector of the voltage generation module for comparison with the frequency of the input signal.

[0086] In this embodiment of the application, the voltage-to-current converter, current-controlled oscillator, and frequency divider in the recovery module are used to adjust the oscillation frequency of the current-controlled oscillator by controlling the current, so as to obtain the recovery clock signal at the oscillation frequency. Thus, the frequency of the recovery clock signal can be automatically adjusted by automatically adjusting the control current so that the frequency of the input signal is consistent with the oscillation frequency.

[0087] In some embodiments, by including a comparator and a logic submodule in the voltage detection module, a storage submodule and a counting submodule are also provided, thereby enabling more precise adjustment of the control voltage value, such as... Figure 4C As shown, the voltage detection module 302 further includes: a storage submodule 421 and a counting submodule 422;

[0088] The first end of the storage submodule 421 is connected to the fourth end of the logic submodule 403, and the second end of the storage submodule 421 is connected to the first end of the counting submodule 422.

[0089] The counting submodule 422 is used to count the number of times the control voltage and the preset voltage range are compared to obtain a count value.

[0090] Here, the counting submodule 422 can be implemented using a counter. The counter counts once when the control voltage is compared with the minimum or maximum threshold within the preset voltage range. The counter value can be stored in binary form, with an initial value of N+1 zeros, where N+1 is the number of the first current selection branches. The counter increments by 1 when the first and second comparators perform a comparison. The counting submodule 422 feeds the count value back to the storage submodule, but the storage submodule does not necessarily store the count value. The storage submodule stores the current count value when the numerical relationship between the control voltage and the preset voltage range changes. Each time the counting submodule 422 increments the count, the number of target branches increases. Since the total control current remains constant, the initial current of each target branch decreases. Because the initial current is proportional to the control voltage, the control voltage can be reduced through the count value.

[0091] The storage submodule 421 is used to store the target count value corresponding to the counting submodule and send the target count value to the logic submodule when the numerical relationship between the control voltage and the preset voltage range changes.

[0092] Here, the storage submodule 421 can be implemented using a FIFO memory. When the numerical relationship between the control voltage and the preset voltage range changes, it can be a change in the numerical relationship between the control voltage and the minimum or maximum threshold of the preset voltage range. For example, the control voltage changes from being greater than the maximum threshold to being less than the maximum threshold but greater than the minimum threshold; or from being less than the maximum threshold and greater than the minimum threshold to being less than the minimum threshold. The storage submodule 421 stores the current count value counted by the counting submodule when the numerical relationship changes, and sends the target count value to the logic submodule.

[0093] The target count value includes two values: one is the first count value recorded by the counter when the control voltage changes from being greater than the maximum threshold to being less than the maximum threshold but greater than the minimum threshold; the other is the second count value recorded by the counter when the control voltage changes from being less than the maximum threshold but greater than the minimum threshold to being less than the minimum threshold. After obtaining the count value, the comparison between the control voltage and the preset voltage range is stopped, that is, the counter stops counting.

[0094] In some possible implementations, the logic submodule controls the conduction of the current branch in the voltage-to-current converter by storing two target count values ​​uploaded by the storage submodule. Figure 4C In the above, the storage submodule 421 is further configured to: store a first count value corresponding to the counting submodule when the control voltage decreases from a maximum threshold greater than the preset voltage range to a value less than the maximum threshold and greater than the minimum threshold of the preset voltage range; and store a second count value corresponding to the counting submodule when the control voltage decreases from a value less than the maximum threshold and greater than the minimum threshold to a value less than the minimum threshold; wherein the target count value includes the first count value and the second count value.

[0095] Here, when the control voltage decreases from a maximum threshold greater than the preset voltage range to a value less than the maximum threshold but greater than the minimum threshold of the preset voltage range, it indicates that the CP is now operating in a region with good linearity. Storage submodule 421 stores the current count value of counting submodule 422, i.e., the first count value. When the control voltage decreases from less than the maximum threshold and greater than the minimum threshold to a value less than the minimum threshold, it indicates that the region with good linearity for the CP is about to end. After this point, the charging and discharging current of the CP becomes mismatched, and storage submodule 421 stores the current count value of counting submodule 422, i.e., the second count value.

[0096] The logic submodule 403 is used to generate the current branch selection signal based on the first count value and the second count value.

[0097] Here, the logic submodule 403 calculates the average of two binary numbers (a first count value and a second count value) and generates a current branch selection signal based on this average. Since both the first and second count values ​​are N+1-bit binary values, the average is also an N+1-bit binary value, where each bit corresponds to a branch in the voltage-to-current converter. If this bit is 1, the corresponding branch is turned on; if it is 0, the corresponding branch is turned off. Thus, by storing the first and second count values ​​uploaded by the counter in the storage submodule, the logic submodule can set the current branch selection signal according to the average of these two target count values, ensuring that the control voltage is centered between the two target count values. Since the voltages corresponding to the two target count values ​​are within a preset voltage range, even if the control voltage changes slightly, it will still remain within the preset voltage range, and therefore, the performance of the CDR will not be affected by small changes in the control voltage.

[0098] The logic submodule 403 is used to generate the current branch selection signal based on the target count value.

[0099] Here, after receiving the target count value, the logic submodule 403 calculates the average of the two target count values. Based on this average, a current branch selection signal is generated to determine which current branch needs to be turned on or off. In some possible implementations, ... Figure 8 For example, the storage submodule can be Figure 8 The memory 801 in the memory, the counting submodule can be Figure 8 Counter 802 in the middle.

[0100] In this embodiment, by introducing a storage submodule and a counting submodule into the voltage detection module, the counting submodule records the target count value when the numerical relationship between the control voltage and the preset voltage range changes. The current branch in the control voltage-current converter satisfies the average value between the target count values, thereby making the control voltage work in the center of the preset voltage range, and thus more effectively improving the performance of the CDR.

[0101] In some possible implementations, the conversion from control voltage to control current is achieved by incorporating a second current conversion unit, a second current holding branch, and multiple current selection branches within the voltage-to-current converter. Simultaneously, a voltage-to-current converter with the following structure is configured within the voltage detection module, in addition to including a storage submodule and a counting submodule:

[0102] The voltage-to-current converter in the recovery module includes: a second current conversion unit, a second current holding branch, and a second current selection branch including at least two branches with different structures.

[0103] The input terminal of the second current conversion unit is connected to the second terminal of the voltage generation module 301 for receiving the control voltage; the output terminal of the second current conversion unit is connected to the input terminal of the second current holding branch and the first input terminal of the second current selection branch respectively; the second input terminal of the second current selection branch is connected to the second terminal of the voltage detection module for receiving the current branch selection signal; the output terminal of the second current selection branch is connected to the output terminal of the second current holding branch.

[0104] Here, the second current conversion unit can be implemented using a transistor. This transistor performs current conversion on the applied control voltage to obtain an initial current. In some possible implementations, the structure of the second current conversion unit can be the same as that of the first current conversion unit. For example... Figure 9 As shown, the second current conversion unit may include Figure 9 The second current conversion unit uses transistor 91 and transistor MPA as the root current source. The input terminal of the second current conversion unit is the gate of transistor 91, which can be used as the third terminal of the recovery module to receive the control voltage. The second input terminal of the second current selection branch is connected to the second terminal of the voltage detection module to receive the current branch selection signal. The second input terminal of the second current selection branch can be used as the first terminal of the voltage-to-current converter 411, i.e., the first terminal of the recovery module. In the second current conversion unit, the control voltage is converted by transistor 91 and transistor MPA to obtain the initial current.

[0105] The second current conversion unit can have the same structure as the first current conversion unit, and is used to convert the control voltage into current to obtain the initial current.

[0106] The second current holding branch is used to hold and output the initial current.

[0107] Here, the second current holding branch can use a transistor to hold the initial current obtained from the second current conversion unit. For example... Figure 9 As shown, the second current holding branch may include a transistor MP, which holds the initial current I0 and merges the current output from the control current output terminal with the current output from other branches.

[0108] The second current selection branch includes multiple branches with different structures, which are used to determine the target branch that is in the conducting state among the at least two branches based on the current branch selection signal, and output current through the target branch.

[0109] Here, the control current includes the output current of each branch. Each branch in the second selection branch can hold or amplify the initial current obtained from the first current conversion unit using a transistor and a switch. In some possible implementations, the aspect ratio of the transistor in the second current conversion unit is the same as that of the transistor in the second current holding branch; the aspect ratios of the transistors in the at least two structurally different branches are different and greater than the aspect ratio of the transistor in the second current conversion unit. Here, the aspect ratios of the transistors in the at least two structurally different branches increase exponentially. Thus, because the aspect ratios of the transistors in each branch of the second current conversion unit, the second current holding branch, and the second current selection branch increase exponentially, the current value flowing through each branch also increases exponentially. The output terminal of the second current conversion unit is the port where the gate of transistor MPA and one end of transistor 91 are connected. The converted voltage is output through this terminal. The gate of transistor MPA and one end of transistor 91 are connected to the input terminals of the second current holding branch and the second current selection branch, respectively. This allows the second current holding circuit, in conjunction with transistor 91 in the second current conversion unit, to convert the control voltage to obtain the current of the second current holding circuit. Furthermore, when the switch in the second current selection branch is closed, the second current selection branch, in conjunction with transistor 91 in the second current conversion unit, converts the control voltage to obtain the current when the second current selection branch is on. Figure 9 As shown, the second selection branch includes multiple selection branches. Taking four selection branches as an example: the first branch may include transistor MP0 and switch SW. <0> The second branch may include transistor MP1 and switch SW. <1> The third branch may include transistor MP2 and switch SW. <2> The fourth branch may include a transistor MP3 and a switch SW. <3> In this circuit, the aspect ratios of transistor MP0 in the first branch, transistor MP1 in the second branch, transistor MP2 in the third branch, and transistor MP3 in the fourth branch increase exponentially by a factor of 2, for a total of N+1 branches. Furthermore, the aspect ratio of the transistor in the first branch is the same as that of the transistor in the second current holding branch, thus ensuring that the current output from the first branch is the same as the current output from the second current holding branch.

[0110] In these N+1 selection branches, each selection branch corresponds to a single bit in the current selection signal; this current selection signal is an N+1-bit binary number. For example, if the current selection signal is (0010), then the switch in the second selection is closed, and the other branches are open, meaning the second branch is on. Since the aspect ratio of the transistor in the second branch is twice that of the transistor in the first branch, the output current of the second branch is twice the initial current. Thus, the control current is the sum of the output current of the second current holding branch and the output current of the second branch, i.e., the control current is three times the initial current. In this way, the current branch selection signal can automatically adjust the current branches that are conducting in the voltage-to-current converter, and since the current value in each branch is different, the control current output of the voltage-to-current converter can be adjusted more precisely. This allows for automatic adjustment of the oscillation frequency of the oscillator, thereby improving the performance of the CDR.

[0111] In some embodiments, the voltage generation module compares the frequency difference and the phase difference, and charges and discharges according to the difference signal obtained from the comparison to generate a control voltage. The voltage generation module 303 includes: a difference generation submodule and a charge pump.

[0112] The first terminal of the difference generation submodule is connected to the output terminal of the input signal, and the third terminal of the difference generation submodule is connected to the second terminal of the recovery module; the second terminal of the difference generation submodule is connected to the first terminal of the charge pump; the second terminal of the charge pump is connected to the first terminal of the voltage detection module and the third terminal of the recovery module, respectively.

[0113] The difference generation submodule is used to determine the difference signal between the input signal and the recovered clock signal;

[0114] Here, the first terminal of the difference generation submodule is also the first terminal of the voltage generation module, used to receive the input signal; the third terminal of the difference generation submodule is also the third terminal of the voltage generation module, used to receive the recovery clock signal fed back by the recovery module. By frequency discrimination of the input signal and the recovery clock signal, the frequency difference between the two signals is obtained; and by phase discrimination of the two signals, the phase difference is obtained. The difference signal includes both frequency and phase differences. After obtaining the difference signal, the difference generation submodule sends the difference signal to the charge pump.

[0115] In some possible implementations, the difference generation submodule may include a frequency and phase detector, a phase detector, and a frequency locking unit. The first terminal of the frequency and phase detector is connected to the output terminal of the input signal and to the first terminal of the phase detector. The second terminal of the frequency and phase detector is connected to the second terminal of the recovery module. The third terminal of the frequency and phase detector is connected to the frequency adjustable terminal of the frequency locking unit.

[0116] Here, the first terminal of the frequency and phase detector is connected to the first terminal of the phase detector, both receiving input signals. The second terminal of the frequency and phase detector is connected to the recovery clock signal fed back from the recovery module. The third terminal of the frequency and phase detector is connected to the low-level terminal of the frequency locking unit; when the frequency locking unit is at a low level, frequency locking is not performed.

[0117] The second end of the phase detector is connected to the second end of the recovery module, and the third end of the phase detector is connected to the frequency locking end of the frequency locking unit; the output end of the frequency locking unit is connected to the first end of the charge pump.

[0118] Here, the third terminal of the phase detector is connected to the high level of the frequency locking unit. When the frequency locking unit is at a high level, frequency locking is performed. The second terminal of the phase detector is connected to the second terminal of the recovery module, so that the recovery clock signal fed back by the recovery module can be received when the phase detector is working.

[0119] The frequency and phase detector is used to distinguish the frequency and phase of the input signal and the recovered clock signal to obtain a first phase difference signal, and send the first difference signal to the charge pump.

[0120] Here, during the unlocked frequency phase, i.e., the clock training phase, the frequency and phase detectors are activated and deactivated. The frequency and phase detectors determine whether the clock frequency of the input signal is equal to the clock frequency of the feedback signal. If they are not equal, the control voltage is adjusted until the clock frequency of the input signal equals the clock frequency of the feedback signal, at which point the frequency locking unit locks the frequency. Furthermore, if the frequencies of the input signal and the recovered clock signal are the same, a high-level signal is sent to the frequency locking unit, disconnecting the connection with the frequency locking unit.

[0121] The frequency locking unit is used to lock the frequency of the input signal and connect it to the phase detector when the frequency difference between the input signal and the recovered clock signal is less than a preset difference threshold.

[0122] Here, the preset difference threshold can be a small, custom-set value. For example, the preset difference threshold can be set to 3%, meaning the frequency difference between the input signal and the recovered clock signal is less than 3%. After receiving the high-level signal from the frequency and phase detector, the frequency locking unit locks the frequency of the input signal and connects the frequency locking unit to the phase detector.

[0123] The phase detector is used to detect the phase difference between the input signal and the recovered clock signal after the frequency is locked by the frequency locking unit, obtain the second phase difference signal, and send the second phase difference signal to the charge pump.

[0124] Here, after frequency locking, the phase detector disconnects and the phase detector activates, which performs phase detection on the data in the input signal and the feedback clock signal. The phase detector determines the difference between the phase of the data in the input signal and the phase of the feedback signal, obtaining a phase difference signal, which is then fed back to the charge pump to enable charging and discharging. Thus, before frequency locking, the phase detector performs frequency and phase detection on the input and feedback signals, allowing for a more accurate determination of the difference between them. After frequency locking, the phase detector receives the input signal for data transmission, enabling a more precise recovery of the transmitted data and its clock signal.

[0125] The charge pump is used to charge and discharge based on the difference signal to generate the control voltage.

[0126] Here, if the difference signal indicates that the frequency of the input signal is greater than the frequency of the recovery clock signal (i.e., the oscillation frequency of the current oscillator in the recovery module), then the charge pump charges and generates a control voltage during the charging process. If the difference signal indicates that the frequency of the input signal is less than the frequency of the recovery clock signal, then the charge pump discharges and generates a control voltage during the charging process.

[0127] In this embodiment, by setting a difference generation submodule and a charge pump in the voltage generation module, the difference generation submodule can accurately determine the difference signal between the input signal and the feedback signal, thereby controlling the charge pump to charge and discharge through the difference signal, and generating a control voltage during the charging and discharging process. In this way, by changing the frequency or phase of the feedback signal, the difference signal can be changed, thereby changing the control voltage, realizing automatic adjustment of the control voltage to obtain a control voltage with a small difference in frequency and phase between the input signal and the feedback signal. Thus, using this control voltage in the CDR can improve the working performance of the CDR circuit.

[0128] This application provides a control method for a clock data recovery circuit, applied to the clock data recovery circuit in the above embodiment, and the method can be executed by the processor of a computer device. Figure 5 This is a schematic diagram illustrating the implementation flow of a control method for a clock data recovery circuit provided in an embodiment of this application, as shown below. Figure 5 As shown, the method includes the following steps S501 to S503:

[0129] Step S501: Using the voltage generation module in the clock data recovery circuit, a control voltage is generated based on the input signal and the recovery clock signal fed back by the recovery module in the clock data recovery circuit.

[0130] Here, the clock data recovery circuit can be applied in a driver chip. In this circuit, a voltage generation module determines the frequency and phase differences between the input signal and the recovered clock signal fed back by the recovery module. The frequency and phase differences control the charge pump in the voltage generation module to charge and discharge, and the voltage generated during this process is used as the control voltage. The voltage generation module then sends this control voltage to the voltage detection module in the clock data recovery circuit.

[0131] Step S502: The voltage detection module in the clock data recovery circuit is used to detect whether the control voltage is within the preset voltage range matched by the voltage generation module. If the control voltage is not within the preset voltage range, a current branch selection signal is generated.

[0132] Here, after receiving the control voltage, the voltage detection module, based on the characteristics of the charge pump that generates the control voltage, obtains the minimum and maximum voltage values ​​corresponding to the charge pump operating in a region with good linearity. Using these minimum and maximum voltage values, it obtains the preset voltage range. Based on the numerical relationship between the control voltage and the minimum and maximum voltage values ​​within the preset voltage range, it determines whether the control voltage is within the preset voltage range. If the control voltage is not within the preset voltage range, a current branch selection signal is generated based on the control voltage. This current branch selection signal is then fed back to the recovery module.

[0133] Step S503: The recovery module adjusts the control voltage based on the current branch selection signal to obtain the recovery clock signal until the control voltage is within the preset voltage range, thereby locking the clock data recovery circuit.

[0134] Here, in the recovery module, the control voltage is first converted into current, and the corresponding current branch is connected via a current branch selection signal, thus transmitting the current in the connected current branch. Then, the currents output from all connected current branches are combined to obtain the control current. Finally, the oscillation frequency of the current oscillator in the recovery module is adjusted using this control current, and this oscillation frequency is divided by a frequency divider to obtain the signal after clock data recovery, thereby realizing the clock data recovery of the input signal. In this way, during the process of adjusting the oscillation frequency through the control current, the oscillation frequency and the control current are matched. Therefore, the control voltage is adjusted by using the recovered clock signal generated by this oscillation frequency and the re-input signal to keep the control voltage within a preset voltage range.

[0135] In this embodiment, by introducing a voltage detection module for controlling the voltage Vctrl in the CDR, it is possible to determine whether Vctrl is within a preset voltage range, and then determine whether the charge pump in the voltage generation module is in a working region with good linearity. Based on this, Vctrl is automatically adjusted to a working region with good linearity of the charge pump when Vctrl is too large or too small, thereby improving the working performance of the CDR.

[0136] The following describes the application of the clock data recovery circuit provided in the embodiments of this application in a real-world scenario, taking the introduction of a control voltage detection circuit into the clock data circuit to automatically adjust the control voltage as an example.

[0137] This application provides a clock data recovery circuit, such as... Figure 6 As shown, Figure 6 This is a schematic diagram of the composition structure of the clock data recovery circuit provided in the embodiments of this application. Figure 1 Based on the above, a control voltage detection circuit 601 is added. This detection circuit 601 is connected between CP 13 and V2I 14 to detect the control voltage Vctrl of the clock data recovery circuit. The detection circuit 601 includes: a logic circuit 602 and comparators (COMP0 and COMP1). The positive terminal of COMP1 is connected to the output terminal of CP 13, i.e., connected to the control voltage Vctrl, and the negative terminal is connected to the control voltage Vref1. The output is the comparison value VC1, which is then output to the logic circuit 602. The positive terminal of COMP0 is connected to the output terminal of CP 13, i.e., connected to the control voltage Vctrl, and the negative terminal is connected to the control voltage Vref0. The output is the comparison value VC0, which is also output to the logic circuit 602.

[0138] exist Figure 6In the clock data recovery circuit shown, Vref0 and Vref1 are bandgap references, with their values ​​being the lower and upper limits of the operating region where CP13 has good linearity. Vref0 is less than Vref1. Comparator COMP0 is used to compare the magnitudes of Vctrl and Vref0, and comparator COMP1 is used to compare the magnitudes of Vctrl and Vref1. Figure 6 The circuit structure of V2I 14 is as follows: Figure 7 As shown, the V2I 14 circuit includes: transistors MPA, MP0, MP1, and MP2; switches SW0 and SW1; and transistor 71 corresponding to the control voltage Vctrl. In this circuit, the current I0 increases as Vctrl increases. The aspect ratios of MP0, MP1, and MP2 are the same as those of MPA, so the current in each branch is also I0. Initially, the default value of SW0 is 1, and the default value of SW1 is 0, so the current in Ictrl is 2*I0. When the CDR operates at a high frequency, At this time When switch SW1 is closed, the current in Ictrl is 3*I0. After the CDR stabilizes, Vctrl decreases. When the CDR operates at a low frequency, At this time When switch SW0 is open, the current in Ictrl is I0. After the CDR stabilizes, Vctrl increases. This automatically adjusts Vctrl, ensuring the CP operates within a region of good linearity. However, this method only guarantees that Vctrl is between Vref0 and Vref1 under the current operating conditions. If Vctrl is slightly larger than Vref0 or slightly smaller than Vref1, the Vctrl detection circuit will still consider it within the appropriate range. However, in this case, Vctrl may change due to variations in temperature or power supply noise, potentially falling below Vref0 or exceeding Vref1.

[0139] In the embodiments of this application, in Figure 6 Based on the detection circuit 601, a counter and a memory (FIFO) are added, such as... Figure 8 As shown, in the detection circuit 601, one end of the memory 801 is connected to the logic circuit 602, and the other end of the memory (FIFO) 801 is connected to the counter 802, thereby further optimizing the detection circuit 601. Figure 8 In this process, a counter 802 is used to count the number of comparisons, and a memory 801 is used to store the comparison values ​​and send them to the logic circuit. Based on the logic circuit, the output SW is generated. <n:0>The settings are used to control V2I, thereby obtaining the appropriate Vctrl control voltage. Figure 8 The circuit structure of V2I14 in the example is as follows Figure 9 As shown, the circuit of V2I 14 includes: transistor MPA, transistor MP, transistor MP0, transistor MP1, transistor MP2..., transistor MP... N Switch SW <0> Switch SW <1> Switch SW <2> ..., switch SW <n>And transistor 91 corresponding to the control voltage Vctrl. Figure 9 In the V2I 14 circuit shown, MP has the same aspect ratio as MPA, the current in this branch is I0, and this circuit is always on. MP0 has the same aspect ratio as MPA, MP1 has twice the aspect ratio of MPA, MP2 has four times the aspect ratio of MPA, and so on. N The aspect ratio is 2N times that of MPa. Therefore, the circuits on these branches are I0, 2*I0, ..., 2 N *I0. When the system powers on, counter 802 is set to the default value of 000…0 (N+1 zeros), at which point Ictrl is I0. , Gradually increase the counter value; the Vctrl voltage decreases. Become ,and At that time, the current value of the Fifo storage counter is SW. L Continue increasing the counter value until... Become That is, = At that time, the current value of the Fifo storage counter is SW. H The relationship between the control voltage Vctrl and the counter value, such as... Figure 10 As shown, Figure 10 This is a schematic diagram illustrating the correspondence between the counter and the control voltage provided in the embodiments of this application. Figure 10 In the diagram, the horizontal axis represents the counter value, the vertical axis represents the control voltage value, and the straight line 1001 shows how the control voltage value changes as the counter value changes. Figure 10 It can be seen that at point 1002 on curve 1001, the counter value is SW. L , The control voltage is Vref1. At point 1003 on curve 1001, the counter value is SW. H , The control voltage is Vref0. The SW corresponding to the average value is obtained by averaging the counter values ​​corresponding to points 1002 and 1003 on curve 1001. <n:0>, At this point, the corresponding voltage value is the control voltage Vctrl. Figure 10 In the middle, it is clear that the value of the counter is in SW. L and SW H The settings in between all satisfy the Vctrl detection circuit. The logic circuit receives SW. L and SW H After obtaining the value, take SW. L and SW H The average value is used to set This ensures that Vctrl is positioned between Vref0 and Vref1. Therefore, even if factors such as temperature or power supply noise change, Vctrl remains within a relatively safe range.

[0140] The control method for the clock data recovery circuit provided in this application embodiment can be achieved through, for example... Figure 11 The steps shown are implemented, combined with Figure 11 The steps shown are explained below:

[0141] Step S1101: When the system is powered on or reset, it enters the clock training phase.

[0142] In step S1102, the CDR is reset, and the initial value of the counter is set, and the control voltage is set to be greater than the two reference voltages.

[0143] Here, the initial value of the counter is set to 00…0 (N+1 zeros), and the control voltage Vctrl is set to be greater than Vref1 and Vref0.

[0144] Step S1103: Update the counter value.

[0145] Here, the counter value is incremented by 1.

[0146] Step S1104: Determine whether the control voltage is between the two reference voltages.

[0147] Here, it is determined whether the control voltage Vctrl is greater than Vref0 and less than Vref1. If Vctrl is greater than Vref0 and less than Vref1, proceed to step S1105; otherwise, return to step S1103.

[0148] Step S1105: Use the memory to store the current value SW of the counter. L .

[0149] Step S1106: Continue updating the counter value.

[0150] Here, the counter value is incremented by 1.

[0151] Step S1107: Determine that the control voltage is less than two reference voltages.

[0152] Here, it is determined whether the control voltage Vctrl is less than Vref0 and less than Vref1. If Vctrl is less than Vref0 and less than Vref1, proceed to step S1108; otherwise, return to step S1106.

[0153] Step S1108: Use the memory to store the current value SW of the counter. H And adopt logic circuit based on SW L and SW H Determine SW <n:0>.

[0154] Here, SW <n:0>This is the output value of the logic circuit.

[0155] Step S1109: Lock the CDR.

[0156] Here, the CDR frequency and control voltage are locked. If it is in the vertical cancellation stage of the display panel, that is, whether the display panel has finished displaying the previous frame image and has not yet displayed the next frame image, then return to step S1104, that is, after the screen display ends, check again whether the control voltage is within the preset voltage range to realize the verification of the control voltage.

[0157] Step S1110: Receive data packets and display data.

[0158] In this embodiment, the control voltage Vctrl is adjusted during the vertical blank (V-blank) phase. Because no data transmission occurs during this phase, the screen maintains the state of the previous frame. Adjusting Vctrl during normal display would lead to instability in the displayed image. The Vctrl detection circuit is activated during the V-blank phase and deactivated during normal system operation. After Vctrl adjustment is complete, the CDR (Continuous Data Retrieval) is locked, and the system enters the normal data transmission phase (receiving data packets and displaying data). If the CDR is unlocked, the Vctrl detection circuit reactivates, thus enabling adaptive adjustment of the control voltage Vctrl.

[0159] Based on the foregoing embodiments, this application provides a control device for a clock data recovery circuit. The device includes various units and modules included in each unit, which can be implemented by a processor in a computer device; of course, it can also be implemented by specific logic circuits. In the implementation process, the processor can be a central processing unit (CPU), a microprocessor unit (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA), etc.

[0160] The descriptions of the apparatus embodiments above are similar to those of the method embodiments above, and have similar beneficial effects. In some embodiments, the functions or modules included in the apparatus provided in this disclosure can be used to perform the methods described in the method embodiments above. For technical details not disclosed in the apparatus embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0161] It should be noted that, in the embodiments of this application, if the control method of the clock data recovery circuit described above is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of this application, or the part that contributes to the related technology, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, mobile hard drives, read-only memory (ROM), magnetic disks, or optical disks. Thus, the embodiments of this application are not limited to any specific hardware, software, or firmware, or any combination of hardware, software, and firmware.

[0162] This application provides a computer device including a memory and a processor. The memory stores a computer program that can run on the processor. When the processor executes the program, it implements some or all of the steps in the above-described method.

[0163] This application provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements some or all of the steps in the above-described method. The computer-readable storage medium can be transient or non-transient.

[0164] This application provides a computer program including computer-readable code, wherein when the computer-readable code is executed in a computer device, a processor in the computer device performs some or all of the steps in the above-described method.

[0165] This application provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps in the above-described method. This computer program product can be implemented specifically through hardware, software, or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium; in other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0166] It should be noted that the descriptions of the various embodiments above tend to emphasize the differences between them, while their similarities or commonalities can be referred to interchangeably. The descriptions of the above embodiments of the device, storage medium, computer program, and computer program product are similar to the descriptions of the above method embodiments and have similar beneficial effects. For technical details not disclosed in the embodiments of the device, storage medium, computer program, and computer program product of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0167] It should be noted that, Figure 12 This is a schematic diagram of a hardware entity of a computer device in an embodiment of this application, such as... Figure 12 As shown, the hardware entity of the computer device 1200 includes: a processor 1201, a communication interface 1202, and a memory 1203, wherein:

[0168] Processor 1201 typically controls the overall operation of computer device 1200.

[0169] Communication interface 1202 enables computer devices to communicate with other terminals or servers via a network.

[0170] The memory 1203 is configured to store instructions and applications executable by the processor 1201, and can also cache data to be processed or already processed (e.g., image data, audio data, voice communication data, and video communication data) in the processor 1201 and various modules in the computer device 1200. It can be implemented using flash memory or random access memory (RAM). Data transfer between the processor 1201, the communication interface 1202, and the memory 1203 can be performed via bus 1204.

[0171] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above embodiments of this application are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0172] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0173] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0174] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0175] In addition, each functional unit in the various embodiments of this application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0176] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0177] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, magnetic disks, or optical disks.

[0178] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. < / n>

Claims

1. A clock data recovery circuit, characterized in that, The clock data recovery circuit includes: a voltage generation module, a voltage detection module, and a recovery module; The first terminal of the voltage generation module is connected to an input signal, and the second terminal of the voltage generation module is connected to the first terminal of the voltage detection module and the third terminal of the recovery module, respectively; the second terminal of the voltage detection module is connected to the first terminal of the recovery module, and the second terminal of the recovery module is connected to the third terminal of the voltage generation module. The voltage generation module is used to generate a control voltage based on the input signal and the recovery clock signal fed back by the recovery module; The voltage detection module is used to detect whether the control voltage is within the preset voltage range matched by the voltage generation module, and to generate a current branch selection signal when the control voltage is not within the preset voltage range. The recovery module is used to adjust the control voltage based on the current branch selection signal to obtain a recovery clock signal, and feed the recovery clock signal back to the voltage generation module until the control voltage is adjusted to the preset voltage range, at which point the clock data recovery circuit is locked. The voltage detection module includes a logic submodule, a storage submodule, and a counting submodule; the first terminal of the storage submodule is connected to the fourth terminal of the logic submodule, and the second terminal of the storage submodule is connected to the first terminal of the counting submodule. The counting submodule is used to count the number of times the control voltage and the preset voltage range are compared to obtain a count value; The storage submodule is used to store the target count value corresponding to the counting submodule and send the target count value to the logic submodule when the numerical relationship between the control voltage and the preset voltage range changes. The logic submodule is used to generate the current branch selection signal based on the target count value.

2. The circuit according to claim 1, characterized in that, The voltage detection module further includes: a first comparator and a second comparator; The positive terminal of the first comparator is connected to the second terminal of the voltage generation module, and the negative terminal is connected to the output terminal of the minimum threshold of the preset voltage range; the positive terminal of the second comparator is connected to the second terminal of the voltage generation module, and the negative terminal is connected to the output terminal of the maximum threshold of the preset voltage range; the first terminal of the logic submodule is connected to the output terminal of the first comparator, the second terminal of the logic submodule is connected to the output terminal of the second comparator, and the third terminal of the logic submodule is connected to the first terminal of the recovery module; The first comparator is configured to generate a first comparison value based on the control voltage and the minimum threshold. The second comparator is used to generate a second comparison value based on the control voltage and the maximum threshold. The logic submodule is used to detect whether the control voltage is within the preset voltage range matched by the voltage generation module based on the first comparison value and the second comparison value, and to generate the current branch selection signal if the control voltage is not within the preset voltage range.

3. The circuit according to claim 2, characterized in that, The logic submodule is further configured to determine that the control voltage is not within the preset voltage range when the first comparison value indicates that the control voltage is less than the minimum threshold, or the second comparison value indicates that the control voltage is greater than the maximum threshold, and generate the current branch selection signal based on the first comparison value and the second comparison value.

4. The circuit according to any one of claims 1 to 3, characterized in that, The recovery module includes: a voltage-to-current converter, a current-controlled oscillator, and a frequency divider; The first terminal of the voltage-current converter is connected to the second terminal of the voltage detection module, the second terminal of the voltage-current converter is connected to the first terminal of the current-controlled oscillator, and the third terminal of the voltage-current converter is connected to the second terminal of the voltage generation module; the second terminal of the current-controlled oscillator is connected to the first terminal of the frequency divider, and the second terminal of the frequency divider is connected to the third terminal of the voltage generation module. The voltage-to-current converter is used to perform current conversion on the control voltage based on the current branch selection signal to obtain a control current; The current-controlled oscillator is used to adjust the oscillation frequency based on the control current, and to generate a feedback clock signal based on the adjusted oscillation frequency. The frequency divider is used to divide the feedback clock signal to obtain the recovered clock signal.

5. The circuit according to claim 4, characterized in that, The voltage-to-current converter includes: a first current conversion unit, a first current holding branch, and a first current selection branch including at least two branches with identical structures; The input terminal of the first current conversion unit is connected to the second terminal of the voltage generation module for receiving the control voltage; the output terminal of the first current conversion unit is connected to the input terminal of the first current holding branch and the first input terminal of the first current selection branch; the second input terminal of the first current selection branch is connected to the second terminal of the voltage detection module for receiving the current branch selection signal; the output terminal of the first current selection branch is connected to the output terminal of the first current holding branch. The first current conversion unit is used to convert the control voltage into current to obtain an initial current; The first current holding branch is used to hold and output the initial current; The first current selection branch is used to determine a target branch in the conducting state among the at least two branches based on the current branch selection signal, and output the initial current through the target branch; wherein, the control current includes the initial current output by each branch.

6. The circuit according to claim 5, characterized in that, The transistors in the first current conversion unit, the first current holding branch, and the first current selection branch have the same aspect ratio.

7. The circuit according to claim 1, characterized in that, The storage submodule is further configured to: store a first count value corresponding to the counting submodule when the control voltage decreases from a maximum threshold greater than the preset voltage range to a value less than the maximum threshold and greater than the minimum threshold of the preset voltage range; and store a second count value corresponding to the counting submodule when the control voltage decreases from a value less than the maximum threshold and greater than the minimum threshold to a value less than the minimum threshold; wherein the target count value includes the first count value and the second count value. The logic submodule is used to generate the current branch selection signal based on the first count value and the second count value.

8. The circuit according to claim 1, characterized in that, The voltage-to-current converter in the recovery module includes: a second current conversion unit, a second current holding branch, and a second current selection branch including at least two branches with different structures; The input terminal of the second current conversion unit is connected to the second terminal of the voltage generation module for receiving the control voltage; the output terminal of the second current conversion unit is connected to the input terminal of the second current holding branch and the first input terminal of the second current selection branch; the second input terminal of the second current selection branch is connected to the second terminal of the voltage detection module for receiving the current branch selection signal; the output terminal of the second current selection branch is connected to the output terminal of the second current holding branch.

9. The circuit according to claim 8, characterized in that, The aspect ratio of the transistor in the second current conversion unit is the same as that of the transistor in the second current holding branch; the aspect ratios of the transistors in the at least two structurally different branches are different and are greater than the aspect ratio of the transistor in the second current conversion unit.

10. The circuit according to claim 1, characterized in that, The voltage generation module includes: a difference generation submodule and a charge pump; The first terminal of the difference generation submodule is connected to the output terminal of the input signal, and the third terminal of the difference generation submodule is connected to the second terminal of the recovery module; the second terminal of the difference generation submodule is connected to the first terminal of the charge pump; the second terminal of the charge pump is connected to the first terminal of the voltage detection module and the third terminal of the recovery module, respectively. The difference generation submodule is used to determine the difference signal between the input signal and the recovered clock signal; The charge pump is used to charge and discharge based on the difference signal to generate the control voltage.

11. The circuit according to claim 10, characterized in that, The difference generation submodule includes: a frequency and phase detector, a phase detector, and a frequency locking unit; The first terminal of the frequency and phase detector is connected to the output terminal of the input signal and to the first terminal of the phase detector; the second terminal of the frequency and phase detector is connected to the second terminal of the recovery module; the third terminal of the frequency and phase detector is connected to the frequency adjustable terminal of the frequency locking unit. The second terminal of the phase detector is connected to the second terminal of the recovery module, and the third terminal of the phase detector is connected to the frequency locking terminal of the frequency locking unit; the output terminal of the frequency locking unit is connected to the first terminal of the charge pump. The frequency and phase detector is used to distinguish the frequency and phase of the input signal and the recovered clock signal to obtain a first difference signal, and send the first difference signal to the charge pump. The frequency locking unit is used to lock the frequency of the input signal and connect it to the phase detector when the frequency difference between the input signal and the recovered clock signal is less than a preset difference threshold. The phase detector is used to phase-detect the input signal and the recovered clock signal after the frequency is locked by the frequency-locking unit, obtain a second difference signal, and send the second difference signal to the charge pump; wherein, the difference signal includes the first difference signal and the second difference signal.

12. A control method for a clock data recovery circuit, characterized in that, The method is applied to the clock data recovery circuit of any one of claims 1 to 11, and the method includes: The voltage generation module in the clock data recovery circuit generates a control voltage based on the input signal and the recovered clock signal fed back by the recovery module in the clock data recovery circuit. The voltage detection module in the clock data recovery circuit is used to detect whether the control voltage is within the preset voltage range matched by the voltage generation module. If the control voltage is not within the preset voltage range, a current branch selection signal is generated. The recovery module adjusts the control voltage based on the current branch selection signal to obtain the recovery clock signal until the control voltage is within the preset voltage range, thereby locking the clock data recovery circuit. The step of using the voltage detection module in the clock data recovery circuit to detect whether the control voltage is within the preset voltage range matched by the voltage generation module, and generating a current branch selection signal when the control voltage is not within the preset voltage range, includes: The counting submodule in the voltage detection module counts the number of times the control voltage and the preset voltage range are compared, and a count value is obtained. When the numerical relationship between the control voltage and the preset voltage range changes, the storage submodule in the voltage detection module stores the target count value corresponding to the counting submodule and sends the target count value to the logic submodule. The logic submodule in the voltage detection module generates the current branch selection signal based on the target count value.

13. A display panel, characterized in that, The clock data recovery circuit includes any one of claims 1 to 11.

14. A computer device comprising a memory and a processor, the memory storing a computer program executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method of claim 12.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method of claim 12.

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