Hardware architecture and method for systematic erasure coding
By combining hardware architecture and neural networks, the parity check matrix is dynamically updated, solving the problem of high computational complexity in erasure correction in existing technologies and achieving more efficient erasure correction and computational acceleration.
CN115499019BActive Publication Date: 2026-07-14SAMSUNG ELECTRONICS CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SAMSUNG ELECTRONICS CO LTD
- Filing Date
- 2021-12-14
- Publication Date
- 2026-07-14
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Figure CN115499019B_ABST
Abstract
A hardware architecture and method for systematic erasure decoding is provided. The hardware architecture for systematic erasure decoding includes a first matrix constructor circuit that receives a parity check matrix H of a codeword C and an erasure portion of the codeword C and outputs a matrix H1 of columns of H that are located at erasure coordinates of the code C; a second matrix constructor circuit that receives the matrix H and the erasure portion of the codeword C and outputs a matrix H2 of columns of H that are located at non-erasure coordinates of the code C; a neural network that computes a matrix J1 that is an approximate inverse of the matrix H1. The matrix J1 is used to determine new erasures and new erasure coordinates in the parity check matrix H. The matrices H1 and H2 are updated and the updated H1 is provided as feedback to the first matrix constructor circuit. A calculator circuit recovers erasure coordinates of a product codeword C from the matrix J1, the matrix H2, and a non-erasure portion of the codeword C.
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