Semiconductor components, their fabrication methods, and optical coupling systems

Abstract

A semiconductor component, a method for forming the same, and an optical coupling system are disclosed. An edge coupler with high coupling efficiency and low polarization-dependent loss is disclosed, as well as a method for manufacturing the edge coupler. In one embodiment, a semiconductor component for optical coupling is disclosed. The semiconductor component includes: a substrate; an optical waveguide on the substrate; and multiple layers on the optical waveguide. The multiple layers include multiple coupling pillars disposed at the edges of the semiconductor component. The multiple coupling pillars form an edge coupler configured to optically couple the optical waveguide to an optical fiber located at the edge of the semiconductor component.

Description

Technical Field

[0001] This disclosure relates to an edge coupler and a method for manufacturing the same. Background Technology

[0002] Optical couplers are frequently used to enable communication between light sources and other components, such as photodetectors. For example, edge couplers can be used to redirect light from an optical fiber to a waveguide within a chip. To achieve effective optical coupling between the fiber and the waveguide, the mode dimensions, or mode field diameters (MFDs), need to be matched. To match large optical modes, such as 10 micrometers in an optical fiber, several methods have been used to modify the waveguide mode dimensions, such as by changing the waveguide geometry or by using different materials in the waveguide. However, geometry modifications and / or the addition of dissimilar materials can significantly complicate the manufacturing process. For instance, while undercutting in edge couplers helps match the mode dimensions of the fiber and the waveguide, it can lead to instability and make the manufacturing process unreliable. Furthermore, existing edge couplers cannot simultaneously achieve good coupling efficiency, low polarization-dependent loss, and compatibility with complementary metal-oxide-semiconductor (CMOS) platforms. Summary of the Invention

[0003] A semiconductor component according to an embodiment of the present invention for optical coupling includes: a substrate; an optical waveguide on the substrate; and a plurality of layers on the optical waveguide, wherein the plurality of layers include a plurality of coupling pillars disposed at the edge of the semiconductor component, and the plurality of coupling pillars form an edge coupler, the edge coupler being configured to optically couple the optical waveguide to an optical fiber located at the edge of the semiconductor component.

[0004] An embodiment of the present invention provides a system for optical coupling, comprising: a semiconductor component including: a substrate; an optical waveguide on the substrate; and a plurality of layers on the optical waveguide, wherein the plurality of layers include a plurality of coupling posts disposed at an edge of the semiconductor component; and an optical fiber connected to the edge of the semiconductor component, wherein the plurality of coupling posts optically couple the optical fiber to the optical waveguide.

[0005] An embodiment of the present invention provides a method for forming a semiconductor component, comprising: (a) forming an optical waveguide on a silicon-on-insulator (SOI) substrate; (b) depositing a coupling layer on the optical waveguide and the SOI substrate; (c) depositing a dielectric layer on the coupling layer; (d) etching the dielectric layer to form a metal layer therein; (e) forming an inter-metal dielectric (IMD) layer on the metal layer, wherein the IMD layer serves as an additional coupling layer; and (f) repeating steps (c) to (e) a predetermined number of times to generate a plurality of coupling layers, wherein the plurality of coupling layers include a plurality of coupling pillars disposed at the edge of the semiconductor component, and the plurality of coupling pillars form an edge coupler configured to optically couple the optical waveguide to an optical fiber located at the edge of the semiconductor component. Attached Figure Description

[0006] The aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that the various features are not necessarily drawn to scale. In fact, the dimensions and geometries of the various features can be increased or decreased at will for clarity of illustration.

[0007] Figure 1A Cross-sectional views of an exemplary semiconductor component are shown according to some embodiments of this disclosure.

[0008] Figure 1B A side view of an exemplary semiconductor component is shown according to some embodiments of this disclosure.

[0009] Figure 2 A first exemplary configuration of coupling pillars in a semiconductor component is illustrated according to some embodiments of the present disclosure.

[0010] Figure 3 A second exemplary configuration of coupling pillars in a semiconductor component is illustrated according to some embodiments of this disclosure.

[0011] Figure 4 A third exemplary configuration of coupling pillars in a semiconductor assembly is illustrated according to some embodiments of this disclosure.

[0012] Figure 5 A fourth exemplary configuration of coupling pillars in a semiconductor assembly is illustrated according to some embodiments of the present disclosure.

[0013] Figure 6A-6J Cross-sectional views of exemplary optical waveguides at various stages of the manufacturing process are shown according to some embodiments of this disclosure.

[0014] Figures 7A-7P Cross-sectional views of exemplary semiconductor components including edge couplers at various stages of the manufacturing process are shown according to some embodiments of this disclosure.

[0015] Figure 8 Flowcharts illustrating exemplary methods for forming semiconductor components are shown according to some embodiments of this disclosure.

[0016] [Explanation of Symbols]

[0017] 100-1: Component

[0018] 100-2: Semiconductor Components

[0019] 101: Edge Coupler

[0020] 102: Surface

[0021] 105: Circle

[0022] 106: Outer diameter

[0023] 110, 710: Substrate

[0024] 120, 702, 720, 730: Dielectric layer

[0025] 122: Thickness

[0026] 130, 704, 740, 750, 760, 770: Covering layer

[0027] 132, 134, 136, 600: Optical waveguides

[0028] 138, 148, 158, 168, 230, 350, 450, 550, 745, 748, 755, 765: Layers

[0029] 141, 142, 151, 152, 161, 162, 741, 742, 751, 752, 761, 762: Through holes

[0030] 145, 155, 165: Metal layer

[0031] 147, 149, 157, 159, 167, 169, 177, 179, 187, 189, 197, 199, 215, 222, 224, 232, 234, 315, 322, 324, 332, 334, 355, 415, 422, 424, 432, 434, 442, 444, 455, 515, 532, 534, 555: Coupling pillars

[0032] 190: Fiber optic

[0033] 192: Inner diameter

[0034] 200: First Exemplary Configuration

[0035] 300: Second Exemplary Configuration

[0036] 600-7: Stage

[0037] 610: First Floor

[0038] 615: Second layer

[0039] 620: Third Floor

[0040] 621, 623, 631: Right side portion

[0041] 622, 632: Middle section

[0042] 625: Raster

[0043] 626: Shallow Ditch

[0044] 630, 640: Mask layer

[0045] 633: Left side

[0046] 645: Stacking

[0047] 646: Ditch

[0048] 651: Grating section

[0049] 652: Waveguide section

[0050] 700: Semiconductor Components

[0051] 732, 734, 736: Coupled gratings

[0052] 738: Coupling Layer

[0053] 758, 768: IMD layer

[0054] 800: Demonstration Method

[0055] 802, 804, 806, 808, 810, 811, 812: Operation

[0056] IMD1: Intermetallic Dielectric Layer 1

[0057] IMD2: Intermetallic Dielectric Layer 2

[0058] IMD3: Intermetallic Dielectric Layer 3

[0059] M1: Metal 1

[0060] M2: Metal 2

[0061] M3: Metal 3

[0062] X, Y, Z: Direction Detailed Implementation

[0063] The following disclosure describes various exemplary embodiments for implementing different features of the subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, it should be understood that when a component is referred to as being "connected to" or "coupled to" another component, it may be directly connected to or coupled to another component, or one or more intermediate components may exist.

[0064] Optical applications may use different fiber types and different mode field diameters (MFDs), ranging from 2 to 30 micrometers. Constructing optical coupling interfaces (such as edge couplers) to transmit optical signals between bulky optical fibers and tiny optical waveguides is not straightforward. For example, to match a 10-micrometer optical mode in an optical fiber, the effective index in the waveguide needs to be approximately 1.6.

[0065] In one option, when using silicon waveguides, the waveguide width or thickness is significantly reduced to achieve the desired effective index, as silicon has a very high effective index of approximately 3.5. For example, the silicon waveguide width needs to be less than 100 nanometers or its thickness needs to be less than 150 nanometers to achieve an effective index of 1.6. In this option, a costly mask with high resolution is required to achieve a critical dimension (CD) below 100 micrometers. While the silicon thickness on silicon-on-insulator (SOI) wafers is typically greater than 150 micrometers in photonics applications, SOI silicon needs to be thinned to achieve an effective index of 1.6; however, maintaining a CD below 100 micrometers through thinning processes would be very challenging. Furthermore, since polarization-dependent loss (PDL) is highly dependent on waveguide symmetry, if the waveguide width is not equal to the waveguide height, the PDL will be large and degrade waveguide efficiency.

[0066] In another option, materials with a smaller refractive index than silicon can be used in the waveguide to increase the mode size and achieve an effective index of 1.6. Complementary metal-oxide-semiconductor (CMOS) platforms, especially at mature technology nodes, have very stringent requirements, making it difficult to introduce new materials or process modules. Therefore, both options increase the complexity of the manufacturing process and face the aforementioned challenges.

[0067] This disclosure presents various embodiments of edge couplers that achieve both high coupling efficiency and low polarization-dependent loss (PDL) through CMOS-compatible solutions for designing dielectric layers in standard back-end process (BEOL) fabrication. In some embodiments, the disclosed edge coupler is located at the edge of a photonic assembly and above the optical waveguide of the photonic assembly. The photonic assembly can be formed using CMOS-compatible materials after a CMOS-compatible fabrication process. The edge coupler is configured to optically couple the waveguide to an optical fiber located at the edge of the assembly. The edge coupler may include a plurality of dielectric pillars arranged along a geometry to achieve a mode shape and / or size that matches the mode shape and / or size of the optical fiber, thereby achieving high coupling efficiency. The geometry may be circular, semi-circular, square, rectangular, triangular, or elliptical. In some embodiments, at least some pillars may be located in different inter-metal dielectric (IMD) layers to achieve low PDL without changing the thickness of the waveguide.

[0068] The disclosed pattern-matching solution relaxes process tolerances in manufacturing and provides extensive design flexibility to modify waveguide pattern shape and size, flexible material selection, and waveguide geometry. The disclosed edge coupler is suitable for any silicon photonics application, including but not limited to: transceivers in data centers, biosensors in medicine, LiDAR in automobiles, or angular velocity sensors in the defense or aerospace industries.

[0069] Figure 1A A cross-sectional view of an exemplary semiconductor component 100-1 is shown according to some embodiments of this disclosure. Figure 1B According to some embodiments of this disclosure, corresponding to Figure 1A A side view of an exemplary semiconductor component 100-2 of semiconductor component 100-1 in FIG1. ​​It should be noted that component 100-1 is merely an example and is not intended to limit this disclosure. Therefore, it should be understood that additional functional blocks may be provided or coupled in component 100-1 of FIG1, and some other functional blocks may only be briefly described herein.

[0070] refer to Figure 1AComponent 100-1 includes: a substrate 110; optical waveguides 132, 134, and 136 on the substrate 110; and multiple layers 138, 148, 158, and 168 on the optical waveguides 132, 134, and 136. In some embodiments, the optical waveguides on the substrate 110 include multiple coupling gratings 132, 134, and 136. In some embodiments, at least two coupling gratings have different shapes from each other; and at least one of the coupling gratings includes an active photonic component. For example, the optical waveguide may include raised gratings 132, 136 and / or rectangular grating 134. In some embodiments, at least one of the coupling gratings may be an active photonic component. In some embodiments, at least one of the coupling gratings may be a slab waveguide or a strip waveguide. Figure 1A As shown, coupling gratings 132, 134, and 136 are formed in dielectric layer 120, which is disposed on substrate 110. In some embodiments, substrate 110 comprises silicon, and dielectric layer 120 comprises silicon oxide. Coupling gratings 132, 134, and 136 are formed on silicon-on-insulator (SOI) substrate including substrate 110 and dielectric layer 120.

[0071] like Figure 1A As shown, the semiconductor component 100-1 further includes a cladding layer 130 over the optical waveguides 132, 134, 136 and the dielectric layer 120. In some embodiments, the cladding layer 130 comprises silicon oxide, and a plurality of metal layers 145, 155, 165 are formed within the cladding layer 130. The plurality of layers on the optical waveguides 132, 134, 136 include inter-metal dielectric (IMD) layers disposed between two adjacent metal layers of the plurality of metal layers 145, 155, 165. For example, an IMD1 layer 148 is disposed between metal layer 1 (M1) 145 and metal layer 2 (M2) 155; an IMD2 layer 158 is disposed between metal layer 155 and metal layer 3 (M3) 165; and an IMD3 layer 168 is disposed between metal layer 165 and other metal layers (not shown) above metal layer 165. Figure 1A As shown, layer M1 145 is electrically coupled to photonic component 132 through vias 141 and 142; layer M2 155 is electrically coupled to layer M1 145 through vias 151 and 152; and layer M3 165 is electrically coupled to layer M2 155 through vias 161 and 162. In some embodiments, each of metal layers 145, 155, 165 and vias 141, 142, 151, 152, 161, 162 comprises a metallic material, and each of IMD1 layers 148, 158, 168 comprises a dielectric material, such as polysilicon, silicon nitride, or silicon oxide.

[0072] In some embodiments, the plurality of layers 138, 148, 158, 168 include a plurality of coupling pillars disposed at the edge of the semiconductor component 100-1. Figure 1B As shown, multiple coupling pillars 138, 147, 149, 157, 159...197, 199 are arranged in a pattern on different layers, for example... Figure 1B The pie pattern shown, or half of a pattern, can be circular, square, rectangular, triangular, or elliptical in other examples. For example, coupling pillars 138 are arranged on layer 138; coupling pillars 147 and 149 are arranged on layer IMD1; coupling pillars 157 and 159 are arranged on layer IMD2; coupling pillars 167 and 169 are arranged on layer IMD3; coupling pillars 177 and 179 are arranged on layer IMD4; coupling pillars 187 and 189 are arranged on layer IMD5; and coupling pillars 197 and 199 are arranged on layer IMD6. Figure 1A and Figure 1B As shown, each of the plurality of coupling pillars extends along a lateral direction (X direction) parallel to the top surface of the substrate 110. In some embodiments, the semiconductor component 100-1 can be formed using CMOS-compatible materials after a CMOS-compatible fabrication process, which reduces costs and simplifies the fabrication process. For example, while CMOS fabrication processes can use an IMD layer as an etch stop layer to control the etching process, Figure 1A and Figure 1B The coupling pillars in the process can be formed as a portion of the etch stop layer (near the edge of the semiconductor component 100-1, close to the fiber 190) without altering the main steps of the CMOS fabrication process. Although Figure 1B The diagram shows 13 coupling pillars 138, 147, 149, 157, 159...197, 199, but semiconductor component 100-1 may include any number of coupling pillars in other embodiments.

[0073] In some embodiments, such as Figure 1A and Figure 1B As shown, at least one of the multiple coupling pillars, for example Figure 1A The pillar 138 in the semiconductor component 100-1 has a tapered structure, the width of which gradually increases along the X direction from a first end inside the semiconductor component 100-1 to a second end at the edge of the semiconductor component 100-1. For example... Figure 1A and Figure 1B As shown, at least one of the multiple coupling pillars, for example Figure 1B The pillars 147, 149, 157, 159...197, 199 in the IMD layer have a non-tapered structure, and their width remains constant along the Y direction from a first end within the semiconductor component 100-1 to a second end at the edge of the semiconductor component 100-1. In some embodiments, the pillars in one of the IMD layers may have a tapered structure, while the other pillars of the semiconductor component 100-1 have a non-tapered structure.

[0074] In some embodiments, each of the plurality of coupling pillars may have a cross-section whose shape is one of the following: polygonal, circular, or elliptical. Figure 1B In the example shown, each of the multiple coupling pillars has a rectangular cross-section. The cross-section can be on a surface 102 perpendicular to the X direction.

[0075] like Figure 1B As shown, multiple coupling pillars extend from the same surface 102 perpendicular to the X-direction to the edge of the semiconductor component. The multiple coupling pillars 138, 147, 149, 157, 159...197, 199 form a shape on the same surface 102, which can be circular, semi-circular, square, rectangular, triangular, or elliptical. Figure 1B In the example shown, the shape is a circle 105 with an outer diameter of 106. In some embodiments, the outer diameter is between 0.5 and 1.5 micrometers.

[0076] In some embodiments, the plurality of coupling pillars 138, 147, 149, 157, 159...197, 199 have the same length, measured from the same surface 102 to the edge of the semiconductor component. In other embodiments, such as Figure 1B As shown, multiple coupling pillars 138, 147, 149, 157, 159...197, 199 have different lengths, measured from the same surface 102 to the edge of the semiconductor component; the lengths of the multiple coupling pillars 138, 147, 149, 157, 159...197, 199 gradually decrease as the distance between the respective coupling pillar and the substrate 110 increases. In some embodiments, each pillar has a length between 50 and 150 micrometers.

[0077] Back Figure 1AMultiple coupling posts form an edge coupler 101, configured to optically couple optical waveguides 132, 134, 136 to an optical fiber 190 located at the edge of the semiconductor assembly 100-1. The optical fiber 190 has an inner diameter 192. In some embodiments, the inner diameter 192 is twice the thickness 122 of the oxide layer 120. In some embodiments, the thickness 122 of the oxide layer 120 is between 2 and 3 micrometers; while the inner diameter 192 of the optical fiber 190 is between 8 and 30 micrometers. Therefore, the optical fiber 190 has a larger mode size than the optical waveguides 132, 134, 136. Therefore, the edge coupler 101 acts as a mode size converter, configured to transmit optical signals between the optical waveguides 132, 134, 136 and the optical fiber 190. Because a smaller waveguide width results in a larger mode size, the waveguides at the edge mating with the optical fiber 190 may have a pointed structure, similar to the coupling posts, which would expand the optical mode size at the edge of the semiconductor assembly 100-1. Figure 1A and Figure 1B With the structure shown, the edge coupler 101 can achieve a very high coupling efficiency, and the undercut in the dielectric layer 120 under the coupling pillar 138 at the edge of the semiconductor component 100-1 is not required.

[0078] exist Figure 1A In the example shown, one of the multiple coupling pillars, such as pillar 138, is disposed within the oxide layer 120 and has a tapered structure, the width of which gradually increases along the X direction from a first end within the semiconductor component 100-1 to a second end at the edge of the semiconductor component 100-1. In some embodiments, the cladding layer 130 comprises a dielectric material; and each of the multiple coupling pillars 138, 147, 149, 157, 159...197, 199 comprises a material having a greater refractive index than the dielectric material in the cladding layer 130. The material in each coupling pillar may include at least one of the following: silicon, silicon nitride, silicon carbide, or silicon oxide. In one example, coupling pillar 138 is formed of silicon; coupling pillars 147, 149, 157, 159...197, 199 are made of silicon carbide; and the cladding layer 130 is formed of silicon oxide.

[0079] Long propagation in fiber 190 randomizes light polarization, indicating the simultaneous presence of transverse electric (TE) and transverse magnetic (TM) light. Therefore, the performance of the edge coupler 101 should balance TE and TM functionality. Polarization-dependent loss (PDL), defined by the difference in loss between TE and TM, becomes the fundamental metric for evaluating the performance of the edge coupler 101. In some embodiments, both TE and TM light vary due to the cross-sectional shape of each coupling post and the circular arrangement of the coupling posts on surface 102, making the modes of TE and TM polarization symmetric; that is, the mode shapes of TE and TM appear similar to reduce PDL. In various embodiments, the coupling posts may have different arrangements on surface 102.

[0080] Figure 2 A first exemplary configuration 200 of coupling pillars in a semiconductor component is shown according to some embodiments of this disclosure. Figure 2 As shown, coupling pillar 215 is positioned at layer 210; two coupling pillars 222 and 224 are arranged at layer 220; and two coupling pillars 232 and 234 are arranged at layer 230. The coupling pillars 215, 222, 224, 232, and 234 are positioned to form a semi-circular shape.

[0081] Figure 3 A second exemplary configuration 300 of coupling pillars in a semiconductor component according to some embodiments of the present disclosure is shown. Figure 3 As shown, coupling pillar 315 is disposed at layer 310; two coupling pillars 322 and 324 are disposed at layer 320; two coupling pillars 332 and 334 are disposed at layer 330; and one coupling pillar 355 is disposed at layer 350. The coupling pillars 315, 322, 324, 332, 334, and 355 are disposed at positions that form the shape, with the lower part being semi-circular and the upper part being triangular.

[0082] Figure 4 A third exemplary configuration of coupling pillars in a semiconductor assembly is shown according to some embodiments of this disclosure. Figure 4 As shown, coupling pillar 415 is disposed at layer 410; two coupling pillars 422 and 424 are disposed at layer 420; two coupling pillars 432 and 434 are disposed at layer 430; two coupling pillars 442 and 444 are disposed at layer 440; and coupling pillar 455 is disposed at layer 450. Coupling pillars 415, 422, 424, 432, 434, 442, 444, and 455 are disposed at positions forming a circular shape.

[0083] Figure 5 A fourth exemplary configuration of coupling pillars in a semiconductor assembly is shown, according to some embodiments of this disclosure. For example... Figure 5As shown, coupling pillar 515 is disposed at layer 510; two coupling pillars 532 and 534 are disposed at layer 530; and coupling pillar 555 is disposed at layer 550. The coupling pillars 515, 532, 534, and 555 are disposed at positions forming a rhombus or square shape.

[0084] Figure 2-5 Each layer in can correspond to Figure 1A The dielectric layer or IMD layer shown. The coupling pillars of the semiconductor component form edge couplers, the coupling efficiency of which can vary depending on the arrangement of the coupling pillars in different shapes and / or sizes. For example, by... Figure 4 The circle formed by the coupling pillars 415, 422, 424, 432, 434, 442, 444, and 455 can have an outer diameter of approximately 1 micrometer. In some embodiments, Figure 2-5 Each coupling pillar in the structure can have a width of approximately 0.2 micrometers along the Y direction and a thickness of approximately 0.2 micrometers along the Z direction.

[0085] Figure 6A-6J Cross-sectional views of an exemplary optical waveguide 600 at various stages of the manufacturing process are shown according to some embodiments of this disclosure. Figure 6A This is a cross-sectional view of an optical waveguide 600 according to an embodiment of the present disclosure, including a silicon-on-insulator (SOI) substrate, which, at one of the various stages of fabrication, includes a first layer 610, a second layer 615 disposed on the first layer 610, and a third layer 620 disposed on the second layer 615. The first layer 610 may be formed of silicon or another semiconductor material. The second layer 615 may be formed of silicon oxide or other oxide materials. The third layer 620 may be formed of silicon or another semiconductor material.

[0086] Figure 6B This is a cross-sectional view of an optical waveguide 600 according to some embodiments of the present disclosure, including a mask layer 630 on a silicon layer 620, which is formed at one of the various stages of fabrication. The mask layer 630 on the silicon layer 620 may include a photoresist (PR) material.

[0087] Figure 6C This is a cross-sectional view of an optical waveguide 600 according to some embodiments of the present disclosure, including a middle portion 632 of a mask layer 630, which is formed on a silicon layer 620 at one of the various stages of fabrication. The mask layer 630 is patterned to leave the middle portion 632 on the silicon layer 620, for example by removing a left portion 633 and a right portion 631 based on waveguide lithography and development.

[0088] Figure 6DThis is a cross-sectional view of an optical waveguide 600 according to some embodiments of the present disclosure, including a middle portion 622 of a silicon layer 620, which is formed at one of the various stages of manufacturing. Because a mask layer 630 is patterned to have openings over the left and right portions 623, 621 of the silicon layer 620, the left and right portions 623, 621 exposed by the mask layer are removed by, for example, via, wet, or dry etching processes.

[0089] Figure 6E This is a cross-sectional view of an optical waveguide 600 according to some embodiments of the present disclosure, in which the mask layer 632 is removed at one of the various stages of manufacturing. For example, the mask layer 632 can be removed by resist stripping.

[0090] Figure 6F This is a cross-sectional view of an optical waveguide 600 according to some embodiments of the present disclosure, including another mask layer 640 formed on a remaining silicone layer 622 during one of the various stages of manufacturing. The mask layer 640 coated on the silicone layer 622 may include a photoresist (PR) material. Figure 6F As shown, the coated mask layer 640 not only covers the silicone layer 622, but also covers the left and right sides of the first layer 610.

[0091] Figure 6G This is a cross-sectional view of an optical waveguide 600 according to some embodiments of the present disclosure, which, at one of the various stages of fabrication, includes a plurality of trenches 646 formed on a silicon layer 622. Based on waveguide lithography and development, a mask layer 640 is patterned to include a plurality of stacks 645 formed on the silicon layer 622, for example by etching and mask layer 640 to form a plurality of trenches 646 between the plurality of stacks 645.

[0092] Figure 6H This is a cross-sectional view of an optical waveguide 600 according to some embodiments of the present disclosure, including a plurality of gratings 625 formed at one of the various stages of manufacturing. Because a mask layer 640 is patterned to have openings 646 above a silicon layer 622, exposed portions of the silicon layer 622 are removed, for example by vias, wet or dry etching processes, to form the plurality of gratings 625.

[0093] Figure 6I This is a cross-sectional view of an optical waveguide 600 according to some embodiments of the present disclosure, wherein a mask layer 640 is removed during one of the various stages of manufacturing. For example, the mask layer 640 can be removed by resist stripping. Figure 6I In the illustrated embodiment, silicon layer 622 includes a grating portion 651 and a waveguide portion 652 coupled to the grating portion 651. The grating portion 651 includes a plurality of coupled gratings 625 separated by shallow trenches 626. The shallow trenches 626 can be formed by a single-step etching process.

[0094] Figure 6J This is a cross-sectional view of an optical waveguide 600 according to some embodiments of the present disclosure, showing the removal of the mask layer 640 during one of the various stages of manufacturing. Figure 6J In the illustrated embodiment, silicon layer 622 includes a grating portion 651 and a waveguide portion 652 coupled to the grating portion 651. The grating portion 651 includes a plurality of coupled gratings 625 separated by a deep trench 626. The deep trench 626 may be formed by a multi-step etching process. For example, for Figure 6H The patterned mask layer 640 on the silicon layer 622 shown can be formed by performing at least two or three etching steps on the exposed portion of the silicon layer 622. Figure 6J The multiple high-resolution gratings 625 shown are illustrated.

[0095] According to various embodiments, the disclosed semiconductor components may include, for example: Figure 6I The coupling grating shown is separated by shallow trenches, or as... Figure 6J The coupling grating is shown as being separated by deep trenches. In some embodiments, the coupling grating in the disclosed semiconductor component may vary in shape, height, width, and / or length, for example, based on waveguide lithography and development. Figure 6G The mask layer 640 is located in stages 600-7, when the mask layer 640 follows different patterns and / or when the etching process after stage 600-7 has different durations or depths.

[0096] Figures 7A-7P A cross-sectional view of an exemplary semiconductor component 700 is shown according to some embodiments of the present disclosure, which includes edge couplers at various stages of the manufacturing process. Figure 7A This is a cross-sectional view of a semiconductor component 700, including: a substrate 710; a dielectric layer 720 disposed on the substrate 710; according to some embodiments of this disclosure, at one of the manufacturing stages, a plurality of coupling gratings 732, 734, 736 are disposed on the dielectric layer 720. The substrate 710 may be formed of silicon or another semiconductor material. The dielectric layer 720 may be formed of silicon oxide or other oxide materials. Each of the coupling gratings 732, 734, 736 may be formed of silicon or another semiconductor material.

[0097] Figure 7B This is a cross-sectional view of a semiconductor component 700 according to some embodiments of the present disclosure, including a coupling layer 738 formed on coupling gratings 732, 734, 736 and dielectric layer 720 at one of the manufacturing stages. In some embodiments, coupling layer 738 can be formed by depositing a waveguide material, such as silicon or silicon nitride, on coupling gratings 732, 734, 736 and dielectric layer 720.

[0098] Figure 7CYes, according to a cross-sectional view of a semiconductor component 700 according to some embodiments of this disclosure, one of the manufacturing stages includes the formation of another dielectric layer 730 on a coupling layer 738. In some embodiments, dielectric layer 730 can be formed by depositing a dielectric material, such as silicon oxide, or another oxide material on coupling layer 738. In some embodiments, dielectric layer 720 and dielectric layer 730 can be formed of the same material and are collectively referred to as dielectric layer 702.

[0099] Figure 7D This is a cross-sectional view of a semiconductor component 700 according to some embodiments of the present disclosure, including a cladding layer 740 formed on a dielectric layer 730 at one of the manufacturing stages. In some embodiments, the cladding layer 740 can be formed by depositing a dielectric material, such as silicon oxide or another oxide material, on the dielectric layer 730.

[0100] Figure 7E This is a cross-sectional view of a semiconductor component 700 according to some embodiments of the present disclosure, including vias 741 and 742 formed through a cladding layer 740, a dielectric layer 730, and a coupling layer 738 at one of the manufacturing stages. In some embodiments, vias 741 and 742 may be formed by etching the cladding layer 740, the dielectric layer 730, and the coupling layer 738; and by depositing a metal material to form metal vias 741 and 742.

[0101] Figure 7F This is a cross-sectional view of a semiconductor component 700 according to some embodiments of the present disclosure, showing a metal 1 (M1) layer 745 formed on vias 741, 742 at one of the manufacturing stages. In some embodiments, the M1 layer 745 may be made of a metallic material and formed by etching and deposition processes. Thus, the M1 layer 745 is electrically coupled to a waveguide 732 through the metal vias 741, 742, which may be a photonic component.

[0102] Figure 7G This is a cross-sectional view of a semiconductor component 700 according to some embodiments of the present disclosure, including, at one of the manufacturing stages, an inter-metal dielectric (IMD) layer 748 formed on an M1 layer 745 and a cladding layer 740. In some embodiments, the IMD layer 748 can be formed by depositing a dielectric material, such as silicon nitride, silicon carbide, silicon oxide, or any combination thereof, on the M1 layer 745 and the cladding layer 740.

[0103] Figure 7H This is a cross-sectional view of a semiconductor component 700 according to some embodiments of the present disclosure, showing a cladding layer 750 formed on an IMD layer 748 at one of the various stages of manufacturing. In some embodiments, the cladding layer 750 can be formed by depositing a dielectric material, such as silicon oxide or another oxide material, on the IMD layer 748.

[0104] Figure 7I This is a cross-sectional view of a semiconductor component 700 according to some embodiments of the present disclosure, showing, at one of the manufacturing stages, vias 751 and 752 formed through a coating layer 750 and an IMD layer 748. In some embodiments, vias 751 and 752 may be formed by etching the coating layer 750 and the IMD layer 748; and by depositing a metal material to form metal vias 751 and 752.

[0105] Figure 7J This is a cross-sectional view of a semiconductor component 700 according to some embodiments of the present disclosure, showing a metal 2 (M2) layer 755 formed on vias 751, 752 at one of the manufacturing stages. In some embodiments, the M2 layer 755 may be made of a metallic material and formed by etching and deposition processes. Thus, the M2 layer 755 is electrically coupled to the M1 layer 745 through the metal vias 751 752.

[0106] Figure 7K This is a cross-sectional view of a semiconductor component 700 according to some embodiments of the present disclosure, including an IMD layer 758 formed on an M2 layer 755 and a cladding layer 750 at one of the manufacturing stages. In some embodiments, the IMD layer 758 can be formed by depositing a dielectric material, such as silicon nitride, silicon carbide, silicon oxide, or any combination thereof, on the M2 layer 755 and the cladding layer 750.

[0107] Figure 7L This is a cross-sectional view of a semiconductor component 700 according to some embodiments of the present disclosure, including a cladding layer 760 formed on an IMD layer 758 at one of the manufacturing stages. In some embodiments, the cladding layer 760 can be formed by depositing a dielectric material, such as silicon oxide or another oxide material, on the IMD layer 758.

[0108] Figure 7M This is a cross-sectional view of a semiconductor component 700 according to some embodiments of the present disclosure, showing, at one of the manufacturing stages, vias 761, 762 formed through a cladding layer 760 and an IMD layer 758. In some embodiments, vias 761, 762 may be formed by etching the cladding layer 760 and the IMD layer 758; and by depositing a metal material to form metal vias 761, 762.

[0109] Figure 7N This is a cross-sectional view of a semiconductor component 700 according to some embodiments of the present disclosure, showing a metal 3 (M3) layer 765 formed on vias 761, 762 at one of the manufacturing stages. In some embodiments, the M3 layer 765 may be formed using a metallic material and by etching and deposition processes. Thus, the M3 layer 765 is electrically coupled to the M2 layer 755 through the metal vias 761, 762.

[0110] Figure 7O This is a cross-sectional view of a semiconductor component 700 according to some embodiments of the present disclosure, including an IMD layer 768 formed on an M3 layer 765 and a cladding layer 760 at one of the manufacturing stages. In some embodiments, the IMD layer 768 can be formed by depositing a dielectric material, such as silicon nitride, silicon carbide, silicon oxide, or any combination thereof, on the M3 layer 765 and the cladding layer 760.

[0111] Figure 7P This is a cross-sectional view of a semiconductor component 700 according to some embodiments of the present disclosure, showing a cladding layer 770 formed on an IMD layer 768 at one of the various stages of manufacturing. In some embodiments, the cladding layer 770 can be formed by depositing a dielectric material, such as silicon oxide or another oxide material, on the IMD layer 768. Further metal layers may be formed on the cladding layer 770, but are omitted here for simplicity.

[0112] In some embodiments, cladding layers 740, 750, 760, and 770 may be formed of the same covering material, such as silicon oxide, and are collectively referred to as cladding layer 704. In some embodiments, coupling layer 738 comprises silicon, silicon nitride, or another material having a greater refractive index than the covering material in cladding layer 704. In some embodiments, each of IMD layers 748, 758, and 768 serves as a coupling layer and comprises a material comprising one or more of the following: silicon nitride, silicon carbide, silicon oxide, or another material having a greater refractive index than the covering material in cladding layer 704.

[0113] Figure 8 A flowchart illustrating an exemplary method 800 for forming a semiconductor component according to some embodiments of the present disclosure, such as the semiconductor component shown in any of Figures 1-7P. In operation 802, an optical waveguide is formed on a silicon-on-insulator (SOI) substrate. In operation 804, a coupling layer is deposited on the optical waveguide and the SOI substrate. In operation 806, a dielectric layer is deposited on the coupling layer. In operation 808, the dielectric layer is etched to form a metal layer within the dielectric layer. In operation 810, an inter-metal dielectric (IMD) layer is formed on the metal layer, wherein the IMD layer serves as an additional coupling layer. In operation 811, it is determined whether the number of coupling layers is less than a predetermined threshold. If yes, the process returns to operation 806 to deposit an additional dielectric layer. If not, the process proceeds to operation 812 to deposit more coating material. Figure 8 The order of operations can be changed depending on the embodiments of this disclosure.

[0114] In one embodiment, a semiconductor component for optical coupling is disclosed. The semiconductor component includes: a substrate; an optical waveguide on the substrate; and multiple layers on the optical waveguide. The multiple layers include multiple coupling pillars disposed at the edges of the semiconductor component. The multiple coupling pillars form an edge coupler configured to optically couple the optical waveguide to an optical fiber located at the edge of the semiconductor component.

[0115] In some embodiments of the invention, each of the plurality of coupling pillars extends along a lateral direction parallel to the top surface of the substrate. In some embodiments of the invention, at least one of the plurality of coupling pillars has a tapered structure, the width of which gradually increases along the lateral direction from a first end within the semiconductor assembly to a second end at the edge of the semiconductor assembly; and at least one of the plurality of coupling pillars has a non-tapered structure, the width of which remains constant along the lateral direction from the first end within the semiconductor assembly to the second end at the edge of the semiconductor assembly. In some embodiments of the invention, each of the plurality of coupling pillars has a cross-section, the shape of which is one of a polygon, a circle, or an ellipse; and the cross-section is on a surface perpendicular to the lateral direction. In some embodiments of the invention, the plurality of coupling pillars extend from the same surface perpendicular to the lateral direction to the edge of the semiconductor assembly; the positions of the plurality of coupling pillars on the same surface form a shape; and the shape includes at least one of the following: circular, semi-circular, square, rectangular, triangular, or elliptical. In some embodiments of the invention, the plurality of coupling pillars have the same length, the length being measured from the same surface to the edge of the semiconductor assembly. In some embodiments of the invention, the plurality of coupling pillars have different lengths, the lengths being measured from the same surface to the edge of the semiconductor component; and the lengths of the plurality of coupling pillars gradually decrease as the distance between the respective coupling pillar and the substrate increases. In some embodiments of the invention, the semiconductor component further includes an oxide layer on the substrate, wherein the optical waveguide is disposed within the oxide layer; and one of the plurality of coupling pillars is disposed within the oxide layer and has a tapered structure, the width of which gradually increases along the lateral direction from a first end inside the semiconductor component to a second end at the edge of the semiconductor component. In some embodiments of the invention, the inner diameter of the optical fiber is greater than twice the thickness of the oxide layer; the mode size of the optical fiber is larger than that of the optical waveguide; and the edge coupler is configured as a mode size converter for transmitting optical signals between the optical waveguide and the optical fiber. In some embodiments of the invention, the optical waveguide includes a plurality of coupling gratings on the substrate; at least two of the plurality of coupling gratings have different shapes from each other; and at least one of the plurality of coupling gratings includes an active photonic component. In some embodiments of the invention, the semiconductor component is formed using CMOS-compatible materials after a CMOS-compatible process.In some embodiments of the present invention, the semiconductor component further includes: a cladding layer over the optical waveguide; and a plurality of metal layers formed within the cladding layer, wherein at least one of the plurality of layers is an inter-metal dielectric (IMD) layer disposed between two adjacent metal layers of the plurality of metal layers. In some embodiments of the present invention, the cladding layer comprises a dielectric material; each of the plurality of coupling pillars comprises a material with a refractive index greater than that of the dielectric material; and the material in each coupling pillar comprises at least one of the following: silicon, silicon nitride, silicon carbide, or silicon oxide.

[0116] In another embodiment, a system for optical coupling is disclosed. The system includes a semiconductor component and an optical fiber. The semiconductor component includes a substrate; an optical waveguide on the substrate; and multiple layers on the optical waveguide. The multiple layers include multiple coupling posts disposed at the edges of the semiconductor component. The optical fiber is connected to the edges of the semiconductor component. The multiple coupling posts optically couple the optical fiber to the optical waveguide.

[0117] In some embodiments of the invention, the mode size of the optical fiber is larger than that of the optical waveguide; and the edge coupler is configured as a mode size converter for transmitting optical signals between the optical waveguide and the optical fiber. In some embodiments of the invention, each of the plurality of coupling pillars extends along a lateral direction parallel to the top surface of the substrate; the plurality of coupling pillars extend from the same surface perpendicular to the lateral direction to the edge of the semiconductor component; the positions of the plurality of coupling pillars on the same surface form a shape; and the shape includes at least one of the following: circular, semi-circular, square, rectangular, triangular, or elliptical. In some embodiments of the invention, the optical waveguide includes a plurality of coupling gratings on the substrate; at least two of the plurality of coupling gratings have different shapes from each other; and at least one of the plurality of coupling gratings includes an active photonic component.

[0118] In another embodiment, a method for forming a semiconductor component is disclosed. The method includes: (a) forming an optical waveguide on a silicon-on-insulator (SOI) substrate; (b) depositing a coupling layer on the optical waveguide and the SOI substrate; (c) depositing a dielectric layer on the coupling layer; (d) etching the dielectric layer to form a metal layer within the dielectric layer; (e) forming an inter-metal dielectric (IMD) layer on the metal layer, wherein the IMD layer serves as an additional coupling layer; and (f) repeating steps (c) through (e) a predetermined number of times to generate a plurality of coupling layers. The plurality of coupling layers include a plurality of coupling pillars disposed at the edge of the semiconductor component. The plurality of coupling pillars form an edge coupler configured to optically couple the optical waveguide to an optical fiber located at the edge of the semiconductor component.

[0119] In some embodiments of the invention, each dielectric layer deposited on the coupling layer comprises a dielectric material; each of the plurality of coupling pillars comprises a material with a refractive index greater than that of the dielectric material; and the material in each of the coupling pillars comprises at least one of silicon, silicon nitride, silicon carbide, or silicon oxide. In some embodiments of the invention, the optical waveguide comprises a plurality of gratings formed using silicon; and at least two of the plurality of gratings have shapes different from each other.

[0120] While various embodiments of this disclosure have been described above, it should be understood that they are presented by way of example only and not as limitations. Similarly, various figures may depict exemplary architectures or configurations provided to enable those skilled in the art to understand the exemplary features and functionality of this disclosure. However, those skilled in the art will understand that this disclosure is not limited to the exemplary architectures or configurations shown, but can be implemented using various alternative architectures and configurations. Furthermore, as those skilled in the art will understand, one or more features in one embodiment may be combined with one or more features in another embodiment described herein. Therefore, the breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above.

[0121] It should also be understood that any reference to components using names such as “first”, “second”, etc., herein does not generally limit the number or order of those components. Rather, these names are used herein as convenient means of distinguishing two or more components or instances of components. Therefore, references to first and second components do not imply that an apparatus can only use two components, or that the first component must somehow precede the second component.

[0122] Furthermore, those skilled in the art will understand that information and signals can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, and symbols, such as those mentioned above, can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0123] Those skilled in the art will further understand that any of the various illustrative logic blocks, modules, processors, devices, circuits, methods, and functions described in connection with the aspects disclosed herein can be implemented by electronic hardware (e.g., digital implementation, analog implementation, or a combination of both), firmware, program or design code in various forms containing instructions (which may be referred to herein as "software" or "software module"), or these technologies.

[0124] To clearly illustrate this interchangeability of hardware, firmware, and software, various illustrative components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. Whether such functionality is implemented as hardware, firmware, or software, or a combination of these technologies, depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art can implement the described functionality in various ways for each specific application, but such implementation decisions will not deviate from the scope of this disclosure. According to various embodiments, processors, components, elements, circuits, structures, machines, modules, etc., can be configured to perform one or more of the functions described herein. As used herein with respect to a specified operation or function, the term "configured to" or "configured as" means physically constructed, programmed, arranged, and / or formatted to perform the specified operation or function.

[0125] Furthermore, those skilled in the art will understand that the various illustrative logic blocks, modules, components, elements, and circuits described herein may include digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic components, or any combination thereof. Logic blocks, modules, and circuits may also include antennas and / or transceivers for communication with various elements within a network or component. A processor programmed to perform these functions will be a specially programmed, or dedicated, processor and may be implemented as a combination of computing components, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other suitable architecture to perform the functions described herein.

[0126] If implemented in software, these functions can be stored as one or more instructions or code on a computer-readable medium. Therefore, the steps of the methods or algorithms disclosed herein can be implemented as software stored on a computer-readable medium. Calculator-readable media include calculator storage media and communication media, including any media capable of transferring calculator programs or code from one place to another. Storage media can be any available media accessible to the calculator. By way of example and not limitation, such calculator-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage, disk storage or other magnetic storage components, or any other media required for storage. Program code appears in the form of instructions or data structures and can be accessed by the calculator.

[0127] In this document, the term "module" as used herein refers to software, firmware, hardware, and any combination of these components for performing the relevant functions described herein. Furthermore, for the purposes of discussion, various modules are described as discrete modules; however, it will be apparent to those skilled in the art that two or more modules can be combined to form a single module that performs the relevant functions according to embodiments of this disclosure.

[0128] Various modifications to the embodiments described in this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the embodiments shown herein, but is accorded the broadest scope consistent with the novel features and principles disclosed herein.

Claims

1. A semiconductor component for optical coupling, characterized in that, include: Substrate; Optical waveguide, on the substrate; as well as Multiple layers, on top of the optical waveguide, The plurality of layers include a plurality of coupling pillars disposed at the edge of the semiconductor component, and The plurality of coupling pillars form an edge coupler, which is configured to optically couple the optical waveguide to an optical fiber located at the edge of the semiconductor assembly. The optical waveguide includes a plurality of coupling gratings on the substrate; At least two of the plurality of coupled gratings have different shapes from each other; and At least one of the plurality of coupled gratings includes an active photonic component.

2. The semiconductor component according to claim 1, wherein, Each of the plurality of coupling pillars extends in a transverse direction parallel to the top surface of the substrate.

3. The semiconductor component according to claim 2, wherein, At least one of the plurality of coupling pillars has a tapered structure, the width of which gradually increases along the lateral direction from a first end within the semiconductor component to a second end at the edge of the semiconductor component; and At least one of the plurality of coupling pillars has a non-tapered structure, the width of which remains constant along the lateral direction from the first end within the semiconductor assembly to the second end at the edge of the semiconductor assembly.

4. The semiconductor component according to claim 2, wherein, Each of the plurality of coupling pillars has a cross-section, the shape of which is one of polygonal, circular, or elliptical; and The cross-section is on a surface perpendicular to the lateral direction.

5. The semiconductor component according to claim 2, wherein, The plurality of coupling pillars extend from the same surface perpendicular to the lateral direction to the edge of the semiconductor assembly; The plurality of coupling pillars are positioned on the same surface to form a shape; and The shape includes at least one of the following: circle, semicircle, square, rectangle, triangle or ellipse.

6. The semiconductor component according to claim 5, wherein, The plurality of coupling pillars have the same length, which is measured from the same surface to the edge of the semiconductor assembly.

7. The semiconductor component according to claim 5, wherein, The plurality of coupling pillars have different lengths, the lengths being measured from the same surface to the edge of the semiconductor assembly; and As the distance between the corresponding coupling pillar and the substrate increases, the length of the plurality of coupling pillars gradually decreases.

8. The semiconductor component of claim 2, further comprising an oxide layer on the substrate, wherein, The optical waveguide is disposed within the oxide layer; One of the plurality of coupling pillars is disposed within the oxide layer and has a tapered structure, the width of which gradually increases along the lateral direction from a first end inside the semiconductor component to a second end at the edge of the semiconductor component.

9. The semiconductor component of claim 8, further comprising an oxide layer on the substrate, wherein, The inner diameter of the optical fiber is greater than twice the thickness of the oxide layer; The mode size of the optical fiber is larger than that of the optical waveguide; and The edge coupler is configured as a mode-size converter to transmit optical signals between the optical waveguide and the optical fiber.

10. The semiconductor component according to claim 1, wherein, The semiconductor component is formed using CMOS-compatible materials after a CMOS-compatible process.

11. The semiconductor component according to claim 1, wherein, The semiconductor component further includes: a cladding layer on the optical waveguide; and Multiple metal layers are formed within the cladding layer, wherein at least one of the multiple layers is an inter-metal dielectric (IMD) layer disposed between two adjacent metal layers of the multiple metal layers.

12. The semiconductor component of claim 11, wherein, The coating layer includes a dielectric material; Each of the plurality of coupling pillars comprises a material with a refractive index greater than that of the dielectric material; as well as The material in each coupling post includes at least one of the following: silicon, silicon nitride, silicon carbide, or silicon oxide.

13. An optical coupling system, characterized in that, include: Semiconductor components include: Substrate; Optical waveguide, on the substrate; and Multiple layers, on the optical waveguide, wherein the multiple layers include multiple coupling pillars disposed at the edges of the semiconductor component; and An optical fiber is connected to the edge of the semiconductor component, wherein the plurality of coupling pillars optically couple the optical fiber to the optical waveguide. The optical waveguide includes a plurality of coupling gratings on the substrate; At least two of the plurality of coupled gratings have different shapes from each other; and At least one of the plurality of coupled gratings includes an active photonic component.

14. The optical coupling system according to claim 13, wherein The mode size of the optical fiber is larger than that of the optical waveguide; and The plurality of coupling pillars form an edge coupler, which acts as a mode-size converter and is configured to transmit optical signals between the optical waveguide and the optical fiber.

15. The optical coupling system according to claim 13, wherein, Each of the plurality of coupling pillars extends in a lateral direction parallel to the top surface of the substrate; The plurality of coupling pillars extend from the same surface perpendicular to the lateral direction to the edge of the semiconductor assembly; The plurality of coupling pillars are positioned on the same surface to form a shape; and The shape includes at least one of the following: circle, semicircle, square, rectangle, triangle or ellipse.

16. A method for forming a semiconductor component, characterized in that, include: (a) Forming an optical waveguide on an insulating silicon-coated substrate; (b) Depositing a coupling layer on the optical waveguide and the insulating silicon-coated substrate; (c) Deposit a dielectric layer on the coupling layer; (d) Etching the dielectric layer to form a metal layer in the dielectric layer; (e) An intermetallic dielectric layer is formed on the metal layer, wherein the intermetallic dielectric layer serves as an additional coupling layer; as well as (f) Repeat steps (c) through (e) a predetermined number of times to generate multiple coupling layers, wherein: The plurality of coupling layers include a plurality of coupling pillars disposed at the edge of the semiconductor component, and The plurality of coupling pillars form an edge coupler, which is configured to optically couple the optical waveguide to an optical fiber located at the edge of the semiconductor assembly. The optical waveguide includes a plurality of gratings formed using silicon; and At least two of the plurality of gratings have shapes that are different from each other.

17. The method of forming a semiconductor component according to claim 16, wherein, Each dielectric layer deposited on the coupling layer includes a dielectric material; Each of the plurality of coupling pillars comprises a material with a refractive index greater than that of the dielectric material; as well as The material in each of the coupling pillars includes at least one of the following: silicon, silicon nitride, silicon carbide, or silicon oxide.

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