Multiple-input serial adder
By designing a multi-input serial adder functional unit, the problem of low efficiency in implementing serial adders in FPGAs was solved, realizing efficient utilization of logic units and construction of mathematical functions.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GOOGLE LLC
- Filing Date
- 2022-10-28
- Publication Date
- 2026-06-02
AI Technical Summary
Existing programmable devices such as FPGAs are inefficient when implementing serial adders, resulting in underutilization of logic units and excessive burden on wiring networks.
Design a multi-input serial adder functional unit that accumulates more than two serial inputs and generates a single serial output through a full adder circuit. Utilize programmable interconnects and registers to maintain the carry state and implement a logic tree structure, suitable for field-programmable gate arrays (FPGAs).
It improves the logic utilization of programmable devices, reduces wiring burden, and allows the construction of various mathematical functions such as matrix multiplication.
Smart Images
Figure CN115509488B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to a multi-input serial adder. Background Technology
[0002] Mapping mathematical functions to programmable devices, such as field-programmable gate arrays (FPGAs), can achieve good latency results. However, some programmable devices, such as FPGAs, can be inefficient in implementing basic logic units such as serial adders. For example, a serial adder with two main inputs can consume the entire 6-input lookup table (LUT) in an FPGA. Therefore, the logic of the programmable device can be underutilized, and the wiring of the programmable device can become overwhelmed by the number of networks required for the circuit implementation. Summary of the Invention
[0003] This document generally discloses an implementation of a functional unit for use in logic circuits capable of accumulating more than two serial inputs and providing a serial summation output. The serial inputs and outputs can be single-bit or multi-bit buses. The functional unit can be implemented as a logic tree, where any two points are connected by a path. The functional unit can be incorporated into the processing unit of a programmable device such as a field-programmable gate array (FPGA) to allow the construction of various mathematical functions, such as matrix multiplication.
[0004] This disclosure provides a programmable device including one or more processing units coupled to a programmable interconnect. The processing units include a plurality of full adder circuits configured to collectively receive at least three serial inputs and generate a single serial output, the single serial output being the sum of the at least three serial inputs. A carry state is maintained among the plurality of full adder circuits.
[0005] In the example, the number of inputs to the processing unit is one more than the number of multiple full adder circuits. In another example, each serial input is a multi-bit input. In yet another instance, each full adder circuit includes three single-bit inputs, a sum output, and a carry output.
[0006] In yet another example, the sum output of the full adder circuit is the input of another full adder circuit. In yet another example, the carry output of the full adder circuit is held in a register so that it can be used as the carry input of the full adder circuit in subsequent loops. In yet another instance, the carry output of the full adder circuit is the input of another full adder circuit.
[0007] In yet another example, the programmable interconnect includes at least one of a plurality of logic gates or multiplexers. In yet another example, the programmable interconnect includes one or more registers.
[0008] Another aspect of this disclosure provides a method for operating a processing unit of a programmable device. The processing unit includes a plurality of full adder circuits. The method includes: receiving at least three serial inputs jointly by the plurality of full adder circuits; generating a single serial output by the plurality of full adder circuits, the single serial output being a sum of the at least three serial inputs; and maintaining a carry state among the plurality of full adder circuits.
[0009] In the example, the number of inputs to the processing unit is one more than the number of multiple full adder circuits. In another example, each full adder circuit includes three single-bit inputs, a sum output, and a carry output.
[0010] In yet another example, the method further includes inputting the sum output of the full adder circuit to another full adder circuit. In yet another example, the method further includes holding the carry output of the full adder in a register for application as the carry input of the full adder circuit in a subsequent loop. In yet another example, the method further includes inputting the carry output of the full adder circuit to another full adder circuit.
[0011] Another aspect of this disclosure provides a non-transitory computer-readable medium for storing instructions that, when executed by one or more programmable devices, cause the one or more programmable devices to perform operations including: receiving at least three serial inputs using a plurality of full adder circuits; generating a single serial output using the plurality of full adder circuits, the single serial output being the sum of the at least three serial inputs; and maintaining a carry state among the plurality of full adder circuits.
[0012] In one example, the operation further includes inputting the sum output of the full adder circuit to another full adder circuit. In another example, the operation further includes holding the carry output of the full adder in a register for application as the carry input of the full adder circuit in a subsequent loop. In yet another example, the operation further includes inputting the carry output of the full adder circuit to another full adder circuit.
[0013] In yet another example, the at least three serial inputs are received jointly by multiple registers in a programmable interconnect. Attached Figure Description
[0014] Figure 1 A block diagram depicts an example functional unit having three serial inputs and one serial output according to aspects of this disclosure.
[0015] Figure 2 A block diagram depicts another example functional unit having three serial inputs and one serial output according to aspects of this disclosure.
[0016] Figure 3A block diagram depicts an example functional unit having four serial inputs and one serial output according to aspects of this disclosure.
[0017] Figure 4 A block diagram depicts an example functional unit having five serial inputs and one serial output according to aspects of this disclosure.
[0018] Figure 5 A block diagram depicts another example functional unit with five serial inputs and one serial output according to aspects of this disclosure.
[0019] Figure 6 A block diagram depicts another example functional unit having six serial inputs and one serial output according to aspects of this disclosure.
[0020] Figure 7 A block diagram depicts a functional unit having three serial inputs of multiple bits and one serial output of multiple bits according to aspects of this disclosure.
[0021] Figure 8 A block diagram depicting an example programmable device including a programmable interconnect for masking bits, according to aspects of this disclosure.
[0022] Figure 9 A block diagram depicting an example programmable device including registers in a programmable interconnect for masking bits, according to aspects of this disclosure.
[0023] Figure 10 A block diagram depicting an example programmable device including a programmable interconnect for multiplexing, according to aspects of this disclosure.
[0024] Figure 11 A block diagram depicting an example programmable device including a programmable interconnect for multi-layer multiplexing, according to aspects of this disclosure.
[0025] Figure 12 A block diagram depicting an example environment for implementing functional units and / or programmable devices according to aspects of this disclosure. Detailed Implementation
[0026] This document generally discloses implementations of functional units for use in logic circuits, said functional units being capable of accumulating more than two serial inputs and providing a serial summation output. The serial inputs and outputs can be single-bit or multi-bit buses. The functional unit can be implemented as a logic tree, where any two points are connected by a path. The functional unit can be incorporated into the processing unit of a programmable device such as a field-programmable gate array (FPGA) to allow the construction of various mathematical functions, such as matrix multiplication.
[0027] Figure 1A block diagram depicts an example functional unit 100 having three serial inputs 102 and one serial output 104. Functional unit 100 may include a first full adder 106, a second full adder 108, a first register 110, and a second register 112. Each full adder may include three inputs and two outputs. One of the three inputs may be referred to as a carry input. The outputs may be a sum output and a carry output. The carry output may be held in a register so that it can be applied as a carry input to its corresponding adder in subsequent summation loops. The sum output may be the sum of the three inputs.
[0028] The two inputs of the first full adder 106 can be two of the three serial inputs 102, and the input of the second full adder 108 can be the third serial input 102. The carry output 114 of the first full adder 106 can be stored in the first register 110 for use as the carry input 116 of the first full adder 106 in subsequent loops. The sum output 118 of the first full adder 106 can be one of the three inputs of the second full adder 108. The carry output 120 of the second full adder 108 can be stored in the second register 112 for use as the carry input 122 of the second full adder 108 in subsequent loops. The sum output of the second full adder 108 can be a serial output 104, which outputs the sum of the three serial inputs 102.
[0029] Figure 2 A block diagram depicts another example functional unit 200 having three serial inputs 202 and one serial output 204. Functional unit 200 may include a first full adder 206, a second full adder 208, a first register 210, and a second register 212. The carry output of any full adder can be held in a register to be applied as a carry input to another full adder.
[0030] The two inputs of the first full adder 206 can be two of the three serial inputs 202, and the input of the second full adder 208 can be the third serial input 202. The carry output 214 of the first full adder 206 can be stored in the first register 210 to be applied to the second full adder 208 as carry input 216 in a subsequent loop. The sum output 218 of the first full adder 206 can be one of the three inputs of the second full adder 208. The carry output 220 of the second full adder 208 can be stored in the second register 212 to be applied to the first full adder 208 as carry input 222 in a subsequent loop. The sum output of the second full adder 208 can be a serial output 204, which outputs the sum of the three serial inputs 202.
[0031] A functional unit can include any number of serial inputs greater than two and one serial output. The number of full adders in a functional unit can be one less than the number of serial inputs. The number of registers in a functional unit can be less than the number of serial inputs. A functional unit can be a balanced or unbalanced tree of full adders, such that the number of levels of the full adders can be at most equal to the number of full adders in the functional unit. The following... Figures 3 to 6 Example functional units for four, five, and six serial inputs are provided to further illustrate the concepts and this disclosure is not limited to the examples shown.
[0032] Figure 3 A block diagram depicts an example functional unit 300 having four serial inputs 302 and one serial output 304. Functional unit 300 includes a first full adder 306, a second full adder 308, a third full adder 310, a first register 312, a second register 314, and a third register 316. In one example, for each full adder, the carry output can be held in a register to be applied as a carry input to its corresponding adder in subsequent loops. In another example, not shown, the carry output of the full adder can be held in a register to be applied as a carry input to different full adders.
[0033] The first full adder 306 and the third full adder 310 can form a three-serial-input adder, such as Figure 1 As described in the text. The second full adder 308 and the third full adder 310 can also form a three-serial-input adder.
[0034] The two inputs of the first full adder 306 can be two of the four serial inputs 302, and the two inputs of the second full adder can be the other two of the four serial inputs 302. The carry output 318 of the first full adder 306 can be held in the first register 312 for use as the carry input 320 of the first full adder 306 in subsequent loops. The sum output 322 of the first full adder 306 can be the first input of the three inputs of the third full adder 310. The carry output 324 of the second full adder 308 can be held in the second register 314 for use as the carry input 326 of the second full adder 308 in subsequent loops. The sum output 328 of the second full adder 308 can be the second input of the three inputs of the third full adder 310. The carry output 330 of the third full adder 310 can be held in the third register 316 for use as the carry input 332 of the third full adder 310 in subsequent loops. The summation output of the third full adder 310 can be a serial output 304, which can output the sum of four serial inputs 302.
[0035] The functional unit 300 with four serial inputs includes two layers of full adders, wherein the first layer includes a first full adder 306 and a second full adder 308, and the second layer includes a third full adder 310. Although not shown, another example of the functional unit 300 can include three layers with one full adder, wherein the first layer includes a first full adder 306, the second layer includes a second full adder 308, and the third layer includes a third full adder 310. Here, the sum output 322 of the first full adder 306 can be an input of the second full adder 308, and the sum output 328 of the second full adder 308 can be an input of the third full adder 310. The first full adder 306 can include two of the serial inputs 302, the second full adder 308 can include one of the serial inputs 302, and the third full adder 310 can include a fourth serial input 302.
[0036] Figure 4 A block diagram depicts an example functional unit 400 with five serial inputs 402 and one serial output 404. Functional unit 400 includes four full adders 406 to 412 and four registers 414 to 420. In one example, for each full adder, the carry output can be held in a register to be applied as a carry input to its corresponding adder in subsequent loops. In another example, not shown, the carry output of the full adder can be held in a register to be applied as a carry input to different full adders.
[0037] The first full adder 406, the second full adder 408, and the third full adder 410 can form a four-serial-input adder, such as Figure 3 As depicted in the diagram. The third full adder 410 and the fourth full adder 412 can form a three-serial-input adder, such as... Figure 1 As depicted in the text.
[0038] The two inputs of the first full adder 406 can be two of the five serial inputs 402, the two inputs of the second full adder 408 can be the other two of the five serial inputs 402, and the input of the fourth full adder 412 can be the fifth serial input 402. The carry output 422 of the first full adder 406 can be stored in the first register 414 for use as the carry input 424 of the first full adder 406 in subsequent loops. The sum output 426 of the first full adder 406 can be the first input of the three inputs of the third full adder 410. The carry output 428 of the second full adder 408 can be stored in the second register 416 for use as the carry input 430 of the second full adder 408 in subsequent loops. The sum output 432 of the second full adder 408 can be the second input of the three inputs of the third full adder 410. The carry output 434 of the third full adder 410 can be held in the third register 418 for use as the carry input 436 of the third full adder 410 in subsequent loops. The sum output 438 of the third full adder 410 can be one of the three inputs of the fourth full adder 412. The carry output 440 of the fourth full adder 412 can be held in the fourth register 420 for use as the carry input 442 of the fourth full adder 412 in subsequent loops. The sum output of the fourth full adder 412 can be a serial output 404 that outputs the sum of five serial inputs 402.
[0039] Figure 5 A block diagram of another example functional unit 500 with five serial inputs 502 and one serial output 504 is shown. This functional unit 500 has one less register to reduce area. Functional unit 500 includes four full adders 506 to 512 and three registers 514 to 518.
[0040] The inputs of the first full adder 506 can be one of the five serial inputs 502, the three inputs of the second full adder 508 can be three of the five serial inputs 502, and the input of the fourth full adder 512 can be the fifth serial input 502. The sum output 520 of the first full adder 506 and the sum output 522 of the second full adder 508 can be two of the inputs of the fourth full adder 512. The carry output 524 of the first full adder 506, the carry output 526 of the second full adder 508, and the carry output 528 of the fourth full adder 512 can be the three inputs of the third full adder 510. The sum output 530 of the third full adder 510 can be held in the first register 514 so that it can be applied to the first full adder 506 as the first carry input 532 in a subsequent loop. The carry output 534 of the third full adder 510 can be held in the second register 516, and further held in the third register 518 in a subsequent loop, so that it can be applied to the first full adder 506 as the second carry input 536 in another subsequent loop. The sum output of the fourth full adder 512 can be a serial output 504, which can output the sum of five serial inputs 502.
[0041] Figure 6 A block diagram depicts another example functional unit 600 having six serial inputs 602 and one serial output 604. Functional unit 600 includes five full adders 606 to 614 and five registers 616 to 624. In one example, for each full adder, the carry output can be held in a register to be applied as a carry input to its corresponding adder in subsequent loops. In another example, not shown, the carry output of the full adder can be held in a register to be applied as a carry input to different full adders.
[0042] The first full adder 606, the second full adder 608, and the fourth full adder 612 can form a four-serial-input adder, such as Figure 3 As depicted in the diagram. The second full adder 608, the fourth full adder 612, and the fifth full adder 614 can also form a four-serial-input adder. The third full adder 610 and the fifth full adder 614 can form a three-serial-input adder, such as... Figure 1 As described in the text. The fourth full adder 612 and the fifth full adder 614 can also form a three-serial-input adder.
[0043] The two inputs of the first full adder 606 can be two of the six serial inputs 602, the two inputs of the second full adder 608 can be the other two of the six serial inputs 602, and the two inputs of the third full adder 610 can be the remaining two of the six serial inputs 602. The carry output 626 of the first full adder 606 can be stored in the first register 616 for use as the carry input 628 of the first full adder 606 in subsequent loops. The sum output 430 of the first full adder 606 can be the first of the three inputs of the fourth full adder 612. The carry output 632 of the second full adder 608 can be stored in the second register 618 for use as the carry input 634 of the second full adder 608 in subsequent loops. The sum output 63 of the second full adder 608 can be the second of the three inputs of the fourth full adder 612. The carry output 638 of the third full adder 610 can be held in the third register 620 for use as the carry input 640 of the third full adder 610 in subsequent loops. The sum output 642 of the third full adder 610 can be the first of the three inputs of the fifth full adder 614. The carry output 644 of the fourth full adder 612 can be held in the fourth register 622 for use as the carry input 646 of the fourth full adder 612 in subsequent loops. The sum output 648 of the fourth full adder 612 can be the second of the three inputs of the fifth full adder 614. The carry output 650 of the fifth full adder 614 can be held in the fifth register 624 for use as the carry input 652 of the fifth full adder 614 in subsequent loops. The sum output of the fifth full adder 614 can be a serial output 604 that outputs the sum of six serial inputs 602.
[0044] Serial inputs and outputs can include buses with multiple bits, rather than a single bit. Figure 7 A block diagram depicts a functional unit 700 having three multi-bit serial inputs 702 and one multi-bit serial output 704. Functional unit 700 may include a first multi-bit full adder 706, a second multi-bit full adder 708, a first register 710, and a second register 712. Each multi-bit full adder includes a plurality of single-bit full adders equal in number to the number of bits in the multi-bit full adder, said multi-bit full adders being implemented such that each single-bit full adder takes the carry of the previous single-bit full adder as input. An example of a multi-bit full adder could be a ripple carry adder.
[0045] The two inputs of the first multi-bit full adder 706 can be two of the three multi-bit serial inputs 702, and the input of the second multi-bit full adder 708 can be the third multi-bit serial input 702. The carry output 714 of the first multi-bit full adder 706 can be held in the first register 710 for use as the carry input 716 of the first multi-bit full adder 706 in a subsequent loop. The multi-bit sum output 718 of the first multi-bit full adder 706 can be an input of the second multi-bit full adder 708. The carry output 720 of the second multi-bit full adder 708 can be held in the second register 712 for use as the carry input 722 of the second multi-bit full adder 708 in a subsequent loop. The multi-bit sum output of the second multi-bit full adder 708 can be a multi-bit serial output 704, which can output the sum of the three multi-bit serial inputs 702.
[0046] As with the single-bit example, a functional unit can include any number of serial inputs of multiple bits greater than two and a serial output of multiple bits. The number of full adders of multiple bits in a functional unit can be one less than the number of serial inputs of multiple bits. The number of registers in a functional unit can be less than the number of serial inputs of multiple bits. The number of full adder layers can be at most equal to the number of full adders in the functional unit.
[0047] Functional units can be incorporated into the processing units of a programmable device to allow the construction of various functions. As an example, a programmable device can include one or more processing units and programmable interconnects, wherein the processing units can include one or more functional units, such as one of the example functional units described above.
[0048] Figure 8 A block diagram depicts an example programmable device 800 including a programmable interconnect for masking bits. The programmable device 800 may include a first processing unit 802 and a second processing unit 804 connected by a programmable interconnect 806 for masking bits. It should be noted that the first processing unit 802 and the second processing unit 804 may be the same processing unit or part of a separate processing unit.
[0049] The first processing unit 802 may include a first functional unit 808, and the second processing unit 804 may include a second functional unit 810 and a third functional unit 812. Although the second functional unit 810 and the third functional unit 812 are depicted within the same processing unit, it should be noted that a functional unit may also be part of a separate processing unit. Here, a functional unit corresponds to a functional unit with three serial inputs, such as in... Figure 1Or as depicted in 2. However, the functional units can correspond to any of the examples provided herein or other examples not shown. Each functional unit can also be the same or different. For example, although only three serial input functional units are depicted for simplicity, in another embodiment, the first functional unit 808 can be five serial input functional units, the second functional unit 810 can be three serial input functional units, and the third functional unit 812 can be six serial input functional units. Each processing unit can also include any number of functional units.
[0050] Programmable interconnect 806 can be connected between the sum output of the first functional unit 808 and the inputs of the second functional unit 810 and the third functional unit 812. Programmable interconnect 806 can be connected to any of the three inputs of the second functional unit 810 and the third functional unit 812. Programmable interconnect 806 can include logic gates 814, such as AND gates, for masking bits to zero or one. Logic gates 814 can be input using configuration bits 816 for masking bits to zero or one. The sum output of the first functional unit 808 can be masked by programmable interconnect 806, and the masked sum can be input to the second functional unit 810 and the third functional unit 812.
[0051] Figure 9 A block diagram depicts an example programmable device 900 including registers. Registers can increase latency to achieve higher clock rates. The latency can correspond to a multiplication of two. Therefore, registers can be included at some outputs of a programmable interconnect to produce different results.
[0052] The programmable device 900 may include a first processing unit 902 and a second processing unit 904 connected by a programmable interconnect 906 for masking bits. The first processing unit 902 may include a first functional unit 908, and the second processing unit 904 may include a second functional unit 910 and a third functional unit 912. Figure 8 Similarly, for illustrative purposes only, the functional unit here corresponds to a functional unit with three serial inputs. The number of functional units depicted is also for illustrative purposes only.
[0053] Programmable interconnect 906 can be connected between the sum output of the first functional unit 908 and the inputs of the second functional unit 910 and the third functional unit 912. Programmable interconnect 906 can include a first logic gate 914 and a second logic gate 916 for masking bits to zero or one. Logic gates 914 and 916 can be input using a configuration bit 918 for masking bits to zero or one. Programmable interconnect 906 can further include a first register 920 and a second register 922 for holding bits for one cycle. The first register 920 can be connected between the sum output of the first functional unit 908 and the logic gates 914 and 916. The second register 922 can be connected between the output of the first logic gate 914 and the input of the second functional unit 910.
[0054] The summed output of the first functional unit 808 can be looped in the first register 920. The output of the first register 920 can be masked by the first logic gate 914 and the second logic gate 916. The masked output of the first logic gate 914 can be looped in the second register 922 and can be input to the second functional unit 910. The masked output of the second logic gate 916 can be input to the third functional unit 912. Due to the second register 922, the second functional unit 910 and the third functional unit 912 can have different inputs derived from the output of the first functional unit 908.
[0055] Figure 10 A block diagram depicts an example programmable device 1000 including a programmable interconnect for multiplexing. The programmable device 1000 may include a first processing unit 1002 and a second processing unit 1004 connected by a programmable interconnect 1006. The first processing unit 1002 may include a first functional unit 1008 and a second functional unit 1010, and the second processing unit 1004 may include a third functional unit 1012 and a fourth functional unit 1014. (This is consistent with previous...) Figure 1 For illustrative purposes only, the functional unit described here corresponds to a functional unit with three serial inputs. The number of functional units depicted is also for illustrative purposes only.
[0056] Programmable interconnect 1006 can be connected between the summed output of first functional unit 1008 and second functional unit 1010 and the inputs of third functional unit 1012 and fourth functional unit 1014. Programmable interconnect 1006 can include multiple multiplexers 1016 for selecting which summed outputs of first functional unit 1008 and second functional unit 1010 are provided to which inputs of third functional unit 1012 and fourth functional unit 1014. Multiplexers 1016 can be input using configuration bits 1018 for selecting which summed output. The selected summed output can be input to its corresponding functional unit. Although multiplexers 1016 are shown as having two inputs, they can include any number of inputs. Although not shown, registers can be included between components to increase latency or provide different outputs.
[0057] Figure 11 A block diagram depicts an example programmable device 1100 including a programmable interconnect for multi-layer multiplexing, wherein multiplexers can be connected to other multiplexers. The programmable device 1100 may include a first processing unit 1102 and a second processing unit 1104 connected by a programmable interconnect 1106. The first processing unit 1102 may include a first plurality of functional units 1108, and the second processing unit 1104 may include a second plurality of functional units 1110. (Compared to previous...) Figure 1 For illustrative purposes only, the functional unit described here corresponds to a functional unit with three serial inputs. The number of functional units depicted is also for illustrative purposes only.
[0058] Programmable interconnect 1106 can be connected between the summed output of a first plurality of functional units 1108 and the input of a second plurality of functional units 1110. Programmable interconnect 1106 can include a first plurality of multiplexers 1112 for selecting which summed outputs of the first plurality of functional units 1108 are provided to which of the second plurality of multiplexers 1114, which further selects which input of the second plurality of functional units 1110 is provided to. Although two layers of multiplexers are shown for simplicity, it should be noted that any number of multiplexer layers can be included in programmable interconnect 1106, each layer having any number of multiplexers. Furthermore, although not shown, registers can be included between components to increase latency or provide different outputs. Multi-layer multiplexing with functional units allows for efficient use of inputs on a programmable device.
[0059] Figure 12A block diagram depicts an example environment 1200 for implementing functional units and / or programmable devices. System 1200 can be implemented on one or more computing devices 1202 in one or more locations—such as in a server or client computing device. Computing device 1202 can include one or more programmable devices 1204 having one or more processing units 1206 connected by programmable interconnects 1208. Programmable device 1204 can include one or more central processing units (CPUs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs), and / or application-specific integrated circuits (ASICs), such as tensor processing units (TPUs). Processing units 1206 can include one or more functional units, such as those depicted in the previous examples. Programmable interconnects 1208 can functionally and / or physically connect processing units 1206, such as to logic units or multiplexers depicted in the previous examples.
[0060] The computing device 1202 may further include a memory 1210 capable of storing information accessible by the programmable device 1204, including instructions 1212 executable by the programmable device 1204. The memory 1210 may also include data 1214 capable of being retrieved, manipulated, or stored by the programmable device 1204. The memory 1210 may be a type of non-transitory computer-readable medium capable of storing information accessible by the programmable device 1204, such as volatile and non-volatile memory.
[0061] Instruction 1212 can include one or more instructions that, when executed by programmable device 1204, cause programmable device 1204 to perform the actions defined by instruction 1212. Instruction 1212 can be stored in object code format for direct processing by programmable device 1204, or stored in other formats, including interpretable scripts or sets of independent source code modules that are interpreted on demand or pre-compiled.
[0062] The programmable device 1204 is capable of retrieving, storing, or modifying data 1214 according to instructions 1212. Data 1214 can be stored as a table with multiple different fields and records, or as a JSON, YAML, prototype, or XML document in a computer register, relational, or non-relational database. Data 1214 can also be formatted in a computer-readable format, such as, but not limited to, binary values, ASCII, or Unicode. Furthermore, data 1214 can include information sufficient to identify relevant information, such as numbers, descriptive text, proprietary code, pointers, references to data stored in other memory locations, including other network locations, or information used by functions to calculate relevant data.
[0063] If the computing device 1202 is a client computing device, it may also include user output 1216 and user input 1218. User output 1216 may be configured to display an interface and / or include one or more speakers, transducers or other audio outputs, a haptic interface, or other haptic feedback to provide non-visual and non-auditory information to the user of the computing device 1202. User input 1218 may include any suitable mechanism or technology for receiving input from the user, such as a keyboard, mouse, mechanical actuator, soft actuator, touchscreen, microphone, and sensors.
[0064] although Figure 12 The programmable device 1204 and memory 1210 are illustrated as being within the computing device 1202; however, the components described herein can include multiple programmable devices 1204 and memories capable of operating in different physical locations and not within the same computing device. For example, some of the instructions 1212 and data 1214 can be stored on a removable SD card, while others can be stored within a read-only computer chip. Some or all of the instructions 1212 and data 1214 can be stored in a location physically remote from the programmable device 1204, but still accessible by the programmable device 1204. Similarly, the programmable device 1204 can include a collection of processing units capable of performing simultaneous and / or sequential operations. The computing device 1202 may include one or more internal clocks that provide timing information, which can be used for timing measurements of operations and programs run by the computing device 1202.
[0065] Therefore, this document generally discloses an implementation of a functional unit capable of accumulating more than two serial inputs and providing a serial summation output. The serial inputs and outputs can be single-bit or multi-bit buses. The functional unit can be implemented as a logic tree, where any two points are connected by a path. The functional unit can be incorporated into the processing unit of a programmable device to allow the construction of various functions.
[0066] Unless otherwise stated, the foregoing alternative examples are not mutually exclusive, but can be implemented in various combinations to achieve unique advantages. Since these and other variations and combinations of the features discussed above can be utilized without departing from the subject matter defined by the claims, the foregoing description of the embodiments should be interpreted rather than limiting the subject matter defined by the claims. Furthermore, the examples provided herein, as well as clauses expressed in phrases such as "such as," "comprising," etc., should not be construed as limiting the subject matter of the claims to the specific examples; rather, the examples are intended to illustrate only one of many possible embodiments. Moreover, the same reference numerals in different figures can identify the same or similar elements.
Claims
1. A programmable device, comprising: A first processing unit and a second processing unit are coupled to a programmable interconnect. Each of the first processing unit and the second processing unit includes a plurality of full adder circuits configured to collectively receive at least three serial inputs and generate a single serial output, the single serial output being the sum of the at least three serial inputs. The carry state is maintained in the plurality of full adder circuits. Furthermore, the programmable interconnect is connected between the first processing unit and the second processing unit and includes logic gates, wherein the programmable interconnect is configured as follows: The single serial output is received from the plurality of full adder circuits of the first processing unit; The logic gate is used to mask the single serial output; and The masked single serial output is output to the plurality of full adder circuits of the second processing unit as at least one of the three serial inputs of the second processing unit.
2. The programmable device according to claim 1, wherein, The number of inputs to each of the first processing unit and the second processing unit is equal to one more than the number of the plurality of full adder circuits.
3. The programmable device according to claim 1, wherein, Each serial input is a multi-bit input.
4. The programmable device according to claim 1, wherein, Each full adder circuit includes three single-bit inputs, a sum output, and a carry output.
5. The programmable device according to claim 4, wherein, The sum output of the full adder circuit is the input of another full adder circuit.
6. The programmable device according to claim 4, wherein, The carry output of the full adder circuit is held in a register to be used as the carry input of the full adder circuit in subsequent loops.
7. The programmable device according to claim 4, wherein, The carry output of the full adder circuit is the input of another full adder circuit.
8. The programmable device according to claim 1, wherein, The programmable interconnect includes at least one multiplexer.
9. The programmable device according to claim 1, wherein, The programmable interconnect includes one or more registers.
10. A method for operating a programmable device, the programmable device including a first processing unit and a second processing unit, the first processing unit and the second processing unit being coupled to a programmable interconnect, each of the first processing unit and the second processing unit including a plurality of full adder circuits, wherein the programmable interconnect includes at least one logic gate and is connected between the first processing unit and the second processing unit, the method comprising: The multiple full adder circuits are used to collectively receive at least three serial inputs; A single serial output is generated using the plurality of full adder circuits, the single serial output being the sum of the at least three serial inputs; Maintain the carry state in the plurality of full adder circuits; The single serial output is received from the plurality of full adder circuits of the first processing unit; The logic gate is used to mask the single serial output; as well as The masked single serial output is output to the plurality of full adder circuits of the second processing unit as at least one of the three serial inputs of the second processing unit.
11. The method according to claim 10, wherein, The number of inputs to each of the first processing unit and the second processing unit is equal to one more than the number of the plurality of full adder circuits.
12. The method according to claim 10, wherein, Each full adder circuit includes three single-bit inputs, a sum output, and a carry output.
13. The method of claim 12, further comprising inputting the sum output of the full adder circuit to another full adder circuit.
14. The method of claim 12, further comprising holding the carry output of the full adder in a register for application as a carry input of the full adder circuit in a subsequent loop.
15. The method of claim 12, further comprising inputting the carry output of the full adder circuit to another full adder circuit.
16. A non-transitory computer-readable medium for storing instructions that, when executed by a programmable device, cause the programmable device to perform operations, the programmable device including a first processing unit and a second processing unit coupled to a programmable interconnect, each of the first processing unit and the second processing unit including a plurality of full adder circuits, wherein the programmable interconnect includes at least one logic gate and is connected between the first processing unit and the second processing unit, the operations including: Multiple full adder circuits are used to jointly receive at least three serial inputs; A single serial output is generated using the plurality of full adder circuits, the single serial output being the sum of the at least three serial inputs; Maintain the carry state in the plurality of full adder circuits; The single serial output is received from the plurality of full adder circuits of the first processing unit; The logic gate is used to mask the single serial output; as well as The masked single serial output is output to the plurality of full adder circuits of the second processing unit as at least one of the three serial inputs of the second processing unit.
17. The non-transitory computer-readable medium according to claim 16, wherein, The operation further includes inputting the sum output of the full adder circuit into another full adder circuit.
18. The non-transitory computer-readable medium according to claim 16, wherein, The operation further includes holding the carry output of the full adder in a register so that it can be used as the carry input of the full adder circuit in subsequent cycles.
19. The non-transitory computer-readable medium according to claim 16, wherein, The operation further includes inputting the carry output of the full adder circuit to another full adder circuit.
20. The non-transitory computer-readable medium of claim 16, wherein, The at least three serial inputs are received jointly by multiple registers in a programmable interconnect.