A method for implementing a high-speed CPU instruction interpreter

Abstract

The application relates to the technical field of instruction interpreters, in particular to a method for implementing a high-speed CPU instruction interpreter, which comprises the following steps: S1: running a CPU instruction analysis module to analyze all original CPU instructions of a binary file to be interpreted and executed to obtain instruction logic. In the application, the interpreters provided are all implemented by 1-2 real instructions, and the original real instructions are averagely decomposed into 3-4 instructions. If the commonly used real instructions are added to the interpreter instructions, the binary file to be interpreted and executed is analyzed before the interpreter is run, the real instruction set is converted into the interpreter instruction set, the real instructions do not need to be analyzed again during running, the interpreter directly runs fast according to the analysis result before running, the speed is very fast, the interpreter is run in a process composed of real CPU instructions, all system libraries are locally run by the real CPU instructions except the binary file to be interpreted and executed, and the running speed of the whole system is further improved.

Description

Technical Field

[0001] This invention relates to the field of instruction interpreter technology, and in particular to a method for implementing a high-speed CPU instruction interpreter. Background Technology

[0002] In the history and development of computers, the interpreter has played a crucial role, forming a corresponding concept to the compiler. Compared to native programs compiled by a compiler that can run directly on the CPU, programs interpreted by an interpreter run relatively slowly. However, interpreters also possess many advantages that native programs compiled by a compiler cannot match: developers have complete control over the program when running it, and can easily detect problems during runtime, including but not limited to memory leaks, stack overflows, and system call logs. Furthermore, interpreters do not require compilation; they run immediately after being written, and are not subject to the security policies of the system platform on which the program runs. This has made them popular among many developers. In actual use, however, the interpreter's running speed is relatively slow, typically ranging from 20 to 700 times slower than native programs compiled by a compiler. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art and to propose a method for implementing a high-speed CPU instruction interpreter.

[0004] To achieve the above objectives, the present invention adopts the following technical solution: a method for implementing a high-speed CPU instruction interpreter, comprising the following steps:

[0005] S1: Run the CPU instruction parsing module to parse all the original CPU instructions in the binary file to be interpreted and executed to obtain the instruction logic;

[0006] S2: The interpreter instruction generation module obtains the instruction logic parsed by the CPU instruction parsing module, and decomposes and reassembles the instructions according to the logic to generate interpreter instructions specifically for use by the interpreter instruction execution module;

[0007] S3: Custom dynamic linker modules map the binary files that need to be interpreted into the memory space of the process to be executed, and bind or delay binding the mutual call relationship between the file and system modules;

[0008] S4: The system callback entry module will prepare a block of executable memory for each possible callback entry to deal with the situation of returning from the system module to the interpreter;

[0009] S5: The custom dynamic linker hands over control to the interpreter instruction execution module and executes the interpreter instructions generated in S2 quickly.

[0010] S6: When a binary file that needs to be interpreted and executed needs to call a system function, the ABI translation module is responsible for placing all the parameters and return values ​​required by the system function into the specified memory / register location in accordance with the ABI specification.

[0011] As a further aspect of the present invention, in step S1, the parsing of the binary file that needs to be interpreted and executed is accomplished by the core of the open-source software Capstone.

[0012] As a further aspect of the present invention, in step S2, the step of generating interpreter instructions specifically for the interpreter instruction execution module based on the logical decomposition and reorganization of instructions specifically involves assuming that the set of registers used in the real CPU instruction set is S, then defining a subset C of this set, so that the real CPU instructions of the interpreter instructions only use the registers in C. Using this subset can effectively reduce the number of interpreter instructions, avoid the explosive growth of the interpreter size consuming a large amount of memory, and each interpreter instruction is assigned a number a.

[0013] As a further aspect of the present invention, in step S2, generating interpreter instructions specifically for use by the interpreter instruction execution module based on the logical decomposition and reorganization instructions includes:

[0014] S201: When converting real CPU instructions to the interpreter, save all registers in the C set to the corresponding memory locations;

[0015] S202: If the operation register in the current real instruction belongs to set S but not to C, then the value of the operation register in the current real instruction is transferred from set S to any register in set C by the assignment instruction; if the operation register in the current real instruction belongs to set C, then the memory corresponding to the register in set C saved in S201 is loaded into any register in set C by the memory load instruction.

[0016] S203: The interpreter contains all instructions that use the C set registers. Use the interpreter to execute the instruction.

[0017] S204: If the result register of the current real instruction belongs to set S but not to C, then the value of the result register of the interpreter instruction execution is transferred from set C back to the register of set S in the original instruction through an assignment instruction; if the result register of the current real instruction belongs to set C, then the result is saved from the result register to the memory location corresponding to the register of set C in S201 through a memory storage instruction.

[0018] S205: Restore all registers in the C set from memory when the interpreter is translating into actual CPU instructions;

[0019] S206: The original CPU instruction, which was split from S201 to S205, is transformed into several instructions that exist in the interpreter. Each instruction in the interpreter is represented by a number 'a'. The original CPU instruction is transformed into several 'a's and stored.

[0020] As a further aspect of the present invention, in S3, the mapping of the binary file to be interpreted and executed into the memory space of the process to be executed, and the binding or delayed binding of the mutual calling relationship between the file and the system module are completed by the open-source dyld or linker.

[0021] As a further aspect of the present invention, in step S2, generating interpreter instructions specifically for use by the interpreter instruction execution module based on the logical decomposition and reorganization instructions includes:

[0022] S401: The interpreter compiles a jump instruction that spans an entire memory page. Each jump instruction reads data located after a memory page in size to perform the jump.

[0023] S402: Obtain the entry points for all binary files that need to be called back and interpreted;

[0024] S403: Maps a memory page in S401 as executable, and then maps another page of readable and writable memory immediately after this page. All jump instructions in S401 can then read the next page of readable and writable memory to carry different data.

[0025] S404: Allocates a jump instruction in the memory page of S401 to each entry point, and writes relevant data at an address after the jump instruction, which is one memory page in size, so that the jump instruction can carry unique and correct information when jumping into the interpreter entry point;

[0026] S405: When the number of required entry points exceeds the number of jump instructions that a single memory page can hold, the operating system's remapping function is used to repeatedly map the memory pages in S401 to expand the number of jump instructions.

[0027] As a further aspect of the present invention, S501: During the compilation process, an instruction jump table is generated, and a number is assigned to all interpreter instructions belonging to the C set;

[0028] S502: Reads the input generated in S2, which consists of different numbers 'a', and jumps to different interpreter instructions based on the numbers;

[0029] S503: If the current interpreter instruction is a call to a system function, it is handled by the ABI translation module;

[0030] S504: If there are more numbers 'a', return to S501; otherwise, end.

[0031] As a further aspect of the present invention, S601: Before the CPU executes the actual instruction, all registers belonging to set C are loaded back into the registers from the memory location where the registers are stored using a memory load instruction.

[0032] S602: When the CPU finishes executing the actual instruction, it uses a memory storage instruction to save all registers belonging to set C into their corresponding locations in memory.

[0033] Compared with the prior art, the advantages and positive effects of the present invention are as follows:

[0034] In this invention, the provided interpreters all use 1-2 real instructions to implement interpreter instructions, while the original real instructions are decomposed into an average of 3-4 instructions. If commonly used real instructions are added to the interpreter instructions, the original real instructions do not even need to be decomposed, resulting in minimal additional overhead. It is theoretically the fastest CPU instruction interpreter. Before the interpreter runs, it analyzes the binary file to be interpreted and executes, converting the real instruction set into the interpreter instruction set. During runtime, there is no need to analyze the real instructions again. The interpreter runs quickly directly based on the analysis results before execution, resulting in high speed. By placing the interpreter in a process composed of real CPU instructions, all system libraries, except for the binary file to be interpreted and executed, run natively as real CPU instructions, further accelerating the overall system speed. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the structure of the high-speed CPU instruction interpreter of the present invention.

[0036] Figure 2 This is a flowchart of the high-speed CPU instruction interpreter of the present invention.

[0037] Figure 3 This is a flowchart of the algorithm for decomposing, recombining, and generating interpreter instructions from CPU instructions according to the present invention.

[0038] Figure 4 The flowchart below shows the algorithm of the callback entry module of the system of this invention.

[0039] Figure 5 A flowchart of the algorithm for fast execution of interpreter instructions in this invention.

[0040] Figure 6 This is a flowchart of the algorithm for the ABI conversion module of the present invention. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0042] In the description of this invention, it should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, in the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0043] Example 1

[0044] Please see Figure 1 This embodiment includes a target binary file to be interpreted and executed, a CPU instruction parsing module, an interpreter instruction generation module, an interpreter instruction set, a custom linker module, an interpreter instruction execution module, an ABI conversion module, and a system callback entry module. The target binary file to be interpreted and executed is a binary file of arm64 instruction set running under the iOS system. The CPU instruction parsing module parses the CPU instructions contained in the target binary file to be interpreted and executed, and outputs them to the interpreter instruction generation module. The interpreter instruction generation module splits and reassembles the real instructions into an interpreter instruction set. The custom linker module loads and binds the target binary file to be interpreted and executed. The interpreter instruction execution module executes the previously generated interpreter instruction set. The ABI conversion module is responsible for performing ABI conversion for the interpreter instruction execution module. The system callback entry module prepares a system callback entry for the interpreter instruction execution module.

[0045] Please see Figure 2 The usage method of Example 1 includes the following steps:

[0046] ① Analyze the target binary file that needs to be interpreted and executed.

[0047] ② Split the raw instructions of the target binary file to generate an interpreter instruction set file, see Figure 3 The specific algorithm for splitting the target binary file using the original instructions is as follows:

[0048] I. Obtain the operation register of the original instruction;

[0049] II. Determine whether the operation register belongs to set S. If it does, proceed to step III; otherwise, proceed to step IV.

[0050] III. Add an interpreter instruction that loads the value of the register from memory into the interpreter's operation register, and jump to step V;

[0051] IV. Add an interpreter instruction that moves from the original instruction operation register to the interpreter's operation register;

[0052] V. Are there any more operation registers? If so, return to step I.

[0053] VI. Add an interpreter instruction of the same type as the original instruction, but which only uses the S set register;

[0054] VII. Obtain the result register of the original instruction;

[0055] VIII. Determine whether the result register belongs to set S. If it does, proceed to step IX; otherwise, jump to step X.

[0056] IX. Add an interpreter instruction that stores the value of the interpreter's result register in memory, and jump to step XI;

[0057] X. Add an interpreter instruction that moves the interpreter's result register to the result register of the original instruction;

[0058] XI. Are there more result registers? If so, return to step VII; otherwise, end.

[0059] ③ The custom dynamic linker module loads the target binary file and the interpreter instruction set file;

[0060] ④ The system callback entry module prepares the system callback entry, see Figure 4 The specific algorithm for preparing the system callback entry is as follows:

[0061] I. Compile a jump instruction that takes up an entire memory page. Each jump instruction reads data located after a memory page in size to perform the jump.

[0062] II. Obtain the entry points for all binary files that need to be called back and interpreted for execution;

[0063] III. Map the jump instruction memory page to be executable, and then map another readable and writable memory page immediately following this memory page;

[0064] IV. Allocate a jump instruction to a memory page for each entry, and write the relevant data at an address that is one memory page in size after the jump instruction;

[0065] V. Determine if the number of entry points exceeds the number of jump instructions. If so, proceed to step VI; otherwise, end.

[0066] VI. Remap the jump instruction page and data page, and return to step IV;

[0067] ⑤ Begin interpreting and executing the target binary file, see Figure 5 The specific algorithm for fast interpretation and execution is as follows:

[0068] I. During the compilation process, an instruction jump table is generated, and a number is assigned to each interpreter instruction;

[0069] II. Read the interpreter instruction file and jump to different implementations according to the instructions;

[0070] III. Determine if the current instruction is a call to a system function; if so, hand it over to the ABI translation module for processing.

[0071] IV. Determine if there are more interpreter instructions. If so, return to step II; otherwise, end.

[0072] ⑥ Determine if a system API is being called; otherwise, return to step ④.

[0073] ⑦ Perform ABI conversion to access the system API, see Figure 6 The specific algorithm for ABI conversion is as follows:

[0074] I. Load all registers belonging to set C back into the registers from the memory locations where the registers were stored using memory load instructions;

[0075] II. Execute the actual instructions;

[0076] Ⅲ. Use memory storage instructions to save all registers belonging to set C into their corresponding memory locations.

[0077] ⑧ Return to the interpreter;

[0078] Determine if the application chooses to exit; if so, end the process; otherwise, return to step ⑤.

[0079] Please see Figure 1-6 The present invention provides a technical solution, a method for implementing a high-speed CPU instruction interpreter, comprising the following steps: S1: running the CPU instruction parsing module to parse all the original CPU instructions of the binary file to be interpreted and executed to obtain the instruction logic;

[0080] S2: The interpreter instruction generation module obtains the instruction logic parsed by the CPU instruction parsing module, and decomposes and reassembles the instructions according to the logic to generate interpreter instructions specifically for use by the interpreter instruction execution module;

[0081] S3: Custom dynamic linker modules map the binary files that need to be interpreted into the memory space of the process to be executed, and bind or delay binding the mutual call relationship between the file and system modules;

[0082] S4: The system callback entry module will prepare a block of executable memory for each possible callback entry to deal with the situation of returning from the system module to the interpreter;

[0083] S5: The custom dynamic linker hands over control to the interpreter instruction execution module and executes the interpreter instructions generated in S2 quickly.

[0084] S6: When a binary file that needs to be interpreted and executed needs to call a system function, the ABI translation module is responsible for placing all the parameters and return values ​​required by the system function into the specified memory / register location in accordance with the ABI specification.

[0085] In S1, parsing the binary files that need to be interpreted and executed is done by the core of the open-source software Capstone.

[0086] In S4, based on the logical decomposition and reorganization of instructions, interpreter instructions specifically for the interpreter instruction execution module are generated. Specifically, assuming the set of registers used in the actual CPU instruction set is S, a subset C of this set is defined. The actual CPU instructions implementing the interpreter instructions only use registers in C. Using this subset effectively reduces the number of interpreter instructions, avoiding an explosive increase in interpreter size and excessive memory consumption. Each interpreter instruction is assigned a number 'a'. Based on this logical decomposition and reorganization, interpreter instructions specifically for the interpreter instruction execution module are generated, including:

[0087] S201: When converting real CPU instructions to the interpreter, save all registers in the C set to the corresponding memory locations;

[0088] S202: If the operation register in the current real instruction belongs to set S but not to C, then the value of the operation register in the current real instruction is transferred from set S to any register in set C by the assignment instruction; if the operation register in the current real instruction belongs to set C, then the memory corresponding to the register in set C saved in S201 is loaded into any register in set C by the memory load instruction.

[0089] S203: The interpreter contains all instructions that use the C set registers. Use the interpreter to execute the instruction.

[0090] S204: If the result register of the current real instruction belongs to set S but not to C, then the value of the result register of the interpreter instruction execution is transferred from set C back to the register of set S in the original instruction through an assignment instruction; if the result register of the current real instruction belongs to set C, then the result is saved from the result register to the memory location corresponding to the register of set C in S201 through a memory storage instruction.

[0091] S205: Restore all registers in the C set from memory when the interpreter is translating into actual CPU instructions;

[0092] S206: The original CPU instruction, which was split from S201 to S205, is transformed into several instructions that exist in the interpreter. Each instruction in the interpreter is represented by a number 'a'. The original CPU instruction is transformed into several 'a's and stored.

[0093] In S3, the binary file that needs to be interpreted and executed is mapped into the memory space of the process to be executed. The binding or delayed binding of the mutual calling relationship between the file and the system module is done by the open-source dyld or linker.

[0094] In S4, based on this logical decomposition and reorganization of instructions, interpreter instructions specifically for use by the interpreter instruction execution module are generated, including:

[0095] S401: The interpreter compiles a jump instruction that spans an entire memory page. Each jump instruction reads data located after a memory page in size to perform the jump.

[0096] S402: Obtain the entry points for all binary files that need to be called back and interpreted;

[0097] S403: Maps a memory page in S401 as executable, and then maps another page of readable and writable memory immediately after this page. All jump instructions in S401 can then read the next page of readable and writable memory to carry different data.

[0098] S404: Allocates a jump instruction in the memory page of S401 to each entry point, and writes relevant data at an address after the jump instruction, which is one memory page in size, so that the jump instruction can carry unique and correct information when jumping into the interpreter entry point;

[0099] S405: When the number of required entry points exceeds the number of jump instructions that a single memory page can hold, the operating system's remapping function is used to repeatedly map the memory pages in S401 to expand the number of jump instructions.

[0100] S501: During compilation, an instruction jump table is generated, assigning a number to all interpreter instructions belonging to the C set;

[0101] S502: Reads the input generated in S2, which consists of different numbers 'a', and jumps to different interpreter instructions based on the numbers;

[0102] S503: If the current interpreter instruction is a call to a system function, it is handled by the ABI translation module;

[0103] S504: If there are more numbers 'a', return to S501; otherwise, end.

[0104] S601: Before the CPU executes the actual instruction, all registers belonging to set C are loaded back into the registers from the memory locations where the registers are stored using a memory load instruction.

[0105] S602: When the CPU finishes executing the actual instruction, it uses a memory storage instruction to save all registers belonging to set C into their corresponding locations in memory.

[0106] Working principle: The CPU instruction parsing module parses all the original CPU instructions in the binary file to be interpreted and executed to obtain the instruction logic. The interpreter instruction generation module obtains the instruction logic parsed by the CPU instruction parsing module, and decomposes and reassembles the instructions according to the logic to generate interpreter instructions specifically for use by the interpreter instruction execution module. The custom dynamic linker module maps the binary file to be interpreted and executed into the memory space of the process to be executed, and binds or delays binding the mutual call relationship between the file and the system module. The system callback entry module prepares a block of executable memory for each possible callback entry to deal with the situation of returning from the system module to the interpreter. The custom dynamic linker hands over control to the interpreter instruction execution module and executes it quickly according to the interpreter instructions generated in S2. When the binary file to be interpreted and executed needs to call a system function, the ABI translation module is responsible for placing all the parameters and return values ​​required by the system function into the specified memory / register location according to the ABI specification.

[0107] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments that can be applied to other fields. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A method for implementing a high-speed CPU instruction interpreter, characterized in that, Includes the following steps: S1: Run the CPU instruction parsing module to parse all the original CPU instructions in the binary file to be interpreted and executed to obtain the instruction logic; S2: The interpreter instruction generation module obtains the instruction logic parsed by the CPU instruction parsing module, and decomposes and reassembles the instructions according to the logic to generate interpreter instructions specifically for use by the interpreter instruction execution module; S3: Custom dynamic linker modules map the binary files that need to be interpreted into the memory space of the process to be executed, and bind or delay binding the mutual call relationship between the file and system modules; S4: The system callback entry module will prepare a block of executable memory for each possible callback entry to deal with the situation of returning from the system module to the interpreter; S5: The custom dynamic linker hands over control to the interpreter instruction execution module and executes the interpreter instructions generated in S2 quickly. S6: When a binary file that needs to be interpreted and executed needs to call a system function, the ABI translation module is responsible for placing all the parameters and return values ​​required by the system function into the specified memory / register location in accordance with the ABI specification. In step S2, generating interpreter instructions specifically for use by the interpreter instruction execution module based on the logical decomposition and reorganization instructions includes: S201: When converting real CPU instructions to the interpreter, save all registers in the C set to the corresponding memory locations; S202: If the operation register in the current real instruction belongs to set S but not to C, then the value of the operation register in the current real instruction is transferred from set S to any register in set C by the assignment instruction; if the operation register in the current real instruction belongs to set C, then the memory corresponding to the register in set C saved in S201 is loaded into any register in set C by the memory load instruction. S203: The interpreter contains all instructions that use the C set registers. Use the interpreter to execute the instruction. S204: If the result register of the current real instruction belongs to set S but not to C, then the value of the result register of the interpreter instruction execution is transferred from set C back to the register of set S in the original instruction through an assignment instruction; if the result register of the current real instruction belongs to set C, then the result is saved from the result register to the memory location corresponding to the register of set C in S201 through a memory storage instruction. S205: Restore all registers in the C set from memory when the interpreter is translating into actual CPU instructions; S206: The original CPU instruction, split from S201 to S205, is transformed into several instructions existing in the interpreter. Each instruction existing in the interpreter is represented by a number 'a'. The several 'a's transformed from the original CPU instruction are stored. In S2, the step of generating interpreter instructions specifically for the interpreter instruction execution module by logically decomposing and reorganizing the instructions specifically involves assuming that the set of registers used in the real CPU instruction set is S, then defining a subset C of this set, so that the real CPU instructions of the interpreter instructions only use the registers in C.

2. The method for implementing a high-speed CPU instruction interpreter according to claim 1, characterized in that, In S1, the parsing of the binary file that needs to be interpreted and executed is done by the core of the open-source software Capstone.

3. The method for implementing a high-speed CPU instruction interpreter according to claim 1, characterized in that, In step S3, the mapping of the binary file to be interpreted and executed into the memory space of the process to be executed, and the binding or delayed binding of the mutual calling relationship between the file and the system module are completed by the open-source dyld or linker.

4. The method for implementing a high-speed CPU instruction interpreter according to claim 1, characterized in that, S4 includes: S401: The interpreter compiles a jump instruction that spans an entire memory page. Each jump instruction reads data located after a memory page in size to perform the jump. S402: Obtain the entry points for all binary files that need to be called back and interpreted; S403: Maps a memory page in S401 as executable, and then maps another page of readable and writable memory immediately after this page. All jump instructions in S401 can then read the next page of readable and writable memory to carry different data. S404: Allocates a jump instruction in the memory page of S401 to each entry point, and writes relevant data at an address after the jump instruction, which is one memory page in size, so that the jump instruction can carry unique and correct information when jumping into the interpreter entry point; S405: When the number of required entry points exceeds the number of jump instructions that a single memory page can hold, the operating system's remapping function is used to repeatedly map the memory pages in S401 to expand the number of jump instructions.

5. The method for implementing a high-speed CPU instruction interpreter according to claim 1, characterized in that, S501: During compilation, an instruction jump table is generated, assigning a number to all interpreter instructions belonging to the C set; S502: Reads the input generated in S2, which consists of different numbers 'a', and jumps to different interpreter instructions based on the numbers; S503: If the current interpreter instruction is a call to a system function, it is handled by the ABI translation module; S504: If there are more numbers 'a', return to S502; otherwise, end.

6. The method for implementing a high-speed CPU instruction interpreter according to claim 1, characterized in that, S601: Before the CPU executes the actual instruction, all registers belonging to set C are loaded back into the registers from the memory locations where the registers are stored using a memory load instruction. S602: When the CPU finishes executing the actual instruction, it uses a memory storage instruction to save all registers belonging to set C into their corresponding locations in memory.

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