A method for online burning configuration chip

Abstract

The application provides a method for online burning configuration chip, comprising the following steps: using a bidirectional level conversion chip to control the connection between the QSPI interface signal of CPU / FPGA / DSP and the configuration chip; controlling the enable control signal of the bidirectional level conversion chip; controlling the power supply of the bidirectional level conversion chip and the configuration chip; using the ISP interface to provide a signal connection channel between the burner / programmer and the configuration chip, the burner / programmer provides additional power supply for the bidirectional level conversion chip and the configuration chip through the ISP interface, and the different power supplies are isolated; when the ISP interface is suspended, the QSPI interface signal and the power supply are connected with the configuration chip; when the burner / programmer is inserted into the ISP interface, the configuration chip is only connected with the burner / programmer, so that the online burning of the configuration chip is realized. The bidirectional level conversion chip and the field effect transistor are used, the burner / programmer can be used to burn the configuration chip online, and the method has universality.

Description

Technical Field

[0001] This invention relates to the field of CPU / FPGA / DSP configuration chip technology, and more specifically, to a method for online programming of configuration chips. Background Technology

[0002] Currently, in CPU / FPGA / DSP based products, the hardware circuit usually has a configuration chip with a QSPI or SPI interface, which is used to store configuration information that the CPU / FPGA / DSP needs to access first when the product is powered on, such as BIOS, bootloader, firmware program or FPGA configuration file, to realize functions such as hardware initialization, loading the boot program, running the firmware program or performing field configuration of the FPGA.

[0003] To improve reliability, configuration chips are typically soldered directly onto the product's printed circuit board. During product debugging or maintenance upgrades, if configuration information needs to be updated, the configuration chip must be removed from the product and then programmed using a programmer. This method increases the difficulty of updating configuration information on-site. In some product applications, it's not possible to use disassembly tools like soldering stations on-site, necessitating return to the factory for processing, thus reducing the efficiency of product maintenance and upgrades.

[0004] One compromise is to avoid directly soldering the configuration chip onto the product's printed circuit board. Instead, the product provides a mounting socket for the configuration chip, which is then installed. When configuration information needs updating, the configuration chip can be easily removed using simple tools like tweezers. However, mounting the configuration chip in a socket reduces the reliability of the chip's pin connections compared to direct soldering. This is especially true for surface-mount packages, where the pin connections resemble gold fingers. Under conditions of strong vibration and impact in the product's operating environment, the configuration chip is highly susceptible to loosening or even detachment, leading to product malfunctions.

[0005] While CPUs / FPGAs / DSPs can be programmed with configuration chips using dedicated emulators, the programming process requires specialized development software. Emulators and development software vary depending on the CPU / FPGA / DSP and are not interchangeable. Furthermore, the programmed hardware circuitry involves a large loop through the emulator, CPU / FPGA / DSP, and configuration chip, resulting in low signal transmission quality and slow programming speed. For large configuration files, programming can typically take tens of minutes. Therefore, this programming method is inefficient and lacks versatility. Summary of the Invention

[0006] The present invention aims to provide a method for online programming and configuration of chips to solve the above-mentioned problems.

[0007] The present invention provides a method for online programming and configuration of a chip, comprising the following steps: A bidirectional level conversion chip is used to disconnect or close the connection between the QSPI interface signal of the CPU / FPGA / DSP and the configuration chip, and a field-effect transistor and a jumper cap are used to control the enable control signal of the bidirectional level conversion chip. The power supply to the bidirectional level conversion chip and the configuration chip is controlled by a field-effect transistor; An ISP interface is used to provide a signal connection channel between the programmer and the configuration chip. The programmer provides additional power to the bidirectional level conversion chip and the configuration chip through the ISP interface. Diodes are used to isolate the different power supplies of the bidirectional level conversion chip and the configuration chip. When the ISP interface is floating, the signals and power supply in the QSPI interface of the CPU / FPGA / DSP are connected to the configuration chip, completing the functions of the CPU / FPGA / DSP and the configuration chip under normal product use. When the programmer is plugged into the ISP interface, the connection between the QSPI interface signal of the CPU / FPGA / DSP and the configuration chip is automatically or manually disconnected, depending on the type of programmer. The signal pins of the configuration chip are only connected to the programmer, thereby realizing the function of online programming of the configuration chip.

[0008] Furthermore, the bidirectional level conversion chip has the following configuration: The bidirectional level conversion chip supports multiple signal connections to connect the QSPI interface signals of the CPU / FPGA / DSP to the configuration chip using multiple signals. The bidirectional level conversion chip has independent power supply for terminals A and B, as well as signal connection channels at both ends, supporting the same or different power supply voltages at both ends; it supports interconnection or level conversion of signals with the same or different levels at both ends, and the signal transmission direction does not need to be controlled. The bidirectional level conversion chip supports push-pull and open-drain signal types; The bidirectional level conversion chip has electrostatic discharge protection to ensure the safety of CPUs / FPGAs / DSPs, configuration chips, and programmers that have signal connections with it.

[0009] Furthermore, the bidirectional level conversion chip has a high-level active enable control signal; When the enable control signal is valid, the connection between the QSPI interface signal of the CPU / FPGA / DSP and the configuration chip is closed. When the enable control signal is invalid, the connection between the QSPI interface signal of the CPU / FPGA / DSP and the configuration chip is disconnected.

[0010] Furthermore, the field-effect transistor used to implement the enable control signal is an N-channel MOS type; The drain of the N-channel MOS field-effect transistor is pulled up to the A terminal of the bidirectional level conversion chip for power supply and connected to the enable control signal; The gate of the N-channel MOS field-effect transistor is pulled down to ground and connected to the power supply of the ISP interface; The source of this N-channel MOSFET is connected to ground.

[0011] Furthermore, the field-effect transistor used to control the power supply of the bidirectional level conversion chip and the configuration chip is a P-channel MOS type; The drain of this P-channel MOS field-effect transistor is connected to the power supply in the QSPI interface of the CPU / FPGA / DSP; The gate of the P-channel MOS field-effect transistor is pulled down to ground and connected to the power supply of the ISP interface; The source of this P-channel MOSFET is connected to the power supply of the bidirectional level shifting chip and the configuration chip; The power supply control of the bidirectional level conversion chip and the configuration chip is achieved by using the voltage between the body diode and the gate-source of the P-channel MOS field-effect transistor.

[0012] Furthermore, the ISP interface provides a signal connection channel between the programmer and the configuration chip. The programmer provides additional power to the bidirectional level conversion chip and the configuration chip through the ISP interface. The ISP interface supports configuration chips with QSPI and SPI interfaces.

[0013] Furthermore, the diode is a Schottky diode with a low forward voltage drop, in order to isolate the power supply to the bidirectional level conversion chip and configuration chip from the QSPI interface and ISP interface of the CPU / FPGA / DSP.

[0014] Furthermore, when the ISP interface is left floating (i.e., the programmer / burner is not inserted into the ISP interface), the enable control signal is effective, automatically closing the connection between the CPU / FPGA / DSP's QSPI interface signal and the configuration chip. Simultaneously, the field-effect transistor controlling the power supply of the bidirectional level conversion chip and the configuration chip is turned on, and the power supply of the bidirectional level conversion chip and the configuration chip is provided by the power supply in the CPU / FPGA / DSP's QSPI interface, thereby completing the functions of the CPU / FPGA / DSP and the configuration chip under normal product use.

[0015] Furthermore, when the programmer is plugged into the ISP interface, if the programmer has an external power supply output function, the enable control signal of the bidirectional level conversion chip is invalid, causing the connection between the QSPI interface signal of the CPU / FPGA / DSP and the configuration chip to be disconnected, so that the signal pins of the configuration chip are only connected to the programmer. At the same time, the field-effect transistors that control the power supply of the bidirectional level conversion chip and the configuration chip are turned off. The power supply in the QSPI interface is supplied to the bidirectional level conversion chip and the configuration chip through the body diode of the field-effect transistor or through the ISP interface of the programmer, thereby using the programmer to complete the online programming of the configuration chip.

[0016] Furthermore, when the programmer / programmer is plugged into the ISP interface, if the programmer / programmer does not have an external power output function, the jumper cap needs to be installed. This disables the enable control signal of the bidirectional level conversion chip, disconnecting the QSPI interface signal of the CPU / FPGA / DSP from the configuration chip. Consequently, the signal pins of the configuration chip are only connected to the programmer / programmer. Simultaneously, the field-effect transistor controlling the power supply to the bidirectional level conversion chip and the configuration chip is turned on. The power supply to the bidirectional level conversion chip and the configuration chip is provided by the power supply in the QSPI interface of the CPU / FPGA / DSP, thus enabling the programmer / programmer to complete the online programming of the configuration chip.

[0017] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are: 1. This invention uses a bidirectional level conversion chip and a field-effect transistor to control the signal connection and power supply between the QSPI interface of the CPU / FPGA / DSP and the configuration chip. When the ISP interface is floating, the signal and power supply connection between the CPU / FPGA / DSP and the configuration chip is normal, thus completing the functions of the CPU / FPGA / DSP and the configuration chip under normal product use.

[0018] 2. In this invention, when the programmer / programmer is plugged into the ISP interface, online programming of the configuration chip can be completed regardless of whether the programmer / programmer has an external power output function. Programming the configuration chip does not require a dedicated emulator or development software, and the programmer / programmer supports various types and capacities of configuration chips, thus possessing versatility. Simultaneously, the programmer / programmer connects directly to the signal pins of the configuration chip through the ISP interface, resulting in high signal transmission quality, fast data transmission speed, and high programming efficiency, making it particularly suitable for product development and field maintenance upgrades. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart of the online programming and configuration chip method of the present invention.

[0021] Figure 2 This is a circuit diagram of the online programming configuration chip according to an embodiment of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0023] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0024] Example like Figure 1 As shown in the figure, this embodiment proposes a method for online programming and configuration of chips, including the following steps: A bidirectional level conversion chip is used to disconnect or close the connection between the QSPI interface signal of the CPU / FPGA / DSP and the configuration chip, and a field-effect transistor and a jumper cap are used to control the enable control signal of the bidirectional level conversion chip. The power supply to the bidirectional level conversion chip and the configuration chip is controlled by a field-effect transistor; An ISP interface is used to provide a signal connection channel between the programmer and the configuration chip. The programmer provides additional power to the bidirectional level conversion chip and the configuration chip through the ISP interface. Diodes are used to isolate the different power supplies of the bidirectional level conversion chip and the configuration chip. When the ISP interface is floating, the signals and power supply in the QSPI interface of the CPU / FPGA / DSP are connected to the configuration chip, completing the functions of the CPU / FPGA / DSP and the configuration chip under normal product use. When the programmer is plugged into the ISP interface, the connection between the QSPI interface signal of the CPU / FPGA / DSP and the configuration chip is automatically or manually disconnected, depending on the type of programmer. The signal pins of the configuration chip are only connected to the programmer, thereby realizing the function of online programming of the configuration chip.

[0025] like Figure 2 The diagram shown is a circuit schematic for online programming of the configuration chip in this embodiment. The diagram includes: the CPU / FPGA / DSP QSPI interface U1A, bidirectional level shifter chip U2, configuration chip U3, ISP interface J1, jumper cap J2, MOSFETs Q1~Q2, Schottky diode D1, pull-down resistors R1 and R5, pull-up resistors R2, R3 and R4, signals QSPI_CS, QSPI_D0, QSPI_D1, QSPI_SCLK, QSPI_D2, and QSPI_D3 in the CPU / FPGA / DSP QSPI interface, power supply VDD, power supply VBB for bidirectional level shifter chip U2 and configuration chip U3, enable control signal EN for bidirectional level shifter chip U2, and signals CS, SI, SO, SCLK, D2, D3, and power supply VCC_ISP in the ISP interface.

[0026] In this embodiment, the A and B terminals of the bidirectional level conversion chip U2 are connected together and are both VBB. The B terminal signal of the bidirectional level conversion chip U2 is connected to the signal in the QSPI interface of the CPU / FPGA / DSP, and the A terminal signal of the bidirectional level conversion chip U2 is connected to both the ISP interface and the configuration chip U3.

[0027] During normal use of the product, the ISP interface J1 is left floating, meaning no programmer / burner is inserted. At this time, the VCC_ISP voltage is 0V. The gate voltage of the P-channel MOSFET Q1, which controls the power supply to the bidirectional level conversion chip U2 and the configuration chip U3, is 0V due to the pull-down resistor R1. VDD causes the body diode inside the P-channel MOSFET Q1 to conduct in the forward direction, making the source voltage of the P-channel MOSFET Q1 slightly lower than VDD, thus creating a voltage difference V between the gate and source of the P-channel MOSFET Q1. GS The conduction condition of the P-channel MOSFET Q1 is met, ultimately making VBB approximately equal to VDD. This means the power supply VBB of the bidirectional level shifter chip U2 and the configuration chip U3 is approximately equal to the power supply VDD in the QSPI interface of the CPU / FPGA / DSP. Simultaneously, since the voltage value of VCC_ISP is 0V, the gate of the N-channel MOSFET Q2, which implements the enable control signal EN, is pulled down to ground through resistor R5. Therefore, the voltage difference V between the gate and source of the N-channel MOSFET Q2 is V... GSThe conduction condition of the N-channel MOSFET Q2 is not met, and the jumper cap J2 remains open by default. The enable control signal EN is pulled up to VBB through the pull-up resistor R4, which is a valid high level. This enables the signals at both ends of the bidirectional level conversion chip U2 to conduct, so the signals in the QSPI interface of the CPU / FPGA / DSP are connected to the configuration chip. As a result, the signal connection and power supply of the CPU / FPGA / DSP and the configuration chip are normal, and the functions of the CPU / FPGA / DSP and the configuration chip can be completed under normal product use.

[0028] During product development and on-site maintenance and upgrades, the ISP interface is used to insert a programmer / burner, which falls into the following two categories: 1. If the programmer / programmer has an external power supply output function, the voltage value of VCC_ISP will not be 0V. Its voltage value is the normal power supply voltage of the selected configuration chip U3, which is usually consistent with the power supply VDD in the QSPI interface of the CPU / FPGA / DSP. The gate voltage of the P-channel MOSFET Q1 is VCC_ISP. VDD causes the body diode inside the P-channel MOSFET Q1 to conduct in the forward direction, making the source voltage of the P-channel MOSFET Q1 slightly lower than VDD, thus creating a voltage difference V between the gate and source of the P-channel MOSFET Q1. GS The conduction condition of the P-channel MOSFET Q1 is not met. At this time, VBB is slightly lower than VDD due to the forward voltage drop of the body diode inside the P-channel MOSFET Q1. VCC_ISP is connected to VBB through the Schottky diode D1. VDD and VCC_ISP are isolated by the Schottky diode D1, so the final voltage value of VBB depends on the larger of VDD and VCC_ISP. In this case, the power supply VBB for the bidirectional level converter chip U2 and the configuration chip U3 may come from either the power supply VDD from the QSPI interface or the power supply VCC_ISP from the ISP interface. Normally, VDD and VCC_ISP are of the same value, so the final voltage value of VBB depends on the forward voltage drop of the body diode of the P-channel MOSFET Q1 and the forward voltage drop of the Schottky diode D1. The energy consumed during the programming process is provided by VDD or VCC_ISP, or both. Simultaneously, due to the presence of VCC_ISP, the voltage difference V between the gate and source of the N-channel MOSFET Q2 is... GSWith the N-channel MOSFET Q2 turned on and jumper J2 remaining open by default, the turn-on of Q2 results in an invalid low level for the enable control signal EN. This maintains a high impedance state between the signals on both ends of the bidirectional level conversion chip U2, effectively disconnecting it. Therefore, the signals in the QSPI interface of the CPU / FPGA / DSP are disconnected from the configuration chip U3. In this way, the signal pins of configuration chip U3 are connected only to the programmer / programmer via the ISP interface. Simultaneously, with the power supply VBB of configuration chip U3 normal, in-circuit programming of the configuration chip can be completed. If the power output of the programmer / programmer is sufficiently high, the product power supply can be turned off, and in-circuit programming of the configuration chip can be completed using only the power output of the programmer / programmer.

[0029] 2. If the programmer / burner does not have an external power supply output function, the voltage value of VCC_ISP is 0V. The gate voltage of the P-channel MOSFET Q1 is 0V due to the pull-down resistor R1. VDD causes the body diode inside the P-channel MOSFET Q1 to conduct in the forward direction, making the source voltage of the P-channel MOSFET Q1 slightly lower than VDD. This results in a voltage difference V between the gate and source of the P-channel MOSFET Q1. GS The turn-on condition of the P-channel MOSFET Q1 is met, ultimately making VBB approximately equal to VDD; simultaneously, since the voltage value of VCC_ISP is 0V, the voltage difference V between the gate and source of the N-channel MOSFET Q2 is... GS The conduction condition of the N-channel MOSFET Q2 was not met. Since the enable control signal EN is pulled up to VBB through the pull-up resistor R4, jumper cap J2 needs to be installed to make the enable control signal EN directly grounded, resulting in an invalid low level. This keeps the signals across the bidirectional level conversion chip U2 in a high-impedance state, equivalent to a disconnect. Therefore, the signals in the QSPI interface of the CPU / FPGA / DSP are disconnected from the configuration chip U3. In this way, the signal pins of the configuration chip U3 are only connected to the programmer / programmer through the ISP interface. Simultaneously, the power supply VBB of the configuration chip U3 is normal, allowing in-circuit programming of the configuration chip. The energy consumed during the programming process is provided by VDD.

[0030] This embodiment is designed according to the QSPI interface configuration chip. Since some configuration chips only support the SPI interface, the QSPI_D2 and QSPI_D3 signals in the QSPI interface are control signals for the SPI interface. At the A terminal of the bidirectional level conversion chip U2, these control signals are pulled up through pull-up resistors R2 and R3 to invalidate them, so that the SPI interface configuration chip can be programmed normally.

[0031] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for online programming and configuration of a chip, characterized in that, include: A bidirectional level conversion chip is used to disconnect or close the connection between the QSPI interface signal of the CPU, FPGA or DSP and the configuration chip. The bidirectional level conversion chip has independent A-end and B-end power supply and signal connection channels at both ends, and supports the same or different power supply voltages at both ends. It supports interconnection or level conversion of signals with the same or different levels at both ends, and the signal transmission direction does not need to be controlled; the enable control signal of the bidirectional level conversion chip is controlled by a field-effect transistor and a jumper cap. The power supply to the bidirectional level conversion chip and the configuration chip is controlled by a field-effect transistor; An ISP interface is used to provide a signal connection channel between the programmer or programmer and the configuration chip. The programmer or programmer provides additional power to the bidirectional level conversion chip and the configuration chip through the ISP interface. Diodes are used to isolate the different power supplies of the bidirectional level conversion chip and the configuration chip. When the ISP interface is floating, the signals and power supply in the QSPI interface of the CPU, FPGA or DSP are connected to the configuration chip to complete the functions of the CPU, FPGA or DSP and configuration chip under normal product use. When the programmer or burner is plugged into the ISP interface, the connection between the QSPI interface signal of the CPU, FPGA, or DSP and the configuration chip is automatically or manually disconnected, depending on the type of programmer or burner. The signal pins of the configuration chip are only connected to the programmer or burner, thereby realizing the function of online programming of the configuration chip. The type of programmer or burner includes whether the programmer or burner has an external power supply output function. The field-effect transistor used to implement the enable control signal is an N-channel MOS type; the drain of the N-channel MOS type field-effect transistor is pulled up to the A terminal of the bidirectional level conversion chip for power supply and connected to the enable control signal; the gate of the N-channel MOS type field-effect transistor is pulled down to ground and connected to the power supply of the ISP interface; the source of the N-channel MOS type field-effect transistor is connected to ground; The field-effect transistor used to control the power supply of the bidirectional level conversion chip and the configuration chip is a P-channel MOS type; the drain of the P-channel MOS type field-effect transistor is connected to the power supply in the QSPI interface of the CPU, FPGA or DSP; the gate of the P-channel MOS type field-effect transistor is pulled down to ground and connected to the power supply of the ISP interface; the source of the P-channel MOS type field-effect transistor is connected to the power supply of the bidirectional level conversion chip and the configuration chip; the power supply control of the bidirectional level conversion chip and the configuration chip is realized by the voltage between the body diode and the gate and source of the P-channel MOS type field-effect transistor. The diode is a forward voltage drop Schottky diode to isolate the power supply to the bidirectional level shifting chip and configuration chip from the QSPI and ISP interfaces of the CPU, FPGA, or DSP. The gate voltage VCC_ISP of the P-channel MOSFET Q1 is connected to the power supply VBB of the bidirectional level shifting chip U2 and the configuration chip U3 through the Schottky diode D1. The power supply VDD and VCC_ISP in the QSPI interface of the CPU, FPGA, or DSP are isolated through the Schottky diode D1.

2. The method for online programming and configuration of chips according to claim 1, characterized in that, The bidirectional level conversion chip has the following configuration: The bidirectional level conversion chip supports multiple signal connections to connect the QSPI interface signals of the CPU, FPGA, or DSP to the configuration chip using multiple signals. The bidirectional level conversion chip supports push-pull and open-drain signal types; The bidirectional level conversion chip has electrostatic discharge protection.

3. The method for online programming and configuring chips according to claim 1, characterized in that, The bidirectional level conversion chip has a high-level active enable control signal; When the enable control signal is valid, the connection between the QSPI interface signal of the CPU, FPGA, or DSP and the configuration chip is closed. When the enable control signal is invalid, the connection between the QSPI interface signal of the CPU, FPGA, or DSP and the configuration chip is disconnected.

4. The method for online programming and configuration of chips according to claim 1, characterized in that, The ISP interface provides a signal connection channel between the programmer or burner and the configuration chip. The programmer or burner provides additional power to the bidirectional level conversion chip and the configuration chip through the ISP interface. The ISP interface supports configuration chips with QSPI and SPI interfaces.

5. The method for online programming and configuration of chips according to claim 1, characterized in that, When the ISP interface is left floating (i.e., the programmer or burner is not inserted into the ISP interface), the enable control signal is effective, automatically closing the connection between the QSPI interface signal of the CPU, FPGA, or DSP and the configuration chip. At the same time, the field-effect transistor controlling the power supply of the bidirectional level conversion chip and the configuration chip is turned on, and the power supply of the bidirectional level conversion chip and the configuration chip is provided by the power supply in the QSPI interface of the CPU, FPGA, or DSP, thereby completing the functions of the CPU, FPGA or DSP and the configuration chip under normal product use.

6. The method for online programming and configuration of a chip according to claim 1, characterized in that, When the programmer or programmer is plugged into the ISP interface, if the programmer or programmer has an external power supply output function, the enable control signal of the bidirectional level conversion chip is invalid, which disconnects the connection between the QSPI interface signal of the CPU, FPGA, or DSP and the configuration chip, so that the signal pins of the configuration chip are only connected to the programmer or programmer; at the same time, the field-effect transistors that control the power supply of the bidirectional level conversion chip and the configuration chip are turned off, and the power supply in the QSPI interface is supplied to the bidirectional level conversion chip and the configuration chip through the body diode of the field-effect transistor or through the programmer or programmer via the ISP interface, so that the programmer or programmer can complete the online programming of the configuration chip.

7. The method for online programming and configuration of a chip according to claim 1, characterized in that, When the programmer or programmer is plugged into the ISP interface, if the programmer or programmer does not have an external power output function, the jumper cap needs to be installed. This disables the enable control signal of the bidirectional level conversion chip, disconnecting the QSPI interface signal of the CPU, FPGA, or DSP from the configuration chip. This allows the signal pins of the configuration chip to be connected only to the programmer or programmer. Simultaneously, the field-effect transistor controlling the power supply to the bidirectional level conversion chip and the configuration chip is turned on. The power supply to the bidirectional level conversion chip and the configuration chip is provided by the QSPI interface of the CPU, FPGA, or DSP, allowing the programmer or programmer to complete the online programming of the configuration chip.

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