A pcie port order identification system and method

Abstract

The application belongs to the technical field of PCIE port identification, and specifically provides a PCIE port sequence identification system and method. The system comprises a board card and a mainboard. A mainboard logic chip and a high-speed connector are arranged on the mainboard. A PWM duty ratio or frequency of each port is pre-configured by a mainboard CPU, and the configuration of each port is different. At least one pin of each high-speed connector is selected and set as a detection special pin. The detection special pin of the high-speed connector communicates with the mainboard logic chip. The mainboard logic chip is connected with the board card through the detection special pin. The pre-configured PWM duty ratio or frequency sent by the mainboard logic chip is sent to the corresponding board card. The received PWM duty ratio or frequency is processed, and information is returned to the mainboard logic chip or BMC. The mainboard logic chip analyzes the received information, and records the port attribution information of the corresponding board card to the BMC. The port attribution of PCIE can be quickly distinguished.

Description

Technical Field

[0001] This invention relates to the field of PCIe port identification technology, and specifically to a PCIe port sequence identification system and method. Background Technology

[0002] With the rapid development of the times, the number of high-speed I / O ports of CPUs has gradually increased, and the number of PCIe lanes can be increased to a maximum of 128 lanes and 64 ports. These ports can be used to connect devices such as NVMe hard drives, GPU cards, network cards, and RAID cards. When there are multiple identical devices, the sorting is crucial for maintenance and daily use. The OS can locate the specific card's position by the port order in the CPU.

[0003] Port IDs are defined by defining a set of I2C pins on the PCIe port or by using 2-4 pins. The I2C method is more common. The information is written to the backplane CPLD register or the Riser's FRU via I2C to record the source and ownership information of the current port. Finally, the BMC processes the information from the CPLD register or FRU and displays it on the Web.

[0004] Writing to the FRR or CPLD register via I2C requires at least 4 pins on the high-speed connector, and some designs often do not have 4 IOs available for I2C communication. Summary of the Invention

[0005] Port IDs are defined by either setting a set of I2C pins on the PCIe port or using 2-4 pins. The I2C method is more common. The I2C data is written to the backplane CPLD register or the Riser's FRU to record the port's origin and ownership information. Finally, the BMC processes the information from the CPLD register or FRU and displays it on the web interface. Writing to the FRR or CPLD register via I2C requires at least four pins on the high-speed connector. In some designs, four I / O pins are not available for I2C communication. This invention provides a PCIe port sequence identification system and method.

[0006] In a first aspect, the present invention provides a PCIE port sequence identification system, including a board, a BMC, and a motherboard with a CPU;

[0007] The motherboard is equipped with a motherboard logic chip and a high-speed connector.

[0008] The motherboard CPU pre-configures the PWM duty cycle or frequency for each port, and the configuration for each port is different;

[0009] At least one pin of each high-speed connector is selected as a dedicated detection pin, which communicates with the motherboard logic chip.

[0010] The motherboard logic chip communicates with the board via dedicated detection pins;

[0011] The motherboard logic chip sends a pre-configured PWM duty cycle or frequency to the corresponding board. The board processes the pre-configured PWM duty cycle or frequency sent by the motherboard logic chip and returns the information to the motherboard logic chip or BMC.

[0012] The motherboard logic chip communicates with the BMC to parse the received information and record the port affiliation information of the corresponding board to the BMC.

[0013] Preferably, the board includes a first type of board and / or a second type of board; the first type of board is a board with a logic chip, and the second type of board is a board without a logic chip.

[0014] The motherboard logic chip connects to the logic chip of the first type of board through a dedicated detection pin; the motherboard logic chip sends a pre-configured PWM duty cycle or frequency to the logic chip of the corresponding board; the logic chip of the first type of board analyzes the pre-configured PWM duty cycle or frequency sent by the motherboard logic chip; the logic chip of the first type of board communicates with the BMC and records the port affiliation information of the corresponding board to the BMC.

[0015] The second type of board is equipped with a duty cycle inversion module or a frequency divider module;

[0016] The duty cycle inversion module or frequency divider module on each type II board is connected to the detection pin of the high-speed connector connected to the board. This is used to send the pre-configured PWM duty cycle or frequency issued by the motherboard logic chip to the corresponding duty cycle inversion module or frequency divider module for processing, and return the processed information to the motherboard logic chip.

[0017] The motherboard logic chip communicates with the BMC to parse the received processed information and record the port affiliation information of the corresponding board to the BMC.

[0018] Preferably, the logic chip on the first type of board communicates with the BMC via I2C.

[0019] Preferably, the second type of board includes a Riser card and a backplane without logic chips;

[0020] The first type of board includes a backplane with logic chips.

[0021] Preferably, each type II board is equipped with a power supply, and each high-speed connector has a dedicated detection pin including a first dedicated detection pin and a second dedicated detection pin;

[0022] The duty cycle inversion module includes a MOSFET. The gate of the MOSFET is connected to the first detection pin of the high-speed connector connected to the board on which the MOSFET is located. The drain of the MOSFET is connected to the second detection pin of the high-speed connector connected to the board on which the MOSFET is located. The drain of the MOSFET is also connected to the power supply of the board on which the MOSFET is located through a resistor. The source of the MOSFET is grounded.

[0023] Preferably, the MOS transistor is a P-type MOS transistor.

[0024] Preferably, the frequency divider module includes a D flip-flop;

[0025] When the frequency divider module includes a D flip-flop, the input terminal of the D flip-flop is connected to the first detection pin of the high-speed connector connected to the board on which the D flip-flop is located, and the output terminal of the D flip-flop is connected to the second detection pin of the high-speed connector connected to the board on which the D flip-flop is located.

[0026] Preferably, when the frequency divider module includes more than one D flip-flop, all D flip-flops are cascaded, the input terminal of the first D flip-flop is connected to the first detection pin of the high-speed connector connected to the board on which the D flip-flop is located, and the output terminal of the last D flip-flop is connected to the second detection pin of the high-speed connector connected to the board on which the D flip-flop is located.

[0027] Secondly, the present invention also provides a PCIE port sequence identification method based on the system described in the first aspect, the method comprising the following steps:

[0028] The motherboard logic chip sends the PWM duty cycle or frequency to the corresponding board according to the preset configuration;

[0029] When the motherboard logic chip receives the return information within a set time, it determines that the board is a board without a logic chip, parses the received return information, and records the port ownership information of the current board to the BMC.

[0030] If the motherboard logic chip does not receive a return message within a set time, it determines that the board is a board with a logic chip. The logic chip on the board will parse the received return message and record the port ownership information of the current board to the BMC.

[0031] As can be seen from the above technical solutions, this invention has the following advantages: With an increasing number of PCIe devices on a single server, it can quickly distinguish the port affiliation of PCIe devices and the order of multiple PCIe devices, improving maintainability and aiding in fault location. Different ports are distinguished by different PWM duty cycles and frequencies, saving I2C protocol development resources and reducing development difficulty, costs, and time.

[0032] Furthermore, the design principle of this invention is reliable, the structure is simple, and it has a very wide range of application prospects.

[0033] Therefore, it is evident that the present invention has outstanding substantive features and significant progress compared with the prior art, and the beneficial effects of its implementation are also obvious. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic block diagram of a system according to an embodiment of the present invention.

[0036] Figure 2 This is a schematic diagram of a rotation ratio reversal module according to an embodiment of the present invention.

[0037] Figure 3 This is a schematic diagram of a frequency division module according to an embodiment of the present invention. Detailed Implementation

[0038] When there are multiple identical devices, sorting is crucial for maintenance and daily use. The OS can locate the specific card's position through the port order in the CPU. This is achieved by defining a set of I2C pins on the PCIe port or using 2-4 pins as port IDs. The I2C method is more common. The I2C data is written to the backplane CPLD register or the Riser's FRU to record the current port's origin and ownership information. Finally, the BMC processes the information from the CPLD register or FRU and displays it on the web. Writing to the FRR or CPLD register via I2C requires at least 4 pins on the high-speed connector; some designs lack 4 I / O pins for I2C communication. To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0039] This invention provides a PCIe port sequence identification system, including a board, a BMC, and a motherboard with a CPU;

[0040] The motherboard is equipped with a motherboard logic chip and a high-speed connector.

[0041] The motherboard CPU pre-configures the PWM duty cycle or frequency for each port, and the configuration for each port is different;

[0042] At least one pin of each high-speed connector is selected as a dedicated detection pin, which communicates with the motherboard logic chip.

[0043] The motherboard logic chip communicates with the board via dedicated detection pins;

[0044] The motherboard logic chip sends a pre-configured PWM duty cycle or frequency to the corresponding board. The board processes the pre-configured PWM duty cycle or frequency sent by the motherboard logic chip and returns the information to the motherboard logic chip or BMC.

[0045] The motherboard logic chip communicates with the BMC to parse the received information and record the port affiliation information of the corresponding board to the BMC.

[0046] It should be noted that when the number of CPU ports to be detected is less than 10, which is 4 in this case, all boards are equipped with logic chips. The PWM duty cycles of the first to fourth ports are set to 10%, 20%, 30%, and 40% respectively. When the motherboard logic chip sends a PWM duty cycle of 30%, the logic chip on the board receives the PWM duty cycle of 30%, determines that the board is connected to the third port, and records the port affiliation information of the current board to the BMC.

[0047] In some embodiments, the board includes a first type of board and / or a second type of board; the first type of board is a board with a logic chip, and the second type of board is a board without a logic chip.

[0048] The motherboard logic chip connects to the logic chip of the first type of board through a dedicated detection pin; the motherboard logic chip sends a pre-configured PWM duty cycle or frequency to the logic chip of the corresponding board; the logic chip of the first type of board analyzes the pre-configured PWM duty cycle or frequency sent by the motherboard logic chip; the logic chip of the first type of board communicates with the BMC and records the port affiliation information of the corresponding board to the BMC.

[0049] The second type of board is equipped with a duty cycle inversion module or a frequency divider module;

[0050] The duty cycle inversion module or frequency divider module on each type II board is connected to the detection pin of the high-speed connector connected to the board. This is used to send the pre-configured PWM duty cycle or frequency issued by the motherboard logic chip to the corresponding duty cycle inversion module or frequency divider module for processing, and return the processed information to the motherboard logic chip.

[0051] The motherboard logic chip communicates with the BMC to parse the received processed information and record the port affiliation information of the corresponding board to the BMC.

[0052] The duty cycle inversion module is used to invert the received PWM duty cycle before outputting it.

[0053] The frequency divider module is used to divide the received frequency.

[0054] When the number of CPU ports to be monitored is less than 10 (4 in this case), the PWM duty cycles of the first to fourth ports are set to 10%, 20%, 30%, and 40% respectively. When the motherboard logic chip emits a PWM duty cycle of 30%, and a PWM duty cycle of 70% is received within a set time, it is determined that the current board is a board without a logic chip, the third port is connected, and the port ownership information of the current board is recorded in the BMC. If no return information is received within the set time, it is determined that the current board is a board with a logic chip. When the board's logic chip receives a PWM duty cycle of 70%, it is determined that the third port is connected, and the board's logic chip records the port ownership information of the current board in the BMC.

[0055] When the number of CPU ports to be tested is greater than 10 (N in this case), for ease of testing, a frequency divider module (divided by 2 in this case) is set on all connected boards. The frequencies of the first to Nth ports are set to 100Hz, 200Hz, ..., N*100Hz. When the motherboard logic chip emits a frequency of 100Hz, and a frequency of 50Hz is received within a set time, the board is determined to be without a logic chip. The first port is then connected, and the port ownership information of the current board is recorded in the BMC. If no return information is received within the set time, the board is determined to be equipped with a logic chip. When the board's logic chip receives a frequency of 100Hz, the first port is connected, and the board's logic chip records the port ownership information of the current board in the BMC.

[0056] In some embodiments, the logic chip on the first type of board communicates with the BMC via I2C.

[0057] The second type of board includes Riser cards and backplanes without logic chips;

[0058] The first type of board includes a backplane with logic chips.

[0059] like Figure 1As shown, when the number of CPU ports to be tested is greater than 10, in this case 2N+5, the boards connected to the ports sequentially include N backplanes with logic chips, N Riser cards with frequency divider modules, and 5 Riaer cards with duty cycle inversion modules. The frequency divider modules on the boards are set to divide by two, and the frequencies of the first to the Nth ports are set to 100Hz, 200Hz, ..., N*100Hz; the frequencies of the (N+1)th to the 2Nth ports are set to 1MHz, 2MHz, ..., N*MHz; and so on. The PWM duty cycles for ports 2N+1 to 2N+5 are 10%, 20%, 30%, 40%, and 50%, respectively. When the motherboard logic chip emits a frequency of 2MHz and receives a frequency of 1MHz within a set time, it is determined that the current board has no logic chip, and the N+2 port is connected, recording the port assignment information of the current board to the BMC. When the motherboard logic chip emits a frequency of 200Hz and the board's logic chip receives a frequency of 200Hz, it is determined that the second port is connected, and the board's logic chip records the port assignment information of the current board to the BMC. When the motherboard logic chip emits a PWM duty cycle of 30% and receives a PWM duty cycle of 70% within a set time, it is determined that the current board has no logic chip, and the 2N+3 port is connected, recording the port assignment information of the current board to the BMC; here, the logic chip is a CPLD.

[0060] In some embodiments, each board is provided with a power supply, and each high-speed connector has a dedicated detection pin including a first dedicated detection pin and a second dedicated detection pin.

[0061] like Figure 2 As shown, the duty cycle inversion module includes a MOSFET. The gate of the MOSFET is connected to the first detection pin of the high-speed connector connected to the board on which the MOSFET is located. The drain of the MOSFET is connected to the second detection pin of the high-speed connector connected to the board on which the MOSFET is located. The drain of the MOSFET is also connected to the power supply of the board on which the MOSFET is located through a resistor. The source of the MOSFET is grounded.

[0062] The MOS transistor is a P-type MOS transistor.

[0063] In some embodiments, the frequency divider module includes a D flip-flop;

[0064] like Figure 3 As shown, when the frequency divider module includes a D flip-flop, the input terminal of the D flip-flop is connected to the first detection pin of the high-speed connector connected to the board on which the D flip-flop is located, and the output terminal of the D flip-flop is connected to the second detection pin of the high-speed connector connected to the board on which the D flip-flop is located.

[0065] When the frequency divider module includes more than one D flip-flop, all D flip-flops are cascaded. The input of the first D flip-flop is connected to the first detection pin of the high-speed connector connected to the board on which the D flip-flop is located, and the output of the last D flip-flop is connected to the second detection pin of the high-speed connector connected to the board on which the D flip-flop is located.

[0066] However, if the riser card has two identical ports, one port can be flipped while the other returns to its original path. This will allow you to determine that the same riser has two ports connected.

[0067] This invention also provides a method for PCIe port sequence identification based on the system described in the first aspect, the method comprising the following steps:

[0068] The motherboard logic chip sends the PWM duty cycle or frequency to the corresponding board according to the preset configuration;

[0069] When the motherboard logic chip receives the return information within a set time, it determines that the board is a board without a logic chip, parses the received return information, and records the port ownership information of the current board to the BMC.

[0070] If the motherboard logic chip does not receive a return message within a set time, it determines that the board is a board with a logic chip. The logic chip on the board will parse the received return message and record the port ownership information of the current board to the BMC.

[0071] Although the present invention has been described in detail with reference to the accompanying drawings and preferred embodiments, the invention is not limited thereto. Various equivalent modifications or substitutions can be made to the embodiments of the invention by those skilled in the art without departing from the spirit and essence of the invention, and such modifications or substitutions should all be within the scope of the invention. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the invention should also be covered within the protection scope of the invention. Therefore, the protection scope of the invention should be determined by the scope of the claims.

Claims

1. A PCIe port sequence identification system, characterized in that, This includes circuit boards, BMC, and motherboards with CPUs. The motherboard is equipped with a motherboard logic chip and a high-speed connector. The motherboard CPU pre-configures the PWM duty cycle or frequency for each port, and the configuration for each port is different; At least one pin of each high-speed connector is selected as a dedicated detection pin, which communicates with the motherboard logic chip. The motherboard logic chip communicates with the board via dedicated detection pins; The motherboard logic chip sends a pre-configured PWM duty cycle or frequency to the corresponding board. The board processes the pre-configured PWM duty cycle or frequency sent by the motherboard logic chip and returns the information to the motherboard logic chip or BMC. The motherboard logic chip communicates with the BMC to parse the received information and record the port affiliation information of the corresponding board to the BMC. The board includes a first type of board and / or a second type of board; the first type of board is a board with a logic chip, and the second type of board is a board without a logic chip. The motherboard logic chip connects to the logic chip of the first type of board through a dedicated detection pin; the motherboard logic chip sends a pre-configured PWM duty cycle or frequency to the logic chip of the corresponding board; the logic chip of the first type of board analyzes the pre-configured PWM duty cycle or frequency sent by the motherboard logic chip; the logic chip of the first type of board communicates with the BMC and records the port affiliation information of the corresponding board to the BMC. The second type of board is equipped with a duty cycle inversion module or a frequency divider module; The duty cycle inversion module or frequency divider module on each type II board is connected to the detection pin of the high-speed connector connected to the board. This is used to send the pre-configured PWM duty cycle or frequency issued by the motherboard logic chip to the corresponding duty cycle inversion module or frequency divider module for processing, and return the processed information to the motherboard logic chip. The motherboard logic chip communicates with the BMC to parse the received processed information and record the port affiliation information of the corresponding board to the BMC. The logic chips on the first type of board communicate with the BMC via I2C. The duty cycle inversion module is used to invert the received PWM duty cycle before outputting it. The frequency divider module is used to divide the received frequency by two. Each Class II board is equipped with a power supply, and each high-speed connector has a dedicated detection pin, including a first dedicated detection pin and a second dedicated detection pin. The duty cycle inversion module includes a MOSFET. The gate of the MOSFET is connected to the first detection pin of the high-speed connector connected to the board on which the MOSFET is located. The drain of the MOSFET is connected to the second detection pin of the high-speed connector connected to the board on which the MOSFET is located. The drain of the MOSFET is also connected to the power supply of the board on which the MOSFET is located through a resistor. The source of the MOSFET is grounded. The motherboard logic chip is configured to perform the following steps: Send the PWM duty cycle or frequency to the corresponding board according to the preset configuration; When a return message is received within a set time, the board is determined to be a board without a logic chip, and the received return message is parsed and the port ownership information of the current board is recorded in the BMC. If no return information is received within the set time, the board is determined to be a board with a logic chip. The logic chip on the board will parse the received return information and record the port affiliation information of the current board to the BMC.

2. The PCIe port sequence identification system according to claim 1, characterized in that, The second type of board includes Riser cards and backplanes without logic chips; The first type of board includes a backplane with logic chips.

3. The PCIe port sequence identification system according to claim 1, characterized in that, The MOS transistor is a P-type MOS transistor.

4. The PCIe port sequence identification system according to claim 1, characterized in that, The frequency divider module includes a D flip-flop; When the frequency divider module includes a D flip-flop, the input terminal of the D flip-flop is connected to the first detection pin of the high-speed connector connected to the board on which the D flip-flop is located, and the output terminal of the D flip-flop is connected to the second detection pin of the high-speed connector connected to the board on which the D flip-flop is located.

5. The PCIe port sequence identification system according to claim 4, characterized in that, When the frequency divider module includes more than one D flip-flop, all D flip-flops are cascaded. The input of the first D flip-flop is connected to the first detection pin of the high-speed connector connected to the board on which the D flip-flop is located, and the output of the last D flip-flop is connected to the second detection pin of the high-speed connector connected to the board on which the D flip-flop is located.

6. A method for PCIe port sequence identification based on the system described in any one of claims 1-5, characterized in that, The method includes the following steps: The motherboard logic chip sends the PWM duty cycle or frequency to the corresponding board according to the preset configuration; When the motherboard logic chip receives the return information within a set time, it determines that the board is a board without a logic chip, parses the received return information, and records the port ownership information of the current board to the BMC. If the motherboard logic chip does not receive a return message within a set time, it determines that the board is a board with a logic chip. The logic chip on the board will parse the received return message and record the port ownership information of the current board to the BMC.

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