Space hardware accelerated processing system, method, and storage medium

Abstract

The application relates to a space hardware acceleration processing system, method and storage medium, which comprises a data high-speed internal bus for massive data transmission between modules, an instruction internal bus for instructions between modules, an instruction sequence buffer module for storing and taking out instructions according to a first-in-first-out sequence, an instruction analysis and scheduling control module for inquiring and judging whether there is an instruction in the instruction sequence buffer module and whether the instruction is executed according to the result, a data cache module for caching data, an acceleration core module for accelerating data processing, and an acceleration core information storage module for storing corresponding computing resource information and state information. The application realizes real-time information processing speed improvement in the space field, and improves the high-speed processing capability of a space data processing equipment platform in the space field to massive load data.

Description

Technical Field

[0001] This invention relates to the field of accelerated processing technology, specifically to an aerospace hardware accelerated processing system, method, and storage medium. Background Technology

[0002] In recent years, the demand for real-time onboard information processing in the field of spaceflight (hereinafter referred to as aerospace) has become very urgent. Technologies such as artificial intelligence, deep learning, and data analysis and mining are gradually being applied in various fields of aerospace. This requires onboard data processing equipment platforms to have high-speed processing capabilities for massive payload data. Traditional data processing platforms can hardly fully meet the above requirements. Upgrading data processing platforms and accelerating data processing methods for new processing platforms have become urgent problems to be solved.

[0003] To address the aforementioned needs, using FPGAs for data processing acceleration has become a technological trend. Traditional FPGA design methods are based on RTL-level design, with most of the work consumed in design and functional verification. As software functions become increasingly complex, the time spent on design verification using RTL-level methods surges, and functional correctness verification becomes increasingly complex. In particular, timing verification can take months for complex software, making it difficult to meet the adequacy requirements of testing and verification in a short period. Furthermore, changes in requirements can lead to a large amount of new verification work. Therefore, to address these characteristics, this invention adopts a software-based hardware acceleration concept, and proposes an FPGA-based data processing hardware acceleration method and apparatus. Summary of the Invention

[0004] This invention provides a spacecraft hardware acceleration processing system, method, and storage medium. This system, method, and storage medium improve the processing speed of real-time onboard information in the space field, enhancing the high-speed processing capability of onboard data processing equipment platforms for massive payload data.

[0005] One aspect of the present invention provides an aerospace acceleration processing system, including an FPGA acceleration terminal and a main control terminal connected to the FPGA acceleration terminal;

[0006] The FPGA acceleration terminal includes a high-speed data internal bus, an instruction internal bus, an instruction sequence buffer module, an instruction parsing and scheduling control module, a high-speed data buffer module, an acceleration core module, and an acceleration core information storage module.

[0007] The high-speed internal data bus is used for large-scale data transmission between modules;

[0008] The instruction bus is used for instructions between modules;

[0009] The instruction sequence buffer module stores and retrieves instructions according to a first-in-first-out (FIFO) order;

[0010] The instruction parsing and scheduling control module is used to query and determine whether there is an instruction in the instruction sequence buffer module and to determine whether to execute the instruction if there is one.

[0011] The data high-speed buffer module is used to cache data at high speed;

[0012] The acceleration core module is used to accelerate data processing;

[0013] The acceleration core information storage module is used to store the corresponding computing resource information and status information.

[0014] According to one embodiment of the present invention, the instruction sequence buffer module includes an instruction sequence buffer and a delayed instruction sequence buffer;

[0015] The instruction parsing and scheduling control module is used to query and determine whether there is an instruction in the instruction sequence buffer module, determine whether to execute the instruction if there is an instruction in the instruction sequence buffer module, execute the instruction if the instruction is executed, and store the non-executed instruction in the delayed instruction sequence buffer if the instruction is not executed.

[0016] The high-speed buffer module includes a DDR SDRAM controller;

[0017] The acceleration core module includes several acceleration computing cores;

[0018] The acceleration core information storage module includes an acceleration core status indication module and an acceleration core resource pool module;

[0019] in,

[0020] The instruction sequence buffer is used to store the acceleration instruction and the fetch instruction received for the first time by the instruction bus in first-in-first-out order.

[0021] The acceleration core status indication module is used to record the real-time status information of the plurality of acceleration computing cores. The real-time status information includes the initialization status, ready status, computation completed status, and working status of each acceleration computing core.

[0022] The accelerated core resource pool module is used to store the real-time computing resource information of the plurality of accelerated computing cores. The real-time computing resource information includes the number, type, number of layers, and performance of the accelerated computing cores in the current accelerated core module.

[0023] The accelerated computing core has three dimensions of expansion, allowing for flexible dynamic optimization based on hardware resources.

[0024] According to one embodiment of the present invention, the FPGA acceleration terminal is connected to the main control terminal via an interface.

[0025] According to one embodiment of the present invention, the main control terminal includes a CPU for sending instructions and data and an interface for transmitting data; the FPGA acceleration terminal is provided with an input data interface, an output data interface, a data pre-parsing module, a data transfer controller, and an instruction transfer controller;

[0026] The interfaces include SRIO, PCIe, and AXI;

[0027] After receiving data and / or instructions, the data parsing module parses the data to determine whether it has received data or instructions.

[0028] The data transfer controller is configured according to the currently received data and stores the received data in real time in the high-speed data buffer module through the high-speed data internal bus, or sends the data in the high-speed data buffer module to the main control terminal;

[0029] The instruction transfer controller stores the received instructions into the instruction sequence buffer in real time via the instruction intrabus.

[0030] According to one embodiment of the present invention, the main control terminal is tightly coupled to the FPGA acceleration terminal.

[0031] According to one embodiment of the present invention, the data sent by the master control terminal is stored in the data high-speed buffer module through the high-speed data internal bus, and the instructions sent by the master control terminal are stored in the instruction sequence buffer through the instruction internal bus.

[0032] According to one embodiment of the present invention, the main control terminal includes a judgment unit and a processing unit;

[0033] The judgment terminal is used to determine whether the received data and / or instructions need to be processed faster.

[0034] The processing unit is used to add acceleration instructions to the data and / or instructions that need to be processed faster.

[0035] One aspect of the present invention provides a method for implementing space acceleration processing using the aforementioned space acceleration processing system, comprising the following steps:

[0036] The FPGA acceleration terminal receives acceleration commands and / or data;

[0037] The acceleration instructions are stored in the instruction sequence buffer module via the instruction intrabus, and the data is stored in the data high-speed buffer module via the data high-speed intrabus for data access.

[0038] The instruction parsing and scheduling control module queries and determines whether there are instructions in the instruction sequence buffer module. If there are instructions in the instruction sequence buffer module, it determines whether to execute the instructions. If the instructions are executed, the instructions are executed. If the instructions are not executed, the non-executed instructions are stored in the delayed instruction sequence buffer.

[0039] According to an embodiment of the present invention, the step of determining whether to execute the instruction based on the result of having an instruction in the instruction sequence buffer module, and executing the instruction based on the result of executing the instruction, specifically includes:

[0040] When the result of an instruction in the instruction sequence buffer module is determined to perform an instruction execution action, the status of each accelerated computing core in the accelerated core status indication module is traversed to determine the status information of the accelerated computing core. At the same time, the computing resource information of the accelerated computing core in the accelerated core resource pool module is queried according to the current instruction.

[0041] Based on the current instruction, accelerated computing cores that are not in operation and meet the computing resource information described in the instruction are used for accelerated data processing.

[0042] A final aspect of the invention is to provide a readable storage medium. The readable storage medium stores a processing program, which, when executed by a processor, implements the space acceleration processing method according to an embodiment of the invention.

[0043] Compared with the prior art, the present invention has the following beneficial effects:

[0044] The present invention provides an aerospace hardware acceleration processing system, method, and storage medium to improve the processing speed of real-time information on spacecraft in the aerospace field, and to enhance the high-speed processing capability of on-board data processing equipment platforms in the aerospace field for massive payload data. Attached Figure Description

[0045] Figure 1 According to an embodiment of the present invention, a schematic diagram of the structure of a space acceleration processing system is shown;

[0046] Figure 2 According to an embodiment of the present invention, a schematic diagram of another aerospace acceleration processing system is shown;

[0047] Figure 3 According to an embodiment of the present invention, a schematic diagram of an accelerated core module expansion is shown;

[0048] Figure 4 According to an embodiment of the present invention, a flowchart of a space acceleration processing method is shown;

[0049] Figure 5According to an embodiment of the present invention, a flowchart of a spacecraft executing accelerated processing instructions is shown;

[0050] Figure 6 According to an embodiment of the present invention, a schematic diagram of the structure of a computer-readable storage medium is shown. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention. The term "comprising" and its variations used herein indicate open-ended inclusion, i.e., "including but not limited to". Other explicit and implicit definitions may also be included below. In this invention, space travel refers to the travel of artificial Earth satellites, spacecraft, etc., in space within and outside the solar system. For example, timely and rapid acquisition of the trajectory of asteroids and quick determination of their arrival time on Earth facilitates timely subsequent processing.

[0052] This invention consists of two main parts: a main control unit 100 and an FPGA acceleration unit. The main control unit 100 analyzes whether the data needs accelerated processing based on application requirements. If so, it compiles corresponding acceleration instructions and sends them to the FPGA acceleration unit in conjunction with the data.

[0053] Embodiment 1 of the present invention provides a specific implementation of a space acceleration processing system, see [link to specific implementation]. Figure 1 The aerospace acceleration processing system specifically includes the following components:

[0054] A space acceleration processing system includes an FPGA acceleration terminal and a main control terminal 100 connected to the FPGA acceleration terminal;

[0055] The FPGA acceleration terminal includes a high-speed data bus 112, an instruction bus 113, an instruction sequence buffer module, an instruction parsing and scheduling control module 106, a high-speed data buffer module, an acceleration core module 110, and an acceleration core information storage module.

[0056] The transmitted instructions and data are both accelerated instructions and data sources that require accelerated processing; the high-speed data bus 112 and the instruction bus 113 can work independently and are designed with isolation to prevent mutual interference, while improving parallelism and reliability.

[0057] The high-speed internal data bus 112 is used for large-scale data transmission and interaction between modules, including input and output of the FPGA acceleration end. The internal instruction bus 113 is used for instruction transmission between modules, including interaction between instructions, telemetry, and remote control. The instruction sequence buffer module stores and retrieves instructions according to the first-in-first-out order. This instruction sequence buffer module includes an instruction sequence buffer 105 and a delayed instruction sequence buffer 107.

[0058] The data cache module is used for high-speed data caching. This data cache module includes a DDR SDRAM controller 111. The DDR SDRAM controller 111 can be connected to one or more external hardware units for high-speed data caching.

[0059] The acceleration core module 110 is used to accelerate data processing and includes several acceleration computing cores. These acceleration computing cores have three-dimensional expansion capabilities, allowing for flexible dynamic optimization based on hardware resources. For example, multiple general-purpose acceleration computing cores with different functions, such as acceleration computing core 1 and acceleration computing core n, collectively constitute a three-dimensional elastically expandable microsystem architecture. This architecture can be invoked by the instruction parsing and scheduling control module 106 or directly by the main control terminal 100 as needed. The acceleration computing cores have elastic expansion capabilities in three dimensions: X, Y, and Z. The X-direction represents the scalability of the general-purpose acceleration computing core's capabilities (i.e., performance elastic expansion); the Y-direction represents the scalability of the types of general-purpose acceleration computing cores (i.e., classification); and the Z-direction represents the expansion of the same type of acceleration computing core (i.e., expansion of the entire acceleration core's layer count). This elastic expansion, based on resource availability, effectively improves data processing speed and achieves multi-dimensional win-win acceleration. The aforementioned acceleration computing cores are mainly composed of FPGA logic resources and DSP resources.

[0060] The acceleration core information storage module stores relevant computing resource and status information. This module includes an acceleration core status indicator module 108 and an acceleration core resource pool module 109. The acceleration core resource pool module 109 stores information such as the number, type, and parameters of general-purpose computing cores in the current design, which is then queried by the instruction parsing and scheduling control module 106. It is composed of high-speed SRAM within the FPGA and receives registration information for each acceleration core, which is managed by the instruction parsing and scheduling control module 106.

[0061] The instruction sequence buffer 105 is used to store the first acceleration instruction and fetch instruction received by the instruction bus 113 in a first-in-first-out order; the acceleration core status indicator module 108 is used to record the real-time status information of the plurality of acceleration computing cores, including the initialization status, ready status, computation completed status, and working status of each acceleration computing core; the acceleration core resource pool module 109 is used to store the real-time computing resource information of the plurality of acceleration computing cores, including the number, type, number of layers, and performance of the acceleration computing cores in the current acceleration core module 110.

[0062] The instruction parsing and scheduling control module 106 is used to parse and schedule instructions. The module reads the instruction codes in the instruction sequence buffer 105 sequentially and parses them, for example, parses accelerated instructions. Direct instructions are executed directly, while other instructions are executed sequentially according to priority, rather than processing instructions based on their first-in, first-out order in the instruction sequence buffer. Before executing an accelerated instruction, it first needs to request the corresponding accelerated core resources from the accelerated core resource pool (i.e., accelerated computing cores 1 to n corresponding to accelerated computing core module 110). If accelerated core resources are available, the corresponding accelerated computing core is invoked, and relevant status information is maintained. If no accelerated core resources are available, the instruction is placed in the delayed instruction sequence buffer 107 for later invocation. If a delayed instruction is repeatedly invoked without execution, an error indication is given, and the instruction is discarded to prevent the delayed instruction sequence buffer 107 from overflowing due to errors.

[0063] The instruction parsing and scheduling control module 106 includes a CPU, RTL, or HLS, used to parse the open hardware acceleration instruction set, request corresponding acceleration resources from the acceleration core resource pool based on the parsing results, and manage the resource pool. If resources are not successfully requested, the instruction is stored in the delayed instruction sequence buffer 107. This instruction parsing and scheduling control module 106 can execute several open hardware acceleration instructions simultaneously. This open hardware acceleration instruction set is a complete instruction set formed for hardware acceleration. Its characteristics include that it can be extended for different computing acceleration cores and is open to users, allowing for customized development according to rules as needed.

[0064] The instruction parsing and scheduling control is also used to read the instruction sequence in the instruction sequence buffer 105 through the instruction intrabus 113 and parse the instructions. At the same time, it queries the acceleration core status indicator module 108 through the instruction intrabus 113, and if needed, it requests acceleration resources from the acceleration core resource pool for computing through the instruction intrabus 113.

[0065] The instruction parsing and scheduling control module 106 is used to query and determine whether there is an instruction in the instruction sequence buffer module, determine whether to execute the instruction if there is an instruction in the instruction sequence buffer module, execute the instruction if the instruction is executed, and store the non-executed instruction in the delayed instruction sequence buffer 107 if the instruction is not executed.

[0066] Embodiment 2 of the present invention provides another specific implementation of a space acceleration processing system, see [link to embodiment 2]. Figure 1 The aerospace acceleration processing system specifically includes the following components:

[0067] An aerospace acceleration processing system includes a main control terminal 100 that is independent of the FPGA acceleration terminal and connected to it via an interface.

[0068] The main control terminal 100 includes a CPU for sending instructions and data, and an interface for transmitting data; the FPGA acceleration terminal is equipped with an input data interface, an output data interface, a data pre-parsing module 102, a data transfer controller 103, and an instruction transfer controller 104.

[0069] The main control unit 100 also includes a judgment unit and a processing unit. The judgment unit is used to determine whether the received data and / or instructions need to be accelerated; the processing unit is used to add acceleration instructions to the data and / or instructions that need to be accelerated.

[0070] The main control terminal 100 of this invention analyzes whether the data needs accelerated processing according to application requirements. If so, it compiles corresponding acceleration instructions and sends them to the FPGA acceleration terminal via a high-speed interface. The high-speed interface uses the SRIO interface as an example, but other types of interfaces such as PCIE and AXI can also be used. The data can be obtained from DDR or other high-speed caches by instructing the FPGA acceleration terminal via instructions, or it can be sent directly to the FPGA terminal via the high-speed interface.

[0071] The interfaces include SRIO, PCIe, and AXI. The SRIO interface controller has bidirectional communication capabilities, enabling simultaneous sending and receiving of commands and data. It can be distinguished by physical address, eliminating the need for separate channel transmission. When the SRIO interface controller receives data from the master controller 100, it parses the protocol and converts it into a data format recognizable by the next-level module. When it needs to transmit accelerated processing results to the master controller 100, it receives data from the next-level module, converts it into a data format recognizable by the master module, and sends it to the master controller 100. For example, the interface uses the X4 SRIO 2.1 standard interface, with a speed reaching 20Gbps. The interface speed can be adjusted accordingly as needed. The parsed data is then converted from serial to parallel before being output to the next-level module.

[0072] The data parsing module is used to parse the data header, distinguish between instructions and data, and send the distinguished instructions to the instruction transfer controller 104 and the distinguished data to the data transfer controller 103. For example, the data parsing module can distinguish data content according to different addresses and distribute the distinguished data through different channels.

[0073] After receiving data from the SRIO interface controller at the acceleration end via the parallel interface, the data parsing module first determines the location of the address information according to the data protocol, and then distinguishes between acceleration instructions and data according to the address encoding. For example, in this implementation, the range 0x70000000 to 0x70010000 is designated as the instruction series area; when data falls within this range, it is sent to the instruction transfer controller 104. The range 0x80000000 to 0xFFFFFFFF is the data area; when data falls within this range, it is sent to the data transfer controller 103. The data transfer controller 103 and instruction transfer controller 104 include DMA, DATAMOVER, or a processor to quickly complete data transfer. The data transfer controller 103 is used for high-speed streaming data write-to-memory operations, transferring data from the previous level to the corresponding address memory. After the transfer is complete, a completion flag is generated for use by the instruction parsing and scheduling control module 106. The instruction shift controller 104 is used to push the accelerated instruction sequence onto the stack. Its next level is the high-speed instruction sequence buffer 105. The instructions in the buffer are first-in-first-out by default and can be processed in a streaming manner.

[0074] The data transfer controller 103 configures itself based on the information of the currently received data and stores the received data in real time into the data buffer module via the high-speed data bus 112, or sends the data in the data buffer module to the master control terminal 100. Specifically, the data transfer controller 103 configures the data transfer device to store the data in real time into the corresponding address in the corresponding data buffer module via the high-speed data bus 112 based on the currently received data length, data address, and other information. It also generates a data completion status for querying by the instruction parsing and scheduling control module 106. The data transfer controller 103 can also send data from the corresponding address in the data buffer module to the master control terminal 100.

[0075] Specifically, the instruction transfer controller 104 pre-parses the received data and stores the instructions sent to it in real time into the instruction sequence buffer 105 via the instruction bus 113. The instruction transfer controller 104 sends the received instruction sequence to the instruction sequence buffer 105, and the instructions are arranged in chronological order, following a first-in, first-out (FIFO) principle.

[0076] Embodiment 3 of the present invention provides another specific implementation of a space acceleration processing system, see [link to embodiment 3]. Figure 2 The aerospace acceleration processing system specifically includes the following components:

[0077] An aerospace acceleration processing system includes a main control terminal 100 integrated into the FPGA acceleration terminal, that is, the main control terminal 100 is tightly coupled within the FPGA acceleration terminal.

[0078] The data sent by the master control terminal 100 is stored in the data high-speed buffer module through the high-speed data bus 112, and the instructions sent by the master control terminal 100 are stored in the instruction sequence buffer 105 through the instruction bus 113.

[0079] The main control unit 100 also includes a judgment unit and a processing unit. The judgment unit is used to determine whether the received data and / or instructions need to be accelerated; the processing unit is used to add acceleration instructions to the data and / or instructions that need to be accelerated.

[0080] The main control terminal 100 of this invention analyzes whether the data needs accelerated processing according to application requirements. If so, it compiles corresponding acceleration instructions and sends them to the FPGA acceleration terminal via a high-speed interface. The high-speed interface uses the SRIO interface as an example, but other types of interfaces such as PCIE and AXI can also be used. The data can be obtained from DDR or other high-speed caches by instructing the FPGA acceleration terminal via instructions, or it can be sent directly to the FPGA terminal via the high-speed interface.

[0081] In summary, although structurally divided into such Figure 1 and Figure 2 Both embodiments exist, but functionally, the main control unit 100 includes a judgment unit and a processing unit. The judgment unit is used to determine whether the received data and / or instructions need to be accelerated; the processing unit is used to add acceleration instructions to the data and / or instructions that need to be accelerated.

[0082] Embodiment 4 of the present invention provides a specific implementation of a space acceleration processing method, see [link to embodiment 4]. Figure 5 The aforementioned aerospace acceleration processing method specifically includes the following:

[0083] The FPGA acceleration unit receives acceleration commands and / or data.

[0084] The acceleration instruction is stored in the instruction sequence buffer module via the instruction bus 113, and the data is stored in the data high-speed buffer module via the data high-speed bus 112 for data access.

[0085] The instruction parsing and scheduling control module 106 queries and determines whether there is an instruction in the instruction sequence buffer module. If there is an instruction in the instruction sequence buffer module, it determines whether to execute the instruction. If the instruction is executed, it executes the instruction. If the instruction is not executed, it stores the non-executed instruction in the delayed instruction sequence buffer 107.

[0086] Specifically, the process of determining whether to execute an instruction based on the result of an instruction in the instruction sequence buffer module, and executing the instruction based on the result of the instruction execution, includes the following: Figure 4 Content shown:

[0087] S110: When the result of an instruction in the instruction sequence buffer module is determined to perform an instruction execution action, the status of each accelerated computing core in the accelerated core status indication module 108 is traversed to determine the status information of the accelerated computing core, and at the same time, the computing resource information of the accelerated computing core in the accelerated core resource pool module 109 is queried according to the current instruction.

[0088] Examples such as Figure 3 As shown, the system queries the acceleration core resource pool module 109 to retrieve the computing resource information of all acceleration computing cores stored in the system to execute the instruction, determines the type and performance of the acceleration computing core required to execute the instruction, and then iterates through the status of each acceleration computing core in the acceleration core status indicator module 108 to determine all acceleration computing cores that meet the requirements for executing the instruction. If the first layer of the determined acceleration computing core of type and performance has been occupied, the second layer of the same acceleration computing core of type and performance is selected.

[0089] S120: Based on the current instruction, determine the accelerated computing core that is not in a working state and meets the computing resource information described in the instruction, and perform accelerated data processing.

[0090] It is understood that various aspects of the technical solution of the present invention can be implemented as a system, method, or program product. Therefore, various aspects of the technical solution of the present invention can be specifically implemented in the following forms: a completely hardware implementation, a completely software implementation (including firmware, microcode, etc.), or an implementation combining hardware and software aspects, which can be collectively referred to here as a "circuit", "unit", or "platform".

[0091] Those skilled in the art should understand that the various units or steps of the present invention described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. Optionally, they can be implemented using computing device-executable program code, thereby storing them in a storage medium for execution by the computing device. In some cases, the steps shown or described can be performed in a different order than those described herein, or they can be fabricated as separate integrated circuit units, or multiple units or steps can be fabricated as a single integrated circuit unit.

[0092] In some embodiments of the present invention, a computer-readable storage medium is also provided, on which a computer program is stored, and when executed by a processor, the computer program is able to implement the various functional units in the above-disclosed aerospace acceleration processing system.

[0093] Although other specific implementation methods are not listed exhaustively in this embodiment, in some possible implementation methods, various aspects of the technical solution described in this invention can also be implemented in the form of a program product, which includes program code. When the program product is run on a terminal device, the program code is used to cause the terminal device to execute the steps of the various embodiments of the technical solution described in the aerospace acceleration processing method area of ​​this invention.

[0094] Figure 6 A schematic diagram of the structure of a computer-readable storage medium is shown according to some embodiments of the present invention. For example... Figure 6 As shown, a program product 800 for implementing the above-described method according to an embodiment of the technical solution of the present invention is described. This product may employ a portable compact disc read-only memory (CD-ROM) and include program code, and can run on a terminal device, such as a personal computer. Of course, the program product generated according to this embodiment is not limited to this. In the technical solution of the present invention, the readable storage medium may be any tangible medium containing or storing a program, which may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0095] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0096] Computer-readable storage media may include data signals propagated in baseband or as a carrier wave region, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable storage medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transfer a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0097] Program code for executing the technical solutions of this invention can be written in any combination of one or more programming languages. These programming languages ​​include object-oriented programming languages—such as Java and C++—as well as conventional procedural programming languages—such as C or similar languages. The program code can execute entirely on the user's computing device, locally on the user's device, as a standalone software package, locally on the user's computing device, locally on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0098] In summary, the technical solution proposed in this invention enables the aerospace hardware acceleration processing system, method, and storage medium to improve the processing speed of real-time information on spacecraft in the aerospace field, and enhance the high-speed processing capability of on-board data processing equipment platforms for massive payload data in the aerospace field.

[0099] The above description is merely a description of a preferred embodiment of the technical solution of the present invention and is not intended to limit the scope of the technical solution of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A space acceleration processing system, characterized in that, It includes an FPGA acceleration terminal and a main control terminal connected to the FPGA acceleration terminal; The FPGA acceleration terminal includes a high-speed data internal bus, an instruction internal bus, an instruction sequence buffer module, an instruction parsing and scheduling control module, a high-speed data buffer module, an acceleration core module, and an acceleration core information storage module. The high-speed internal data bus is used for large-scale data transmission between modules; The instruction bus is used for instructions between modules; The instruction sequence buffer module stores and retrieves instructions according to a first-in-first-out (FIFO) order; The instruction parsing and scheduling control module is used to query and determine whether there is an instruction in the instruction sequence buffer module and to determine whether to execute the instruction if there is one. The instruction sequence buffer module includes an instruction sequence buffer and a delayed instruction sequence buffer; The instruction parsing and scheduling control module is used to query and determine whether there is an instruction in the instruction sequence buffer module, determine whether to execute the instruction if there is an instruction in the instruction sequence buffer module, execute the instruction if the instruction is executed, and store the non-executed instruction in the delayed instruction sequence buffer if the instruction is not executed. The data high-speed buffer module is used to cache data at high speed; The acceleration core module is used to accelerate data processing; The acceleration core information storage module is used to store corresponding computing resource information and status information; The data cache module includes a DDR SDRAM controller; The acceleration core module includes several acceleration computing cores; The acceleration core information storage module includes an acceleration core status indication module and an acceleration core resource pool module; in, The instruction sequence buffer is used to store the acceleration instruction and the fetch instruction received for the first time by the instruction bus in first-in-first-out order. The acceleration core status indication module is used to record the real-time status information of the plurality of acceleration computing cores. The real-time status information includes the initialization status, ready status, computation completed status, and working status of each acceleration computing core. The accelerated core resource pool module is used to store the real-time computing resource information of the plurality of accelerated computing cores. The real-time computing resource information includes the number, type, number of layers, and performance of the accelerated computing cores in the current accelerated core module. The accelerated computing core has three dimensions of expansion, which can be flexibly and dynamically optimized according to hardware resources. The accelerated computing core includes three dimensions of elastic expansion: X, Y and Z. The X direction indicates that the capability of the general-purpose accelerated computing core can be expanded, the Y direction indicates that the types of general-purpose accelerated computing cores can be expanded, and the Z direction indicates that the accelerated computing cores of the same type can be expanded.

2. The aerospace acceleration processing system according to claim 1, characterized in that, The FPGA acceleration terminal is connected to the main control terminal via an interface.

3. The aerospace acceleration processing system according to claim 2, characterized in that, The main control unit includes a CPU for sending instructions and data, and an interface for transmitting data; the FPGA acceleration unit is equipped with an input data interface, an output data interface, a data pre-parsing module, a data transfer controller, and an instruction transfer controller. The interfaces include SRIO, PCIe, and AXI; After receiving data and / or instructions, the data pre-parsing module parses the data to determine whether it has received data or instructions. The data transfer controller is configured according to the currently received data and stores the received data in real time in the high-speed data buffer module through the high-speed data internal bus, or sends the data in the high-speed data buffer module to the main control terminal; The instruction transfer controller stores the received instructions into the instruction sequence buffer in real time via the instruction intrabus.

4. The aerospace acceleration processing system according to claim 1, characterized in that, The main control terminal is tightly coupled to the FPGA acceleration terminal.

5. The aerospace acceleration processing system according to claim 4, characterized in that, The data sent by the master control terminal is stored in the high-speed data buffer module through the high-speed data internal bus, and the instructions sent by the master control terminal are stored in the instruction sequence buffer through the instruction internal bus.

6. The aerospace acceleration processing system according to claim 1, characterized in that, The main control unit includes a judgment unit and a processing unit; The judgment unit is used to determine whether the received data and / or instructions need to be processed faster. The processing unit is used to add acceleration instructions to the data and / or instructions that need to be processed faster.

7. A space acceleration processing method implemented using the space acceleration processing system according to any one of claims 1-6, characterized in that, Includes the following steps: The FPGA acceleration terminal receives acceleration commands and / or data; The acceleration instructions are stored in the instruction sequence buffer module via the instruction intrabus, and the data is stored in the data high-speed buffer module via the data high-speed intrabus for data access. The instruction parsing and scheduling control module queries and determines whether there are instructions in the instruction sequence buffer module. If there are instructions in the instruction sequence buffer module, it determines whether to execute the instructions. If the instructions are executed, the instructions are executed. If the instructions are not executed, the non-executed instructions are stored in the delayed instruction sequence buffer.

8. The aerospace acceleration processing method according to claim 7, characterized in that, The step of determining whether to execute an instruction based on the result of an instruction in the instruction sequence buffer module, and executing the instruction based on the result of the instruction execution, specifically includes: When the result of an instruction in the instruction sequence buffer module is determined to perform an instruction execution action, the status of each accelerated computing core in the accelerated core status indication module is traversed to determine the status information of the accelerated computing core. At the same time, the computing resource information of the accelerated computing core in the accelerated core resource pool module is queried according to the current instruction. Based on the current instruction, accelerated computing cores that are not in operation and meet the computing resource information described in the instruction are used for accelerated data processing.

9. A readable storage medium, characterized in that, The readable storage medium stores a processing program, which, when executed by a processor, implements the aerospace acceleration processing method as described in any one of claims 7 to 8.

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