An output driving circuit, a driving method thereof, a data chip and a memory

Abstract

The application discloses an output driving circuit and a driving method thereof, a data chip and a memory, and relates to the technical field of data transmission. The output driving circuit comprises: an output unit, which comprises a pull-up driving tube and a pull-down driving tube connected in series between a power supply voltage and a ground voltage; a first front-stage driving unit connected to the pull-up driving tube and receiving a data signal to be output; a second front-stage driving unit connected to the pull-down driving tube and receiving the data signal; and at least one adjusting unit connected to the first front-stage driving unit and / or the second front-stage driving unit, so as to provide an adjusting voltage to the first front-stage driving unit and / or the second front-stage driving unit. The adjusting voltage is lower than the ground voltage or higher than the power supply voltage, so that the first driving signal can be pulled down to the adjusting voltage which is lower than the ground voltage or the second driving signal can be pulled up to the adjusting voltage which is higher than the power supply voltage, thereby quickly turning on the pull-up driving tube and / or the pull-down driving tube and reducing the delay of data output.

Description

Technical Field

[0001] This application relates to the field of data transmission technology, and in particular to an output driving circuit and its driving method, a data chip, and a memory. Background Technology

[0002] The memory typically contains a data chip for data transmission. The data chip usually contains an output drive circuit to transmit the data in the memory to the corresponding bonding pads. Since the load at the bonding pads is usually large, a large drive transistor (such as a PMOS transistor or NMOS transistor) is usually required at the output end of the output drive circuit, and a corresponding pre-stage drive circuit is also required.

[0003] In the prior art, the driving capability of the front-end driving circuit of the data chip is poor, and it is unable to drive the corresponding driving transistors quickly, resulting in excessively high data output delay. Summary of the Invention

[0004] The main technical problem addressed in this application is how to reduce the latency of data output.

[0005] To address the aforementioned technical problems, a first aspect of this application provides an output driving circuit, comprising: an output unit including a pull-up driving transistor and a pull-down driving transistor connected in series between a power supply voltage and a ground voltage, wherein the connection point between the series-connected pull-up driving transistor and the pull-down driving transistor serves as the output terminal of the output driving circuit; a first pre-stage driving unit connected to the pull-up driving transistor and receiving a data signal to be output, thereby generating a first driving signal for driving the pull-up driving transistor based on the data signal; a second pre-stage driving unit connected to the pull-down driving transistor and receiving a data signal, thereby generating a second driving signal for driving the pull-down driving transistor based on the data signal; and at least one adjustment unit connected to the first pre-stage driving unit and / or the second pre-stage driving unit to provide an adjustment voltage to the first pre-stage driving unit and / or the second pre-stage driving unit, wherein the adjustment voltage is lower than the ground voltage or higher than the power supply voltage, so that the first driving signal can be pulled down to an adjustment voltage lower than the ground voltage or the second driving signal can be pulled up to an adjustment voltage higher than the power supply voltage, thereby quickly turning on the pull-up driving transistor and / or the pull-down driving transistor.

[0006] A second aspect of this application provides a driving method for an output driving circuit, comprising: receiving a data signal to be output; generating a first driving signal for driving a pull-up driving transistor and a second driving signal for driving a pull-down driving transistor based on the data signal and at least one adjustment voltage, wherein the pull-up driving transistor and the pull-down driving transistor are connected in series between a power supply voltage and a ground voltage, the connection point between the series-connected pull-up driving transistor and the pull-down driving transistor serves as the output terminal of the output driving circuit, and at least one adjustment voltage is lower than the ground voltage or higher than the power supply voltage, so that the first driving signal can be pulled down to the adjustment voltage lower than the ground voltage and / or the second driving signal can be pulled up to the adjustment voltage higher than the power supply voltage, thereby enabling the pull-up driving transistor and / or the pull-down driving transistor to be quickly turned on; and turning on / off the pull-up driving transistor and / or the pull-down driving transistor based on the first driving signal and the second driving signal to generate a corresponding output signal at the output terminal.

[0007] A third aspect of this application provides a data chip including the aforementioned output driving circuit.

[0008] A fourth aspect of this application provides a memory including the aforementioned data chip.

[0009] The beneficial effects of this application are as follows: Unlike the prior art, the output driving circuit of this application includes: an output unit, including a pull-up driving transistor and a pull-down driving transistor connected in series between the power supply voltage and the ground voltage, wherein the connection point between the series-connected pull-up driving transistor and the pull-down driving transistor serves as the output terminal of the output driving circuit; a first pre-stage driving unit, connected to the pull-up driving transistor and receiving the data signal to be output, so as to generate a first driving signal to drive the pull-up driving transistor based on the data signal; a second pre-stage driving unit, connected to the pull-down driving transistor and receiving the data signal, so as to generate a second driving signal to drive the pull-down driving transistor based on the data signal; and at least one adjustment unit, connected to the first pre-stage driving unit and / or the second pre-stage driving unit, to provide an adjustment voltage to the first pre-stage driving unit and / or the second pre-stage driving unit, wherein the adjustment voltage is lower than the ground voltage or higher than the power supply voltage, so that the first driving signal can be pulled down to the adjustment voltage lower than the ground voltage or the second driving signal can be pulled up to the adjustment voltage higher than the power supply voltage, thereby quickly turning on the pull-up driving transistor and / or the pull-down driving transistor. The technical solution of this application provides a lower adjustment voltage than ground to the first pre-stage driver unit by using an adjustment unit, thereby reducing the low voltage that the first pre-stage driver unit can provide, and / or provides a higher adjustment voltage than the power supply voltage to the second pre-stage driver unit, thereby increasing the high voltage that the second pre-stage driver unit can provide. This enables the first pre-stage driver unit to quickly turn on the pull-up driver transistor based on the corresponding adjustment voltage, and / or the second pre-stage driver unit to quickly turn on the pull-down driver transistor based on the corresponding adjustment voltage. This improves the response speed of the pull-up driver transistor and / or the pull-down driver transistor when transmitting data and reduces the data transmission delay.

[0010] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this application. Attached Figure Description

[0011] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the technical solutions of this application.

[0012] Figure 1 This is a circuit diagram of one embodiment of the output drive circuit; Figure 2 This is a circuit diagram of one embodiment of the output drive circuit of this application; Figure 3 This is a circuit diagram of another embodiment of the output drive circuit of this application; Figure 4 This is a circuit diagram of yet another embodiment of the output drive circuit of this application; Figure 5 This is a circuit diagram of another embodiment of the output drive circuit of this application; Figure 6 This is a circuit diagram of yet another embodiment of the output drive circuit of this application; Figure 7 This is a circuit diagram of an embodiment of the positive charge pump of this application; Figure 8 This is a circuit diagram of an embodiment of the negative pressure charge pump of this application; Figure 9 This is a schematic diagram of the input and output waveforms of an output drive circuit in the prior art; Figure 10 This is a schematic diagram of the input and output waveforms of the output drive circuit of this application; Figure 11 This is a schematic flowchart of an embodiment of the driving method for the output driving circuit of this application; Figure 12 This is a schematic diagram of the structure of an embodiment of the data chip of this application; Figure 13 This is a schematic diagram of the structure of an embodiment of the memory of this application. Detailed Implementation

[0013] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0014] Figure 1 This is a circuit diagram of one embodiment of the output drive circuit, as shown below. Figure 1 The first pre-stage driver unit 12 of the output driver circuit shown is connected to the power supply and ground respectively, so that the first pre-stage driver unit 12 operates between the power supply voltage and the ground voltage; similarly, as Figure 1 The second pre-stage drive unit 13 of the output drive circuit shown is connected to the power supply and ground respectively, so that the second pre-stage drive unit 13 operates between the power supply voltage and the ground voltage.

[0015] based on Figure 1 The circuit structure of the output drive circuit shown indicates that both the first pre-stage drive unit 12 and the second pre-stage drive unit 13 can only output a first drive signal and a second drive signal to the gate of the corresponding drive transistor, with the maximum voltage being the power supply voltage and the minimum voltage being the ground voltage. When the load at the data signal output terminal connected to the output drive circuit is large, the pull-up drive transistor 111 and the pull-down drive transistor 112 in the output unit 11 need to be large-sized drive transistors. Since the power supply voltage connected to the first pre-stage drive unit 12 and the second pre-stage drive unit 13 is usually not high enough or the ground voltage connected is usually not low enough, the driving capability of the first drive signal and the second drive signal will be slightly insufficient relative to the large-sized drive transistor, and it will be unable to quickly turn on the pull-up drive transistor 111 or the pull-down drive transistor 112, which will result in a large delay in data transmission of the output drive circuit.

[0016] This application provides an output driving circuit, such as Figure 2 As shown, Figure 2 This is a circuit diagram of one embodiment of the output driving circuit of this application. The output driving circuit is used to output data signals, that is, to receive data signals from DATA (data signal input terminal) and output the data signals from PAD (data signal output terminal). This output driving circuit can be used for data output from memory, which may include Nand-flash chips, EEPROM (Electrically Erasable Programmable Read-Only Memory) chips, NOR Flash (Non-Volatile Flash Memory) chips, or other memory chips that need to output data.

[0017] The output drive circuit includes: an output unit 11, a first pre-stage drive unit 12, a second pre-stage drive unit 13, a first negative pressure supply unit 14, and a first positive pressure supply unit 15.

[0018] The output unit 11 includes a pull-up driver transistor 111 and a pull-down driver transistor 112 connected in series between the power supply voltage and the ground voltage. The node at the connection between the pull-up driver transistor 111 and the pull-down driver transistor 112 is the output terminal of the output driving circuit, used to output the corresponding data signal. The pull-up driver transistor 111 can be a PMOS transistor or other types of pull-up driver transistor, and the pull-down driver transistor 112 can be an NMOS transistor or other types of pull-down driver transistor.

[0019] The output terminal of the first pre-stage drive unit 12 is connected to the pull-up drive transistor 111, and the output terminal of the first pre-stage drive unit 12 is used to output a first drive signal to the pull-up drive transistor 111. This first drive signal is a drive signal with a corresponding pulse period determined by the first pre-stage drive unit 12 based on the logic level of the data signal to be output received at its input terminal. The function of this first drive signal is to turn the pull-up drive transistor 111 on or off.

[0020] The output terminal of the second pre-stage drive unit 13 is connected to the pull-down drive transistor 112, and the output terminal of the second pre-stage drive unit 13 is used to output a second drive signal to the pull-down drive transistor 112. This second drive signal is a drive signal with a corresponding pulse period determined by the second pre-stage drive unit 13 based on the logic level of the data signal to be output received at its input terminal. The function of this second drive signal is to turn the pull-down drive transistor 112 on or off.

[0021] At least one adjustment unit (e.g.) Figure 2 (14 and 15 in the diagram) are connected to the first pre-stage drive unit 12 and / or the second pre-stage drive unit 13 to provide an adjustment voltage to the first pre-stage drive unit 12 and / or the second pre-stage drive unit 13. The adjustment voltage is lower than the ground voltage or higher than the power supply voltage, so that the first drive signal can be pulled down to the adjustment voltage lower than the ground voltage or the second drive signal can be pulled up to the adjustment voltage higher than the power supply voltage, thereby quickly turning on the pull-up drive transistor 111 and / or the pull-down drive transistor 112.

[0022] Optionally, based on the output drive circuit provided in this application, and depending on the number of adjustment units and the provided adjustment voltage, the following three further output drive circuit schemes can be provided.

[0023] Option A: like Figure 2 As shown, at least one adjustment unit includes: a first negative pressure providing unit 14 and a first positive pressure providing unit 15.

[0024] The first negative voltage providing unit 14 is connected to the first pre-stage driving unit 12 and is used to provide the first pre-stage driving unit 12 with a first adjustment voltage lower than ground. Furthermore, in this embodiment, the first pre-stage driving unit 12 is also connected to the power supply voltage VCC. That is, the first pre-stage driving unit 12 operates between the power supply voltage VCC and the first adjustment voltage, and the first adjustment voltage is lower than ground GND. Therefore, the first pre-stage driving unit 12 generates a first driving signal based on the received data signal. The first driving signal has at least one pulse that switches between the power supply voltage VCC and the first adjustment voltage, and the pulse duration of the first driving signal corresponds to the duration of the logic level of the data signal. In addition, the first pre-stage driving unit 12 can switch the first driving signal to the first adjustment voltage, which is lower than ground GND, when it is necessary to turn on the pull-up driving transistor 111. Therefore, a sufficiently low first adjustment voltage can achieve rapid turn-on of the pull-up driving transistor 111.

[0025] The first positive voltage providing unit 15 is connected to the second pre-stage driving unit 13 and is used to provide the second pre-stage driving unit 13 with a second adjustment voltage higher than the power supply voltage. Furthermore, in this embodiment, the second pre-stage driving unit 13 is also connected to ground voltage GND. That is, the second pre-stage driving unit 13 operates between the second adjustment voltage and ground voltage GND, and the second adjustment voltage is higher than the power supply voltage VCC. Therefore, the second pre-stage driving unit 13 generates a second driving signal based on the received data signal. The second driving signal has at least one pulse that switches between the second adjustment voltage and ground voltage GND, and the pulse duration of the second driving signal corresponds to the duration of the logic level of the data signal. In addition, the second pre-stage driving unit 13 can switch the second driving signal to the second adjustment voltage, which is higher than the power supply voltage VCC, when it is necessary to turn on the pull-down driving transistor 112. Therefore, a sufficiently high second adjustment voltage can achieve rapid turn-on of the pull-down driving transistor 112.

[0026] In this embodiment, the first pre-stage driving unit 12 receives a data signal from DATA, and when the data signal is at a first logic level (e.g., a high logic level "1"), the first pre-stage driving unit 12 provides a sufficiently low driving signal to the gate of the pull-up driving transistor 111 based on a first adjustment voltage provided by the first negative voltage providing unit 14, which is lower than the ground voltage of the output driving circuit. This allows the pull-up driving transistor 111 to form a sufficiently large difference between the gate-source voltage and the threshold voltage when the data signal is at the first logic level, thereby achieving rapid turn-on of the pull-up driving transistor 111. Similarly, the second pre-stage driving unit 13 receives a data signal from DATA, and... When the data signal is at the second logic level (e.g., low logic level "0"), the second pre-stage driving unit 13 provides a sufficiently high driving signal to the gate of the pull-down driving transistor 112 based on the second adjustment voltage provided by the first positive voltage providing unit 15, which is higher than the power supply voltage of the output driving circuit. This allows the pull-down driving transistor 112 to form a sufficiently large difference between the gate-source voltage and the threshold voltage when the data signal is at the second logic level, thereby achieving rapid turn-on of the pull-down driving transistor 112. Based on the above working principle, the driving capability of the pre-stage driving circuit in the output driving circuit for the pull-up driving transistor and the pull-down driving transistor is improved, and the data transmission delay is reduced.

[0027] Furthermore, in scheme A, the first pre-stage drive unit 12 can also be connected to the power supply voltage, so that the first pre-stage drive unit 12 operates between the power supply voltage and the first adjustment voltage.

[0028] The second pre-stage drive unit 13 is also connected to ground voltage, thereby enabling the second pre-stage drive unit 13 to operate between the second adjustment voltage and ground voltage.

[0029] In this embodiment, when the data signal is at a first logic level (e.g., a high logic level "1"), the first front-end driving unit 12 can provide a first adjustment voltage as a driving signal to the gate of the pull-up driving transistor 111 to quickly turn on the pull-up driving transistor 111. At this time, the second front-end driving unit 13 can provide a ground voltage as a driving signal to the pull-down driving transistor 112 to turn off the pull-down driving transistor 112. When the data signal is at a second logic level (e.g., a low logic level "0"), the first front-end driving unit 12 can provide a power supply voltage as a driving signal to the gate of the pull-up driving transistor 111 to turn off the pull-up driving transistor 111. The second front-end driving unit 13 can provide a second adjustment voltage as a driving signal to the pull-down driving transistor 112 to quickly turn on the pull-down driving transistor 112. This achieves rapid blocking and rapid turning on of the pull-up driving transistor 111 and the pull-down driving transistor 112, thereby enabling rapid switching between high and low levels of the data signal during transmission and reducing data transmission delay.

[0030] Option B: Figure 3 This is a circuit diagram of another embodiment of the output drive circuit of this application, in which... Figure 3 In the output drive circuit shown, at least one adjustment unit includes: a first negative pressure providing unit 14.

[0031] The first negative voltage providing unit 14 is connected to the first pre-stage driving unit 12 and is used to provide the first pre-stage driving unit 12 with a first adjustment voltage lower than ground voltage. Furthermore, in this embodiment, the first pre-stage driving unit 12 is also connected to the power supply voltage VCC, meaning that the first pre-stage driving unit 12 operates between the power supply voltage VCC and the first adjustment voltage, and the first adjustment voltage is lower than ground voltage GND. The second pre-stage driving unit 13 is connected to both the power supply voltage VCC and the ground voltage GND, meaning that the second pre-stage driving unit 13 operates between the power supply voltage VCC and the ground voltage GND.

[0032] In this embodiment, the first pre-stage driving unit 12 receives a data signal from DATA. When the data signal is at a first logic level (e.g., a high logic level "1"), the first pre-stage driving unit 12 provides a sufficiently low driving signal to the gate of the pull-up driving transistor 111 based on a first adjustment voltage provided by the first negative voltage providing unit 14, which is lower than the ground voltage of the output driving circuit. This allows the pull-up driving transistor 111 to form a sufficiently large difference between the gate-source voltage and the threshold voltage when the data signal is at the first logic level, thereby achieving rapid turn-on of the pull-up driving transistor 111. Based on the above working principle, the driving capability of the pre-stage driving circuit in the output driving circuit for the pull-up driving transistor is improved, and the data transmission delay is reduced.

[0033] Furthermore, in Scheme B, the first pre-stage drive unit 12 can also be connected to the power supply voltage, thereby enabling the first pre-stage drive unit 12 to operate between the power supply voltage and the first adjustment voltage.

[0034] In this embodiment, when the data signal is at a first logic level (e.g., a high logic level "1"), the first front-end driving unit 12 can provide a first adjustment voltage as a driving signal to the gate of the pull-up driving transistor 111 to quickly turn on the pull-up driving transistor 111. When the data signal is at a second logic level (e.g., a low logic level "0"), the first front-end driving unit 12 can provide a power supply voltage as a driving signal to the gate of the pull-up driving transistor 111 to turn off the pull-up driving transistor 111, thereby achieving rapid turn-on of the pull-up driving transistor 111 and reducing data transmission delay.

[0035] Option C: Figure 4 This is a circuit diagram of another embodiment of the output drive circuit of this application, in which... Figure 4In the output drive circuit shown, at least one adjustment unit includes: a first positive pressure providing unit 15.

[0036] The first positive voltage providing unit 15 is connected to the second pre-stage driving unit 13 and is used to provide the second pre-stage driving unit 13 with a second adjustment voltage higher than the power supply voltage. Furthermore, in this embodiment, the second pre-stage driving unit 13 is also connected to ground voltage GND. That is, the second pre-stage driving unit 13 operates between the second adjustment voltage and ground voltage GND, and the second adjustment voltage is higher than the power supply voltage VCC. The first pre-stage driving unit 12 is connected to both the power supply voltage VCC and ground voltage GND, meaning that the first pre-stage driving unit 12 operates between the power supply voltage VCC and ground voltage GND.

[0037] In this embodiment, the second pre-stage driving unit 13 receives a data signal from DATA. When the data signal is at a second logic level (e.g., a low logic level "0"), the second pre-stage driving unit 13 provides a sufficiently high-voltage driving signal to the gate of the pull-down driving transistor 112 based on a second adjustment voltage provided by the first positive voltage providing unit 15, which is higher than the power supply voltage of the output driving circuit. This allows the pull-down driving transistor 112 to form a sufficiently large difference between the gate-source voltage and the threshold voltage when the data signal is at the second logic level, thereby achieving rapid turn-on of the pull-down driving transistor 112. Based on the above working principle, the driving capability of the pre-stage driving circuit in the output driving circuit for the pull-down driving transistor is improved, and the data transmission delay is reduced.

[0038] Furthermore, in scheme C, the second pre-stage drive unit 13 can also be connected to ground voltage, thereby enabling the second pre-stage drive unit 13 to operate between the second adjustment voltage and ground voltage.

[0039] In this embodiment, when the data signal is at a first logic level (e.g., a high logic level "1"), the second pre-stage driving unit 13 can provide a ground voltage as a driving signal to pull down the driving transistor 112 to turn it off. When the data signal is at a second logic level (e.g., a low logic level "0"), the second pre-stage driving unit 13 can provide a second adjustment voltage as a driving signal to pull down the driving transistor 112 to quickly turn it on, thereby achieving rapid turn-on of the pull-down driving transistor 112 and reducing data transmission delay.

[0040] Furthermore, based on scheme A, B, or C, the first pre-stage drive unit 12 can also be connected to the first positive voltage supply unit 15 to receive the second adjustment voltage provided by the first positive voltage supply unit 15, thereby operating between the second adjustment voltage and the first adjustment voltage; and / or The second pre-stage drive unit 13 is also connected to the first negative pressure supply unit 14 to receive the first adjustment voltage provided by the first negative pressure supply unit 14, thereby operating between the second adjustment voltage and the first adjustment voltage.

[0041] like Figure 5 As shown, Figure 5 This is a circuit diagram of another embodiment of the output drive circuit of this application. Figure 2 Compared with the disclosed output driving circuit, in the output driving circuit of this embodiment, the first pre-stage driving unit 12 is also connected to the first positive voltage providing unit 15 to receive the second adjustment voltage provided by the first positive voltage providing unit 15, so that the first pre-stage driving unit 12 operates between the second adjustment voltage and the first adjustment voltage; the second pre-stage driving unit 13 is also connected to the first negative voltage providing unit 14 to receive the first adjustment voltage provided by the first negative voltage providing unit 14, so that the second pre-stage driving unit 13 operates between the second adjustment voltage and the first adjustment voltage.

[0042] Furthermore, the connection relationships between the first pre-stage drive unit 12, the second pre-stage drive unit 13, and the data signal input terminals of the output unit 11 or the output drive circuit are all consistent with... Figure 2 The output drive circuits in the embodiments are the same, and will not be described again here.

[0043] In this embodiment, the first pre-stage drive unit 12 is connected to the first negative voltage supply unit 14 and the first positive voltage supply unit 15, thereby raising its upper limit of operating voltage to a second adjustment voltage higher than the power supply voltage; the second pre-stage drive unit 13 is connected to the first negative voltage supply unit 14 and the first positive voltage supply unit 15, thereby lowering its lower limit of operating voltage to a first adjustment voltage lower than the ground voltage, thus increasing the maximum voltage difference between the first pre-stage drive unit 12 and the second pre-stage drive unit 13 and accelerating the driving speed of the first pre-stage drive unit 12 and the second pre-stage drive unit 13.

[0044] Furthermore, based on scheme A, B, or C, at least one adjustment unit also includes: The second positive voltage providing unit 16 can be connected to the first pre-stage drive unit 12 to provide a third regulated voltage to the first pre-stage drive unit, operating between the third regulated voltage and the first regulated voltage, wherein the third regulated voltage is higher than the power supply voltage; and / or The second negative voltage providing unit 17 can be connected to the second pre-stage drive unit 13 to provide a fourth adjustment voltage to the second pre-stage drive unit, so as to operate between the second adjustment voltage and the fourth adjustment voltage, wherein the fourth adjustment voltage is lower than the ground voltage.

[0045] like Figure 6 As shown, Figure 6This is a circuit diagram of yet another embodiment of the output drive circuit of this application. Figure 2 Compared with the disclosed output driving circuit, in the output driving circuit of this embodiment, at least one adjustment unit further includes: a second positive pressure providing unit 16 and a second negative pressure providing unit 17.

[0046] The second positive voltage supply unit 16 is connected to the first pre-stage drive unit 12 and provides a third adjustment voltage to the first pre-stage drive unit 12, thereby making the first pre-stage drive unit 12 operate between the third adjustment voltage and the first adjustment voltage, wherein the third adjustment voltage is greater than the power supply voltage. The second negative voltage providing unit 17 is connected to the second pre-stage drive unit 13 and provides a fourth adjustment voltage to the second pre-stage drive unit 13, thereby making the second pre-stage drive unit 13 work between the second adjustment voltage and the fourth adjustment voltage, wherein the fourth adjustment voltage is less than the ground voltage. Furthermore, the connection relationships between the first pre-stage drive unit 12, the second pre-stage drive unit 13, and the data signal input terminals of the output unit 11 or the output drive circuit are all consistent with... Figure 2 The output drive circuits in the embodiments are the same, and will not be described again here.

[0047] In this embodiment, the first pre-stage drive unit 12 is connected to the first negative voltage supply unit 14 and the second positive voltage supply unit 16, respectively, so that the upper limit of the operating voltage of the first pre-stage drive unit 12 is raised to a third adjustment voltage higher than the power supply voltage; the second pre-stage drive unit 13 is connected to the first positive voltage supply unit 15 and the second negative voltage supply unit 17, respectively, so that the lower limit of the operating voltage of the second pre-stage drive unit 13 is lowered to a fourth adjustment voltage lower than the ground voltage, thereby widening the voltage difference between the first pre-stage drive unit 12 and the second pre-stage drive unit 13 and accelerating the driving speed of the two pre-stage drive units.

[0048] Specifically, the first pre-stage drive unit 12 can send a first drive signal to the pull-up drive transistor 111 when it receives a high-level data signal, thereby turning on the pull-up drive transistor 111. When it receives a low-level data signal, the first pre-stage drive unit 12 can send a first drive signal with a voltage equal to its highest operating voltage to the pull-up drive transistor 111, thereby turning off the pull-up drive transistor 111. The second pre-stage drive unit 13 can send a second drive signal with a voltage equal to its highest operating voltage to the pull-down drive transistor 112 when it receives a low-level data signal, thereby turning on the pull-down drive transistor 112. When it receives a high-level data signal, the second pre-stage drive unit 13 can send a second drive signal with a voltage equal to its lowest operating voltage to the pull-down drive transistor 112, thereby turning off the pull-down drive transistor 112. Based on the above working principle, data signal information transmission can be realized.

[0049] Furthermore, the first negative pressure providing unit 14 or the second negative pressure providing unit 17 is a negative pressure charge pump, and / or the first positive pressure providing unit 15 or the second positive pressure providing unit 16 is a positive pressure charge pump.

[0050] Furthermore, such as Figure 7 As shown, Figure 7 This is a circuit diagram of an embodiment of the positive charge pump of this application. The positive charge pump includes: a plurality of unidirectional conductors connected in series, a first capacitor 55, a second capacitor 56 and a third capacitor 57.

[0051] Multiple unidirectional conductors are connected in series to form a unidirectional transport path for the unidirectional transport of positive charges. A first node J1, a second node J2, and a third node J3 are defined on this unidirectional transport path in the positive charge pump. The anode of the first unidirectional conductor in this series-connected configuration is connected to a power supply voltage, and the cathode of the last unidirectional conductor is also connected to a power supply voltage. At least one unidirectional conductor is positioned between the power supply voltage connected to the anode of the first unidirectional conductor and the first node J1, between the first node J1 and the second node J2, between the second node J2 and the third node J3, and between the third node J3 and the cathode of the last unidirectional conductor, thus forming the unidirectional transport path in the positive charge pump.

[0052] One end of the first capacitor 55 is connected to the first node J1, and the other end is used to receive the first clock signal.

[0053] One end of the second capacitor 56 is connected to the second node J2, and the other end is used to receive the second clock signal, wherein the first clock signal and the second clock signal are inverse signals of each other.

[0054] One end of the third capacitor 57 is connected to the third node J3, and the other end is connected to the ground voltage. The third node J3 serves as the output terminal of the positive voltage charge pump to output the second or third adjustment voltage.

[0055] Specifically, such as Figure 7 As shown, in the circuit of the positive charge pump described above, the first unidirectional conductor is the first unidirectional conductor 51, the second unidirectional conductor 52 is provided between the first node J1 and the second node J2, the third unidirectional conductor 53 is provided between the second node J2 and the third node J3, and the last unidirectional conductor is the fourth unidirectional conductor 54.

[0056] like Figure 7The working principle of the positive charge pump shown is mainly based on the bootstrap effect of capacitors, as follows: CLK_A and CLK_B are the first and second clock signals, which are opposite signals. Multiple unidirectional conductors 51~54 are connected in series to form a unidirectional transmission path. The voltage of the three nodes J1~J3 on it is theoretically the initial power supply voltage VCC. When CLK_A switches to a high level, based on the bootstrap effect of the first capacitor 55, the voltage at the first node J1 will increase accordingly to maintain the voltage difference between the two substrates of the first capacitor 55. At this time, the power supply voltage VCC injects more positive charge into the first node J1 through the first unidirectional conductor 51 to increase the voltage value at the first node J1. At the same time, since CLK_B switches to a low level, the voltage at the second node J2 will decrease accordingly due to the bootstrap effect of the second capacitor 56 to maintain the voltage difference between the two substrates of the second capacitor 56. In order to reduce the voltage of the second node J2, the second node J2 discharges to the third node J3 through the third unidirectional conductor 53, thereby reducing the voltage. The positive charge at the second node J2 is reduced; that is, during this switching process, the power supply voltage VCC injects more positive charge into the first node J1 through the first unidirectional conductor 51, so as to increase the voltage at the first node J1; at the same time, the voltage of the second node J2 needs to be reduced, so it discharges to the third node J3 through the third conductor 53 to reduce the voltage of the second node J2, and the voltage difference between the first node J1 and the second node J2 will cause the first node J1 to replenish the positive charge to the second node J2 through the second unidirectional conductor 52. Therefore, this switching process is equivalent to the power supply voltage VCC discharging to the third node J3 through the unidirectional conductors 51~53 under the control of capacitors 55 and 56 to raise the voltage value of the third node J3.When CLK_A switches to low level, CLK_B switches to high level. Based on the bootstrap effect of the second capacitor 56, the voltage at the second node J2 will increase accordingly to maintain the voltage difference between the two substrates of the second capacitor 56. Since a third unidirectional conductor 53 is set between the second node J2 and the third node J3, it cannot be replenished with positive charge through the third node J3. It can only be replenished with positive charge through the first node J1 via the second unidirectional conductor 52. At this time, since CLK_A switches to low level, the voltage at the first node J1... Due to the bootstrap effect of the first capacitor 55, the voltage difference between the two substrates of the first capacitor 55 will decrease accordingly to maintain a constant voltage difference. Therefore, the first node J1 can only discharge positive charge to the second node J2 through the second unidirectional conductor 52 to reduce the voltage of the first node J1. A larger amount of positive charge will accumulate at the second node J2 to obtain a higher voltage. When the voltage difference between the second node J2 and the third node J3 exceeds the forward conduction threshold of the third unidirectional conductor 53, the second node J2 will also discharge to the third node J3 through the third unidirectional conductor 53, thereby increasing the voltage of the third node J3. Therefore, the bootstrap effect of the positive charge pump capacitor can increase the voltage of the positive charge pump output terminal VP (greater than the power supply voltage), thereby outputting the aforementioned second or third adjustment voltage through the positive charge pump output terminal VP.

[0057] also, Figure 7 The positive charge pump is also equipped with a fourth unidirectional conduction element 54. When the voltage difference between the output terminal VP of the positive charge pump and the power supply voltage exceeds the forward conduction threshold of the fourth unidirectional conduction element 54, the output terminal VP of the positive charge pump will deliver positive charge to the power supply voltage. This ensures that the voltage difference between the output terminal VP of the positive charge pump and the power supply voltage does not exceed the forward conduction threshold of the unidirectional conduction element, avoiding the need to configure voltage conversion circuits for the corresponding front-end drive unit, simplifying the structure of the output drive circuit, and improving the efficiency of data transmission.

[0058] Furthermore, such as Figure 8 As shown, Figure 8 This is a circuit diagram of an embodiment of the negative pressure charge pump of this application. The negative pressure charge pump includes: a plurality of unidirectional conductors connected in series, a fourth capacitor 65, a fifth capacitor 66 and a sixth capacitor 67.

[0059] Multiple unidirectional conductors are connected in series to form a unidirectional transport path for the unidirectional transport of positive charges. A fourth node J4, a fifth node J5, and a sixth node J6 are defined on this unidirectional transport path in the negative pressure charge pump. The cathode of the first unidirectional conductor in this series-connected configuration is connected to ground, and the anode of the last unidirectional conductor is also connected to ground. Specifically, at least one unidirectional conductor is positioned between the fourth node J4 and the ground voltage connected to the cathode of the first unidirectional conductor, between the fifth node J5 and the fourth node J4, between the sixth node J6 and the fifth node J5, and between the ground voltage connected to the anode of the last unidirectional conductor and the sixth node J6, thus forming the unidirectional transport path in the negative pressure charge pump.

[0060] One end of the fourth capacitor 65 is connected to the fourth node J4, and the other end is used to receive the first clock signal.

[0061] One end of the fifth capacitor 66 is connected to the fifth node J5, and the other end is used to receive the second clock signal, wherein the first clock signal and the second clock signal are inverse signals of each other.

[0062] One end of the sixth capacitor 67 is connected to the sixth node J6, and the other end is connected to the ground voltage. The sixth node J6 serves as the output terminal of the negative voltage charge pump to output the first or fourth adjustment voltage.

[0063] Specifically, such as Figure 8 As shown, in the circuit of the negative pressure charge pump, the first unidirectional conductor is the fifth unidirectional conductor 61, the sixth unidirectional conductor 62 is provided between the fifth node J5 and the fourth node J4, the seventh unidirectional conductor 63 is provided between the sixth node J6 and the fifth node J5, and the last unidirectional conductor is the eighth unidirectional conductor 64.

[0064] like Figure 8 The working principle of the negative pressure charge pump shown is also based on the bootstrap effect of capacitance, and its principle is similar to that of... Figure 7 The working principle of the positive charge pump shown is similar; it can be understood by analyzing the flow of negative charges, so it will not be elaborated further here.

[0065] Specifically, the aforementioned unidirectional conductor can be a diode or other types of unidirectional conductors, which are not limited here.

[0066] In one application scenario, an input-output comparison was made between the output driving circuit in the prior art and the output driving circuit of this application, such as... Figure 9 and 10 As shown, Figure 9 This is a schematic diagram of the input and output waveforms of an output drive circuit in the prior art. Figure 10This is a schematic diagram of the input and output waveforms of the output drive circuit of this application.

[0067] When the power supply voltage is 1.5V and the ground voltage is 0V, the rise delay of the input data signal and the output data signal of the output driving circuit in the prior art is A (11.3 nanoseconds) and the fall delay is B (9.87 nanoseconds). However, the rise delay of the input data signal and the fall delay of the output data signal of the output driving circuit of this application (the first adjustment voltage is 0.5V lower than the ground voltage and the second adjustment voltage is 0.5V higher than the power supply voltage) is C (5.72 nanoseconds) and the fall delay is D (5.18 nanoseconds).

[0068] As can be seen from the above, the output driving circuit of this application has significant improvements over the output driving circuit in the prior art. The voltage slew rate of the data signal output terminal PAD is significantly improved, thereby greatly reducing the delay of the data signal output through the output driving circuit of this application.

[0069] Unlike existing technologies, the technical solution of this application provides a lower adjustment voltage than ground to the first pre-stage drive unit by using an adjustment unit, thereby reducing the low voltage that the first pre-stage drive unit can provide, and / or provides a higher adjustment voltage than the power supply voltage to the second pre-stage drive unit, thereby increasing the high voltage that the second pre-stage drive unit can provide. This enables the first pre-stage drive unit to quickly turn on the pull-up drive transistor based on the corresponding adjustment voltage, and / or the second pre-stage drive unit to quickly turn on the pull-down drive transistor based on the corresponding adjustment voltage. This improves the response speed of the pull-up drive transistor and / or the pull-down drive transistor when transmitting data and reduces the data transmission delay.

[0070] This application also provides a driving method for an output driving circuit, such as... Figure 11 As shown, Figure 11 This is a schematic flowchart of an embodiment of the driving method for the output driving circuit of this application. The driving method may include: Step S11: Receive the data signal to be output.

[0071] In this embodiment, the data signal to be output is received through the input terminal of the output driving circuit. This data signal may come from a data chip, memory, or other data storage module.

[0072] Step S12: Generate a first drive signal to drive the pull-up drive transistor and a second drive signal to drive the pull-down drive transistor based on the data signal and at least one adjustment voltage.

[0073] In this circuit, the pull-up drive transistor and the pull-down drive transistor are connected in series between the power supply voltage and the ground voltage. The connection point between the series-connected pull-up drive transistor and the pull-down drive transistor serves as the output terminal of the output drive circuit. At least one adjustment voltage is lower than the ground voltage or higher than the power supply voltage, so that the first drive signal can be pulled down to the adjustment voltage lower than the ground voltage and / or the second drive signal can be pulled up to the adjustment voltage higher than the power supply voltage, thereby enabling the pull-up drive transistor and / or the pull-down drive transistor to be quickly turned on.

[0074] In this embodiment, the pull-up driver transistor can be connected to the first pre-stage driver unit, and the pull-down driver transistor can be connected to the second pre-stage driver unit. The first and second pre-stage driver units can generate a first drive signal and a second drive signal based on the received data signal and at least one adjustment voltage to drive the pull-up driver transistor and the pull-down driver transistor. Alternatively, other electronic devices can be used to implement the steps of generating the first drive signal for driving the pull-up driver transistor and the second drive signal for driving the pull-down driver transistor based on the data signal and at least one adjustment voltage, which is not limited here.

[0075] Step S13: Based on the first drive signal and the second drive signal, turn on / off the pull-up drive transistor and / or pull-down drive transistor to generate a corresponding output signal at the output terminal.

[0076] In this embodiment, the first and second drive signals generated in step S12 based on the data signal and at least one adjustment voltage (lower than ground voltage or higher than power supply voltage) can be used to quickly turn on the pull-up drive transistor and / or pull-down drive transistor, thereby reducing the data transmission delay.

[0077] Optionally, generating a first drive signal to drive the pull-up drive transistor and a second drive signal to drive the pull-down drive transistor based on the data signal and at least one adjusted voltage includes: A first drive signal for driving the pull-up drive transistor is generated based on the data signal and the first adjustment voltage, and a second drive signal for driving the pull-down drive transistor is generated based on the data signal. The first adjustment voltage is lower than the ground voltage. The first drive signal switches between the power supply voltage and the first adjustment voltage to quickly turn on the pull-up drive transistor when the first adjustment voltage is applied. The second drive signal switches between the power supply voltage and the ground voltage. A first drive signal for driving the pull-up transistor is generated based on the data signal, and a second drive signal for driving the pull-down transistor is generated based on the data signal and a second adjustment voltage, wherein the second adjustment voltage is higher than the power supply voltage, and the second drive signal switches between the second adjustment voltage and ground voltage to quickly turn on the pull-down transistor when the second adjustment voltage is applied; the first drive signal switches between the power supply voltage and ground voltage; or A first drive signal for driving the pull-up drive transistor is generated based on the data signal and a first adjustment voltage, and a second drive signal for driving the pull-down drive transistor is generated based on the data signal and a second adjustment voltage. The first adjustment voltage is lower than ground, and the second adjustment voltage is higher than the power supply voltage. The first drive signal switches between the power supply voltage and the first adjustment voltage to quickly turn on the pull-up drive transistor when the first adjustment voltage is applied. The second drive signal switches between the second adjustment voltage and ground to quickly turn on the pull-down drive transistor when the second adjustment voltage is applied. A first drive signal for driving the pull-up drive transistor is generated based on the data signal, a first adjustment voltage, and a second adjustment voltage. A second drive signal for driving the pull-down drive transistor is also generated based on the data signal, the first adjustment voltage, and the second adjustment voltage. The first adjustment voltage is lower than ground, and the second adjustment voltage is higher than the power supply voltage. The first drive signal switches between the first and second adjustment voltages to quickly turn on the pull-up drive transistor when the first adjustment voltage is applied. The second drive signal switches between the first and second adjustment voltages to quickly turn on the pull-down drive transistor when the second adjustment voltage is applied. A first drive signal for driving the pull-up drive transistor is generated based on the data signal, the first adjustment voltage, and the third adjustment voltage, and a second drive signal for driving the pull-down drive transistor is generated based on the data signal, the second adjustment voltage, and the fourth adjustment voltage. The first adjustment voltage and the fourth adjustment voltage are lower than the ground voltage, and the second adjustment voltage and the third adjustment voltage are higher than the power supply voltage. The first drive signal switches between the first adjustment voltage and the third adjustment voltage to quickly turn on the pull-up drive transistor when the first adjustment voltage is applied, and the second drive signal switches between the second adjustment voltage and the fourth adjustment voltage to quickly turn on the pull-down drive transistor when the second adjustment voltage is applied.

[0078] Specifically, the steps of generating a first drive signal to drive the pull-up drive transistor and a second drive signal to drive the pull-down drive transistor based on the data signal and at least one adjustment voltage can be any of the following five schemes: Option 1: A second drive signal is generated based on the data signal, power supply voltage, and ground voltage to drive the pull-down drive transistor, and a first drive signal is generated based on the data signal, power supply voltage, and a first adjustment voltage lower than ground voltage to quickly turn on the pull-up drive transistor when the first drive signal is at the first adjustment voltage.

[0079] Option 2: A first drive signal is generated based on the data signal, power supply voltage, and ground voltage to drive the pull-up drive transistor. A second drive signal is generated based on the data signal, ground voltage, and a second adjustment voltage higher than the power supply voltage to quickly turn on the pull-down drive transistor when the second drive signal is at the second adjustment voltage.

[0080] Option 3: A first drive signal is generated based on the data signal, the power supply voltage, and a first adjustment voltage lower than ground voltage, so as to quickly turn on the pull-up drive transistor when the first drive signal is at the first adjustment voltage. A second drive signal is generated based on the data signal, the ground voltage, and a second adjustment voltage higher than the power supply voltage, so as to quickly turn on the pull-down drive transistor when the second drive signal is at the second adjustment voltage.

[0081] Option 4: A first drive signal and a second drive signal are generated based on the data signal, a first adjustment voltage below ground voltage, and a second adjustment voltage above power supply voltage, so as to quickly turn on the pull-up drive transistor when the first drive signal is at the first adjustment voltage, and quickly turn on the pull-down drive transistor when the second drive signal is at the second adjustment voltage.

[0082] Fifth option: A first drive signal is generated based on the data signal, a third adjustment voltage higher than the power supply voltage, and a first adjustment voltage lower than the ground voltage, so as to quickly turn on the pull-up drive transistor when the first drive signal is at the first adjustment voltage. A second drive signal is generated based on the data signal, a fourth adjustment voltage lower than the ground voltage, and a second adjustment voltage higher than the power supply voltage, so as to quickly turn on the pull-down drive transistor when the second drive signal is at the second adjustment voltage.

[0083] Unlike existing technologies, the technical solution of this application receives the data signal to be output and generates a first drive signal for driving the pull-up drive transistor and a second drive signal for driving the pull-down drive transistor based on the data signal and at least one adjustment voltage. This enables the first drive signal to be pulled down to an adjustment voltage lower than ground and / or the second drive signal to be pulled up to an adjustment voltage higher than the power supply voltage. This allows the pull-up drive transistor and / or pull-down drive transistor to be turned on quickly, thereby improving the response speed of the pull-up drive transistor and / or pull-down drive transistor when transmitting data and reducing the data transmission delay.

[0084] This application also provides a data chip, such as Figure 12 As shown, Figure 12 This is a schematic diagram of the structure of a data chip according to an embodiment of this application. The data chip 1200 includes at least an output driving circuit 1201, which is used to output data stored in the data chip. The output driving circuit 1201 is the output driving circuit disclosed in the above embodiment, and will not be described again here.

[0085] Unlike existing technologies, the technical solution of this application provides a lower adjustment voltage than ground to the first pre-stage drive unit by using an adjustment unit, thereby reducing the low voltage that the first pre-stage drive unit can provide, and / or provides a higher adjustment voltage than the power supply voltage to the second pre-stage drive unit, thereby increasing the high voltage that the second pre-stage drive unit can provide. This enables the first pre-stage drive unit to quickly turn on the pull-up drive transistor based on the corresponding adjustment voltage, and / or the second pre-stage drive unit to quickly turn on the pull-down drive transistor based on the corresponding adjustment voltage. This improves the response speed of the pull-up drive transistor and / or the pull-down drive transistor when transmitting data and reduces the data transmission delay.

[0086] This application also provides a memory, such as Figure 13 As shown, Figure 13 This is a schematic diagram of a memory embodiment of the present application. The memory 1300 includes at least a data chip 1301, which is used to output data stored in the memory through an output driving circuit. The data chip 1301 is the data chip disclosed in the above embodiments, and will not be described again here.

[0087] Unlike existing technologies, the technical solution of this application provides a lower adjustment voltage than ground to the first pre-stage drive unit by using an adjustment unit, thereby reducing the low voltage that the first pre-stage drive unit can provide, and / or provides a higher adjustment voltage than the power supply voltage to the second pre-stage drive unit, thereby increasing the high voltage that the second pre-stage drive unit can provide. This enables the first pre-stage drive unit to quickly turn on the pull-up drive transistor based on the corresponding adjustment voltage, and / or the second pre-stage drive unit to quickly turn on the pull-down drive transistor based on the corresponding adjustment voltage. This improves the response speed of the pull-up drive transistor and / or the pull-down drive transistor when transmitting data and reduces the data transmission delay.

[0088] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. An output driving circuit, characterized in that, include: The output unit includes a pull-up drive transistor and a pull-down drive transistor connected in series between the power supply voltage and the ground voltage, wherein the connection point between the series-connected pull-up drive transistor and the pull-down drive transistor serves as the output terminal of the output drive circuit. The first pre-stage driving unit is connected to the pull-up driving transistor and receives the data signal to be output, so as to generate a first driving signal to drive the pull-up driving transistor based on the data signal. The second pre-stage drive unit is connected to the pull-down drive transistor and receives the data signal to generate a second drive signal to drive the pull-down drive transistor based on the data signal. At least one adjustment unit is connected to the first pre-stage drive unit and / or the second pre-stage drive unit to provide an adjustment voltage to the first pre-stage drive unit and / or the second pre-stage drive unit, wherein the adjustment voltage is lower than the ground voltage or higher than the power supply voltage, so that the first drive signal can be pulled down to the adjustment voltage lower than the ground voltage or the second drive signal can be pulled up to the adjustment voltage higher than the power supply voltage, thereby quickly turning on the pull-up drive transistor and / or the pull-down drive transistor.

2. The output driving circuit according to claim 1, characterized in that, The at least one adjustment unit includes: a first negative voltage providing unit, connected to the first pre-stage driving unit to provide a first adjustment voltage to the first pre-stage driving unit, wherein the first adjustment voltage is lower than the ground voltage, so as to quickly turn on the pull-up driving transistor when the first driving signal generated by the first pre-stage driving unit is at the first adjustment voltage; or The at least one adjustment unit includes: a first positive voltage supply unit connected to the second pre-stage drive unit to provide a second adjustment voltage to the second pre-stage drive unit, wherein the second adjustment voltage is higher than the power supply voltage, so as to quickly turn on the pull-down drive transistor when the second drive signal generated by the second pre-stage drive unit is at the second adjustment voltage; or The at least one adjustment unit includes: a first negative voltage providing unit connected to the first pre-stage driving unit to provide a first adjustment voltage to the first pre-stage driving unit, wherein the first adjustment voltage is lower than the ground voltage, so as to quickly turn on the pull-up driving transistor when the first driving signal generated by the first pre-stage driving unit is at the first adjustment voltage; and a first positive voltage providing unit connected to the second pre-stage driving unit to provide a second adjustment voltage to the second pre-stage driving unit, wherein the second adjustment voltage is higher than the power supply voltage, so as to quickly turn on the pull-down driving transistor when the second driving signal generated by the second pre-stage driving unit is at the second adjustment voltage.

3. The output driving circuit according to claim 2, characterized in that, The first pre-stage drive unit is also connected to the power supply voltage to operate between the power supply voltage and the first adjustment voltage; and / or The second pre-stage drive unit is also connected to the ground voltage to operate between the second adjustment voltage and the ground voltage.

4. The output driving circuit according to claim 2, characterized in that, The first pre-stage drive unit is also connected to the first positive voltage supply unit to receive the second adjustment voltage provided by the first positive voltage supply unit, thereby operating between the second adjustment voltage and the first adjustment voltage; and / or The second pre-stage drive unit is also connected to the first negative pressure supply unit to receive the first adjustment voltage provided by the first negative pressure supply unit, thereby operating between the second adjustment voltage and the first adjustment voltage.

5. The output driving circuit according to claim 2, characterized in that, The at least one adjustment unit further includes: A second positive voltage supply unit is connected to the first pre-stage drive unit to provide a third regulated voltage to the first pre-stage drive unit, operating between the third regulated voltage and the first regulated voltage, wherein the third regulated voltage is higher than the power supply voltage; and / or The second negative voltage providing unit is connected to the second pre-stage drive unit to provide a fourth adjustment voltage to the second pre-stage drive unit, so as to operate between the second adjustment voltage and the fourth adjustment voltage, wherein the fourth adjustment voltage is lower than the ground voltage.

6. The output drive circuit according to any one of claims 2-4, characterized in that, The first negative pressure providing unit, and / or the first positive pressure providing unit is a positive pressure charge pump.

7. The output driving circuit according to claim 5, characterized in that, The first negative pressure providing unit or the second negative pressure providing unit is a negative pressure charge pump, and / or the first positive pressure providing unit or the second positive pressure providing unit is a positive pressure charge pump.

8. The output driving circuit according to claim 7, characterized in that, The positive pressure charge pump includes: A plurality of unidirectional conductors are connected in series, wherein the plurality of unidirectional conductors form a unidirectional transmission path, the anode of the first unidirectional conductor is connected to the power supply voltage, the cathode of the last unidirectional conductor is connected to the power supply voltage, and a first node, a second node and a third node are defined on the unidirectional transmission path. At least one unidirectional conductor is respectively provided between the power supply voltage connected to the anode of the first unidirectional conductor and the first node, between the first node and the second node, between the second node and the third node, and between the third node and the power supply voltage connected to the cathode of the last unidirectional conductor. The first capacitor has one end connected to the first node and the other end used to receive the first clock signal. The second capacitor has one end connected to the second node and the other end used to receive the second clock signal, wherein the first clock signal and the second clock signal are inverse signals of each other; The third capacitor has one end connected to the third node and the other end connected to the ground voltage. The third node serves as the output terminal of the positive charge pump to output the second adjustment voltage or the third adjustment voltage.

9. The output driving circuit according to claim 7, characterized in that, The negative pressure charge pump includes: A plurality of unidirectional conductors are connected in series, wherein the plurality of unidirectional conductors form a unidirectional transmission path, the cathode of the first unidirectional conductor is connected to the ground voltage, the anode of the last unidirectional conductor is connected to the ground voltage, and a fourth node, a fifth node and a sixth node are defined on the unidirectional transmission path. At least one unidirectional conductor is respectively provided between the fourth node and the ground voltage connected to the cathode of the first unidirectional conductor, between the fifth node and the fourth node, between the sixth node and the fifth node, and between the ground voltage connected to the anode of the last unidirectional conductor and the sixth node. The fourth capacitor has one end connected to the fourth node and the other end used to receive the first clock signal; The fifth capacitor has one end connected to the fifth node and the other end used to receive the second clock signal, wherein the first clock signal and the second clock signal are inverse signals of each other; The sixth capacitor has one end connected to the sixth node and the other end connected to the ground voltage. The sixth node serves as the output terminal of the negative voltage charge pump to output the first adjustment voltage or the fourth adjustment voltage.

10. A driving method for an output driving circuit, characterized in that, include: Receive the data signal to be output; Based on the data signal and at least one adjustment voltage, a first drive signal for driving the pull-up drive transistor and a second drive signal for driving the pull-down drive transistor are generated. The pull-up drive transistor and the pull-down drive transistor are connected in series between the power supply voltage and the ground voltage. The connection point between the series-connected pull-up drive transistor and the pull-down drive transistor serves as the output terminal of the output drive circuit. The at least one adjustment voltage is lower than the ground voltage or higher than the power supply voltage, so that the first drive signal can be pulled down to the adjustment voltage lower than the ground voltage and / or the second drive signal can be pulled up to the adjustment voltage higher than the power supply voltage, thereby enabling the pull-up drive transistor and / or the pull-down drive transistor to be quickly turned on. Based on the first drive signal and the second drive signal, the pull-up drive transistor and / or the pull-down drive transistor are turned on / off to generate a corresponding output signal at the output terminal.

11. The driving method according to claim 10, characterized in that, The generation of a first drive signal for driving the pull-up drive transistor and a second drive signal for driving the pull-down drive transistor based on the data signal and at least one adjustment voltage includes: A first drive signal for driving the pull-up drive transistor is generated based on the data signal and the first adjustment voltage, and a second drive signal for driving the pull-down drive transistor is generated based on the data signal, wherein the first adjustment voltage is lower than the ground voltage, the first drive signal switches between the power supply voltage and the first adjustment voltage to quickly turn on the pull-up drive transistor when the first adjustment voltage is applied, and the second drive signal switches between the power supply voltage and the ground voltage; or A first drive signal for driving the pull-up drive transistor is generated based on the data signal, and a second drive signal for driving the pull-down drive transistor is generated based on the data signal and a second adjustment voltage, wherein the second adjustment voltage is higher than the power supply voltage, and the second drive signal switches between the second adjustment voltage and the ground voltage to quickly turn on the pull-down drive transistor when the second adjustment voltage is applied; the first drive signal switches between the power supply voltage and the ground voltage; or A first drive signal for driving the pull-up drive transistor is generated based on the data signal and a first adjustment voltage, and a second drive signal for driving the pull-down drive transistor is generated based on the data signal and a second adjustment voltage, wherein the first adjustment voltage is lower than the ground voltage, and the second adjustment voltage is higher than the power supply voltage. The first drive signal switches between the power supply voltage and the first adjustment voltage to quickly turn on the pull-up drive transistor when the first adjustment voltage is applied, and the second drive signal switches between the second adjustment voltage and the ground voltage to quickly turn on the pull-down drive transistor when the second adjustment voltage is applied; or A first drive signal for driving the pull-up drive transistor is generated based on the data signal, the first adjustment voltage, and the second adjustment voltage, and a second drive signal for driving the pull-down drive transistor is generated based on the data signal, the first adjustment voltage, and the second adjustment voltage, wherein the first adjustment voltage is lower than the ground voltage, the second adjustment voltage is higher than the power supply voltage, the first drive signal switches between the first adjustment voltage and the second adjustment voltage to quickly turn on the pull-up drive transistor when the first adjustment voltage is applied, and the second drive signal switches between the first adjustment voltage and the second adjustment voltage to quickly turn on the pull-down drive transistor when the second adjustment voltage is applied; or A first drive signal for driving the pull-up drive transistor is generated based on the data signal, a first adjustment voltage, and a third adjustment voltage, and a second drive signal for driving the pull-down drive transistor is generated based on the data signal, a second adjustment voltage, and a fourth adjustment voltage. The first and fourth adjustment voltages are lower than the ground voltage, and the second and third adjustment voltages are higher than the power supply voltage. The first drive signal switches between the first and third adjustment voltages to quickly turn on the pull-up drive transistor when the first adjustment voltage is applied, and the second drive signal switches between the second and fourth adjustment voltages to quickly turn on the pull-down drive transistor when the second adjustment voltage is applied.

12. A data chip, characterized in that, The data chip includes the output driving circuit as described in any one of claims 1 to 9.

13. A memory, characterized in that, The memory includes the data chip as described in claim 12.

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