Charge coupled field effect rectifier diode and method of manufacturing the same

Abstract

Various embodiments of this disclosure relate to charge-coupled field-effect rectifier diodes and methods for manufacturing the same. A trench in a semiconductor substrate is lined with a first insulating layer. Etching is controlled using a hard mask layer deposited on the first insulating layer, selectively removing a first portion of the first insulating layer from an upper trench portion while leaving a second portion of the first insulating layer in a lower trench portion. After removing the hard mask layer, the upper portion of the trench is lined with a second insulating layer. An opening in the trench is then filled by a single deposition of polysilicon material forming a single gate / field plate conductor for the field-effect rectifier diode. This opening includes a lower opening portion defined by the second portion of the first insulating layer in the lower trench portion and an upper opening portion defined by the second insulating layer in the upper trench portion.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 197,599, filed June 7, 2021, the disclosure of which is incorporated herein by reference. Technical Field

[0003] This invention relates generally to charge-coupled integrated circuit devices, and more specifically to charge-coupled field-effect rectifier diodes and methods for manufacturing the same. Background Technology

[0004] refer to Figure 1 , Figure 1 A cross-section of an embodiment of a charge-coupled field-effect rectifier diode (FERD) device 10, as taught in U.S. Patent Application Publication No. 2020 / 0105946 (now U.S. Patent No. 11,239,376) (incorporated herein by reference), is shown. Device 10 is formed in and on a semiconductor substrate 12 (e.g., silicon). Substrate 12 has a front side 14 and a back side 16. Substrate 12 provides a cathode region of the field-effect diode 10, comprising a first doped region 12a heavily doped with an n-type dopant and an overlying second doped region 12b lightly doped with an n-type dopant. A cathode metal layer 38 extends over the back side 16 of substrate 12 to provide a metallic connection to the cathode region.

[0005] Multiple trenches 18 extend from the front side 14 into the substrate 12 along the depth direction. The trenches 18 are regularly spaced apart and extend longitudinally parallel to each other in a direction perpendicular to the cross-section (i.e., into and out of the page of the figure), wherein adjacent trenches define the side edges of the mesa region 13 of the diode. As a variation, the trenches 18 may be formed as annular around the mesa region 13.

[0006] A region 24 doped with p-type dopant is buried in a mesa region 13 of substrate 12 at a certain depth offset from the front side 14 (i.e., below it) and positioned to extend parallel to the front side 14 on opposite sides of each trench 18. The doped region 24 forms the body (channel) region of the field-effect diode, wherein the trenches 18 completely penetrate the doped body region 24 and enter the substrate 12 below the doped body region 24. A surface region 26 heavily doped with n-type dopant is provided in the mesa region 13 at the front side 14 of substrate 12, and the surface region 26 is positioned to extend parallel to the front side 14 on opposite sides of each trench 18 and to contact the top of the doped body region 24. The doped region 26 forms the source region of the field-effect diode, wherein the trenches 18 completely penetrate the doped source region 26 and further extend as described above to completely penetrate the doped body region 24 and enter the substrate 12 below the doped body region 24. A contact region 28 heavily doped with p-type dopant is provided on the front side 14 of the substrate 12 between adjacent trenches 18, and the contact region 28 extends through the doped region 26 to contact the doped region 24.

[0007] The sidewalls and bottom of each trench 18 are lined with an insulating layer 20, for example, made of silicon oxide. The insulating layer 20 has a first thickness in the lower portion of the trench 18 and a second thickness (wherein the second thickness is less than the first thickness) in the upper portion of the trench 18. Each trench 18 is filled with doped polysilicon material to form a conductive structure 22. Due to the thickness difference of the insulating layer 20 within the trench 18, the conductive structure 22 has a first lateral width in the lower portion of the trench 18 and a second lateral width (wherein the second lateral width is greater than the first lateral width) in the upper portion of the trench 18. The conductive structure 22 is a single conductive material body comprising a combination of a gate electrode 22a (in the upper portion of the trench) for a diode and a field plate electrode 22b (in the lower portion of the trench). Given the thickness difference of the insulating layer 20, when a potential is applied to the conductive structure 22, the gate electrode 22a and the field plate electrode 22b will exert different electrostatic effects on the semiconductor region along the depth of the trench 18. In particular, the gate electrode 22a will have a stronger electrostatic effect than the field plate electrode 22b.

[0008] The conductive structure 22 (including its gate electrode 22a and field plate electrode 22b), the doped region 26 forming the source region, and the doped region 28 forming the body contact are all electrically connected to the anode terminal of the field-effect diode. An anode metal layer 32 extends over the substrate 12 and the trench 18. Layer 32 may be made of, for example, aluminum, aluminum-copper, or aluminum-silicon-copper. A conductive interface layer 34 is located between the anode metal layer 32 and the substrate 12 having the trench 18. Layer 34 may, for example, include a silicide layer. Alternatively, layer 34 may include a metallic barrier material, such as titanium. Layer 34 may not be a continuous layer (as shown), but may be discontinuous and only locally present at locations where semiconductor material is present.

[0009] Figure 1 Fabrication of the structure shown has proven to be a challenge and typically requires multiple precise etching operations and two separate polysilicon deposition steps to form the field electrode 22b and gate electrode 22a of the conductive structure 22, respectively.

[0010] Alternative sites include U.S. Patent Application Publication No. 2020 / 0105946 (now U.S. Patent No. 11,239,376). Figure 2 A- Figure 2 As shown in Figure F, using a manufacturing process, the conductive structure 22 is actually produced as two separate parts, including a separated gate electrode portion 22a' and a field plate electrode portion 22b' that are insulated from each other by an oxide layer 19 in the trench 18 and electrically connected to each other by an anode metal layer 32. This structure in... Figure 2 As shown in the image.

[0011] There is a need in the art for a more efficient and effective method to manufacture products with, for example... Figure 1 The charge-coupled FERD device 10 is shown in the configuration shown. Summary of the Invention

[0012] In one embodiment, a method includes: forming a trench in a semiconductor substrate to provide a cathode region for a field-effect rectifier diode (FERD); lining the trench with a first insulating layer; depositing a hard mask layer on the first insulating layer; performing an etching controlled by the hard mask layer to selectively remove a first portion of the first insulating layer from the upper portion of the trench while leaving a second portion of the first insulating layer in the lower portion of the trench; removing the hard mask layer from the trench; lining the upper portion of the trench with a second insulating layer extending from the second portion of the first insulating layer; and performing a single deposition of a polysilicon material in the trench to fill an opening in the trench, said opening including: The trench includes a lower opening portion defined by a second portion of a first insulating layer at the lower part and an upper opening portion defined by a second insulating layer at the upper part; wherein the polysilicon material filling the opening forms a single conductive structure in the trench, the single conductive structure including: a field plate of the FERD insulated from the semiconductor substrate by the second portion of the first insulating layer and a gate of the FERD insulated from the semiconductor substrate by the second insulating layer; a body region of the FERD formed by implanting and activating a first type of dopant in the semiconductor substrate; and a source region of the FERD formed by implanting and activating a second type of dopant in the semiconductor substrate.

[0013] In one embodiment, a method includes: forming a trench in a semiconductor substrate; lining the trench with a first insulating layer; depositing a hard mask layer on a surface of the first insulating layer in the trench; performing an etching controlled by the hard mask layer to selectively remove a first portion of the first insulating layer from the upper portion of the trench while leaving a second portion of the first insulating layer in the lower portion of the trench; removing the hard mask layer from the trench; lining the upper portion of the trench with a second insulating layer extending from the second portion of the first insulating layer; and performing a single deposition of a polysilicon material in the trench to fill an opening in the trench, said opening having a lower opening portion defined by the second portion of the first insulating layer in the lower portion of the trench and an upper opening portion defined by the second insulating layer in the upper portion of the trench.

[0014] In one embodiment, an integrated circuit includes: a semiconductor substrate having a front side and a back side; a trench extending from the front side into the semiconductor substrate, the trench including a lower portion and an upper portion; a first insulating layer lining the sidewalls of the lower portion of the trench; a second insulating layer lining the sidewalls of the upper portion of the trench; wherein the first insulating layer is thicker than the second insulating layer; wherein the first insulating layer includes a tapered thickness region transitioning between a first thickness and a second thickness; and a single polysilicon material body filling an opening in the trench, the opening having a lower opening portion defined by the first insulating layer in the lower portion of the trench and an upper opening portion defined by the second insulating layer in the upper portion of the trench. Attached Figure Description

[0015] To better understand the embodiments, reference will now be made to the accompanying drawings by way of example only, in which:

[0016] Figure 1 and Figure 2 It is a cross-section of a charge-coupled field-effect rectifier diode (FERD) device taught in U.S. Patent Application Publication No. 2020 / 0105946 (now U.S. Patent No. 11,239,376);

[0017] Figures 3-15 The steps of a method for manufacturing a charge-coupled FERD are shown;

[0018] Figure 16 It shows the way Figures 3-15 The cross-section of a charge-coupled FERD device produced by the method;

[0019] Figure 17 A cross-section of an alternative embodiment of a charge-coupled FERD device is shown;

[0020] Figure 18 , Figure 19 and Figures 20A to 22A It shows the manufacturing process. Figure 17 The steps of the charge-coupled FERD method;

[0021] Figures 20B-22B The steps of a method for manufacturing a charge-coupled FERD are shown; and

[0022] Figure 23 It shows that according to Figures 20B-22B A cross-section of an alternative embodiment of a charge-coupled FERD device manufactured by the process. Detailed Implementation

[0023] In the following description, when terms such as “front,” “back,” “top,” “bottom,” “left,” and “right” are used to define absolute position, or terms such as “above,” “below,” “upper,” and “lower” are used to define relative position, or terms such as “horizontal” and “vertical” are used to define direction, it refers to the orientation of the drawing or its normal use position.

[0024] Now for reference Figures 3-15 , Figures 3-15 It shows the use of manufacturing such as Figure 16 The steps of the method for the charge-coupled FERD device 10 shown.

[0025] Figure 3 The formation of a trench 18 extending from the front side 14 of a semiconductor substrate 12 into the semiconductor substrate 12 is illustrated. The illustrated trench 18 is one of a plurality of trenches formed in relation to the fabrication of a diode 10. The semiconductor substrate 12 includes a first doped region 12a heavily doped with n-type dopant and an overlying second doped region 12b lightly doped with n-type dopant. The trench 18 does not extend to the first doped region 12a in the second doped region 12b. The trench 18 can be formed using conventional photolithography techniques. For example, a mask is formed on the substrate 12, having mask openings at the locations where each trench 18 is to be formed. An etching process is then used to form openings in the trench 18 within the substrate 12.

[0026] After forming trench 18, an insulating dielectric layer 120a is conformally formed on the exposed surface of substrate 12, for example, by thermal oxidation. This includes the front side 14 of the substrate and the sidewalls and bottom of trench 18. The thickness of layer 120a is controlled to be less than half the lateral width of each trench 18, thus leaving an opening 121 in the center of trench 18. The result is... Figure 4 As shown in the image.

[0027] Then, as Figure 5As shown, a conformal (blanket) deposition of a nitride layer 104 is performed on substrate 12. The nitride layer 104 covers the front side 14 of the substrate, the layer 120a along the sidewalls, and the bottom of the openings 121 left in the trench 18. The thickness of layer 104 is controlled to be less than half the lateral width of each opening 121, thus leaving an opening 105 in the center of the trench 18. As described below, this nitride layer 104 is ultimately used as a hard mask.

[0028] Then, as Figure 6 The deposited resist layer 106 is shown to cover the layer 104 and fill the opening 105.

[0029] Then, photolithographically patterning of the resist 106 is performed to remove it from the area above and around the trench 18. A portion 106a of the resist is then retained in the opening 105 at the center of the trench 18. The result is... Figure 7A and Figure 7B The text is a mix of Chinese characters and symbols, making it impossible to translate accurately. It appears to be a collection of fragments from various sources Figure 7B It is focused on the top of groove 18 Figure 7A The image shown is a scanning electron microscope (SEM) image of the cross-section. It should be noted that the horizontal portion of layer 104 is exposed due to the photolithographic patterning of the resist layer 106.

[0030] Then, dry etching is performed to remove the horizontal portion of the nitride layer 104 and thus define the structure of the nitride hard mask relative to layer 120a. This etching also removes a portion of the resist 106a at the upper part of the trench 18 (leaving the portion 106b at the bottom of the trench). The result is... Figure 8A and Figure 8B The text is a mix of Chinese characters and symbols, making it impossible to translate accurately. It appears to be a collection of fragments from various sources Figure 8B It is focused on the top of the trench. Figure 8A The image shown is a scanning electron micrograph (SEM) of the cross-section, in which the horizontal portion of the nitride layer 104 and the portion of the resist 106a at the top of the trench 18 have been removed. The effect of this dry etching to remove the horizontal portion of the nitride layer 104 is to expose the upper end of layer 120a in the trench 18.

[0031] Then, a wet etching process is performed on the field plate oxide to remove portions of layer 120a that are not protected by the nitride layer hard mask or the resist 106b above the nitride hard mask. This is actually a selective etching process that removes the recessed portion of layer 120a from the exposed upper end. The result is... Figure 9A and Figure 9B The text is a mix of Chinese characters and symbols, making it impossible to translate accurately. It appears to be a collection of fragments from various sources Figure 9B yes Figure 9A(Scanning electron micrograph (SEM) image of the cross-section shown). The etching forms an opening 107 between layer 104 and the sidewalls of trench 18, and shapes a portion of the insulating layer 20 made of layer 120a at the bottom of the trench into a tapered thickness region 101 in which the thickness of layer 120a increases from the sidewalls of trench 18 as the depth into the trench increases. The provision and shaping of the tapered thickness region 101 is a result of etching controlled by the presence of hard mask layer 104 and creating a recess in layer 120a.

[0032] The advantages of using nitride layer 104 as a hard mask during the process of creating a recess in layer 120a using wet etching with field plate oxides. Figure 9B It is quite obvious. The quality of the recess of layer 120a above the multiple trenches 18 is ensured to uniformly remove a portion of layer 120a in the upper part of the trench and uniformly define the shape of layer 120a in the lower part of the trench. Regarding the shape of layer 120a in the lower part of the trench, there is almost no change from trench to trench.

[0033] It should be noted that using nitrides as the material for the hard mask provided by layer 104 is merely an example. Any suitable material can be used for layer 104, as long as it provides the necessary hard mask functionality associated with the etching process used to recess layer 120a in trench 18.

[0034] Then, the remaining portion of the resist 106b in the trench 18 is stripped to leave an opening 105 in the trench 18. The result is... Figure 10 As shown in the figure. Here, it is worth noting that the recess of layer 120a is only associated with the nitride hard mask, and as an alternative step in the process, the remainder of resist 106b can be etched away after dry etching of the nitride hard mask.

[0035] Then, a nitride wet etching process is performed to remove the nitride hard mask portion of layer 104. The result is... Figure 11 As shown in the figure. This leaves only a portion of layer 120a at the bottom of the trench and defines an opening 107 in the center of the trench 18, which has an upper portion defined by the sidewalls of the trench 18 and a lower portion defined by the remaining portion of layer 120a.

[0036] Then, for example by thermal oxidation, an insulating dielectric layer 120b is conformally formed on the exposed surface of substrate 12. This will include the front side 14 of the substrate and the sidewalls not covered by layer 120a at the upper portion of the trench 18 in the opening 107. The result is... Figure 12As shown, an insulating dielectric layer 120b extends along the trench sidewall from a portion of layer 120a retained in the trench. Insulating layers 120a and 120b form the insulating layer 20 of diode 10 and define an opening 109 in trench 18. The opening 109 includes a lower portion 109a and an upper portion 109b. The lower portion 109a has a first width extending between the lower portions of the insulating layer 20 (formed by the remaining portion of layer 120a in the trench), and the upper portion 109b has a second width extending between the upper portions of the insulating layer 20 (formed by a portion of layer 120b in the trench). The second width is greater than the first width. The thickness of layer 120b is controlled to provide the desired gate oxide thickness of diode 10.

[0037] Then, a single deposition of n-type highly doped polysilicon material 122 is performed to fill the opening 109 and form the conductive structure 22 of the diode 10. Excess polysilicon material above the front side 14 of the substrate 12 is removed using polysilicon dry etching, such that the upper surface of the conductive structure 22 is coplanar (or substantially coplanar) with the upper surface of layer 120b (or the upper surface of the substrate 12). The result is... Figure 13A and Figure 13B The text is a mix of Chinese characters and symbols, making it impossible to translate accurately. It appears to be a collection of fragments from various sources Figure 13B yes Figure 13A The image shown is a scanning electron microscope (SEM) image of the cross-section. The deposited polycrystalline silicon material 122 forms a unitary body of the conductive structure 22, which includes a gate electrode portion 22a of the diode (in the upper part of the trench) and a field plate electrode portion 22b (in the lower part of the trench).

[0038] Then, conventional processes known in the art for implanting and activating dopants to form the p-type doped region 24, the n-type doped source region 26, and the p-type doped contact region 28 are performed. Due to its high doping level, there is no risk of forming a pn junction in the polysilicon material 122. The result is... Figure 14 As shown in the image.

[0039] A conductive interface layer 34 is then formed on the substrate. In one embodiment, the horizontal portion of layer 120b at the front side 14 of the substrate 12 may be removed. Layer 34 may include a silicide layer in contact with the polysilicon material 122 of the conductive structure 22 and the semiconductor material for the n-type doped source region 26 and the p-type doped contact region 28. Alternatively, layer 34 may include a metal barrier. An anode metal layer 32 is then deposited layer by layer on the interface layer 34 and photolithographically patterned as needed to provide electrical connection to the anode terminal of the field-effect diode. The back side 16 of the substrate 12 is further treated with back grinding and / or polishing to provide a surface on which the cathode metal layer 38 is deposited. Figure 15 As shown in the figure, and used to form such Figure 16The process of the charge-coupled FERD device 10 shown is completed.

[0040] Now for reference Figure 17 , Figure 17 A cross-section of another embodiment of the charge-coupled field-effect rectifier diode (FERD) device 10 is shown. Similar reference numerals refer to similar or related components. Figure 17 Device 10 and Figure 16 The difference with device 10 is that the above structure is fabricated above the front side 14 of substrate 12. A pre-metallized dielectric (PMD) layer 200 extends above the front side 14 of substrate 12. An opening 202 is formed to extend through the PMD layer 200 to reach the conductive structure 22. Furthermore, an opening 204 is formed to extend through the PMD layer 200 and the doped source region 26 to at least reach the top of the doped region 24. A p-type doped contact region 28 is formed at the bottom of the opening 204. A silicide layer (not explicitly shown) may be formed at the bottom of each opening 202 and 204 to improve contact resistance. Openings 202 and 204 are filled with a metallic material to form electrical contacts 206. Then, an anode metal layer 32 is deposited layer by layer on the PMD layer 200 and photolithographically patterned as needed to provide an electrical connection to the anode terminal of the field-effect diode.

[0041] Used for manufacturing Figure 17 The process of using diode device 10 with Figures 3-13A and Figure 13B The process shown follows the same steps. Figure 13A and Figure 13B The steps following the first step are for completing the device manufacturing process. Figure 18 , Figure 19 and Figures 20A-22A As shown in the image.

[0042] exist Figure 13A and Figure 13B Following the processing steps, conventional processes known in the art for implanting and activating dopants to form the p-type doped body region 24 and the n-type doped source region 26 are then performed. Due to its high doping level, no pn junction is formed in the polycrystalline silicon material 122. As a result... Figure 18 As shown in the image.

[0043] Then, a dielectric material layer is formed on the substrate to provide the PMD layer 200. In one embodiment, the horizontal portion of layer 120b at the front side 14 of the substrate 12 may be removed. The result is... Figure 19 As shown in the image.

[0044] Figure 20AThe formation of openings 202 and 204 extending from the upper surface of PMD layer 200 is shown. Opening 202 extends completely through PMD layer 200 to reach conductive structure 22. Opening 204 extends completely through both PMD layer 200 and doped source pole region 26 to at least reach the top of doped body region 24. Openings 202 and 204 can each be formed using conventional photolithography techniques. For example, a mask is formed on PMD layer 200, with mask openings at the locations where openings (202 or 204) are to be formed. An etching process is then used to form openings of the desired depth. In conjunction with the formation of opening 204, a dopant implantation process is performed to implant body contact regions 28 into body region 24 at the bottom of each opening 204.

[0045] Then, openings 202 and 204 are filled with a metallic material (e.g., tungsten) to form electrical contacts 206. The result is... Figure 21A As shown in the image.

[0046] Then, an anode metal layer 32 is deposited layer-by-layer on the PMD layer 200 and photolithographically patterned as needed to provide electrical connection to the anode terminal of the field-effect diode. The back side 16 of the substrate 12 is further processed by back grinding and / or polishing to provide a surface on which the cathode metal layer 38 is deposited. The result is... Figure 22A As shown in the figure, and used to form such Figure 17 The process of diode 10 shown is complete.

[0047] It should be noted that the above combination Figure 20A , Figure 21A and Figure 22A The described process typically requires the use of two different masking and etching operations to form openings 202 and 204. In an alternative implementation, only one masking and etching operation is used for the formation of openings 202 and 204. Figure 20B The formation of openings 202 and 204 extending from the upper surface of PMD layer 200 is shown. Openings 202 and 204 are formed simultaneously using a single masking and etching operation employing conventional photolithography. Opening 202 extends completely through both PMD layer 200 and doped source region 26 to reach at least the top of doped body region 24. Opening 204 extends completely through PMD layer 200 and into polysilicon material 122. For example, openings 202 and 204 may have similar depths depending on the etching rate relative to doped source region 26 and doped polysilicon material 122. In conjunction with the formation of openings 202 and 204, a dopant implantation process is performed to implant body contact regions 28 into body region 24 at the bottom of each opening 204. It should be noted that a high doping concentration level in polysilicon material 122 will prevent the formation of pn junctions at openings 202.

[0048] Then, openings 202 and 204 are filled with a metallic material (e.g., tungsten) to form electrical contacts 206. The result is... Figure 21B As shown in the image.

[0049] Then, an anode metal layer 32 is deposited layer-by-layer on the PMD layer 200 and photolithographically patterned as needed to provide electrical connection to the anode terminal of the field-effect diode. The back side 16 of the substrate 12 is further processed by back grinding and / or polishing to provide a surface on which the cathode metal layer 38 is deposited. The result is... Figure 22B As shown in the figure, and used to form such Figure 23 The process of diode 10 shown is complete.

[0050] While the invention has been detailed and described in the accompanying drawings and foregoing description, such description is to be considered illustrative or exemplary rather than restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments will be understood and implemented by those skilled in the art in practicing the claimed invention through study of the drawings, the disclosure, and the appended claims.

Claims

1. A method for manufacturing a field-effect rectifier diode, comprising: A trench is formed in the semiconductor substrate to provide the cathode region of the field-effect rectifier diode; The trench is lined with a first insulating layer; A hard mask layer is deposited on the first insulating layer; The openings in the trench are filled with a resist material, and the openings are left in the trench after the hard mask layer is deposited. An etching controlled by the hard mask layer is performed to selectively remove a first portion of the first insulating layer from the upper part of the trench, while leaving a second portion of the first insulating layer in the lower part of the trench. Remove the hard mask layer from the trench; The upper part of the trench is lined with a second insulating layer extending from the second portion of the first insulating layer; The opening in the trench includes: a lower opening portion defined by the second portion of the first insulating layer in the lower part of the trench and an upper opening portion defined by the second insulating layer in the upper part of the trench; A single deposition of polycrystalline silicon material is performed in the trench to fill the opening in the trench; The polycrystalline silicon material filling the opening forms a single conductive structure in the trench, the single conductive structure comprising: a field plate of the field-effect rectifier diode that is insulated from the semiconductor substrate by the second portion of the first insulating layer, and a gate of the field-effect rectifier diode that is insulated from the semiconductor substrate by the second insulating layer; Implanting and activating a first type of dopant in the semiconductor substrate to form the body region of the field-effect rectifier diode; and A second type of dopant is implanted and activated in the semiconductor substrate to form the source region of the field-effect rectifier diode.

2. The method according to claim 1, further comprising: A cathode metal layer is formed on the back side of the semiconductor substrate, and the cathode metal layer is electrically connected to the cathode region; as well as An anode metal layer is formed on the front side of the semiconductor substrate, and the anode metal layer is electrically connected to both the polycrystalline silicon material and the source region.

3. The method of claim 2, further comprising electrically connecting the anode metal layer to the body region.

4. The method of claim 3, wherein the electrical connection includes injecting and activating the first type of dopant to form a body contact region at the body region.

5. The method of claim 1, wherein depositing the hard mask layer comprises conformally depositing a nitride layer in the trench on the surface of the first insulating layer.

6. The method of claim 1, wherein removing the hard mask layer from the trench further comprises removing the resist material from the trench.

7. The method of claim 1, further comprising, after depositing the hard mask layer on the first insulating layer, removing a portion of the hard mask layer to expose an upper end of the first insulating layer, and wherein performing the etching comprises causing the first insulating layer in the upper portion of the trench to recess from the exposed upper end.

8. A field-effect rectifier diode device manufactured using the method according to claim 1.

9. A method for manufacturing a field-effect rectifier diode, comprising: Trenches are formed in a semiconductor substrate; The trench is lined with a first insulating layer; A hard mask layer is deposited on the surface of the first insulating layer in the trench; The openings in the trench are filled with a resist material, and the openings are left in the trench after the hard mask layer is deposited. An etching controlled by the hard mask layer is performed to selectively remove a first portion of the first insulating layer from the upper part of the trench, while leaving a second portion of the first insulating layer in the lower part of the trench. Remove the hard mask layer from the trench; The upper part of the trench is lined with a second insulating layer extending from the second portion of the first insulating layer; as well as A single deposition of polycrystalline silicon material is performed in the trench to fill an opening in the trench, the opening having a lower opening portion defined by the second portion of the first insulating layer in the lower part of the trench and an upper opening portion defined by the second insulating layer in the upper part of the trench.

10. The method of claim 9, wherein depositing the hard mask layer comprises conformally depositing a nitride layer in the trench on the surface of the first insulating layer.

11. The method of claim 9, wherein removing the hard mask layer from the trench further comprises removing the resist material from the trench.

12. The method of claim 9, further comprising, after depositing the hard mask layer on the first insulating layer, removing a portion of the hard mask layer to expose an upper end of the first insulating layer, and wherein performing the etching comprises causing the first insulating layer in the upper portion of the trench to recess from the exposed upper end.

13. An integrated circuit device manufactured using the method according to claim 9.

14. An integrated circuit, comprising: A semiconductor substrate having a front side and a back side; A trench extending from the front side into the semiconductor substrate, the trench comprising a lower portion and an upper portion; A first insulating layer lining the lower sidewall of the trench; A second insulating layer is provided to line the upper sidewall of the trench; The first insulating layer is thicker than the second insulating layer; The first insulating layer includes a tapered thickness region transitioning between a first thickness and a second thickness, wherein the tapered thickness region of the first insulating layer is defined by a recessed etching controlled by a hard mask layer deposited in the trench on the surface of the first insulating layer. as well as A single polycrystalline silicon material body fills an opening in the trench, the opening having a lower opening portion defined by a first insulating layer in the lower part of the trench and an upper opening portion defined by a second insulating layer in the upper part of the trench.

15. The integrated circuit of claim 14, wherein the integrated circuit is a field effect rectifier diode, and wherein the single body of polysilicon material forms a conductive structure in the trench, the conductive structure comprising: The field plate of the field-effect rectifier diode is insulated from the semiconductor substrate by the first insulating layer, and the gate of the field-effect rectifier diode is insulated from the semiconductor substrate by the second insulating layer.

16. The integrated circuit of claim 15, wherein the semiconductor substrate provides the cathode region of the field-effect rectifier diode.

17. The integrated circuit of claim 16, further comprising: The body region of the field-effect rectifier diode is formed in a first type of doped region in the semiconductor substrate; as well as The source region of the field-effect rectifier diode is formed in a second type of doped region in the semiconductor substrate.

18. The integrated circuit of claim 17, further comprising: A cathode metal layer is located on the back side of the semiconductor substrate, and the cathode metal layer is electrically connected to the cathode region. as well as An anode metal layer is located on the front side of the semiconductor substrate, and the anode metal layer is electrically connected to the single polycrystalline silicon material body and the source region.

19. The integrated circuit of claim 18, further comprising an electrical connection between the anode metal layer and the body region.

20. The integrated circuit of claim 19, further comprising a first type of doped region forming a body contact region at the body region, wherein the electrical connection to the body contact region is made.

21. The integrated circuit of claim 14, wherein the second insulating layer is formed after the recess etching is performed.

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