Method of forming a semiconductor element and method of performing a physical deposition process

Abstract

A method of forming a semiconductor device and a method of performing a physical deposition process, the method of forming a semiconductor device includes forming a dielectric layer on a wafer. The dielectric layer is etched to form an opening. A plasma deposition process is performed to form a seed layer in the opening, wherein performing the plasma deposition process includes positioning the wafer under a magnet module and rotating the magnet module, the magnet module including a carrier structure, a puck, and a magnet, a center of the carrier structure, a center of the puck, and a center of the magnet forming a triangle. A fill layer is formed on the seed layer.

Description

Technical Field

[0001] This disclosure relates to a method for forming semiconductor devices and a method for performing physical deposition processes. Background Technology

[0002] Physical vapor deposition (PVD) is commonly used in the semiconductor industry, as well as in solar energy, glass coating, and other industries. PVD systems are used to deposit metal layers on substrates, such as semiconductor wafers, positioned within a vacuum plasma chamber. PVD processes are used to deposit target materials on semiconductor wafers. In some PVD systems, the target to be coated is placed in a vacuum chamber containing an inert gas such as argon. Summary of the Invention

[0003] According to some embodiments of this disclosure, a method for forming a semiconductor device includes forming a dielectric layer on a wafer. The dielectric layer is etched to form an opening. A plasma deposition process is performed to form a seed layer in the opening, wherein performing the plasma deposition process includes placing the wafer under a magnet module and rotating the magnet module, the magnet module including a carrier structure, a placement disk, and a magnet, wherein the center of the carrier structure, the center of the placement disk, and the center of the magnet form a triangle. A fill layer is formed on the seed layer.

[0004] According to some embodiments of this disclosure, a method of forming a semiconductor device includes forming a dielectric layer on a wafer. The dielectric layer is etched to form an opening. A plasma deposition process is performed to form a seed layer in the opening, wherein performing the plasma deposition process includes rotating a magnet module on the wafer to control plasma for the plasma deposition process. The magnet module has a radius of rotation, and the target for the plasma deposition process has a diameter, the ratio of the radius of rotation to the diameter being 0.013 to 0.038. A fill layer is formed on the seed layer.

[0005] According to some embodiments disclosed herein, a method for performing a physical deposition process includes setting up a baffle to define a chamber. A wafer pedestal stage is set in the chamber, the wafer pedestal stage being configured to support a wafer. A magnet module is set on the wafer pedestal stage, the magnet module including a carrier structure and a magnet. A target is set under the carrier structure, wherein the target includes a first region and a second region, the first region being closer to a center of the target than the second region. The distance between the center of the carrier structure and the center of the magnet is determined based on the etch depth variation of the first and second regions of the target. Attached Figure Description

[0006] The detailed description of the embodiments of the present invention will be fully understood when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the features may be increased or decreased arbitrarily for clarity of explanation. Similar features are denoted by the same reference numerals in the specification and drawings.

[0007] Figure 1 A schematic diagram of a processing apparatus according to some embodiments of this disclosure is shown;

[0008] Figure 2 The illustration depicts a magnet module of a processing apparatus according to some embodiments of this disclosure;

[0009] Figure 3A and Figure 3B A schematic diagram illustrating the relationship between the erosion depth and the radius of the target material according to some embodiments of this disclosure is provided.

[0010] Figures 4 to 9 This illustration discloses semiconductor elements at different stages of some implementation methods;

[0011] Figure 10 A schematic plan view of a cluster tool according to some embodiments of this disclosure is shown.

[0012] [Symbol Explanation]

[0013] 100: Processing equipment

[0014] 102: Enclosure barriers

[0015] 104: Chamber

[0016] 110: Collimator

[0017] 104a: upper part

[0018] 104b:lower part

[0019] 120: Wafer pedestal stage

[0020] 130: Power Supply

[0021] 132: Power Supply

[0022] 134: Power Supply

[0023] 140: Magnet Module

[0024] 142: Carrier Structure

[0025] 144: Magnet

[0026] 146: Placement tray

[0027] 150: Electromagnetic coil

[0028] 160: Electrode plate

[0029] 170: Shielding panel

[0030] 200: Wafer

[0031] 210: Dielectric layer

[0032] 220: Opening

[0033] 230: First Barrier Layer

[0034] 240: Second Barrier Layer

[0035] 250: Seed layer

[0036] 260: Fill layer

[0037] 300: Processing Station

[0038] 310: Central Transmission Chamber

[0039] 312: Central Transmission Agency

[0040] 320: Processing Chamber

[0041] 330: Processing Chamber

[0042] 340: Processing Chamber

[0043] 350: Processing Chamber

[0044] 360a: Wafer Carrier Transport Chamber

[0045] 360b: Wafer Carrier Transport Chamber

[0046] 370: Device front-end module

[0047] 372: Loading locking mechanism

[0048] 380: Transport vehicle

[0049] 1: Area

[0050] 2: Area

[0051] 3: Area

[0052] A: Point

[0053] A1: Point

[0054] D: Width

[0055] L1: Distance

[0056] L2: Distance

[0057] M: Center

[0058] M1: Center

[0059] M2: Center (Angle)

[0060] P: Plasma

[0061] r: Distance (radius of rotation)

[0062] T: Target material

[0063] W: Wafer

[0064] θ1: included angle

[0065] θ2: included angle Detailed Implementation

[0066] The following describes several embodiments of this disclosure with reference to the accompanying drawings. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit this disclosure. That is, in some embodiments of this disclosure, these practical details are not essential and therefore should not be used to limit this disclosure. In addition, for the sake of simplicity in the drawings, some conventional structures and components will be shown in a simplified schematic manner. Furthermore, for the reader's convenience, the dimensions of the components in the drawings are not drawn to scale.

[0067] It should be understood that relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship of one element to another, as illustrated in the accompanying drawings. It should be understood that relative terms are intended to include different orientations of the device beyond those shown in the figures. For example, if a device in one of the figures is flipped, an element described as being “down” to other elements will be oriented “up” to other elements. Thus, the exemplary term “down” can include both “down” and “up” orientations, depending on the specific orientation of the figure. Similarly, if a device in one of the figures is flipped, an element described as being “down” or “below” to other elements will be oriented “above” to other elements. Thus, the exemplary term “down” or “below” can include both “up” and “down” orientations.

[0068] Furthermore, the terms "about," "approximately," "generally," or "substantially" used in this article generally refer to numerical errors or ranges within 20 percent, preferably within 10 percent, and more preferably within 5 percent. Unless otherwise specified, all numerical values ​​mentioned are considered approximate, i.e., having the errors or ranges indicated by "about," "approximately," "generally," or "substantially."

[0069] Figure 1 A schematic diagram of a processing apparatus 100 according to some embodiments of this disclosure is shown. (See also...) Figure 1 The processing apparatus 100 can be configured to perform deposition and etching processes. The processing apparatus 100 includes a baffle 102, a chamber 104, a collimator 110, a wafer pedestal stage 120, a power supply 130, a power supply 132, a power supply 134, and a magnet module 140.

[0070] Enclosure baffle 102 is configured to form (define) chamber 104. Chamber 104 includes an upper portion 104a and a lower portion 104b, which may be separated by collimator 110. Collimator 110 may be mounted between wafer pedestal 120 and magnet module 140. For example, collimator 110 may be mounted on enclosure baffle 102 via multiple fixing elements (such as screws). In some embodiments, collimator 110 may include multiple channels, and the channels may have a hexagonal cross-sectional configuration. For example, the channels of collimator 110 may collectively form a honeycomb profile, making it less likely that atoms or molecules entering the channels will adhere to the corners of the channels, thereby extending the lifetime of collimator 110. In some other embodiments, the channels of collimator 110 may also have other shaped cross-sectional configurations, such as triangles, squares, rectangles, other shapes that can form a honeycomb, or combinations thereof.

[0071] The wafer pedestal 120 is configured to support a wafer W. In other words, the wafer W is disposed within the lower portion 104b of the chamber 104. In some embodiments, the wafer pedestal 120 may be an electrostatic chuck. For example, a Coulomb force or Johnsen-Rahbek force can be generated by applying a voltage to the wafer pedestal 120 to secure the wafer W to the wafer pedestal 120. In some other embodiments, the wafer pedestal 120 may have chuck pins positioned on the edge of the wafer W to ensure that the wafer W is secured to the wafer pedestal 120. In some embodiments, the wafer pedestal 120 may contain a temperature control and maintenance system that allows for temperature control of the wafer W. For example, the wafer pedestal 120 may be used to cool the wafer W when the chamber 104 is heated and plasma P is generated therein. Adjusting the temperature of wafer W can improve the properties of the material layer deposited on wafer W and increase the deposition rate.

[0072] Power supplies 130, 132, and 134 are disposed in processing apparatus 100 to generate and control plasma P in chamber 104 and to guide sputtering, etching, or re-etching as needed. Specifically, power supply 130 may be a direct current (DC) power supply and is electrically coupled to magnet module 140 (e.g., carrier structure 142) to provide DC power to carrier structure 142. Power supply 132 may be a radio frequency alternating current (RF AC) power supply and is electrically coupled to wafer pedestal 120. Power supply 134 may be an RF AC power supply and may be electrically coupled to electrode plate 160 in chamber 104 to generate and control plasma P. In some embodiments, power supply 134 may be electrically coupled to electromagnetic coil 150 to generate an electromagnetic field to guide ions in chamber 104. The electromagnetic coil 150 is located outside the enclosure baffle 102. In some embodiments, in addition to the power supply 130, another radio frequency AC power supply may also be electrically coupled to the magnet module 140. In some embodiments, the power supply 130 applies approximately 20 kW or more of power (e.g., DC power) to the carrier structure 142. In some embodiments, the power supply 132 applies approximately 500 W or more of power (e.g., radio frequency power) to the wafer pedestal stage 120. In some embodiments, the radio frequency of the power supply 132 is greater than that of the power supply 134. For example, the radio frequency of the power supply 132 is approximately 10 MHz to approximately 15 MHz (e.g., approximately 13.5 MHz), while the radio frequency of the power supply 134 is approximately 1 MHz to approximately 5 MHz (e.g., approximately 2 MHz).

[0073] In some embodiments disclosed herein, plasma P can be generated in processing apparatus 100 by introducing a plasma feed gas, such as argon (Ar), into chamber 104. Electrons supplied by power supplies 130, 132, and 134 collide with atoms in the plasma feed gas to generate ions (e.g., copper ions). A negative bias applied by power supply 130 attracts the ions toward target T. The ions collide with target T at high energy. In other words, the negative bias applied by power supply 130 accelerates the cations of plasma P toward target T to sputter atoms from target T. Sputtered atoms migrate from the surface of target T through direct momentum transfer. The sputtered atoms may or may not be ionized, and a subset of the sputtered atoms may be deposited onto wafer W.

[0074] A magnet module 140 is disposed on the upper portion 104a of the chamber 104. The magnet module 140 may include a carrier structure 142 and a magnet (magnetron) 144. The carrier structure 142 is configured to support the target T and ensures that the target T is fixed to the carrier structure 142 during the deposition process. The target T is a material layer and is formed on the wafer W in a subsequent deposition process. The target T may be a conductive material and reacts with a gas in the chamber 104 to form a deposited metal layer. For example, the target T may contain a metal or alloy material, wherein the metal may be, for example, titanium (Ti), aluminum (Al), tantalum (Ta), copper (Cu), manganese (Mn) or other suitable metal materials, and the alloy may be, for example, a copper-manganese (Cu-Mn) alloy or other suitable alloy materials. The magnet 144 may be disposed on the carrier structure 142 to generate a magnetic field in the chamber 104. In detail, magnet 144 can be fixed to carrier structure 142 via a magnet holder. Magnet 144 and target material T are respectively disposed on opposite sides of carrier structure 142. Magnet 144 provides a magnetic field for chamber 104, which can increase the residence time of electrons by causing electrons to spiral through plasma P. By changing the shape of the magnetic field of magnet 144, plasma P can be directionally controlled. Therefore, the degree of ionization of plasma gas can be increased. In some embodiments, by providing radio frequency or DC bias, magnet 144 can control the uniformity of plasma P (especially the uniformity of plasma P near wafer W). Furthermore, since wafer W is typically a circular wafer, concentric electromagnetic coils can be used. More details about the structure of magnet module 140 will be provided in [the following section]. Figure 2 The relevant paragraphs will be discussed in detail.

[0075] In some embodiments, the processing apparatus 100 further includes a shielding plate 170 disposed above the upper portion 104a of the chamber 104. The shielding plate 170 may be disposed between the carrier structure 142 and the collimator 110. More specifically, the shielding plate 170 is disposed between the target material T and the wafer W to prevent ions (e.g., copper ions) during the process from depositing on the wafer pedestal 120 and contaminating the wafer W.

[0076] Figure 2 The illustration depicts a magnet module 140 of a processing apparatus 100 according to some embodiments of this disclosure. For example... Figure 1 and Figure 2As shown, the magnet module 140 includes a carrier structure 142, a magnet 144, and a placement tray 146. The carrier structure 142, the magnet 144, and the placement tray 146, viewed from above (top view), may all have a circular outline. The placement tray 146 may be located at the edge of the carrier structure 142, and the magnet 144 may be located at the edge of the placement tray 146. In other words, the placement tray 146 can be considered as a magnet holding device for the magnet module, used to fix the magnet 144 to the carrier structure 142. In some embodiments, the magnet 144 is located at the edges of the placement tray 146 and the carrier structure 142, and... Figure 2 In this embodiment, the carrier structure 142 is substantially tangent to the edge of the placement disk 146 at point A, and / or the edge of the placement disk 146 is substantially tangent to the edge of the magnet 144 at point A1. In some embodiments, points A and A1 are located at different positions. For example, points A and A1 are located at two different points on the circumference of the placement disk 146. In some embodiments, points A and A1 overlap, for example, when the angle θ2 between distances L1 and L2 is substantially 0.

[0077] The carrier structure 142 has a center M1. In some embodiments, the center of the target material T also overlaps with the center M1 of the carrier structure 142. The placement disk 146 has a center M2. The center M1 of the carrier structure 142 and the center M2 of the placement disk 146 do not overlap and are separated by a distance L1. In some embodiments, the distance L1 is a constant, that is, the placement disk 146 can be fixed off-axis to the carrier structure 142, but the placement disk 146 can rotate along the center M1 of the carrier structure 142 with a rotation radius of distance L1.

[0078] Additionally, the magnet 144 has a center M. The center M2 of the placement disk 146 does not overlap with the center M of the magnet 144, and they are separated by a distance L2. In some embodiments, the distance L2 is a constant, meaning that the magnet 144 can be fixed off-axis to the placement disk 146, but the magnet 144 can rotate along the center M2 of the placement disk 146 with a rotation radius of distance L2, thereby changing the relative position between the center M of the magnet 144 and the center M1 of the carrier structure 142.

[0079] In some embodiments, the center M1 of the carrier structure 142, the center M2 of the placement disk 146, and the center M of the magnet 144 are not on the same straight line. In other words, the line segment connecting the center M1 of the carrier structure 142, the center M2 of the placement disk 146, and the center M of the magnet 144 is not a straight line; for example, it may form a triangle. In some embodiments, the distance L1 between the center M1 of the carrier structure 142 and the center M2 of the placement disk 146 is substantially greater than the distance L2 between the center M2 of the placement disk 146 and the center M of the magnet 144. In some embodiments, both the distance L1 between the center M1 of the carrier structure 142 and the center M2 of the placement disk 146, and the distance L2 between the center M2 of the placement disk 146 and the center M of the magnet 144, are constants. For example, distance L1 is approximately 4 inches to approximately 5 inches, and distance L2 is approximately 2 inches to approximately 3 inches.

[0080] In some embodiments, the distance L1 between the center M1 of the carrier structure 142 and the center M2 of the placement disk 146 forms an angle θ1 with a reference line, and an angle θ2 (i.e., the exterior angle of angle M2 of the triangle formed by centers M1, M2, and M) forms between distance L1 and distance L2. In some embodiments, angle θ2 is substantially greater than angle θ1. In some embodiments disclosed herein, by adjusting the relative positions of the center M1 of the carrier structure 142, the center M2 of the placement disk 146, and the center M of the magnet 144, angle θ2 can be an acute angle (greater than 0 degrees). When angle θ2 is acute, the plasma P distribution is altered, resulting in a more uniform degree of erosion by plasma P in each region of the target material T, thereby improving the erosion uniformity of the target material T and extending its lifespan. In some embodiments, angle θ2 ranges from approximately 70 degrees to approximately 80 degrees. For example, angle θ2 can be approximately 75 degrees. If the included angle θ2 is less than approximately 70 degrees or greater than approximately 80 degrees, the plasma P will be overly concentrated in certain areas of the target material T, resulting in poor uniformity of erosion of the target material T. For example, a certain area of ​​the target material T may be eroded too quickly by the plasma P, causing the target material T to be eroded through prematurely. Furthermore, areas eroded too quickly by the plasma P will generate a large number of metal particles, which may cause premature blockage of certain channels of the collimator 110.

[0081] In some embodiments, by adjusting the relative positions of the center M1 of the carrier structure 142, the center M2 of the placement disk 146, and the center M of the magnet 144, the distance r between the center M1 of the carrier structure 142 and the center M of the magnet 144 can be changed (increased), where the distance r can be considered as the rotation radius of the magnet 144. In other words, as the included angle θ2 decreases from 180 degrees to an acute angle, the distance r (i.e., the rotation radius of the magnet 144) can be increased. That is, during the deposition process, the included angle θ2 is a constant value (i.e., the relative positions between the placement disk 146 and the magnet 144 do not change), and the included angle θ2 is an acute angle, while the placement disk 146 drives the magnet 144 to rotate along the center M1 of the carrier structure 142 (i.e., the included angle θ1 changes). This arrangement can improve the erosion uniformity of the target material T, prevent or avoid premature erosion of certain areas of the target material T, thereby increasing the service life of the target material T, and increasing the utilization rate of other areas of the target material T (e.g., by about 5%). Furthermore, it can reduce the time it takes for metal particles to block the collimator 110 channel.

[0082] In some embodiments, the rotation radius r of magnet 144 can range from about 2.455 inches to about 6.689 inches. If the rotation radius r is less than 2.455 inches, the target material T will be etched through prematurely and the erosion uniformity of the target material T will be poor; if the rotation radius r is greater than 6.689 inches, it may be impossible to control the position of the interaction between plasma P and target material T, and thus the erosion uniformity of target material T cannot be effectively improved.

[0083] Additionally, the target material T has a width (or diameter) D. In some embodiments, the rotation radius r is less than half the width D (i.e., less than D / 2). For example, the ratio of the rotation radius r to the width D (r / D) is approximately 0.013 to approximately 0.038. If the ratio r / D falls within the above range, similar results can be obtained. Figure 3B The target erosion distribution is shown by curve C2; ​​if the ratio r / D falls outside the above range, a similar result may be obtained. Figure 3A The target erosion distribution is shown by curve C1.

[0084] Figure 3A and Figure 3B A schematic diagram illustrating the relationship between the erosion depth and the target radius according to some embodiments of this disclosure is provided. See also... Figure 1 , Figure 2 , Figure 3A and Figure 3B When the center M1 of the carrier structure 142, the center M2 of the placement disk 146, and the center M of the magnet 144 are aligned (e.g., center M is located between centers M1 and M2), the angle θ2 between the distance L1 between the center M1 of the carrier structure 142 and the center M2 of the placement disk 146, and the distance L2 between the center M2 of the placement disk 146 and the center M of the magnet 144, is 180 degrees. Figure 3A As shown in curve C1 (after approximately 3500 kWh of use on target T), the erosion depth of target T varies significantly across different regions (e.g., the difference ranges from approximately 2.36 inches to 5.5 inches (from approximately 60 mm to approximately 140 mm)). This results in uneven erosion of target T, and while regions 1 and 3 of target T still have usable thickness, region 2 of target T may be eroded prematurely. However, when the angle θ2 between the distance L1 between the center M1 of carrier structure 142 and the center M2 of placement disk 146 and the distance L2 between the center M2 of placement disk 146 and the center M of magnet 144 is acute, as... Figure 3B Curve C2 (which represents the time it takes for target T to be used for approximately 4000 kW) is shown, and... Figure 3A Compared to curve C1, the erosion depth of target material T increases in region 3, while the erosion depth decreases in regions 1 and 2. Therefore, the erosion depth of target material T can be more uniform across all regions. That is, the distance r between the center M1 of the carrier structure 142 and the center M of the magnet 144 is determined by the variation in erosion depth in each region of target material T (such as region 1, region 2, and / or region 3). In this way, target material T can achieve higher utilization efficiency and extend its service life. For example, Figure 3A The curve C1 shows that the lifespan of the target material T is approximately 4300 kilowatt-hours, while Figure 3B The lifespan of the target material T, as shown by curve C2, can be increased to approximately 4600 kilowatt-hours.

[0085] In addition, such as Figure 3A As shown in curve C1, because the erosion depth of target material T in region 2 is relatively large, more metal particles are generated below region 2 of target material T. These excessive metal particles may prematurely block part of the channels in the relative region of collimator 110, resulting in uneven distribution of metal particles passing through collimator 110. Conversely, as Figure 3B As shown in curve C2, since the erosion depth of the target material T in regions 1, 2 and 3 is similar, the uniformity of the metal particles generated in each region is similar, thus mitigating the uneven blockage of the channels in each region of the collimator 110.

[0086] The deposition method described above can be applied to semiconductor manufacturing processes. Figures 4 to 9 This illustration discloses semiconductor devices at different stages of implementation. For example... Figure 4 As shown, a dielectric layer 210 is formed on wafer 200. It should be understood that... Figures 4 to 9 The wafer 200 can be regarded as Figure 1The wafer W is described below. In some embodiments, wafer 200 may include a substrate located below dielectric layer 210, and may include, for example, an active layer of doped silicon, undoped silicon, or silicon-on-insulator (SOI) substrate. In some embodiments, the SOI substrate includes a semiconductor material layer (e.g., a silicon material layer) formed on the insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulating layer is disposed on the substrate and may be a silicon or glass substrate. In some embodiments, other substrates may also be used, such as multilayer or gradient substrates.

[0087] In some embodiments, the circuit is formed on a substrate and may be certain types of circuits suitable for a particular application. In some embodiments, the circuit includes electronic components formed on the substrate, wherein one or more dielectric layers cover the electronic components. Metal layers may be formed between the overlying dielectric layers to route electrical signals between the electronic components. The electronic components may also be formed in one or more dielectric layers. For example, the circuit may include various N-type metal-oxide-semiconductor (NMOS) and / or P-type metal-oxide-semiconductor (PMOS) elements, such as transistors, capacitors, resistors, diodes, photodiodes, fuses, etc., interconnected to perform one or more functions. Functions may include memory structures, processing structures, sensors, amplifiers, power dividers, input / output circuits, etc. It should be understood that the above examples are for illustrative purposes only to further explain the application of some embodiments of this disclosure and are not intended to limit the embodiments of this disclosure.

[0088] The dielectric layer 210 may comprise a low-k dielectric material (a material with a dielectric constant lower than that of silicon dioxide), such as silicon oxynitride (SiON), phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorosilicate glass (FSG), SiOxCy, SiOxCyHz, spin-coated glass, spin-coated polymer, silicon-carbon material, the compounds described above, the composite materials described above, or other suitable materials. In some embodiments, the dielectric layer 210 may comprise an extremely low-k dielectric material, such as a dielectric material with a dielectric constant less than about 2.9 (e.g., a K value between about 2.5 and 2.6). In some embodiments, the method of forming the dielectric layer 210 may include performing chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or other suitable deposition methods.

[0089] See Figure 5An etching process is performed on dielectric layer 210 to form opening 220. Opening 220 exposes wafer 200. The etching process can be dry etching or wet etching. When using dry etching, the process gas may include carbon tetrafluoride (CF4), trifluoromethane (CHF3), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), bromine (Br2), hydrogen bromide (HBr), chlorine (Cl2), or any combination thereof. Rare gases such as nitrogen (N2), oxygen (O2), or argon (Ar) may be selectively used. When using wet etching, the etchant may include ammonium hydroxide:hydrogen peroxide:water (NH4OH:H2O2:H2O) (also known as APM), hydroxylamine (NH2OH), potassium hydroxide (KOH), nitric acid:ammonium fluoride:water (HNO3:NH4F:H2O), and / or other suitable etchants.

[0090] See Figure 6 In some implementations, it is possible to... Figure 5 The structure performs a degassing process to remove residues such as moisture (H2O), organic matter, or other residues from the surface of wafer 200. For example, the degassing process can remove moisture from the surface of wafer 200 by heating to a high temperature (e.g., 150 to 500 degrees Celsius).

[0091] After the degassing process, the native oxide on the surface of wafer 200 can be removed. In some embodiments, hydrogen ions can be provided to the surface of wafer 200, causing the hydrogen ions to react with the native oxide to remove it.

[0092] Next, a first barrier layer 230 is conformally formed in the opening 220 of the dielectric layer 210. In some embodiments, the first barrier layer 230 may be a metal layer comprising tantalum (Ta), cobalt (Co), titanium (Ti), or a nitride of the aforementioned metals (such as tantalum nitride (TaN) or titanium nitride (TiN)). In some embodiments, the method for forming the first barrier layer 230 may include physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable deposition methods.

[0093] Next, a second barrier layer 240 is conformally formed on the first barrier layer 230. The second barrier layer 240 may include tantalum (Ta), tantalum nitride (TaN), cobalt (Co), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), combinations thereof, or other suitable materials. In some embodiments, the method for forming the second barrier layer 240 may include physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable deposition methods. In some embodiments, the first barrier layer 230 and the second barrier layer 240 are formed using the same deposition method, such as physical vapor deposition. In some embodiments, the first barrier layer 230 and the second barrier layer 240 are made of different materials. For example, the first barrier layer 230 is made of tantalum nitride (TaN), while the second barrier layer 240 is made of tantalum (Ta).

[0094] See also Figure 1 , Figure 2 , Figure 3B as well as Figure 7 After the first barrier layer 230 and the second barrier layer 240 are formed, a seed layer 250 is conformally formed on the second barrier layer 240. In some embodiments disclosed herein, a seed layer 250 may be used. Figure 1 The processing apparatus 100 is used to form a seed layer 250 on wafer 200 (wafer W). Due to the configuration of the magnet module 140 (i.e., the angle θ2 between distances L1 and L2 is acute), the target material T can have a more uniform etch profile, thus improving the lifespan of the target material T. This improves the uniformity of the seed layer 250. In some embodiments, the seed layer 250 can be a metal layer comprising titanium (Ti), aluminum (Al), tantalum (Ta), copper (Cu), manganese (Mn), or other suitable metallic materials. In some embodiments, the seed layer 250 can be a metal alloy, such as a copper-manganese (Cu-Mn) alloy or other suitable alloy materials. In some embodiments, the method for forming the seed layer 250 may use... Figure 1 The processing equipment 100 is used to form the wafer W (wafer 200) by performing physical vapor deposition (PVD).

[0095] See Figure 8 After the seed layer 250 is formed, a conductive material is filled into the openings 220 of the dielectric layer 210 to form a fill layer 260. In some embodiments, the fill layer 260 comprises a metal, an elemental metal, a transition metal, or other suitable conductive material. For example, the fill layer may be copper.

[0096] See Figure 9After the fill layer 260 is formed, a planarization process is performed to remove the first barrier layer 230, the second barrier layer 240, the seed layer 250, and the fill layer 260 outside the opening 220. In some embodiments, the planarization process is a chemical-mechanical polishing (CMP) process. In some embodiments, the top surfaces of the dielectric layer 210, the first barrier layer 230, the second barrier layer 240, the seed layer 250, and the fill layer 260 are coplanar. In this way, an interconnect structure, conductive lines, or conductive through-structure comprising the dielectric layer 210, the first barrier layer 230, the second barrier layer 240, the seed layer 250, and the fill layer 260 can be formed on the wafer 200.

[0097] Figure 10 A schematic plan view of a cluster tool 300 according to some embodiments of this disclosure is shown. Figure 10 As shown, the processing station 300 includes a central transmission chamber 310, a processing chamber 320, a processing chamber 330, a processing chamber 340, and a processing chamber 350.

[0098] The central transport chamber 310 includes a central transport mechanism 312, which can handle wafers (e.g., Figure 1 wafer W or Figures 4 to 9 The physical transport of wafers (200) is described. A central transport chamber 310 is connected to processing chambers 320 to 350 and wafer load locks 360a and 360b. In this configuration, the central transport chamber 310 can transport at least one wafer between processing chambers 320 to 350 and wafer load locks 360a and 360b. In some embodiments, multiple wafers can be transported within the processing station 300.

[0099] Processing chambers 320 to 350 may be configured to perform manufacturing steps on a wafer. Wafer manufacturing steps may include deposition processes, etching processes, thermal processing, cleaning processes, planarization processes, and / or testing processes. Deposition processes may include physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), electrochemical deposition (ECD), atomic layer deposition (ALD), and / or other suitable deposition processes. Etching processes may include dry etching, wet etching, ion beam etching, lithography, ion plating, or other suitable etching processes. Thermal processing may include annealing, thermal oxidation, or other suitable thermal processing. Cleaning processes may include rinsing, plasma ashing, or other suitable cleaning processes. In some embodiments, processing chambers 320 to 350 may perform different processes separately, as will be described in detail in the following paragraphs.

[0100] In some embodiments, the processing chamber 320 may be configured to perform a wafer degassing process. In some embodiments, it may be... Figure 4 The process involves placing the semiconductor device into the processing chamber 320 and performing a degassing process to remove residues such as moisture (H2O), organic matter, or other residues from the surface of the wafer 200. For example, the degassing process can remove moisture from the wafer surface by heating to a high temperature (e.g., 150 to 500 degrees Celsius).

[0101] The processing chamber 330 can be configured to remove native oxide on the wafer to expose conductive features within the wafer. In some embodiments, it can be... Figure 6 The steps involve placing the semiconductor device into the processing chamber 330 and introducing hydrogen ions, which react with the native oxide to remove the native oxide.

[0102] The processing chamber 340 can be configured to form a barrier layer on the wafer. In some embodiments, it is possible to... Figure 6 The steps involve placing a semiconductor device into a processing chamber 340 and conformally forming a first barrier layer 230 and a second barrier layer 240 in an opening 220 on a wafer 200.

[0103] The processing chamber 350 can be configured to form a seed layer on the wafer. In some embodiments, it is possible to... Figure 7 The steps involve placing a semiconductor device into a processing chamber 350 and conformally forming a seed layer 250 over the first barrier layer 230 and the second barrier layer 240. In some embodiments, the processing chamber 350 may be considered as a processing device 100.

[0104] In some embodiments, processing station 300 may include an equipment front end module (EFEM) 370. A central transfer chamber 310 is connected to the EFEM 370 via load-locking chambers 360a and 360b. Wafers can be inserted into the wafer carrier transfer chamber load-locking chamber 360a before entering processing chambers 320 to 350. The wafer carrier transfer chamber 360a can generate a gaseous environment compatible with the EFEM 370 or the central transfer chamber 310 depending on the next position or step of the loaded wafer. For example, the gas content of the wafer carrier transfer chamber 360a can be altered by mechanisms such as adding purified gas, creating a vacuum, and / or other mechanisms for regulating the load-locking chamber 360a.

[0105] The front-end module 370 provides a sealed environment, allowing the wafer ( Figure 1 wafer W or Figures 4 to 9The wafer 200 can enter or exit the processing station 300 from a sealed environment. The device front-end module 370 includes a loading and locking mechanism 372 that performs the physical transfer of the wafer. The wafer can enter the processing station 300 through a loading port in a transport carrier 380. In some embodiments, the transport carrier 380 is configured to accommodate the wafer. The transport carrier 380 is sealed to provide a microenvironment for the wafer to prevent contamination.

[0106] In some implementations... Figure 5 The wafer (hereinafter referred to as the wafer) can first be placed on the transport carrier 380, and then enter the wafer carrier transfer chamber 360a from the front-end module 370. After the wafer carrier transfer chamber 360a is evacuated, the wafer enters the central transfer chamber 310, and is then fed into the processing chamber 320 by the central conveying mechanism 312 for a degassing process. Next, the wafer is conveyed by the central conveying mechanism 312 into the processing chamber 330 for a process to remove native oxides. Then, the wafer is conveyed by the central conveying mechanism 312 into the processing chamber 340 for a process to form the first barrier layer 230 and the second barrier layer 240. Afterward, the wafer is conveyed by the central conveying mechanism 312 into the processing chamber 350 to form the seed layer 250. Figure 1 The processing device 100 can be placed in the processing chamber 350, and the included angle θ2 of the magnet module can be adjusted within the processing chamber 350 (e.g., Figure 2 (As shown).

[0107] In summary, since the processing device of some embodiments of this disclosure has a magnet module, and the angle between the distance between the center of the carrier structure of the magnet module and the center of the placement disk and the distance between the center of the placement disk and the center of the magnet is an acute angle, the uniformity of target material erosion can be improved, thereby increasing the service life of the target material.

[0108] According to some embodiments of this disclosure, a method of forming a semiconductor device includes forming a dielectric layer on a wafer. The dielectric layer is etched to form an opening. A plasma deposition process is performed to form a seed layer in the opening, wherein performing the plasma deposition process includes placing the wafer under a magnet module and rotating the magnet module, the magnet module including a carrier structure, a placement disk, and a magnet, wherein the center of the carrier structure, the center of the placement disk, and the center of the magnet form a triangle. A fill layer is formed on the seed layer.

[0109] In some embodiments, the center of the placement disk has an outer angle in the triangle formed by the center of the carrier structure, the center of the placement disk, and the center of the magnet, and the outer angle is acute. In some embodiments, the outer angle ranges from 70 degrees to 80 degrees. In some embodiments, the seed layer comprises a copper-manganese alloy.

[0110] According to some embodiments of this disclosure, a method of forming a semiconductor device includes forming a dielectric layer on a wafer. The dielectric layer is etched to form an opening. A plasma deposition process is performed to form a seed layer in the opening, wherein performing the plasma deposition process includes rotating a magnet module on the wafer to control plasma for the plasma deposition process. The magnet module has a radius of rotation, and the target for the plasma deposition process has a diameter, the ratio of the radius of rotation to the diameter being about 0.013 to about 0.0378. A fill layer is formed on the seed layer.

[0111] In some embodiments, the magnet module includes a carrier structure, a placement disk placed on the carrier structure, and a magnet placed on the placement disk. In the top view, the center of the carrier structure, the center of the placement disk, and the center of the magnet are not located in a straight line. In some embodiments, the target material and the magnet are located on opposite sides of the carrier structure.

[0112] According to some embodiments disclosed herein, a method for performing a physical deposition process includes setting a containment baffle to define a chamber. A wafer pedestal stage is set in the chamber, the wafer pedestal stage being configured to support a wafer. A magnet module is set on the wafer pedestal stage, the magnet module including a carrier structure and a magnet. A target is set under the carrier structure, wherein the target includes a first region and a second region, the first region being closer to a center of the target than the second region. The distance between the center of the carrier structure and the center of the magnet is determined based on the variation in etching depth between the first and second regions of the target.

[0113] In some embodiments, the distance is from approximately 2.455 inches to approximately 6.689 inches. In some embodiments, the distance between the center of the carrier structure and the center of the magnet is determined such that the erosion depth of the first region of the target material is reduced and the erosion depth of the second region of the target material is increased.

[0114] Although the present disclosure has been described above with reference to embodiments, it is not intended to limit the present disclosure. Any person skilled in the art may make various modifications and alterations without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the scope defined in the appended claims.

Claims

1. A method for forming a semiconductor device, characterized in that, Include: A dielectric layer is formed on a wafer; The dielectric layer is etched to form an opening; Performing a plasma deposition process to form a sublayer in the opening, wherein performing the plasma deposition process includes placing the wafer under a magnet module and rotating the magnet module, the magnet module including a carrier structure, a placement disk and a magnet, wherein a center of the carrier structure, a center of the placement disk and a center of the magnet form a triangle, the triangle having an outer angle that is acute; and A filling layer is formed on the seed layer.

2. The method according to claim 1, characterized in that, The distance between the center of the carrier structure and the center of the placement disk is greater than the distance between the center of the placement disk and the center of the magnet.

3. The method according to claim 1, characterized in that, The outer angle ranges from 70 to 80 degrees.

4. The method according to claim 1, characterized in that, The seed layer contains a copper-manganese alloy.

5. A method for forming a semiconductor device, characterized in that, Include: A dielectric layer is formed on a wafer; The dielectric layer is etched to form an opening; Performing a plasma deposition process to form a sublayer in the opening, wherein performing the plasma deposition process includes rotating a magnetic module on the wafer to control the plasma of the plasma deposition process, the magnetic module having a radius of rotation, and a target of the plasma deposition process having a diameter, the ratio of the radius of rotation to the diameter being 0.013 to 0.038, the magnetic module including a carrier structure, a placement disk disposed on the carrier structure, and a magnet disposed on the placement disk, wherein the target and the magnet are respectively located on opposite sides of the carrier structure; and A filling layer is formed on the seed layer.

6. The method according to claim 5, characterized in that, In the top view, the center of the carrier structure, the center of the placement disk, and the center of the magnet are not in a straight line.

7. The method according to claim 5, characterized in that... The rotation radius of the magnet module is less than half the diameter of the target material.

8. A method for performing a physical deposition process, characterized in that, Include: Set up a enclosure to define a chamber; A wafer pedestal stage is disposed in the chamber, and the wafer pedestal stage is configured to support a wafer. A magnet module is disposed on the wafer pedestal, the magnet module comprising a carrier structure and a magnet; A target is disposed under the carrier structure, wherein the target includes a first region and a second region, the first region being closer to a center of the target than the second region; and Based on the variation in erosion depth between the first and second regions of the target material, a distance is determined between a center of the carrier structure and a center of the magnet, wherein the distance is between 2.455 inches and 6.689 inches.

9. The method according to claim 8, characterized in that... Both the carrier structure and the magnet have a circular outline when viewed from above.

10. The method according to claim 8, characterized in that, The distance between the center of the carrier structure and the center of the magnet is determined such that the erosion depth of the first region of the target material is reduced and the erosion depth of the second region of the target material is increased.

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