A semiconductor structure and a method of manufacturing the same

Abstract

Embodiments of the present disclosure disclose a semiconductor structure and a manufacturing method thereof. The manufacturing method comprises: providing a substrate; forming an etching stop layer covering a part of an upper surface of the substrate; forming a dielectric layer on the substrate, the dielectric layer covering the etching stop layer; etching the etching stop layer from a top of the dielectric layer to form a first via hole exposing the etching stop layer; forming a first conductive layer in the first via hole; etching the substrate from a lower surface opposite to the upper surface of the substrate to the etching stop layer to form a second via hole exposing the etching stop layer; removing the etching stop layer to form an opening; and forming a second conductive layer in the second via hole and the opening.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] Semiconductor structures, such as memory, typically include a substrate and a dielectric layer on the substrate, within which devices, metal layers, and other structures are usually formed. In practical manufacturing processes, through-silicon vias (TSVs) can be formed in semiconductor structures to achieve vertical interconnections between multiple semiconductor structures. A TSV can be formed by first creating a via that penetrates the dielectric layer and extends into the substrate using a one-step etching process, followed by the formation of a conductive layer within the via for conducting electrical signals.

[0003] However, due to the large depth-to-width ratio of vias, it is difficult to etch the dielectric layer and substrate to form vias. The via profile is poor and defects are easily formed on the inner wall of the via, which in turn affects the filling of the subsequent conductive layer and reduces the performance of silicon vias. Summary of the Invention

[0004] This disclosure provides a method for manufacturing a semiconductor structure, including:

[0005] Provide substrate;

[0006] An etch barrier layer is formed, the etch barrier layer covering a portion of the upper surface of the substrate;

[0007] A dielectric layer is formed on the substrate, the dielectric layer covering the etch barrier layer;

[0008] Etching is performed from the top of the dielectric layer toward the etch barrier layer to form a first via that exposes the etch barrier layer;

[0009] A first conductive layer is formed within the first through-hole;

[0010] The substrate is etched from the lower surface opposite to the upper surface of the substrate toward the etch barrier layer to form a second via exposing the etch barrier layer;

[0011] Remove the etching barrier layer to form an opening;

[0012] A second conductive layer is formed within the second through hole and the opening.

[0013] In some embodiments, the mask positions of the first through-hole and the second through-hole are aligned with reference to the position of the etch barrier layer.

[0014] In some embodiments, the etching rate of the etching barrier layer is less than the etching rate of the dielectric layer.

[0015] In some embodiments, an etch barrier layer is formed, including:

[0016] An etching barrier material layer is formed on the substrate;

[0017] A mask stack is formed on the etching barrier material layer;

[0018] A mask pattern is formed on the mask stack;

[0019] Using the mask pattern as a mask, the mask stack and the etching barrier material layer are etched to transfer the pattern of the mask pattern onto the etching barrier material layer, thereby forming the etching barrier layer.

[0020] In some embodiments, the method further includes, prior to forming the etch barrier layer:

[0021] A first insulating layer is formed, which covers the upper surface of the substrate, and the etching barrier layer is located on the first insulating layer.

[0022] In some embodiments, after forming the etch barrier layer, the method further includes:

[0023] A second insulating layer is formed on the substrate, the second insulating layer covering the sidewalls and the top surface of the etching barrier layer.

[0024] In some embodiments, after forming the etch barrier layer, the method further includes forming a device structure stacked on the upper surface of the substrate in the peripheral region of the etch barrier layer.

[0025] In some embodiments, a device structure is formed in the peripheral region of the etch barrier layer, including:

[0026] A device mask layer is formed on the upper surface of the substrate, and the device mask layer covers the etching barrier layer;

[0027] Using the patterned device mask layer as a mask, the substrate located in the area surrounding the etch barrier layer is etched to form isolation trenches in the substrate, the isolation trenches dividing the substrate into multiple active regions;

[0028] An isolation structure is formed within the isolation trench;

[0029] A device structure is formed on the isolation structure and the active region.

[0030] In some embodiments, a dielectric layer is formed on the substrate, the dielectric layer covering the etch barrier layer, including:

[0031] The dielectric layer is formed on the substrate, and the dielectric layer covers the device structure and the second insulating layer.

[0032] In some embodiments, etching is performed from the top of the dielectric layer toward the etch barrier layer to form a first via exposing the etch barrier layer, including:

[0033] The dielectric layer and the second insulating layer covered by the dielectric layer are etched from the top of the dielectric layer toward the etch barrier layer to form the first via, the first via exposing the etch barrier layer and the second insulating layer covering the sidewalls of the etch barrier layer.

[0034] In some embodiments, the method further includes:

[0035] In the same step of forming the etching barrier layer, a first alignment mark is formed on the substrate;

[0036] In the same step of forming the device structure, a second alignment mark is formed on the substrate;

[0037] The position of the mask for the first through hole is aligned with reference to the position of the first alignment mark and / or the second alignment mark.

[0038] In some embodiments, a first conductive layer is formed within the first through-hole, including:

[0039] A third insulating material layer is formed, which covers the sidewalls and bottom surface of the first through hole and the upper surface of the dielectric layer;

[0040] Remove the third insulating material layer covering the bottom surface of the first through hole;

[0041] A first conductive material layer is formed, which covers the third insulating material layer and fills the first through-hole;

[0042] A planarization process is performed on the first conductive material layer and the third insulating material layer to form the first conductive layer and the third insulating layer, respectively. The upper surfaces of the first conductive layer and the third insulating layer are flush with the upper surface of the dielectric layer. The third insulating layer covers the sidewall of the first through hole, and the first conductive layer covers the third insulating layer and fills the first through hole.

[0043] In some embodiments, the thickness of the third insulating layer is the same as the thickness of the second insulating layer.

[0044] In some embodiments, etching the substrate from a lower surface opposite to the upper surface of the substrate toward the etch barrier layer to form a second via exposing the etch barrier layer includes:

[0045] The substrate is etched from its lower surface, opposite the upper surface, toward the etch barrier layer to form the second via, the second via exposing the etch barrier layer and the second insulating layer covering the sidewalls of the etch barrier layer.

[0046] In some embodiments, the method further includes:

[0047] In the same step of forming the etching barrier layer, a first alignment mark is formed on the substrate;

[0048] In the same step of forming the device structure, a second alignment mark is formed on the substrate;

[0049] The position of the mask for the first through hole is aligned with reference to the position of the first alignment mark and / or the second alignment mark.

[0050] In some embodiments, removing the etch barrier layer to form an opening includes:

[0051] The etching barrier layer and the second insulating layer covering the sidewalls of the etching barrier layer are removed to form the opening, which exposes the first conductive layer.

[0052] In some embodiments, a second conductive layer is formed within the second through-hole and the opening, including:

[0053] A fourth insulating material layer is formed, which covers the sidewalls of the opening and the second through hole, the surface of the first conductive layer exposed by the opening, and the lower surface of the substrate;

[0054] Remove the fourth insulating material layer covering the surface of the first conductive layer;

[0055] A second conductive material layer is formed, which covers the fourth insulating material layer and fills the opening and the second through hole;

[0056] A planarization process is performed on the second conductive material layer and the fourth insulating material layer to form the second conductive layer and the fourth insulating layer, respectively. The fourth insulating layer covers the opening and the sidewall of the second through hole, and the second conductive layer covers the fourth insulating layer and fills the opening and the first through hole.

[0057] This disclosure also provides a semiconductor structure, which is fabricated using any of the methods described above.

[0058] The semiconductor structure and manufacturing method thereof provided in this disclosure include: providing a substrate; forming an etch stop layer covering a portion of the upper surface of the substrate; forming a dielectric layer on the substrate covering the etch stop layer; etching from the top of the dielectric layer toward the etch stop layer to form a first via exposing the etch stop layer; forming a first conductive layer within the first via; etching the substrate from a lower surface opposite to the upper surface of the substrate toward the etch stop layer to form a second via exposing the etch stop layer; removing the etch stop layer to form an opening; and forming a second conductive layer within the second via and the opening. This disclosure first forms a first via, then forms a second via. Thus, the via with a high aspect ratio is formed in at least two etching steps, reducing the process difficulty, effectively improving the contours of the first and second vias, avoiding or reducing defects in the vias, and improving the filling quality of the first and second conductive layers. At the same time, before forming the first via, this disclosure embodiment forms an etching barrier layer on the substrate to define the positions of the first and second vias to be formed subsequently, avoiding over-etching during the formation of the first and second vias, thereby affecting the morphology of the first and second vias.

[0059] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the accompanying drawings and claims. Attached Figure Description

[0060] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0061] Figure 1 A flowchart illustrating the semiconductor structure provided in the embodiments of this disclosure;

[0062] Figures 2 to 17 A process flow diagram of a method for manufacturing a semiconductor structure provided in an embodiment of this disclosure. Detailed Implementation

[0063] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0064] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0065] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0066] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0067] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0068] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0069] Semiconductor structures, such as memory, typically include a substrate and a dielectric layer on the substrate, within which devices, metal layers, and other structures are usually formed. In practical manufacturing processes, through-silicon vias (TSVs) can be formed in semiconductor structures to achieve vertical interconnections between multiple semiconductor structures. TSVs are formed by first using a one-step etching process to create a via that penetrates the dielectric layer and extends into the substrate, followed by forming a conductive layer within the via for conducting electrical signals.

[0070] However, due to the large depth-to-width ratio of vias, especially in dynamic random access memory (DRAM), which includes capacitor structures with large heights, the dielectric layer is also relatively tall. This makes it more difficult to etch the dielectric layer and substrate to form vias, resulting in poor via profiles and the formation of defects on the inner walls of the vias. This, in turn, affects the filling of subsequent conductive layers. For example, gaps can easily form between the conductive layer and the inner walls of the vias, reducing the performance of the silicon vias.

[0071] Based on this, the following technical solutions are proposed for embodiments of this disclosure:

[0072] This disclosure provides a method for manufacturing a semiconductor structure; please refer to the following for details. Figure 1 As shown in the figure, the method includes the following steps:

[0073] Step 101: Provide a substrate;

[0074] Step 102: Form an etch barrier layer that covers part of the upper surface of the substrate;

[0075] Step 103: Form a dielectric layer on the substrate, the dielectric layer covering the etch barrier layer;

[0076] Step 104: Etch from the top of the dielectric layer toward the etch barrier layer to form a first via that exposes the etch barrier layer;

[0077] Step 105: Form a first conductive layer inside the first through hole;

[0078] Step 106: Etch the substrate from the lower surface opposite the upper surface of the substrate toward the etch barrier layer to form a second via that exposes the etch barrier layer;

[0079] Step 107: Remove the etching barrier layer to form an opening;

[0080] Step 108: Form a second conductive layer inside the second through hole and opening.

[0081] This disclosure first forms a first via, then forms a second via. Thus, the via with a high aspect ratio is formed in at least two etching steps, reducing the process difficulty, effectively improving the contours of the first and second vias, avoiding or reducing defects in the vias, and improving the filling quality of the first and second conductive layers. At the same time, before forming the first via, this disclosure embodiment forms an etching barrier layer on the substrate to define the positions of the first and second vias to be formed subsequently, avoiding over-etching during the formation of the first and second vias, thereby affecting the morphology of the first and second vias.

[0082] The manufacturing method provided in this disclosure can be used to manufacture dynamic random access memory (DRAM). However, it is not limited to this; the manufacturing method can also be used to manufacture any semiconductor structure including through-silicon vias (TSVs).

[0083] The specific embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, the schematic diagrams may be partially enlarged without adhering to the usual proportions for ease of explanation, and the schematic diagrams are merely examples and should not be construed as limiting the scope of protection of this disclosure.

[0084] Figures 2 to 17 A process flow diagram of a method for manufacturing a semiconductor structure provided in this disclosure. The following is in conjunction with... Figures 2 to 17 The method for manufacturing the semiconductor structure provided in the embodiments of this disclosure will be described in further detail.

[0085] First, perform step 101, as follows: Figure 2 As shown, a substrate 10 is provided.

[0086] The substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, the substrate is a silicon substrate, which may be doped or undoped.

[0087] Next, proceed to step 102, as follows: Figures 3 to 4 As shown, an etch barrier layer 12 is formed, which covers a portion of the upper surface of the substrate 10.

[0088] Specifically, an etch barrier layer 12 is formed, including:

[0089] An etch barrier material layer 12' is formed on the substrate 10; a mask stack 26 is formed on the etch barrier material layer 12'; and a mask pattern 27 is formed on the mask stack 26.

[0090] Using the mask pattern 27 as a mask, the mask stack 26 and the etch barrier material layer 12′ are etched to transfer the pattern of the mask pattern 27 onto the etch barrier material layer 12′, forming the etch barrier layer 12.

[0091] The etch barrier layer 12′ can be formed using processes such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). In one embodiment, the material of the etch barrier layer 12 is a nitride, such as silicon nitride.

[0092] Subsequently, a first via will be formed on the substrate, and a second via will be formed inside the substrate. The mask positions of the first via and the second via will be aligned with reference to the position of the etch stop layer.

[0093] like Figure 3 As shown, in one embodiment, the mask stack 26 includes a first mask layer 261 and a second mask layer 262 located on the first mask layer 261. The first mask layer 261 includes, but is not limited to, a spin-coated hard mask layer, which may be an amorphous silicon layer or an amorphous carbon layer, etc. The material of the second mask layer 262 includes, but is not limited to, oxide nitride, for example, silicon oxynitride. The mask pattern 27 is located above the area where the etch barrier layer 12 is to be formed, and the material of the mask pattern 27 includes photoresist.

[0094] See you again Figure 3 Before forming the etch barrier layer 12, the method further includes forming a first insulating layer 11, which covers the upper surface of the substrate 10, and the etch barrier layer 12 is located on the first insulating layer 11. The first insulating layer 11 is used to protect the substrate 10 from damage or contamination in subsequent processes. The first insulating layer 11 can be formed using processes such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). The material of the first insulating layer 11 includes, but is not limited to, oxides, such as silicon oxide.

[0095] In practice, semiconductor structures are typically formed on a wafer. In one embodiment, the same step of forming the etch stop layer 12 further includes: forming a first alignment mark on the substrate 10. The first alignment mark may be formed on a wafer dicing track close to the etch stop layer 12. The first alignment mark and the etch stop layer 12 are located in the same layer. The position of the etch stop layer 12 can be calculated based on the position of the first alignment mark.

[0096] Next, proceed to step 103, as follows: Figure 6 As shown, a dielectric layer 16 is formed on the substrate 10, and the dielectric layer 16 covers the etch barrier layer 12.

[0097] like Figure 5 As shown, in one embodiment, before forming the dielectric layer 16, the method further includes forming a second insulating layer 13 on the substrate 10, the second insulating layer 13 covering the sidewalls and upper surface of the etch barrier layer 12. The second insulating layer 13 is used to protect the etch barrier layer 12 from damage or contamination in subsequent process steps. In some embodiments, the second insulating layer 13 also covers the first insulating layer 11. The second insulating layer 13 can be formed using processes such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). The material of the second insulating layer 13 includes, but is not limited to, oxides, such as silicon oxide.

[0098] See you again Figure 6 In one embodiment, after forming the etch barrier layer 12, the method further includes: forming a device structure 15 stacked on the upper surface of the substrate 10 in the peripheral region of the etch barrier layer 12. In a specific embodiment, forming the device structure 15 in the peripheral region of the etch barrier layer 12 includes: forming a device mask layer (not shown) on the upper surface of the substrate 10, the device mask layer (not shown) covering the etch barrier layer 12; using the patterned device mask layer (not shown) as a mask, etching the substrate 10 located in the peripheral region of the etch barrier layer 12 to form an isolation trench S in the substrate 10, the isolation trench S dividing the substrate 10 into a plurality of active regions AA; forming an isolation structure 14 in the isolation trench S; and forming the device structure 15 on the isolation structure 14 and the active regions AA. More specifically, the device structure 15 is formed after forming the second insulating layer 13, so that during the formation of the device structure 15, the second insulating layer 13 can protect the etch barrier layer 12 from damage or contamination.

[0099] In one embodiment, the device structure 15 may include: a word line structure that runs through the isolation structure 14 and the active region AA, a transistor structure formed in the active region AA, a bit line structure and a capacitor structure located above the isolation structure 14 and the active region AA, and other device structures, and a chip that realizes the access function of dynamic random access memory through the various device structures and the interconnection between the device structures.

[0100] In one embodiment, the substrate 10 is divided into a cell region 201 and a peripheral region 202 adjacent to the cell region 201 according to the function of the device structure 15. The cell region 201 includes memory cell devices, and the peripheral region 202 includes controllers for controlling the memory cells. An etch stop layer 12 is located in the peripheral region 202 to prevent subsequently formed through-silicon vias from occupying the area of ​​the cell region 201. In a specific embodiment, the semiconductor structure is a memory, and the device structure 15 includes a memory array 152 located in the cell region 201 and peripheral circuits 151 located in the peripheral region 202. The peripheral circuits 151 are disposed adjacent to the etch stop layer 12. In a more specific embodiment, the semiconductor structure is a dynamic random access memory (DRAM), and the memory array 152 includes word lines, bit lines, conductive plugs, storage capacitors, and other structures. However, it is not limited to these; the semiconductor structure can also be a logic chip, etc.

[0101] During the formation of device structure 15, for example, the position of the mask in the exposure process is aligned with the position of the first alignment mark. In one embodiment, a second alignment mark is formed on substrate 10 in the same step as forming device structure 15. Specifically, the second alignment mark can be formed in peripheral region 202, and the second alignment mark is located in the same layer as device structure 15.

[0102] See also Figure 6 In one embodiment, a dielectric layer 16 is formed on a substrate 10, and the dielectric layer 16 covers an etch barrier layer 12, including: forming a dielectric layer 16 on the substrate 10, the dielectric layer 16 covering a device structure 15 and a second insulating layer 13. It should be noted that the dielectric layer 16 is not a single-layer structure, but is formed from multiple layers of insulating materials in multiple process steps. The dielectric layer 16 can be formed using processes such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). The material of the dielectric layer 16 includes, but is not limited to, oxides, such as silicon oxide.

[0103] See also Figure 6 In one embodiment, the method further includes: forming metal layers M1, M2, M3 and conductive plugs V1, V2, V3 on the substrate 10, wherein the conductive plugs V1, V2, V3 and the metal layers M1, M2, M3 are alternately arranged in the dielectric layer 16 in a direction perpendicular to the upper surface of the substrate 10.

[0104] In actual operation, the conductive plugs V1, V2, V3 and the metal layers M1, M2, M3 can be formed as follows: First, a dielectric layer 16 covering the device structure 15 and the second insulating layer 13 is formed on the substrate 10; then, a plug hole is formed in the dielectric layer 16, and a conductive material is formed in the plug hole to form a conductive plug V1, which is electrically connected to the device structure 15; next, a dielectric layer 16 covering the conductive plug V1 is formed, the dielectric layer 16 is patterned, and a metal layer M1 connected to the conductive plug V1 is formed in the patterned dielectric layer 16; next, the conductive plugs V2, V3 and the metal layers M2, M3 are sequentially formed, and the formation methods of the conductive plugs V2 and V3 are the same as those of the conductive plug V1, and the formation methods of the metal layers M2 and M3 are the same as those of the metal layer M1. The conductive plugs V1, V2, V3 and the metal layers M1, M2, M3 are made of one or more of the following materials: tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, and metal alloys.

[0105] It should be noted that the number of conductive plugs located within the dielectric layer 16 is not limited to... Figure 6 As shown, the number of conductive plugs can be more or less, for example, 1 layer, 2 layers, or 4 layers; the number of metal layers located within the dielectric layer 16 is not limited to... Figure 6 As shown, the number of metal layers can be more or less, such as 1 layer, 2 layers, or 4 layers.

[0106] Next, proceed to step 104, as follows: Figures 7 to 8 As shown, etching is performed from the top of the dielectric layer 16 toward the etch barrier layer 12 to form a first via T1 that exposes the etch barrier layer 12.

[0107] Specifically, etching from the top of the dielectric layer 16 toward the etch barrier layer 12 to form a first via T1 exposing the etch barrier layer 12 includes: etching the dielectric layer 16 and the second insulating layer 13 covered by the dielectric layer 16 toward the etch barrier layer 12 to form the first via T1, which exposes the etch barrier layer 12 and the second insulating layer 13 covering the sidewalls of the etch barrier layer 12. However, this is not a limitation; the first via T1 may also expose only the etch barrier layer 12. It is understood that, compared to the embodiment where the first via T1 exposes both the etch barrier layer 12 and the second insulating layer 13 located on the sidewalls of the etch barrier layer 12, in the embodiment where the first via T1 exposes only the etch barrier layer 12, an etch barrier layer 12 with a larger area can be pre-formed to ensure that the size of the first via T1 remains unchanged. In some embodiments, the etching rate of the etching barrier layer 12 is less than the etching rate of the dielectric layer 16, so as to reduce the etching of the etching barrier layer 12 during the etching of the dielectric layer 16, avoid over-etching and damage to the morphology of the first via T1, and ensure that the inner wall of the first via T1 is smooth and uniform.

[0108] The position of the mask for the first through hole is aligned with reference to the positions of the first alignment mark and / or the second alignment mark.

[0109] In this embodiment of the disclosure, the etch barrier layer 12 pre-positions the location of the through-silicon via, and the position of the etch barrier layer 12 can be calculated based on the position of the first alignment mark or the second alignment mark. See again Figures 7 to 8 More specifically, forming the first via T1 further includes: forming a first via mask layer 28 on the dielectric layer 16; patterning the first via mask layer 28 using a first alignment mark as an alignment base point, the patterned first via mask layer 28 forming a mask with a first opening 281, that is, the mask of the first via T1 includes the first opening 281, the position of the first opening 281 being aligned with the position of the etch stop layer 12, and in specific implementation, the position of the first opening 281 is defined in the first via mask layer 28 by referring to the position of the first alignment mark and the distance between it and the etch stop layer 12. The first opening 281 exposes the dielectric layer 16, and the orthographic projection of the etch stop layer 12 on the plane of the substrate 10 falls within the orthographic projection of the first opening 281 on the plane of the substrate 10; etching the dielectric layer 16 from the first opening 281 to form the first via T1.

[0110] However, this is not the only method of alignment. In this embodiment, a second alignment mark can also be used for aligning the first via mask. Specifically, forming the first via T1 further includes: forming a first via mask layer 28 on the dielectric layer 16; patterning the first via mask layer 28 using the second alignment mark as an alignment reference point; forming a first opening 281 on the first via mask layer 28; the first opening 281 exposing the dielectric layer 16; the orthographic projection of the etching barrier layer 12 on the plane of the substrate 10 falling within the orthographic projection of the first opening 281 on the plane of the substrate 10; and etching the dielectric layer 16 and the second insulating layer 13 from the first opening 281 to form the first via T1.

[0111] In this embodiment, the first alignment mark and the second alignment mark can also be used simultaneously for mask alignment of the first through hole.

[0112] Next, proceed to step 105, as follows: Figures 9 to 11 As shown, a first conductive layer 18 is formed inside the first through hole T1.

[0113] Specifically, a first conductive layer 18 is formed within the first through-hole T1, including:

[0114] A third insulating material layer 17′ is formed, which covers the sidewalls and bottom surface of the first through hole T1 and the upper surface of the dielectric layer 16.

[0115] Remove the third insulating material layer 17' covering the bottom surface of the first through hole T1; form a first conductive material layer 18', which covers the third insulating layer 17' and fills the first through hole T1;

[0116] A planarization process is performed on the first conductive material layer 18′ and the third insulating material layer 17′ to form the first conductive layer 18 and the third insulating layer 17, respectively. The upper surfaces of the first conductive layer 18 and the third insulating layer 17 are flush with the upper surface of the dielectric layer 16. The third insulating layer 17 covers the sidewall of the first through hole T1, and the first conductive layer 18 covers the third insulating layer 17 and fills the first through hole T1.

[0117] In one embodiment, the thickness of the third insulating layer 17 is the same as the thickness of the second insulating layer 13. Using the same thickness for the second insulating layer 13 and the third insulating layer 17 ensures a smooth sidewall morphology for the first via T1, facilitating the adhesion of the first conductive layer 18 to the sidewalls to form a dense structure and improving the conductivity of the first conductive layer 18. The third insulating material layer 17′ can be formed using processes such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). The material of the third insulating material layer 17′ includes, but is not limited to, oxides, such as silicon oxide.

[0118] The first conductive material layer 18′ can be formed using processes such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, and sputtering. The material of the first conductive material layer 18′ includes tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, metal alloys, or any combination thereof, such as a combination of copper and titanium nitride. Titanium nitride is disposed between copper and the third insulating layer 17 to prevent copper from diffusing into the dielectric layer 16.

[0119] Next, proceed to step 106, as follows: Figures 12 to 13 As shown, the substrate 10 is etched from the lower surface opposite to the upper surface of the substrate 10 toward the etch barrier layer 12 to form a second via T2 that exposes the etch barrier layer 12.

[0120] Specifically, etching the substrate 10 from its lower surface opposite to the upper surface toward the etch barrier layer 12 to form a second via T2 exposing the etch barrier layer 12 includes: etching the substrate 10 from its lower surface opposite to the upper surface toward the etch barrier layer 12 to form the second via T2, wherein the second via T2 exposes the etch barrier layer 12 and a second insulating layer 13 covering the sidewalls of the etch barrier layer 12. However, this is not a limitation; if the first via T1 only exposes the etch barrier layer 12, the second via T2 may also only expose the etch barrier layer 12 to ensure that the cross-sectional dimensions of the first via T1 and the second via T2 are the same. In some embodiments, forming the second via T2 further includes etching the first insulating layer 11 located on the upper surface of the substrate 10.

[0121] The position of the mask for the second through hole is aligned with reference to the positions of the first alignment mark and / or the second alignment mark.

[0122] See you again Figures 12 to 13Specifically, forming the second via T2 further includes: forming a second via mask layer 29 on the lower surface of the substrate 10; patterning the second via mask layer 29 using a first alignment mark as an alignment base point to form a mask with a second opening 291, i.e., the mask of the second via T2 includes the second opening 291, the position of the second opening 291 being aligned with the position of the etch stop layer 12. In specific implementation, the position of the second opening 291 is defined in the second via mask layer 29 by referring to the position of the first alignment mark and the distance between it and the etch stop layer 12. The second opening 291 exposes the lower surface of the substrate 10, and the orthographic projection of the etch stop layer 12 on the plane of the substrate 10 falls within the orthographic projection of the second opening 291 on the plane of the substrate 10; etching the substrate 10 from the second opening 291 to form the second via T2. In a more specific embodiment, the semiconductor structure is inverted before etching from the lower surface opposite the upper surface of the substrate 10 to the etch barrier layer 12, and then the substrate 10 and the first insulating layer 11 are etched to form the second via T2.

[0123] However, this is not the only possibility; the position of the second via T2 can also be determined based on the position of the second alignment mark. Specifically, forming the second via T2 further includes: forming a second via mask layer 29 on the lower surface of the substrate 10; patterning the second via mask layer 29 using the second alignment mark as an alignment base point; forming a second opening 291 on the second via mask layer 29; the second opening 291 exposing the lower surface of the substrate 10; the orthographic projection of the etching barrier layer 12 on the plane of the substrate 10 falling within the orthographic projection of the second opening 291 on the plane of the substrate 10; and etching the substrate 10 from the second opening 291 to form the second via T2.

[0124] In this embodiment, the first alignment mark and the second alignment mark can also be used simultaneously for mask alignment of the second through hole.

[0125] A second conductive layer 25 will subsequently be formed within the second via T2 (see...). Figure 17 Second via T2 and second conductive layer 25 (see...) Figure 17 Both are formed during the packaging stage of the semiconductor structure. Compared to the first via T1 located in the dielectric layer 16 and the first conductive layer 18 located in the first via T1, the second via T2 located in the substrate 10 and the second conductive layer 25 located in the second via T2 (see...) Figure 17 This is particularly important, as it plays a crucial role in the quality of signal transmission. In this embodiment, after forming the active region AA, the device structure 15, and the metal layers M1, M2, and M3 on the device structure 15, a second via T2 and a second conductive layer 25 are formed within the substrate 10 (see...). Figure 17 This avoids the need for multiple processes previously involved in the second via T2 and the second conductive layer 25 (see...). Figure 17The adverse effects of ) were reduced, and the second via T2 and the second conductive layer 25 (see) were improved. Figure 17 This improves the quality of semiconductor structures and enhances their performance.

[0126] Next, proceed to step 107, as follows: Figure 14 As shown, the etching barrier layer 12 is removed to form an opening 24.

[0127] Specifically, removing the etch barrier layer 12 to form the opening 24 includes removing the etch barrier layer 12 and the second insulating layer 13 covering the sidewalls of the etch barrier layer 12 to form the opening 24, which exposes the first conductive layer 18. In some embodiments, the opening 24 also exposes a third insulating layer 17.

[0128] Next, proceed to step 108, as follows: Figures 15 to 17 As shown, a second conductive layer 25 is formed in the second through hole T2 and the opening 24.

[0129] Specifically, a second conductive layer 25 is formed within the second through-hole T2 and the opening 24, including:

[0130] A fourth insulating material layer 23' is formed, which covers the sidewalls of the opening 24 and the second through hole T2, the surface of the first conductive layer 18 exposed by the opening 24, and the lower surface of the substrate 10.

[0131] Remove the fourth insulating material layer 23' covering the surface of the first conductive layer 18; form a second conductive material layer 25', which covers the fourth insulating layer 23' and fills the opening 24 and the second through hole T2;

[0132] A planarization process is performed on the second conductive material layer 25′ and the fourth insulating material layer 23′ to form the second conductive layer 25 and the fourth insulating layer 23, respectively. The fourth insulating layer 23 covers the sidewall of the opening 24 and the second through hole T2, and the second conductive layer 25 covers the fourth insulating layer 23 and fills the opening 24 and the second through hole T2.

[0133] In one embodiment, the thickness of the fourth insulating layer 23 is the same as the thickness of the third insulating layer 17. Using the same thickness for the fourth insulating layer 23 and the third insulating layer 17 ensures a smooth junction between them, facilitating the bonding of the first conductive layer 18 and the second conductive layer 25 and improving the overall conductivity of the first conductive layer 18 and the second conductive layer 25. The fourth insulating material layer 23′ can be formed using processes such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). In a specific embodiment, the material of the fourth insulating material layer 23′ can be the same as the material of the third insulating layer 17, for example, silicon oxide.

[0134] The second conductive material layer 25′ can be formed using processes such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, and sputtering. The material of the second conductive material layer 25′ includes tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, metal alloys, or any combination thereof. In one specific embodiment, the material of the second conductive material layer 25′ is the same as that of the first conductive layer 18, for example, copper and titanium nitride.

[0135] The first conductive layer 18 and the second conductive layer 25 serve as signal transmission layers. In this embodiment, a first via T1 is first formed, followed by a second via T2. Thus, the via with a high aspect ratio is formed in at least two etching steps, reducing the process difficulty, effectively improving the contours of the first via T1 and the second via T2, avoiding or reducing defects in the via, and improving the filling quality of the first conductive layer 18 and the second conductive layer 25. Meanwhile, the second conductive layer 25, which is a major component located in the substrate 10, plays a crucial role in signal transmission. In this embodiment, after forming the active region AA, the device structure 15, and the metal layers M1, M2, and M3 on the device structure 15, the second via T2 and the second conductive layer 25 are formed in the substrate 10. That is, in this embodiment, the second via T2 and the second conductive layer 25 are formed in the packaging section of the semiconductor structure, avoiding the influence of multiple processes on the second via T2 and the second conductive layer 25, and improving the quality of the second via T2 and the second conductive layer 25. Furthermore, in this embodiment of the present disclosure, before forming the first via T1, an etching barrier layer 12 is formed on the substrate 10 to define the positions of the first via T1 and the second via T2 to be formed subsequently, ensuring that the first via T1 and the second via T2 have smooth sidewalls, and avoiding over-etching during the formation of the first via T1 and the second via T2, thereby affecting the morphology of the first via T1 and the second via T2.

[0136] It should be noted that those skilled in the art can make possible changes to the order of the above steps without departing from the scope of protection of this disclosure.

[0137] This disclosure also provides a semiconductor structure, which is fabricated using any of the methods described above.

[0138] It should be noted that the above description is only an optional embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: Provide substrate; An etch barrier layer is formed, the etch barrier layer covering a portion of the upper surface of the substrate; A dielectric layer is formed on the substrate, the dielectric layer covering the etch barrier layer; Etching is performed from the top of the dielectric layer toward the etch barrier layer to form a first via that exposes the etch barrier layer; A first conductive layer is formed within the first through-hole; The substrate is etched from the lower surface opposite to the upper surface of the substrate toward the etch barrier layer to form a second via exposing the etch barrier layer; Remove the etching barrier layer to form an opening; A second conductive layer is formed within the second through hole and the opening; The method further includes, after forming the etch barrier layer: A second insulating layer is formed on the substrate, the second insulating layer covering the sidewalls and the top surface of the etch barrier layer; The formation of a first conductive layer within the first through-hole includes: A third insulating material layer is formed, which covers the sidewalls and bottom surface of the first through hole and the upper surface of the dielectric layer; Remove the third insulating material layer covering the bottom surface of the first through hole; A first conductive material layer is formed, which covers the third insulating material layer and fills the first through-hole; A planarization process is performed on the first conductive material layer and the third insulating material layer to form the first conductive layer and the third insulating layer respectively. The upper surfaces of the first conductive layer and the third insulating layer are flush with the upper surface of the dielectric layer. The third insulating layer covers the sidewall of the first through hole, and the first conductive layer covers the third insulating layer and fills the first through hole. The thickness of the third insulating layer is the same as the thickness of the second insulating layer.

2. The manufacturing method according to claim 1, characterized in that, The mask positions of the first through hole and the second through hole are aligned with reference to the position of the etching barrier layer.

3. The manufacturing method according to claim 1, characterized in that, The etching rate of the etching barrier layer is less than that of the dielectric layer.

4. The manufacturing method according to claim 1, characterized in that, Forming an etch barrier layer, including: An etching barrier material layer is formed on the substrate; A mask stack is formed on the etching barrier material layer; A mask pattern is formed on the mask stack; Using the mask pattern as a mask, the mask stack and the etching barrier material layer are etched to transfer the pattern of the mask pattern onto the etching barrier material layer, thereby forming the etching barrier layer.

5. The manufacturing method according to claim 1, characterized in that, Before forming the etch barrier layer, the method further includes: A first insulating layer is formed, which covers the upper surface of the substrate, and the etching barrier layer is located on the first insulating layer.

6. The manufacturing method according to claim 1, characterized in that, After forming the etch barrier layer, the method further includes forming a device structure stacked on the upper surface of the substrate in the peripheral region of the etch barrier layer.

7. The manufacturing method according to claim 6, characterized in that, A device structure is formed in the peripheral region of the etch barrier layer, including: A device mask layer is formed on the upper surface of the substrate, and the device mask layer covers the etching barrier layer; Using the patterned device mask layer as a mask, the substrate located in the area surrounding the etch barrier layer is etched to form isolation trenches in the substrate, the isolation trenches dividing the substrate into multiple active regions; An isolation structure is formed within the isolation trench; A device structure is formed on the isolation structure and the active region.

8. The manufacturing method according to claim 6, characterized in that, A dielectric layer is formed on the substrate, the dielectric layer covering the etch barrier layer, comprising: The dielectric layer is formed on the substrate, and the dielectric layer covers the device structure and the second insulating layer.

9. The manufacturing method according to claim 8, characterized in that, Etching from the top of the dielectric layer toward the etch barrier layer to form a first via exposing the etch barrier layer includes: The dielectric layer and the second insulating layer covered by the dielectric layer are etched from the top of the dielectric layer toward the etch barrier layer to form the first via, the first via exposing the etch barrier layer and the second insulating layer covering the sidewalls of the etch barrier layer.

10. The manufacturing method according to claim 9, characterized in that, The method further includes: In the same step of forming the etching barrier layer, a first alignment mark is formed on the substrate; In the same step of forming the device structure, a second alignment mark is formed on the substrate; The position of the mask for the first through hole is aligned with reference to the position of the first alignment mark and / or the second alignment mark.

11. The manufacturing method according to claim 6, characterized in that, Etching the substrate from the lower surface opposite the upper surface to the etch barrier layer to form a second via exposing the etch barrier layer includes: The substrate is etched from its lower surface, opposite the upper surface, toward the etch barrier layer to form the second via, the second via exposing the etch barrier layer and the second insulating layer covering the sidewalls of the etch barrier layer.

12. The manufacturing method according to claim 11, characterized in that, The method further includes: In the same step of forming the etching barrier layer, a first alignment mark is formed on the substrate; In the same step of forming the device structure, a second alignment mark is formed on the substrate; The position of the mask for the first through hole is aligned with reference to the position of the first alignment mark and / or the second alignment mark.

13. The manufacturing method according to claim 11, characterized in that, Removing the etch barrier layer to form an opening includes: The etching barrier layer and the second insulating layer covering the sidewalls of the etching barrier layer are removed to form the opening, which exposes the first conductive layer.

14. The manufacturing method according to claim 13, characterized in that, A second conductive layer is formed within the second through-hole and the opening, including: A fourth insulating material layer is formed, which covers the sidewalls of the opening and the second through hole, the surface of the first conductive layer exposed by the opening, and the lower surface of the substrate; Remove the fourth insulating material layer covering the surface of the first conductive layer; A second conductive material layer is formed, which covers the fourth insulating material layer and fills the opening and the second through hole; A planarization process is performed on the second conductive material layer and the fourth insulating material layer to form the second conductive layer and the fourth insulating layer, respectively. The fourth insulating layer covers the opening and the sidewall of the second through hole, and the second conductive layer covers the fourth insulating layer and fills the opening and the first through hole.

15. A semiconductor structure, characterized in that, The semiconductor structure is manufactured using the method described in any one of claims 1 to 14.

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