Semiconductor device and method of forming the same

Abstract

A semiconductor device and a method of forming the same, the method of forming the semiconductor device includes forming a sacrificial layer on a first nanostructure stack and an isolation region. A dummy gate structure is formed over the first nanostructure stack and a first portion of the sacrificial layer. A second portion of the sacrificial layer is removed to expose a sidewall of the first nanostructure stack adjacent to the dummy gate structure. A spacer layer is formed on the dummy gate structure. A first portion of the spacer layer directly contacts the first nanostructure stack.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for forming a semiconductor device. Background Technology

[0002] Semiconductor devices are used in a variety of electronic devices, such as personal computers, mobile phones, digital cameras, and other electronic equipment. A typical semiconductor device process involves sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate, and then using photolithography to pattern the various material layers to generate the circuit elements on them.

[0003] To integrate more components into a specific area, the semiconductor industry continues to reduce the minimum feature size, thereby improving the integration density of various electronic components (such as transistors, diodes, resistors, and capacitors). However, as the minimum feature size is reduced, new problems need to be addressed. Summary of the Invention

[0004] A method for forming a semiconductor device disclosed herein includes: forming a sacrificial layer on a first nanostructure stack and an isolation region, wherein the first nanostructure stack comprises alternating plurality of first nanostructures and plurality of second nanostructures, the first nanostructures being a first semiconductor material and the second nanostructures being a second semiconductor material; forming a dummy gate structure on a first portion of the first nanostructure stack and the sacrificial layer; removing a second portion of the sacrificial layer to expose a sidewall of the first nanostructure stack adjacent to the dummy gate structure; forming a spacer wall layer on the dummy gate structure that is in solid contact with the sidewall of the first nanostructure stack; forming a first source / drain recess through the first nanostructure stack, wherein a plurality of sidewalls of the first and second nanostructures are exposed in the first source / drain recess; and forming a first source / drain region in the first source / drain recess that is in solid contact with a first portion of the spacer wall layer.

[0005] A method for forming a semiconductor device disclosed herein includes: forming a multilayer stack on a semiconductor substrate; patterning the multilayer stack to form a nanostructure stack, wherein the nanostructure stack includes alternating plurality of first nanostructures and plurality of second nanostructures, the first nanostructures being a first semiconductor material and the second nanostructures being a second semiconductor material; forming a sacrificial layer along a plurality of sidewalls of the nanostructure stack; forming a dummy gate structure on the nanostructure stack and the sacrificial layer; removing a portion of the sacrificial layer to form a first recess adjacent to the nanostructure stack, the remaining portion of the sacrificial layer being enveloped in the dummy gate structure; forming a spacer layer on the dummy gate structure, wherein a first portion of the spacer layer fills the first recess; forming a second recess adjacent to the dummy gate structure in the multilayer stack; forming a source / drain region in the second recess that is in solid contact with the first portion of the spacer layer; removing the dummy gate structure to form a third recess; removing one of the first nanostructures and the second nanostructures and at least a portion of the remaining portion of the sacrificial layer; and forming a gate structure in the third recess.

[0006] A semiconductor device disclosed herein includes: a semiconductor substrate; a first channel region on the semiconductor substrate, wherein the first channel region includes a first nanostructure stack; a first gate stack on the first channel region, wherein the first gate stack includes a first gate electrode and a first gate dielectric; a first source / drain region adjacent to the first channel region; a first inner spacer wall between a first sidewall of the first source / drain region and the first gate dielectric; and a first spacer wall substantially in contact with a second sidewall of the first source / drain region, wherein the first spacer wall covers the sidewall of the first inner spacer wall. Attached Figure Description

[0007] The following detailed explanation, accompanied by accompanying illustrations, will provide the best understanding of the currently revealed aspects. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily enlarged or reduced. Figure 1 According to some embodiments, a nano-structured field-effect transistor (nano-FET) is illustrated from a three-dimensional perspective. Figures 2A to 31E According to some embodiments, the intermediate processes for fabricating nanostructured field-effect transistors are illustrated in cross-section and planar views; Figure 32A , Figure 32B , Figure 32C , Figure 32D and Figure 32E According to some embodiments, a nanostructured field-effect transistor is illustrated in cross-section and planar views.

[0008] [Symbol Explanation]

[0009] 20: Divider

[0010] 50: Substrate

[0011] 50N: n-type region

[0012] 50P: p-type region

[0013] 51A: First semiconductor layer

[0014] 51B: First semiconductor layer

[0015] 51C: First semiconductor layer

[0016] 52A: First Nanostructure

[0017] 52B: First Nanostructure

[0018] 52C: First Nanostructure

[0019] 53A: Second semiconductor layer

[0020] 53B: Second semiconductor layer

[0021] 53C: Second semiconductor layer

[0022] 54A: Second Nanostructure

[0023] 54B: Second nanostructure

[0024] 54C: Second Nanostructure

[0025] 55: Nanostructures

[0026] 58: Light Mask

[0027] 58A: First photomask layer

[0028] 58B: Second photomask layer

[0029] 64: Multi-layer stacked body

[0030] 66: Fin

[0031] 68: Shallow trench isolation area

[0032] 70: Virtual dielectric layer

[0033] 71: Virtual gate dielectric

[0034] 72: Virtual Gate Layer

[0035] 74: Photomask layer

[0036] 76: Virtual Gate

[0037] 78: Light Mask

[0038] 80: First interstitial wall layer

[0039] 81: First spacer wall

[0040] 82: Second interstitial wall layer

[0041] 83: Second spacer wall

[0042] 86: Second depression

[0043] 88: Sidewall concavity

[0044] 89: Internal interstitial wall layer

[0045] 90: First inner spacer wall

[0046] 91: Epitaxial region

[0047] 92: Epitaxial source / drain region

[0048] 92A: First semiconductor material layer

[0049] 92B: Second semiconductor material layer

[0050] 92C: Third semiconductor material layer

[0051] 94: Contact Etching Stop Layer

[0052] 96: First interlayer dielectric

[0053] 98: Third depression

[0054] 100: Gate dielectric layer

[0055] 102: Gate electrode

[0056] 102N: Gate electrode

[0057] 102P: Gate electrode

[0058] 104: Gate photomask

[0059] 106: Second interlayer dielectric

[0060] 108: Third depression

[0061] 112: Source / Drain Contact

[0062] 114: Gate contact

[0063] 120: Sacrifice Layer

[0064] 121: First depression

[0065] 124: Padding

[0066] 126: Filling material

[0067] 128: Upper dielectric layer

[0068] 130: Insulating fins

[0069] A-A' : Section A-A'

[0070] B-B': Section B-B'

[0071] C-C': Cross section C-C'

[0072] D-D': Section D-D'

[0073] H1: Height

[0074] H2: Height

[0075] T1: Thickness

[0076] W1: Width Detailed Implementation

[0077] The following disclosure provides many different embodiments or examples to achieve different features of this disclosure. Specific examples of components and combinations are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, when a first feature is described below on or above a second feature, it may include embodiments where the first and second features are in direct contact, or it may include embodiments where another feature is formed between the first and second features, such that the first and second features are not in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples; such repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments and / or configurations discussed.

[0078] Furthermore, spatially related terms such as "below" and "above," which may be used here for simplification, describe the relationship between one element or feature and another element(s) or feature(s). These spatially related terms not only encompass the orientation indicated in the figure but are also intended to include different orientations of the device during use and operation, where the device may be positioned differently (rotated 90 degrees or otherwise), and the spatially related descriptions can be interpreted accordingly.

[0079] In some embodiments, a sacrificial layer is used. For example, in some embodiments, the sacrificial layer is formed along several sidewalls of a nanostructure stack, after which an insulating structure can be formed between adjacent nanostructure stacks. The sacrificial layer material can be chosen such as a semiconductor material, allowing the sacrificial layer to be removed or replaced with a dielectric material when forming the gate spacer. The gate spacer material provides better insulation between the source / drain regions and the gate electrode, thus improving performance.

[0080] Regarding a chip containing several nanostructured field-effect transistors, which are described in specific text below in the embodiments, however, the embodiments may be applied to chips containing different types of transistors (e.g., fin field-effect transistors (FinFETs), or planar transistors, etc.) to replace nanostructured field-effect transistors or combinations thereof.

[0081] Figure 1 Examples of several nanostructured field-effect transistors (e.g., nanowire FETs, nanosheet FETs, etc.) are illustrated in a three-dimensional view according to some embodiments. These nanostructured FETs comprise several nanostructures 55 (e.g., nanosheets, nanowires, etc.) positioned above several fins 66 on a substrate 50 (e.g., a semiconductor substrate). The nanostructures 55 serve as channel regions of the nanostructured FETs and may comprise p-type nanostructures, n-type nanostructures, or combinations thereof. Several shallow trench isolation (STI) regions 68 are positioned between adjacent fins 66 and may protrude above and between adjacent shallow trench isolation regions 68. Although the shallow trench isolation regions 68 are distinguished from the substrate 50 in the description or illustration, the term "substrate" may refer solely to the semiconductor substrate or a combination of the semiconductor substrate and these shallow trench isolation regions as used herein. In addition, although the bottom portion of fin 66 is shown in the illustration as a single and continuous material with substrate 50, the bottom portion of fin 66 and / or substrate 50 may comprise a single or multiple materials. In this document, fin 66 is referred to as the portion extending between adjacent shallow trench isolation regions 68.

[0082] Several gate dielectric layers 100 are located above the surface of the fin 66 and along the surface, sidewalls, and below the surface of the nanostructure 55. Several gate electrodes 102 are located above the gate dielectric layers 100. Epitaxial source / drain regions 92 are located on the fin 66 on the side opposite to the gate dielectric layers 100 and the gate electrodes 102.

[0083] Figure 1 The reference cross-sections are further illustrated in the following figures. Cross-section A-A' is along the longitudinal axis of the gate electrode 102, and is also perpendicular to the current direction between the epitaxial source / drain regions 92 in this example of the nanostructured field-effect transistor. Cross-section B-B' is perpendicular to cross-section A-A' and parallel to the direction of the fin 66 in the nanostructured field-effect transistor, and is also the direction of the current between the epitaxial source / drain regions 92 in this example of the nanostructured field-effect transistor. Cross-section C-C' is parallel to cross-section A-A' and extends through the epitaxial source / drain regions in the nanostructured field-effect transistor. Cross-section D-D' is parallel to cross-section B-B' and extends through the spacer and gate dielectric of the nanostructured field-effect transistor. The following figures will illustrate these reference cross-sections.

[0084] Some embodiments discussed herein use a gate-last process to form nanostructured field-effect transistors, while in other embodiments, a gate-first process may also be used. Furthermore, some embodiments are conceived for application to planar devices such as planar field-effect transistors or FinFETs.

[0085] Figures 2A to 32D Cross-sectional and planar views of intermediate processes for fabricating nano-field-effect transistors according to some embodiments. Figure 2A , Figure 3 , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A, Figure 27A , Figure 28A , Figure 29A , Figure 30A , Figure 31A and Figure 32A Clarify reference Figure 1 The cross section A-A'. Figure 2B , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14E , Figure 15E , Figure 16E , Figure 17E , Figure 18E , Figure 19E , Figure 20E , Figure 21F , Figure 22F , Figure 23G , Figure 24E , Figure 25D , Figure 26D , Figure 27D , Figure 28D , Figure 29E , Figure 30E , Figure 31E and Figure 32E Explain as follows Figure 2A The diagram shown is a plan view of the n-type region 50N, which is on the same layer as the first semiconductor layer 51A. Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 21C , Figure 22B , Figure 22C , Figure 23B , Figure 23E , Figure 24B , Figure 24C , Figure 25B , Figure 26B , Figure 27B , Figure 28B , Figure 29B , Figure 30B , Figure 31B and Figure 32B Clarify reference Figure 1 The cross section B-B'. Figure 14C , Figure 15C , Figure 16C , Figure 17C , Figure 18C , Figure 19C, Figure 20C , Figure 21D , Figure 22D , Figure 23C , Figure 23D , Figure 24C , Figure 25C , Figure 29C , Figure 30C , Figure 31C and Figure 32C Clarify reference Figure 1 The cross section C-C'. Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14D , Figure 15D , Figure 16D , Figure 17D , Figure 18D , Figure 19D , Figure 20D , Figure 21E , Figure 22E , Figure 23F , Figure 24D , Figure 25C , Figure 26C , Figure 27C , Figure 28C , Figure 30D , Figure 31D and Figure 32D Clarify reference Figure 1 The cross section D-D'.

[0086] Substrate 50 at Figure 2A The substrate 50 can be a semiconductor substrate, such as a doped (e.g., p-type or n-type doped) or undoped bulk semiconductor or semiconductor-on-insulator (SOI) substrate. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer or a silicon oxide layer, and is disposed on a substrate, typically a silicon or glass substrate; other substrates such as multilayer or gradient substrates can also be used. In some embodiments, the semiconductor material of substrate 50 may include silicon; germanium; semiconductor compounds containing silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; semiconductor alloys containing silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide, or combinations thereof.

[0087] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can form an n-type device, such as an n-type metal-oxide-semiconductor field-effect transistor (NMOS transistor) or an n-type nanostructure field-effect transistor; while the p-type region 50P can form a p-type device, such as a p-type metal-oxide-semiconductor field-effect transistor (PMOS transistor) or a p-type nanostructure field-effect transistor. The n-type region 50N can be physically separated from the p-type region 50P (as shown by separator 20 in the figure), and any number of device features (such as other active devices, doped regions, and isolation structures) can be disposed between the n-type region 50N and the p-type region 50P. Although the figure shows one n-type region 50N and one p-type region 50P, any number of n-type regions 50N and p-type regions 50P can be configured.

[0088] Further at Figure 2A In this embodiment, a multilayer stack 64 is formed on substrate 50, comprising alternating first semiconductor layers 51A to 51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A to 53C (collectively referred to as second semiconductor layers 53). For clarity and as illustrated in the more detailed discussion below, the second semiconductor layer 53 may be removed, and the first semiconductor layer 51 may be patterned to form a channel region for a nanostructured field-effect transistor in p-type region 50P. Alternatively, the first semiconductor layer 51 may be removed, and the second semiconductor layer 53 may be patterned to form a channel region for a nanostructured field-effect transistor in n-type region 50N. Nevertheless, in some embodiments, the first semiconductor layer 51 may be removed, and the second semiconductor layer 53 may be patterned to form a channel region for a nanostructured field-effect transistor in p-type region 50P, and the second semiconductor layer 53 may be removed, and the first semiconductor layer 51 may be patterned to form a channel region for a nanostructured field-effect transistor in n-type region 50N.

[0089] In other embodiments, the first semiconductor layer 51 may be removed, while the second semiconductor layer 53 may be patterned to simultaneously form channel regions of nanostructured field-effect transistors in both the n-type region 50N and the p-type region 50P. In these embodiments, the channel regions formed simultaneously in the n-type region 50N and the p-type region 50P may be composed of the same material (e.g., silicon or other semiconductor materials), and these channel regions are formed synchronously. Figure 32A , Figure 32B , Figure 32C , Figure 32DFigure 33E serves as an example, illustrating a structure formed by such an embodiment, wherein the channel regions in the p-type region 50P and the n-type region 50N contain silicon.

[0090] For illustrative purposes, the multilayer stack 64, as shown, comprises three first semiconductor layers 51 and three second semiconductor layers 53. In some embodiments, the multilayer stack 64 may comprise any number of first semiconductor layers 51 and two semiconductor layers 53. Each layer of the multilayer stack 64 may be epitaxially formed by a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), or molecular beam epitaxy (MBE). In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for p-type nanostructure field-effect transistors, such as silicon germanium; while the second semiconductor layer 53 may be formed of a second semiconductor material suitable for n-type nanostructure field-effect transistors, such as silicon or silicon carbide. For the purposes of illustration, the multilayer stack 64 shown in the figure has a semiconductor layer at the bottom that is suitable for a p-type nanostructure field-effect transistor. In some embodiments, the multilayer stack 64 may be made so that the bottom layer is a semiconductor layer suitable for an n-type nanostructure field-effect transistor.

[0091] The first semiconductor material and the second semiconductor material may be highly etch-selective towards each other. Therefore, without significantly removing the second semiconductor layer 53 containing the second semiconductor material in the n-type region 50N, the first semiconductor layer 51 containing the first semiconductor material can be removed, allowing the second semiconductor layer 53 to be patterned to form the channel region of an n-type nanosheet field-effect transistor (NSFET). Similarly, without significantly removing the first semiconductor layer 51 containing the first semiconductor material in the p-type region 50P, the second semiconductor layer 53 containing the second semiconductor material can be removed, allowing the first semiconductor layer 51 to be patterned to form the channel region of a p-type nanosheet field-effect transistor (NSFET).

[0092] Figure 2B A planar diagram illustrating the structure of the n-type region 50N, which is in the same layer as the first semiconductor layer 51A, continues... Figure 2B The diagram will illustrate the various planar views of this structure within the same layer.

[0093] In continuation Figure 2A of Figure 3In the illustrated embodiment, a multilayer stack 64 having the desired height and / or number of layers is deposited with a photomask 58, wherein a plan view of the structure co-layered with the first semiconductor layer 51A in the n-type region 50N is shown. Figure 2B Photomask 58 can be used for patterning subsequent multilayer stacks 64 (see below). Figures 4A to 4B It can be deposited on the topmost surface layer of the multilayer stack 64, such as Figure 3 Photomask 58 could be a single-layer photomask or a multi-layer photomask, such as... Figure 3 The diagram shows a first photomask layer 58A and a second photomask layer 58B on top of the first photomask layer 58A. The first photomask layer 58A and the second photomask layer 58B may each be composed of a dielectric material such as silicon oxide, silicon nitride, or a combination thereof, and may be deposited or thermally generated using feasible techniques. The material of the first photomask layer 58A may have higher etch selectivity than the material of the second photomask layer 58B; in this example, the first photomask layer 58A may be formed of silicon oxide, while the second photomask layer 58B may be formed of silicon nitride.

[0094] Now refer to Figure 4A , Figure 4B and Figure 4C According to some embodiments, fins 66 are formed in substrate 50, while nanostructures 55 are formed in multilayer stack 64, with a portion of photomask 58 remaining on the upper surface of nanostructure 55. In some embodiments, nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 50 respectively by etching trenches in multilayer stack 64 and substrate 50. This etching can be any feasible etching technique, such as reactive ion etching (RIE) or neutral beam etching (NBE), or a combination thereof. The etching may be heterogeneous. The nanostructures 55 formed by etching multilayer stack 64 can further define first nanostructures 52A to 52C (collectively referred to as first nanostructures 52) in first semiconductor layer 51, and second nanostructures 54A to 54C (collectively referred to as second nanostructures 54) in second semiconductor layer 53. Figure 4C A planar diagram illustrating the structure is shown, passing through the first nanostructure 52A and within the n-type region 50N. The first nanostructure 52 and the second nanostructure 54 can be further collectively referred to as nanostructure 55.

[0095] Any suitable method, using photomask 58 as an etch mask, can be used to pattern the fins 66 and nanostructures 55. For example, one or more photolithography processes, including double-patterning or multi-patterning processes, may be used to pattern the photomask 58, fins 66, and nanostructures 55. Typically, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, resulting in patterns with, for example, smaller spacing than those using a single, straightforward photolithography process. For example, in one embodiment, a sacrificial layer is formed on the substrate and patterned using a photolithography process, while spacer walls are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacer walls can be used to pattern the fins 66. Patterning may involve one or more etching processes, such as reactive ion etching or neutral ion beam etching, or combinations thereof. Etching may be heterogeneous. In some embodiments, the photomask 58 (or other layers) may remain on the fins 66 and nanostructures 55.

[0096] In order to achieve the purpose of explanation, Figure 4A The fins 66 in the n-type region 50N and p-type region 50P are illustrated to have substantially the same width. In some embodiments, the fins 66 in the n-type region 50N may have a larger or thinner width than the fins 66 in the p-type region 50P. Furthermore, although each fin 66 and nanostructure 55 is illustrated to have a uniform width, in other embodiments the fins 66 and / or nanostructures 55 may have tapered sidewalls, such that the width of each fin 66 and / or nanostructure 55 gradually increases along the direction of the substrate 50. In such embodiments, each nanostructure 55 may have a different width and be trapezoidal in shape.

[0097] exist Figure 5A , Figure 5B and Figure 5CIn the nanostructure 55, a shallow trench isolation region 68 is formed adjacent to the fin 66. The shallow trench isolation region 68 can be formed by depositing an insulating material on and between the substrate 50, the fin 66, and the nanostructure 55. The insulating material can be an oxide such as silicon oxide or a nitride, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD) or flowable chemical vapor deposition (FCVD), or a combination thereof. Other insulating materials formed by any feasible process can also be used. In the illustrated embodiment, the insulating material is formed from silicon oxide by a flowable chemical vapor deposition process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the formation of the insulating material results in an excessive amount of insulating material covering the nanostructure 55. Although the insulating material is illustrated as a single layer, multiple layers can be used in some embodiments. For example, in some embodiments a liner (not shown separately) may be formed first along the surface of substrate 50, fin 66 and nanostructure 55, and then a filler material as discussed above may be formed on the liner.

[0098] A removal process is then used to remove excess insulating material on the nanostructure 55. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), etch-back, or a combination thereof may be used. This planarization process exposes the nanostructure 55 so that the upper surface of the nanostructure 55 and the insulating material are flattened after the planarization process is completed.

[0099] Next, the insulating material is recessed to form shallow trench isolation regions 68, such that the upper parts of the fins 66 in the n-type region 50N and p-type region 50P protrude between adjacent shallow trench isolation regions 68. Furthermore, the upper surface of the shallow trench isolation region 68 can be a flat surface as shown, or a convex, concave (e.g., dish-shaped) surface, or a combination thereof. The upper surface of the shallow trench isolation region 68 can be made planar, convex, and / or concave by a suitable etching process. The shallow trench isolation region 68 can be recessed using a feasible etching process, such as one that is selective for the insulating material (e.g., etching the insulating material at a faster rate than etching the fins 66 and the nanostructure 55), for example, by using an oxidizing agent such as diluted hydrofluoric acid (dHF) for removal.

[0100] The above description of... Figures 2A to 5CThis is just one example of how the fin 66 and nanostructure 55 might be formed. In some embodiments, the fin 66 and / or nanostructure 55 can be formed using a photomask and epitaxial growth process. For example, a dielectric layer can be formed on the upper surface of a substrate 50, and an epitaxial structure can be epitaxially generated in the trenches by etching trenches in the dielectric layer to expose the substrate 50 below. The dielectric layer is then recessed to allow the epitaxial structure to protrude from the dielectric layer to form the fin 66 and / or nanostructure 55. The epitaxial structure may contain alternating semiconductor materials, such as a first semiconductor material and a second semiconductor material, as discussed above. In some embodiments where the epitaxial structure is grown by epitaxy, the epitaxial growth material may be doped in situ during growth to avoid implantation before and / or after, although in-situ and implantation doping can be used simultaneously.

[0101] In addition, for illustrative purposes only, the first semiconductor layer 51 (and the resulting first nanostructure 52) and the second semiconductor layer 53 (and the resulting second nanostructure 54) are illustrated and discussed herein as containing the same material in the p-type region 50P and the n-type region 50N. Therefore, in some embodiments, the first semiconductor layer 51 and the second semiconductor layer 53 may simultaneously or one of them have different materials or be formed in different orders in the p-type region 50P and the n-type region 50N.

[0102] Further in Figure 5A , Figure 5B and Figure 5C In this embodiment, suitable walls (not shown separately) may be formed in the fin 66, nanostructure 55, and / or shallow trench isolation region 68. In some embodiments with different types of walls, different implantation steps of the n-type region 50N and p-type region 50P may be implemented using a photoresist or other photomask (not shown separately), for example, the photoresist may be formed in the n-type region 50N and p-type region 50P above the fin 66 and shallow trench isolation region 68, and the p-type region 50P may be exposed by patterning the photoresist. The photoresist is formed using a spin-on technique and may be patterned using a feasible photolithography technique. Once the photoresist is patterned, the implantation of n-type impurities is performed in the p-type region 50P, and the photoresist may act as a photomask to subsequently prevent the implantation of n-type impurities in the n-type region 50N. The n-type impurities may be phosphorus, arsenic, or antimony, etc., and the concentration of the implanted region ranges from approximately 10¹³ atoms per cubic centimeter to approximately 10¹⁴ atoms per cubic centimeter. After injection, the photoresist is removed, for example, through a feasible ashing process.

[0103] Before or after implantation into the p-type region 50P, a photoresist or photomask (not shown separately) is formed over the fins 66, nanostructures 55, and shallow trench isolation regions 68 in both the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist is formed using spin-coating and can be patterned using a feasible photolithography technique. Once the photoresist is patterned, implantation of p-type impurities is performed in the n-type region 50N, and the photoresist acts as a photomask to subsequently prevent the implantation of p-type impurities into the p-type region 50P. The p-type impurities may be boron, boron fluoride, indium, etc., with a concentration in the implanted region ranging from approximately 10¹³ atoms per cubic centimeter to approximately 10¹⁴ atoms per cubic centimeter. After implantation, the photoresist is removed, for example, by a feasible ashing process.

[0104] Following implantation in the n-type region 50N and the p-type region 50P, an annealing process can be performed to repair implantation defects and activate implanted p-type and / or n-type impurities. In some embodiments, the epitaxial growth material may be doped in situ during growth to avoid implantation, but in-situ and implantation-based doping can be used simultaneously.

[0105] exist Figure 6A , Figure 6B and Figure 6C In this configuration, a sacrificial layer 120 is formed above and around the fin 66 and nanostructure 55, and may also be formed on top of a photomask 58 if present. In some embodiments, the sacrificial layer 120 is formed by epitaxial growth, comprising growing a thin seed layer on the fin 66 and nanostructure 55, and then growing the material of the sacrificial layer 120 from a second layer. The seed layer may be grown after the fin 66 and nanostructure 55 are formed (see above). Figure 4A Part of the seed layer may then be covered by the shallow trench isolation area 68 (see above). Figure 5AThe remaining exposed seed layer portion can be epitaxially grown into a sacrificial layer 120, keeping the upper surface of the shallow trench isolation region 68 exposed. The sacrificial layer 120 can be formed from a semiconductor material (such as silicon germanium or other semiconductor materials), grown using a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), and deposited using a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The sacrificial layer 120 will be used as a temporary spacer in the process and will then be removed to expose a portion of the nanostructure 55 as a channel region for the nanostructure field-effect transistor. Specifically, in the illustrated embodiment, the sacrificial layer 120 and the first nanostructure 52 in the n-type region 50N will be subsequently removed and replaced by a gate structure formed around the second nanostructure 54; the sacrificial layer 120 and the second nanostructure 54 in the p-type region 50P will be subsequently removed and replaced by a gate structure formed around the first nanostructure 52 (see below). Figures 27A to 28C The semiconductor material forming the sacrificial layer 120 may be the same as or different from that of the first nanostructure 52 or the second nanostructure 54. In some embodiments, the material of the sacrificial layer 120 has higher etch selectivity than the material used to etch the second nanostructure 54, higher etch selectivity than the material used to etch the first nanostructure 52, or higher etch selectivity than the material used to etch the first nanostructure 52 and the second nanostructure 54.

[0106] exist Figures 7A to 11C In this process, insulating fins 130 (also called dielectric fins 130 or hybrid fins 130) are formed between fin 66 and the remainder of sacrificial layer 120 on nanostructure 55. Insulating fins 130 can insulate the subsequently formed source / drain regions from each other (see below). Figures 24B to 24E ).exist Figure 7A , Figure 7B and Figure 7C In this structure, a liner 124 is conformally deposited onto the structure using a feasible deposition process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam deposition (MBD), and physical vapor deposition (PVD). The liner 124 can be formed from nitrides such as silicon nitride, silicon carbonitride, or silicon carbonitride oxynitride. The liner 124 can subsequently form a filler material 126 (see below). Figure 9A and Figure 9B This reduces the oxidation of the sacrificial layer 120, which can then be effectively removed later.

[0107] exist Figure 8A , Figure 8B and Figure 8CIn this configuration, filler material 126 is formed on pad 124 and fills the remaining space between adjacent fins 66 and nanostructures 55. Filler material 126 can form most of the lower portion of the insulating fin 130 (see reference). Figure 9A ), and make the subsequently formed source and / or drain regions (see below) Figures 24B to 24E They are insulated from each other. The filler material 126 can be formed by feasible deposition processes, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam deposition (MBD), physical vapor deposition (PVD), etc. The filler material 126 may be a suitable dielectric material such as an oxide like silicon oxide or silicon carbonitride; or a dielectric material with a high k value (e.g., a k value greater than about 7), such as hafnium oxide, zirconium oxide, alumina zirconium, hafnium oxide, hafnium silicon oxide, or aluminum oxide, or combinations thereof.

[0108] exist Figure 9A , Figure 9B and Figure 9C In this process, the upper portion of the pad 124 and the filler material 126 above the upper surface of the photomask 58 can be removed using one or more feasible etching processes, such as one selective for the insulating fin 130 (e.g., selectively etching the material of the pad 124 and the filler material 126 at a rate faster than that for the sacrificial layer 120 material). Excess pad 124 portions and filler material 126 can be removed using planarization processes, such as chemical mechanical polishing. The pad 124 and filler material 126 can be further recessed using one or more etching processes. The upper portion of the pad 124 and filler material 126 can be removed to allow the subsequent photomask 58 to be removed (see below). Figure 12A , Figure 12B and Figure 12C Furthermore, the pad 124 and filler material 126 are further recessed to form a dielectric layer between the upper portion of the fin 66 and the nanostructure 55 (see below). Figures 10A to 10C ).

[0109] exist Figure 10A , Figure 10B and Figure 10CIn this process, one or more upper dielectric layers 128 for insulating fins 130 can be formed on pads 124 and filler material 126. The upper dielectric layers 128 can be formed of dielectric materials with high k-values ​​(e.g., those with k-values ​​greater than about 7), such as hafnium oxide, zirconium oxide, zirconium aluminate hafnium, hafnium silicon oxide, aluminum oxide, etc.; or combinations thereof, and can be deposited by a conformal deposition process (e.g., selecting one of the candidates for forming filler material 126). In some embodiments, the materials forming pads 124 and filler material 126 are the same as those forming the first photomask layer 58A and the second photomask layer 58B; therefore, the material of the upper dielectric layers 128 is selected to be etch-selective for pads 124 and filler material 126, which protects pads 124 and filler material 126 during the subsequent removal of photomask 58 (see reference). Figure 12A ).

[0110] exist Figure 11A , Figure 11B and Figure 11C In this process, a removal process is used to remove excess material from the upper dielectric layer 128 and sacrificial layer 120 on the photomask 58 (if any) or nanostructure 55. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), etching back, or a combination thereof is used, which exposes the photomask 58 or nanostructure 55 such that, after the planarization process, the upper surfaces of the photomask 58 or nanostructure 55, the sacrificial layer 120, and the upper dielectric layer 128 are coplanar (within the range of process variations). In the illustrated embodiment, the photomask 58 is retained after the planarization process. In other embodiments, some or all of the photomask 58 is removed during the planarization process.

[0111] exist Figure 12A , Figure 12B and Figure 12C In this embodiment, photomask 58 is removed and sacrificial layer 120 is recessed, causing insulating fin 130 to protrude beyond adjacent portions of sacrificial layer 120. In embodiments where photomask 58 is absent, a portion of nanostructure 55 may be recessed. Recessing can be achieved using one or more etching processes. For example, photomask 58 can be removed using a feasible etching process, such as selective etching of photomask 58 (e.g., selectively etching the material of photomask 58 at a rate faster than that of the material of the upper dielectric layer 128 of sacrificial layer 120 and insulating fin 130). Sacrificial layer 120 can be selectively recessed using feasible etching processes, such as selective etching of sacrificial layer 120 (e.g., selectively etching the material of sacrificial layer 120 at a rate faster than that of the material of nanostructure 55 and insulating fin 130). Recessing may remove some of the nanostructure 55. For illustrative purposes, the bottom of the upper dielectric layer 128 is shown to be flush with the upper surface of the nanostructure 55, while the bottom of the upper dielectric layer 128 may be above or below the upper surface of the nanostructure 55.

[0112] In the illustrated embodiment, the lower portion of the insulating fin 130 is formed of a dielectric material with a low k-value (including a pad 124 and a filler material 126), while the upper portion (including an upper dielectric layer 128) is formed of a dielectric material with a high k-value. It should be understood that other types of insulating fins 130 can be formed, such as insulating fins 130 with more or fewer layers. In various embodiments, the insulating fin 130 may comprise a lower and upper portion with a low k-value dielectric material; a lower and upper portion with a high k-value dielectric material; a lower portion with a high k-value dielectric material and an upper portion with a low k-value dielectric material; a single-layer lower and / or upper portion; a multi-layer lower and / or upper portion, etc. The upper part of the insulating fin 130 (including the upper dielectric layer 128) may have a height H1 ranging from about 20 nanometers to about 30 nanometers, the lower part of the insulating fin 130 (including the pad 124 and the filler material 126) may have a height H2 ranging from about 55 nanometers to about 60 nanometers, and the overall height of the insulating fin 130 ranges from about 75 nanometers to about 90 nanometers.

[0113] exist Figure 13A , Figure 13B and Figure 13C In this process, a virtual dielectric layer 70 is formed on fin 66 and / or nanostructure 55, sacrificial layer 120, and insulating fin 130. The virtual dielectric layer 70 may be, for example, silicon oxide, silicon nitride, or a combination thereof, and may be deposited or thermally grown according to feasible techniques. A virtual gate layer 72 is formed on the virtual dielectric layer 70, and a photomask layer 74 is formed on the virtual gate layer 72. The virtual gate layer 72 may be deposited on the virtual dielectric layer 70 and then planarized by chemical mechanical polishing. The photomask layer 74 may be deposited on the virtual gate layer 72. The virtual gate layer 72 may be a conductive or non-conductive material, and may be selected from amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The virtual gate layer 72 may be deposited using physical vapor deposition (PVD), chemical vapor deposition, sputtering deposition, or other techniques to deposit the selected material. The dummy gate layer 72 can be made of other materials that have high etch selectivity for etching the shallow trench isolation region 68. The photomask layer 74 can comprise materials such as silicon nitride or silicon oxynitride. In this example, a dummy gate layer 72 and a photomask layer 74 are formed in the n-type region 50N and the p-type region 50P.

[0114] exist Figures 14A to 14E In the middle, photomask layer 74 (reference) Figure 13AThe photomask 78 can be patterned using feasible photolithography and etching techniques. The patterning of the photomask 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70, respectively, to form dummy gates 76 and dummy gate dielectrics 71. The dummy gates 76 cover each channel region of the fin 66. The patterning of the photomask 78 can physically separate each dummy gate 76 from its adjacent counterparts. The dummy gates 76 may also have a longitudinal direction substantially perpendicular to the longitudinal direction of each fin 66.

[0115] exist Figures 15A to 15E In this process, a portion of the sacrificial layer 120 not covered by the dummy gate dielectric 71 is removed to form a first recess 121 between the nanostructure 55 and the insulating fin 130. In a subsequent step, the first recess 121 is formed with a spacer layer (see below). Figures 16A to 16D This filling reduces the generation of short circuits between the subsequently formed source / drain regions and the gate electrode, thereby improving device function. The first recess 121 may be formed by a heterogeneous etching. In some embodiments, the sacrificial layer 120 comprises silicon germanium and an etchant performed by heterogeneous dry etching, such as nitrogen trifluoride, carbon tetrafluoride, trifluoromethane, sulfur hexafluoride, oxygen, hydrogen bromide, fluoromethane, helium, methane, ammonia, or hydrogen fluoride, or combinations thereof. The etching time can range from about 300 seconds to about 400 seconds. The etching power supply can provide a power range from about 400 watts to about 500 watts, and the etch bias power can range from about 200 watts to about 300 watts. In some embodiments, the sacrificial layer 120 beneath the dummy gate and the dummy gate dielectric layer 71 may be horizontally over-etched such that the dummy gate dielectric layer 71 extends beyond the first recess 121 in a width W1 of about 1 nanometer to about 2 nanometers, such as Figure 15D As shown. This can be useful when subsequently forming the spacer layer, in order to create a thicker barrier between the subsequently formed source / drain regions and the gate electrode, thereby reducing circuit short circuits.

[0116] exist Figures 16A to 16E In this process, one or more spacer walls, such as the first spacer wall layer 80 and the second spacer wall layer 82, are respectively located in... Figures 15A to 15D The structure is formed as described in the diagram. The first spacer layer 80 and the second spacer layer 82 will then be patterned as spacers to form self-aligned source / drain regions and protect the sidewalls of the fins 66 and / or nanostructures 55 in subsequent processing. They also form a thicker barrier between the subsequently formed source / drain regions and the gate electrode, thereby reducing circuit short circuits. Figures 16A to 16DIn this structure, a first spacer layer 80 is formed on the upper surface of the shallow trench isolation region 68; the upper surface and sidewalls of the fin 66, nanostructure 55, insulating fin 130, and photomask 78; and the sidewalls of the dummy gate 76 and dummy gate dielectric 71. A second spacer layer 82 is deposited on the first spacer layer 80. The first spacer layer 80 may be composed of silicon oxide, silicon nitride, silicon oxynitride, etc., and is deposited using techniques such as thermal oxidation, chemical vapor deposition, or atomic layer deposition. The second spacer layer 82 may be formed of a material with a different etch rate than the first spacer layer 80, such as silicon oxide, silicon nitride, or silicon oxynitride, and may be deposited using chemical vapor deposition or atomic layer deposition.

[0117] According to some embodiments, the first spacer wall layer 80 and the second spacer wall layer 82 fill the first recess 121 between the nanostructure 55 and the insulating fin 130, such as Figure 16C and Figure 16D As shown, this provides a stronger insulating barrier between the subsequently formed source / drain regions and the gate electrode, and reduces the formation of short circuits between them, thereby improving device functionality.

[0118] After the formation of the first spacer layer 80 and before the formation of the second spacer layer 82, implantation of a lightly doped source / drain (LDD) region (not shown separately) can be performed. Similar to the above description, this process can be repeated in embodiments with different device types. Figure 5A , Figure 5B and Figure 5C In the implantation discussed herein, a photomask, such as a photoresist, can be formed on an n-type region 50N, simultaneously exposing a p-type region 50P. An impurity of a suitable type (e.g., p-type) can be implanted into the exposed fins 66 and nanostructures 55 within the p-type region 50P, after which the photomask can be removed. Subsequently, another photomask, such as a photoresist, can be formed on the p-type region 50P, simultaneously exposing an n-type region 50N. An impurity of a suitable type (e.g., n-type) can be implanted into the exposed fins 66 and nanostructures 55 within the n-type region 50N, after which the photomask can be removed. The n-type impurity can be any n-type impurity discussed previously, and the p-type impurity can be any p-type impurity discussed previously. The lightly doped source / drain regions can have impurity concentrations ranging from approximately 1 x 10¹⁵ atoms per cubic square to approximately 1 x 10¹⁹ atoms per cubic square. Annealing can be used to repair implanted damage and activate the implanted impurities.

[0119] exist Figures 17A to 17EIn this process, the first spacer layer 80 and the second spacer layer 82 are etched to form the first spacer layer 81 and the second spacer layer 83. As will be discussed in detail below, the first spacer layer 81 and the second spacer layer 83 are used to self-align the subsequently formed source / drain regions. The etching of the first spacer layer 80 and the second spacer layer 82 can be performed using a suitable etching process, such as a homogeneous etching process (e.g., wet etching) or a heterogeneous etching process (e.g., dry etching). In some embodiments, the etch rate of the material of the second spacer layer 82 is different from that of the material of the first spacer layer 80, so the first spacer layer 80 can act as an etch stop layer when patterning the second spacer layer 82, making the second spacer layer 82 a photomask when patterning the first spacer layer 80. For example, the second spacer layer 82 can be etched using a heterogeneous etching process, where the first spacer layer 80 acts as an etch stop layer, and the remaining portion of the second spacer layer 82 forms the second spacer layer 83, as shown below. Figure 17B As shown. Subsequently, the second spacer wall 83 serves as a photomask for etching the exposed portion of the first spacer wall layer 80, thereby forming... Figure 17B The first gap wall 81 is shown. The first gap wall 81 and the second gap wall 83 are in Figure 17B , Figure 17D The following diagrams show individual elements for illustrative purposes.

[0120] like Figures 17C to 17E As shown, the remaining portions of the first spacer wall layer 80 and the second spacer wall layer 82 are deposited on the sidewalls of the fin 66 and / or the nanostructure 55 and the sidewalls of the insulating fin 130. As shown in Figures 17C and 17D, portions of the first spacer wall layer 80 and the second spacer wall layer 82 are deposited between the insulating fin 130, the nanostructure 55 (such as the first nanostructure 52A illustrated in Figure 17D), and the remaining portion of the sacrificial layer 120 located under the dummy gate 76.

[0121] It should be noted that the above disclosure describes a process that typically forms spacers and lightly doped source / drain regions. Other processes and sequences can also be used, such as using fewer or additional spacers, different sequence steps (e.g., the first spacer 81 may be patterned before the second spacer layer 82 is deposited), forming and removing additional spacers, and / or other similar methods. Furthermore, n-type and p-type devices can be formed using different structures and steps.

[0122] exist Figures 18A to 18E In some embodiments, a second recess 86 is formed in the fin 66, nanostructure 55, and substrate 50. An epitaxial source / drain region 92 is subsequently formed in the second recess 86. The second recess 86 may extend to the first nanostructure 52 and the second nanostructure 54, and into the substrate 50. Figure 18CAs shown, the upper surface of the shallow trench isolation region 68 may be flush with the lower surface of the second recess 86. In various embodiments, the fin 66 may be etched such that the lower surface of the second recess 86 is deposited below the upper surface of the shallow trench isolation region 68; or similarly. The second recess 86 may be formed by etching the fin 66, nanostructure 55, and substrate 50 using a heterogeneous etching process such as reactive ion etching or neutral ion beam etching. The first spacer wall 81, the second spacer wall 83, and the photomask 78 may cover portions of the fin 66, nanostructure 55, and substrate 50 during the etching process used to form the second recess 86. One or more etching processes may be used to etch each layer of the nanostructure 55 and / or the fin 66. A timed etching process may be used to stop the etching of the second recess 86 after the second recess 86 reaches a desired depth.

[0123] exist Figures 19A to 19E In the process, the sidewall portions of the layers of the multilayer stack 64 exposed by the second recess 86 and formed of the first semiconductor material (e.g., the first nanostructure 52) are etched to form sidewall recesses 88 in the n-type region 50N, and the sidewall portions of the layers of the multilayer stack 64 exposed by the second recess 86 and formed of the second semiconductor material (e.g., the second nanostructure 54) are etched to form sidewall recesses 88 in the p-type region 50P. Although the sidewalls of the first nanostructure 52 and the second nanostructure 54 in the sidewall recesses 88 are... Figure 19B The p-type region 50P is depicted as straight, but the sidewalls can be concave or convex. The sidewalls can be etched using a homogeneous etching process, such as wet etching. The p-type region 50P can be protected by a photomask (not shown), however, an etchant selective for the first semiconductor material is used to etch the first nanostructure 52, such that the second nanostructure 54 and the substrate 50 remain relatively unetched compared to the first nanostructure 52 in the n-type region 50N. Similarly, the n-type region 50N can be protected by a photomask (not shown), however, an etchant selective for the second semiconductor material is used to etch the second nanostructure 54, such that the first nanostructure 52 and the substrate 50 remain relatively unetched compared to the second nanostructure 54 in the p-type region 50P. In one embodiment where the first nanostructure 52 contains, for example, silicon or germanium and the second nanostructure 54 contains, for example, silicon or silicon carbide, a dry etching process containing tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like can be used to etch the sidewalls of the first nanostructure 52 in the n-type region 50N, while a dry etching process containing hydrogen fluoride, other fluorine-based etchants, or the like can be used to etch the sidewalls of the second nanostructure 54 in the p-type region 50P.

[0124] exist Figures 20A to 20E In the middle, the internal spacer wall layer 89 is Figures 19A to 19E The structure shown is formed thereon and will subsequently be used to form the first inner spacer wall 90 (see reference). Figures 21A to 21E This serves as an isolation layer between the subsequently formed source / drain regions and the gate structure. The inner spacer layer 89 can be deposited on multiple nanostructures or nanosheets, such as paired multilayer stacks 64 in the first nanostructure 52 and the second nanostructure 54. As will be discussed in detail below, the source / drain regions will be formed in the second recess 86, and the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P will be replaced by the corresponding gate structures.

[0125] The inner spacer layer 89 can be deposited by a conformal deposition process, such as chemical vapor deposition or atomic layer deposition. The inner spacer layer 89 can contain materials such as silicon nitride, tributyl siloxane, silicon carbon nitride (SiCN), or silicon oxycarbonate (SiOCN), although any suitable material, such as a material with a low dielectric constant (low k value) of less than about 3.5, can be used.

[0126] Next Figures 21A to 21E In this process, the inner spacer wall layer 89 is etched to form the first inner spacer wall 90. In some embodiments, etching is performed by a wet etching process, such as hydrogen fluoride, hydrogen peroxide with water and hydrochloric acid, hydrogen peroxide with water and hydrogen fluoride, hydrogen peroxide with ammonia, a high-temperature sulfur peroxide mixture (sulfuric acid with hydrogen peroxide), or sulfuric acid with hydrogen peroxide with water, or combinations thereof. In some embodiments, etching is performed by a dry etching process, such as carbon tetrafluoride, oxygen, argon, nitrogen trifluoride, fluoromethane, or trifluoromethane, or combinations thereof. The dry etching process may be followed by wet cleaning. Then any suitable etching process or etchant can be used. In other embodiments, the inner spacer wall layer may be etched by a heterogeneous etching process, such as reactive ion etching or neutral ion beam etching. Although the outer wall of the first inner spacer wall 90 is illustrated as being submerged by the sidewall of the second nanostructure 54, the outer wall of the first inner spacer wall 90 may extend beyond or be recessed beyond the sidewall of the second nanostructure 54, and the outer wall may be flat, concave, convex, or otherwise non-linear.

[0127] After etching, the first inner spacer wall 90 may have a first thickness T1 measured along section B-B', ranging from about 3.5 nanometers to about 5.5 nanometers, which may facilitate the subsequent formation of the gate electrode (see below). Figures 29A to 29C The source / drain region subsequently formed by the insulation in the ) (see below) Figures 24B to 24EA first thickness T1 less than about 3.5 nanometers may be disadvantageous because it can lead to a short circuit between the subsequently formed source / drain region and the subsequently formed gate electrode. A first thickness T1 greater than about 5.5 nanometers may be disadvantageous because it can reduce the critical dimension between the subsequently formed source / drain region and the subsequently formed gate electrode, thus degrading device performance. The sidewalls of the first inner spacer wall 90 with the first thickness T1 can be covered by a first spacer wall layer 80 and a second spacer wall layer 82, which can help reduce the subsequently formed source / drain region (see below). Figures 23B to 23G This short-circuits the circuit between the gate electrode and the subsequently formed gate electrode.

[0128] Furthermore, although the outer wall of the first inner spacer wall 90 is in Figure 21B The middle section is shown as straight, but the outer wall of the first inner spacer wall 90 may be concave or convex. For example, in... Figure 21C In one embodiment, the sidewalls of the first nanostructure 52 are concave, the outer wall of the first inner spacer wall 90 is concave, and the first inner spacer wall is recessed from the sidewalls of the second nanostructure 54 in the n-type region 50N. In another illustrated embodiment, the sidewalls of the second nanostructure 54 are concave, the outer wall of the first inner spacer wall 90 is concave, and the first inner spacer wall is recessed from the sidewalls of the first nanostructure 52 in the p-type region 50P. The first inner spacer wall 90 can be used to prevent the subsequent formation of source / drain regions (e.g., as shown below). Figures 23A to 23F The epitaxial source / drain regions discussed (92) are damaged in subsequent etching processes, such as those used for gate structures.

[0129] exist Figures 24A to 24E In this process, the epitaxial region 91 may be formed on the lower surface of the second recess 86. In some embodiments, the inner spacer wall layer 89 forms the first inner spacer wall 90 (refer to above). Figures 21A to 21F Etching of the second recess 86 may cause it to be over-etched to a depth less than expected. Epitaxial region 91 can be used to form epitaxial source / drain regions 92 (see below). Figures 23A to 23F The bottom region of the second recess 86 that has been over-etched is filled beforehand. In some embodiments, the epitaxial region 91 contains silicon and may be formed of silicon epitaxially grown in the second recess 86 at a temperature ranging from about 630 degrees Celsius to about 700 degrees Celsius. This may result in the 100 crystal plane along the lower surface of the second recess 86 growing faster than the 110 crystal plane along the sidewalls of the second recess 86, and may also result in a silicon layer being formed on the bottom surface of the second recess 86 that is thicker than that on the sidewalls of the second recess 86. The silicon formed on the sidewalls of the second recess 86 may be removed by a suitable etching process, leaving the remaining undoped silicon on the bottom surface of the second recess 86 as the epitaxial region 91.

[0130] exist Figures 23A to 23FIn this configuration, an epitaxial source / drain region 92 is formed in the second recess 86, for example, above the epitaxial region 91. In some embodiments, the epitaxial source / drain region 92 may exert stress on the second nanostructure 54 in the n-type region 50N and the first nanostructure 52 in the p-type region 50P, thereby improving performance. Figure 23B As shown, epitaxial source / drain regions 92 are formed in the second recess 86 such that each dummy gate 76 is deposited between its respective adjacent pairs of epitaxial source / drain regions 92. In some embodiments, a first spacer wall 81 and a second spacer wall 83 are used to separate the epitaxial source / drain regions 92 from the dummy gates 76, while a first inner spacer wall 90 is used to separate the epitaxial source / drain regions 92 from the nanostructure 55 by an appropriate lateral distance, so that the epitaxial source / drain regions 92 are not short-circuited with the gate of the subsequently formed nanostructure field-effect transistor.

[0131] The epitaxial source / drain region 92 in the n-type region 50N, such as an n-type metal-oxide-semiconductor region, can be formed by covering the p-type region 50P, such as a p-type metal-oxide-semiconductor region. Next, the epitaxial source / drain region 92 in the n-type region 50N is epitaxially grown in the second recess 86. The epitaxial source / drain region 92 can contain any feasible material suitable for an n-type nanostructure field-effect transistor. For example, assuming the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can contain a material that applies tensile strain to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, or silicon-phosphorus. The epitaxial source / drain region 92 may have a surface raised from the surface of the corresponding nanostructure 55, and may have a facet.

[0132] The epitaxial source / drain region 92 in the p-type region 50P, such as a p-type metal-oxide-semiconductor region, can be formed by covering the n-type region 50N, such as an n-type metal-oxide-semiconductor region. Next, the epitaxial source / drain region 92 in the p-type region 50P is epitaxially grown in the second recess 86. The epitaxial source / drain region 92 can contain any feasible material suitable for a p-type nanostructure field-effect transistor. For example, assuming the first nanostructure 52 is silicon-germanium, the epitaxial source / drain region 92 can contain a material that applies compressive strain to the first nanostructure 52, such as silicon-germanium, boron-doped silicon-germanium, germanium, or germanium-tin. The epitaxial source / drain region 92 may have a surface raised from the surface of the corresponding multilayer stacked nanostructure 55, and may have a facet.

[0133] The epitaxial source / drain region 92, the first nanostructure 52, the second nanostructure 54, and / or the substrate 50 may be implanted with dopants to form the source / drain region, similar to the previously discussed process of forming a lightly doped source / drain region before annealing. The impurity concentration of the source / drain region may be between about 1 x 10¹⁹ atoms per cubic centimeter and about 1 x 10²¹ atoms per cubic centimeter. The n-type and / or p-type impurities of the source / drain region may be any impurities discussed previously. In some embodiments, the epitaxial source / drain region 92 may be doped in situ during growth.

[0134] Due to the epitaxial process used to form the epitaxial source / drain regions 92 in the n-type region 50N and the p-type region 50P, the upper surface of the epitaxial source / drain regions 92 extends laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, such as Figure 23C As shown, after the epitaxial process is completed, adjacent epitaxial source / drain regions 92 are kept separate by means such as insulating fins 130. In other embodiments, the epitaxial process may continue, and these surfaces may cause adjacent epitaxial source / drain regions 92 to merge, as shown. Figure 23D As shown.

[0135] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used in the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of a different semiconductor material and may be doped with different dopant concentrations. In some embodiments, the dopant concentration of the first semiconductor material layer 92A may be less than that of the second semiconductor material layer 92B and greater than that of the third semiconductor material layer 92C. In an embodiment where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited on the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited on the second semiconductor material layer 92B.

[0136] Figure 23E The embodiments illustrate that the sidewalls of the first nanostructure 52 in the n-type region 50N and the sidewalls of the second nanostructure 54 in the p-type region 50P are concave, the outer wall of the first inner spacer wall 90 is concave, and the first inner spacer wall 90 is recessed from the sidewalls of the second nanostructure 54 and the first nanostructure 52, respectively. Figure 23E As shown, the epitaxial source / drain region 92 can be formed in contact with the first inner spacer wall 90, and can extend through the sidewall of the second nanostructure 54 in the n-type region 50N and the sidewall of the first nanostructure 52 in the p-type region 50P.

[0137] exist Figures 24A to 24D In the middle, the first interlayer dielectric (ILD) 96 is deposited on... Figures 23A to 23C and Figure 23F The structure shown is as follows. The first interlayer dielectric 96 can be formed of a dielectric material and can be deposited by any suitable method, such as chemical vapor deposition, plasma chemical vapor deposition (PECVD), or flowable chemical vapor deposition. The dielectric material can contain phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), or undoped silicate glass (USG), etc., and other insulating materials formed using any feasible process can be used. In some embodiments, a contact etch stop layer (CESL) 94 is deposited between the first interlayer dielectric 96 and the epitaxial source / drain region 92, between the photomask layer 74, and between the first spacer 81 and the second spacer 83. The contact etch stop layer 94 may contain a dielectric material such as silicon nitride, silicon oxide, or silicon oxynitride, and has a different etch rate than the material of the first interlayer dielectric 96 above it.

[0138] exist Figures 25A to 25C In this process, a planarization process such as chemical mechanical polishing can flatten the top surface of the first interlayer dielectric 96 and the dummy gate 76 or photomask 78. The planarization process can also remove the photomask 78 on the dummy gate 76, as well as the first gap wall 81 and the second gap wall 83 along the sidewall portion of the photomask 78. After the planarization process, the top surface of the dummy gate 76, the first gap wall 81, the second gap wall 83, and the first interlayer dielectric 96 are flush with each other during the process change. Correspondingly, the top surface of the dummy gate 76 is exposed from the first interlayer dielectric 96. In some embodiments, when the top surface of the first interlayer dielectric 96 is flattened with the top surfaces of the photomask 78, the first gap wall 81, and the second gap wall 83 during the planarization process, the photomask 78 may be retained.

[0139] exist Figures 26A to 26CIn this process, the dummy gate 76 and the photomask layer 74 (if present) are removed in one or more etching steps, resulting in the formation of a third recess 98, and a portion of the dummy gate dielectric 71 in the third recess 98 is also removed. In some embodiments, the dummy gate 76 and the dummy gate dielectric 71 are removed by a heterogeneous dry etching process, for example, the etching process may include a dry etching process using reactive gases(s), which selectively etches the dummy gate 76 at a rate faster than the first interlayer dielectric 96, insulating fin 130, first spacer 81, or second spacer 83. Each third recess 98 exposes and / or covers a portion of the nanostructure 55 to serve as a channel region in the subsequently completed nanostructured field-effect transistor. The portion of the nanostructure 55 used as a channel region is deposited between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy gate dielectric 71 may serve as an etch stop layer when the dummy gate 76 is etched, and the dummy gate dielectric 71 may be removed after the dummy gate 76 is removed.

[0140] exist Figures 27A to 27C In this embodiment, the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P are removed to extend the third recess 98. The remaining portion of the sacrificial layer 120 can also be removed. The first nanostructure 52 can be removed by forming a photomask (not shown) on the p-type region 50P and performing a homogeneous etching process such as wet etching, wherein the etchant used is selective for the materials of the first nanostructure 52 and the sacrificial layer 120; however, the second nanostructure 54, the substrate 50, and the shallow trench isolation region 68 remain relatively unetched compared to the first nanostructure 52. In embodiments where the first nanostructure 52 contains silicon germanium and the second nanostructures 54A to 54C contain silicon or silicon carbide, tetramethylammonium hydroxide (TMAH) or ammonia (NH4OH) can remove the first nanostructure 52 in the n-type region 50N.

[0141] The second nanostructure 54 in the p-type region 50P can be removed by forming a photomask (not shown) on the n-type region 50N and performing a homogeneous etching process such as wet etching. The etchant used is selective for the materials of the second nanostructure 54 and the sacrificial layer 120; however, the first nanostructure 52, the substrate 50, and the shallow trench isolation region 68 remain relatively unetched compared to the second nanostructure 54. In embodiments where the second nanostructure 54 contains silicon-germanium and the first nanostructure 52 contains silicon or silicon carbide, hydrogen fluoride or other fluorine-based etchants can remove the second nanostructure 54 in the p-type region 50P.

[0142] In other embodiments, the channel regions in the n-type region 50N and the p-type region 50P can be formed simultaneously, for example, by simultaneously removing the first nanostructure 52 and the remaining portion of the sacrificial layer 120 in both the n-type region 50N and the p-type region 50P, or by simultaneously removing the second nanostructure 54 and the remaining portion of the sacrificial layer 120 in both the n-type region 50N and the p-type region 50P. In this embodiment, the channel regions of the n-type nanosheet field-effect transistor and the p-type nanosheet field-effect transistor can have the same material composition, such as silicon or silicon-germanium. Figure 32A , 32B 32C illustrates a structure resulting from this embodiment, wherein the channel regions such as p-type region 50P and n-type region 50N are provided by a second nanostructure 54 and contain silicon.

[0143] exist Figures 28A to 28C In this configuration, a gate dielectric layer 100 and a gate electrode 102 are formed to replace the gate. The gate dielectric layer 100 is conformally deposited in the third recess 98. In the n-type region 50N, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the insulating fin 130, the top surface and sidewalls of the substrate 50, and the top surface, sidewalls, and bottom surface of the second nanostructure 54. In the p-type region 50P, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the insulating fin 130, the top surface and sidewalls of the substrate 50, and the top surface, sidewalls, and bottom surface of the first nanostructure 52. The gate dielectric layer 100 may also be deposited on the top surface of the first interlayer dielectric 96, the contact etch stop layer 94, the first spacer 81, the second spacer 83, and the shallow trench isolation region 68.

[0144] According to some embodiments, the gate dielectric layer 100 is formed of one or more dielectric layers, such as oxides or metal oxides, or combinations thereof. For example, in some embodiments, the gate dielectric may comprise a silicon oxide layer and a metal oxide layer on the silicon oxide layer. In some embodiments, the gate dielectric layer 100 comprises a dielectric material with a high k-value, wherein the k-value of the gate dielectric layer 100 in the embodiments may be greater than about 7.0, and may comprise metal oxides or silicates containing hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, and lead, or combinations thereof. The structure of the gate dielectric layer 100 may be the same or different in the n-type region 50N and the p-type region 50P. The method of forming the gate dielectric layer 100 may include molecular beam deposition (MBD), atomic layer deposition, and plasma chemical vapor deposition, etc.

[0145] Gate electrode 102 is deposited on gate dielectric layer 100 and filled in the remainder of third recess 98. Gate electrode 102 may comprise a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although a single-layer gate electrode 102 is... Figures 28A to 28CAs explained, the gate electrode 102 may comprise any number of pad layers, any number of function adjustment layers, and filler material. Any combination of layers constituting the gate electrode 102 may be deposited in the n-type region 50N between adjacent second nanostructures 54 and between the second nanostructure 54A and the substrate 50, and may be deposited in the p-type region 50P between adjacent first nanostructures 52.

[0146] In both the n-type region 50N and the p-type region 50P, the formation of the gate dielectric layer 100 can occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 can also occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region can be formed by different processes, such that the gate dielectric layer 100 may be made of different materials and / or have different numbers of layers, and / or the gate electrode 102 in each region can be formed by different processes, such that the gate electrode 102 may be made of different materials and / or have different numbers of layers. When using different processes, various photomask steps can be used to mask and expose appropriate areas.

[0147] After filling the third recess 98, a planarization process such as chemical mechanical polishing can be performed to remove excess portions of the gate dielectric layer 100 and the material of the gate electrode 102, with the excess portions located on the top surface of the first interlayer dielectric 96. Then, a recess process (such as etch-back) can be performed to recess the top surface of the gate electrode 102 from the top surface of the insulating fin 130. The material of the gate electrode 102 and the remaining portion of the gate dielectric layer 100 thus form the replacement gate structure for the subsequent nanofield-effect transistor. The gate electrode 102 and the gate dielectric layer 100 can be collectively referred to as the "gate structure".

[0148] exist Figures 29A to 29D In this process, the gate structure (including the gate dielectric layer 100 and the corresponding gate electrode 102 thereon) is recessed such that the recess is formed directly between the opposing portions of the gate structure and the first spacer 81 and the second spacer 83. The gate photomask 104 includes one or more layers of dielectric material, such as silicon nitride or silicon oxide, filling the recess. A subsequent planarization process removes excess dielectric material extending to the first interlayer dielectric 96. The gate contact 114, which is then formed (as discussed below), is then referenced. Figure 31A and Figure 31B It passes through the gate photomask 104 to contact the top surface of the recessed gate electrode 102.

[0149] As further explained Figures 29A to 29DThe second interlayer dielectric 106 is deposited on the first interlayer dielectric 96 and the gate photomask 104. In some embodiments, the second interlayer dielectric 106 is a flowable sheet formed by flowable chemical vapor deposition. In some embodiments, the second interlayer dielectric 106 is composed of a dielectric material such as phosphosilicate glass, borosilicate glass, borophosphosilicate glass, or undoped silicate glass, and can be deposited by any suitable method such as chemical vapor deposition or plasma chemical vapor deposition.

[0150] exist Figures 30A to 30D In this process, the second interlayer dielectric 106, the first interlayer dielectric 96, the contact etch stop layer 94, and the gate photomask 104 are etched to form a third recess 108 that exposes the epitaxial source / drain region 92 and / or the gate structure surface. The third recess 108 can be formed by etching using a heterogeneous etching process such as reactive ion etching or neutral ion beam etching. In some embodiments, the third recess 108 can be etched using a first etching process through the second interlayer dielectric 106 and the first interlayer dielectric 96; it can be etched using a second etching process through the gate photomask 104; and it can be etched using a third etching process through the contact etch stop layer 94. A photomask, such as a photoresist, can be formed and patterned on the second interlayer dielectric 106 to cover portions of the second interlayer dielectric 106 from the first and second etching processes. In some embodiments, the etching process may over-etch, such that the third recess 108 extends to the epitaxial source / drain region 92 and / or the gate structure, and the bottom of the third recess 108 may be flush with (e.g., at the same level, or with the same distance from the substrate) or lower (e.g., closer to the substrate) the epitaxial source / drain region 92 and / or the gate structure. Although Figure 30BThe third recess 108 exposes the epitaxial source / drain region 92 and gate structure in the same cross section. However, in various embodiments, the epitaxial source / drain region 92 and gate structure may be exposed in different cross sections to reduce the risk of short circuits in subsequently formed contacts. After the third recess 108 is formed, a silicide region 110 is formed on the epitaxial source / drain region 92. In some embodiments, the silicide region 110 is first formed by depositing a metal (not shown) that reacts with the underlying semiconductor material of the epitaxial source / drain region 92 (such as silicon, silicon-germanium, germanium) to form a silicide or germanium region, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof on the exposed portion of the epitaxial source / drain region 92, and then performing an annealing process to form the silicide region 110. Unreacted deposited metal portions are then removed, for example, by an etching process. Although the silicide region 110 is referred to as a silicide region, it may also be a germanium region or a silicon-germanium region (e.g., a region containing silicon and germanium). In one embodiment, the silicide region 110 is formed of titanium silicon and has a thickness between about 2 nanometers and about 10 nanometers.

[0151] Then in Figures 31A to 31D In this embodiment, contacts 112 and 114 (also referred to as contact plugs) are formed in the third recess 108. Contacts 112 and 114 may each comprise one or more layers, such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, contacts 112 and 114 each comprise a barrier layer and a conductive material, and are electrically coupled to conductive features of the underlying layer (e.g., gate electrode 102 and / or silicide region 110 in the illustrated embodiment). Contact 114, electrically coupled to gate electrode 102, may be referred to as a gate contact, while contact 112, electrically coupled to silicide region 110, may be referred to as a source / drain contact. The barrier layer may comprise titanium, titanium nitride, tantalum, or tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, or nickel, etc. A planarization process such as chemical mechanical polishing may be performed to remove excess material from the surface of the second interlayer dielectric 106.

[0152] According to some alternative embodiments, in Figures 32A to 32D Explain the cross-section and plan view of the device. Figure 32A It clarifies that in Figure 1 The reference section A-A' is shown in the figure. Figure 32B It clarifies that in Figure 1 The reference section B-B' is shown in the figure. Figure 32C It clarifies that in Figure 1 The reference section C-C' shown in the figure. Figure 32D It clarifies that in Figure 31D A floor plan is shown. Figures 32A to 32D In this context, similar components formed using similar processes are used with... Figures 31A to 31DThe numbering designation is structurally similar within the same category. However, in... Figures 32A to 32D In this design, the channel regions of the n-type region 50N and the p-type region 50P contain the same material. For example, the silicon-containing second nanostructure 54 provides a channel region for a p-type nanosheet field-effect transistor in the p-type region 50P and for an n-type nanosheet field-effect transistor in the n-type region 50N. Figures 32A to 32D The structure can be formed, for example, by simultaneously removing a first nanostructure 52 from both the p-type region 50P and the n-type region 50N; depositing a gate dielectric layer 100 and a gate electrode 102P (as is suitable for the gate electrode of a p-type nanosheet field-effect transistor) around a second nanostructure 54 in the p-type region 50P; and depositing a gate dielectric layer 100 and a gate electrode 102N (as is suitable for the gate electrode of an n-type nanosheet field-effect transistor) around the second nanostructure 54 in the n-type region 50N. In such embodiments, the material of the epitaxial source / drain region 92 may differ in the n-type region 50N from that in the p-type region 50P, as explained above.

[0153] The embodiments offer advantages. For example, by removing a portion of the sacrificial layer adjacent to a nanostructure stack before forming the spacer layer, short circuit formation between the source / drain regions and the gate electrode can be reduced. A portion of the spacer layer is filled into the recess, thus providing a stronger barrier between the subsequently formed source / drain regions and the gate electrode to reduce short circuits, thereby improving device functionality.

[0154] According to one embodiment, a method of forming a semiconductor device includes: forming a sacrificial layer over a first nanostructure stack and an isolation region, the first nanostructure stack comprising alternating plurality of first nanostructures and plurality of second nanostructures, the first nanostructures being a first semiconductor material and the second nanostructures being a second semiconductor material; forming a dummy gate structure over the first nanostructure stack and a first portion of the sacrificial layer; removing a second portion of the sacrificial layer to expose a sidewall of the first nanostructure stack adjacent to the dummy gate structure; forming a spacer layer over the dummy gate structure, a first portion of the spacer layer substantially contacting the sidewall of the first nanostructure stack; forming a first source / drain recess through the first nanostructure stack, the plurality of sidewalls of the first and second nanostructures being exposed in the first source / drain recess; and forming a first source / drain region in the first source / drain recess, the first source / drain region substantially contacting the first portion of the spacer layer. In an embodiment, the method further includes: after forming a first source / drain recess, laterally recessing multiple sidewalls of one of the first nanostructure and the second nanostructure to form a plurality of recessed nanostructures; and forming a plurality of inner spacer walls, each inner spacer wall substantially contacting a respective first sidewall of its recessed nanostructure. In an embodiment, a first portion of the spacer wall layer covers the inner spacer wall of the inner spacer wall. In an embodiment, the method further includes: forming an interlayer dielectric over the dummy gate structure, the first source / drain region, and the first portion of the spacer wall layer; and removing the dummy gate structure. In an embodiment, the method further includes: removing the recessed nanostructure and the remaining portion of the sacrificial layer; and forming a replacement gate structure over the first nanostructure stack, the replacement gate structure being located between multiple remaining nanostructures of the first nanostructure stack, the replacement gate structure covering the sidewall of the first portion of the spacer wall layer. In an embodiment, the replacement gate structure includes a gate electrode and a gate dielectric, the gate dielectric substantially contacting the first portion of the spacer wall layer.

[0155] According to another embodiment, a method of forming a semiconductor device includes: forming a multilayer stack on a semiconductor substrate; patterning the multilayer stack to form a nanostructure stack, the nanostructure stack including alternating plurality of first nanostructures and plurality of second nanostructures, the first nanostructures being a first semiconductor material and the second nanostructures being a second semiconductor material; forming a sacrificial layer along a plurality of sidewalls of the nanostructure stack; forming a dummy gate structure on the nanostructure stack and the sacrificial layer; removing a portion of the sacrificial layer to form a first recess adjacent to the nanostructure stack, the remaining portion of the sacrificial layer covering the dummy gate structure; forming a spacer layer on the dummy gate structure, a first portion of the spacer layer filling the first recess; forming a second recess in the multilayer stack, the second recess adjacent to the dummy gate structure; forming a source / drain region in the second recess, the source / drain region physically contacting the first portion of the spacer layer; removing the dummy gate structure to form a third recess; removing one of the first nanostructures and the second nanostructures and at least a portion of the remaining portion of the sacrificial layer; and forming a gate structure in the third recess. In an embodiment, the sacrificial layer comprises silicon germanium. In an embodiment, the method further includes: laterally recessing a plurality of sidewalls of one of the first nanostructure and the second nanostructure to form a plurality of recessed nanostructures, the sidewalls being adjacent to the second recess; and forming a plurality of internal spacer walls, each adjacent to a recessed nanostructure, the respective plurality of first sidewalls of the respective internal spacer walls being covered by a first portion of the spacer wall layer. In an embodiment, the spacer wall layer comprises silicon oxide, silicon nitride, or silicon oxynitride. In an embodiment, the first portion of the spacer wall layer comprises a first spacer wall layer and a second spacer wall layer, the first spacer wall layer surrounding the second spacer wall layer in top view. In an embodiment, the first spacer wall layer is a first material, the second spacer wall layer is a second material, and the etch rate of the second material is different from the etch rate of the first material. In an embodiment, the first spacer wall layer is located between the second spacer wall layer and the semiconductor substrate. In an embodiment, the second spacer wall layer extends below the first spacer wall layer. In an embodiment, removing a portion of the sacrificial layer to form the first recess includes over-etching the sacrificial layer, wherein after over-etching, the first recess extends below the dummy gate structure. In one embodiment, forming the gate structure comprises forming a gate dielectric on a plurality of exposed surfaces of a plurality of residual nanostructures, wherein the gate dielectric covers a plurality of second sidewalls of a plurality of internal spacer walls and a plurality of third sidewalls of a first portion of the spacer wall layer, each of the respective second sidewalls being adjacent to a respective third sidewall.

[0156] According to yet another embodiment, a semiconductor device includes: a semiconductor substrate; a first channel region on the semiconductor substrate, the first channel region including a first nanostructure stack; a first gate stack on the first channel region, the first gate stack including a first gate electrode and a first gate dielectric; a first source / drain region adjacent to the first channel region; a first inner spacer wall located between a first sidewall of the first source / drain region and the first gate dielectric; and a first spacer wall substantially in contact with a second sidewall of the first source / drain region, and the first spacer wall covering the sidewall of the first inner spacer wall. In an embodiment, the first spacer wall includes a first material and a second material, the second material surrounding the first material in top view, and the etch rate of the second material being different from the etch rate of the first material. In an embodiment, it further includes: a first insulating fin adjacent to the first channel region and the first source / drain region, the first spacer wall located between the first source / drain region and the first insulating fin. In an embodiment, the first spacer wall further extends between the first inner spacer wall and the first insulating fin.

[0157] The foregoing outlines the features of several embodiments to provide a better understanding of the portions disclosed herein for those skilled in the art. Those skilled in the art will recognize that they can readily utilize the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or realize the same advantages of the embodiments described herein. Those proficient in the art will also understand that such identical constructions do not depart from the spirit and scope of this disclosure, and that various modifications, substitutions, and replacements can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor device, characterized in that, include: A sacrificial layer is formed on a first nanostructure stack and an isolation region, the first nanostructure stack comprising alternating first nanostructures and second nanostructures, wherein the multiple first nanostructures are a first semiconductor material and the multiple second nanostructures are a second semiconductor material; A virtual gate structure is formed on the first nanostructure stack and a first portion of the sacrificial layer; A second portion of the sacrificial layer is removed to expose a sidewall of the first nanostructure stack adjacent to the virtual gate structure; A gap wall layer is formed on the virtual gate structure, and a first portion of the gap wall layer physically contacts the sidewall of the first nanostructure stack. A first source / drain recess is formed by the stack of the first nanostructures, and the sidewalls of the plurality of first nanostructures and the plurality of second nanostructures are exposed in the first source / drain recess. as well as A first source / drain region is formed in the first source / drain recess, and the first source / drain region substantially contacts the first portion of the spacer wall layer.

2. The method according to claim 1, characterized in that, Further includes: After forming the first source / drain recess, the sidewalls of one of the plurality of first nanostructures and the plurality of second nanostructures are laterally recessed to form a plurality of recessed nanostructures. as well as Multiple internal spacer walls are formed, each of which physically contacts the respective first sidewall of the recessed nanostructure.

3. The method according to claim 2, characterized in that, The first portion of the spacer wall layer covers one of the plurality of inner spacer walls.

4. The method according to claim 3, characterized in that, Further includes: A layer of interlayer dielectric is formed on the virtual gate structure, the first source / drain region and the first portion of the spacer layer; as well as Remove the virtual gate structure.

5. The method according to claim 4, characterized in that, Further includes: Remove the plurality of recessed nanostructures and a remaining portion of the sacrificial layer; as well as An alternative gate structure is formed on the first nanostructure stack, the alternative gate structure is located between a plurality of remaining nanostructures of the first nanostructure stack, and the alternative gate structure covers one sidewall of the first portion of the spacer wall layer.

6. The method according to claim 5, characterized in that, The replacement gate structure includes a gate electrode and a gate dielectric, the gate dielectric material being in contact with the first portion of the spacer wall layer.

7. A method for forming a semiconductor device, characterized in that, include: A multilayer stack is formed on a semiconductor substrate; The multilayer stack is patterned to form a nanostructure stack comprising alternating first nanostructures and second nanostructures, wherein the first nanostructures are a first semiconductor material and the second nanostructures are a second semiconductor material. A sacrificial layer is formed along multiple sidewalls of the nanostructure stack; A virtual gate structure is formed on the nanostructure stack and the sacrificial layer; A portion of the sacrificial layer is removed to form a first recess adjacent to the nanostructure stack, while the remaining portion of the sacrificial layer is encapsulated in the virtual gate structure; A gap wall layer is formed on the virtual gate structure, and a first portion of the gap wall layer fills the first recess; A second recess is formed in the multilayer stack, and the second recess is adjacent to the virtual gate structure; A source / drain region is formed in the second recess, and the source / drain region substantially contacts the first portion of the spacer wall layer; Remove the dummy gate structure to form a third recess; Remove a portion of the remaining portion of the plurality of first nanostructures and the plurality of second nanostructures; as well as A gate structure is formed in the third recess.

8. The method according to claim 7, characterized in that, The sacrificial layer contains silicon germanium.

9. The method according to claim 7, characterized in that, Further includes: A plurality of sidewalls of one of the plurality of first nanostructures and the plurality of second nanostructures are laterally recessed to form a plurality of recessed nanostructures, wherein the plurality of sidewalls are adjacent to the second recess; as well as Multiple internal spacer walls are formed adjacent to the plurality of recessed nanostructures, and the plurality of first sidewalls of each of the plurality of internal spacer walls are covered by the first portion of the spacer wall layer.

10. The method according to claim 7, characterized in that, The spacer wall layer contains silicon oxide, silicon nitride, or silicon oxynitride.

11. The method according to claim 7, characterized in that, The first portion of the spacer wall layer includes a first spacer wall layer and a second spacer wall layer, with the first spacer wall layer surrounding the second spacer wall layer in a top view.

12. The method according to claim 11, characterized in that, The first gap wall layer is a first material, and the second gap wall layer is a second material, the etching rate of the second material is different from the etching rate of the first material.

13. The method according to claim 11, characterized in that, The first gap wall layer is located between the second gap wall layer and the semiconductor substrate.

14. The method according to claim 11, characterized in that, The second gap wall layer extends below the first gap wall layer.

15. The method according to claim 7, characterized in that, Removing a portion of the sacrificial layer to form the first recess involves over-etching the sacrificial layer, wherein the first recess extends beneath the dummy gate structure after the over-etching.

16. The method according to claim 7, characterized in that, The formation of the gate structure includes forming a gate dielectric on multiple exposed surfaces of multiple remaining nanostructures, wherein the gate dielectric covers multiple second sidewalls of each of the multiple inner spacer walls and multiple third sidewalls of the first portion of the spacer wall layer, each of the multiple second sidewalls being adjacent to its respective third sidewall.

17. A semiconductor device, characterized in that, include: A semiconductor substrate; A first channel region is located on the semiconductor substrate, the first channel region comprising a first nanostructure stack; A first gate stack is disposed on the first channel region, the first gate stack comprising a first gate electrode and a first gate dielectric; A first source / drain region, which is adjacent to the first channel region; A first inner spacer wall, the first inner spacer wall being located between a first sidewall of the first source / drain region and the first gate dielectric; as well as A first gap wall is in solid contact with a second sidewall of the first source / drain region, and the first gap wall covers one sidewall of the first inner gap wall.

18. The semiconductor device according to claim 17, characterized in that, The first gap wall comprises a first material and a second material, wherein the second material surrounds the first material when viewed from above, and the etching rate of the second material is different from that of the first material.

19. The semiconductor device according to claim 17, characterized in that, Further includes: A first insulating fin is adjacent to the first channel region and the first source / drain region, and a first gap wall is located between the first source / drain region and the first insulating fin.

20. The semiconductor device according to claim 19, characterized in that, The first gap wall extends between the first inner gap wall and the first insulating fin.

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