Semiconductor package and method of forming the same

Abstract

A semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer, and an encapsulation. The first semiconductor device is disposed on and electrically connected to the redistribution structure, the first semiconductor device having a first bottom surface, a first top surface, and a first side surface connected to the first bottom surface and the first top surface, the first side surface including first and second sub-surfaces connected to each other, the first sub-surface connected to the first bottom surface, and a first obtuse angle between the first and second sub-surfaces. The second semiconductor device is disposed on and electrically connected to the redistribution structure, the second semiconductor device having a second bottom surface, a second top surface, and a second side surface connected to the second bottom surface and the second top surface, the second side surface facing the first side surface, the second side surface including third and fourth sub-surfaces connected to each other, the third sub-surface connected to the second bottom surface, and a second obtuse angle between the third and fourth sub-surfaces. The underfill layer is between the first semiconductor device and the second semiconductor device, between the first semiconductor device and the redistribution structure, and between the second semiconductor device and the redistribution structure. The encapsulation encapsulates the first semiconductor device, the second semiconductor device, and the underfill layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor package and a method for forming the same. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). In most cases, this increase in integration density stems from the continuous reduction in the minimum feature size, allowing more smaller components to be integrated into a given area. These smaller electronic components require smaller packages that occupy less area than previous packages. Some smaller types of packages used for semiconductor devices include quad flat packages (QFP), pin grid array (PGA) packages, and ball grid array (BGA) packages. Currently, integrated fan-out packages are becoming increasingly popular due to their density. Summary of the Invention

[0003] According to an embodiment of the present invention, a semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill adhesive layer, and an encapsulator. The first semiconductor device is disposed on and electrically connected to the redistribution structure. The first semiconductor device has a first bottom surface, a first top surface, and a first side surface connected to the first bottom surface and the first top surface. The first side surface includes a first sub-surface and a second sub-surface connected to each other. The first sub-surface is connected to the first bottom surface, and a first obtuse angle is located between the first sub-surface and the second sub-surface. The second semiconductor device is disposed on and electrically connected to the redistribution structure. The second semiconductor device has a second bottom surface, a second top surface, and a second side surface connected to the second bottom surface and the second top surface. The second side surface faces the first side surface. The second side surface includes a third sub-surface and a fourth sub-surface connected to each other. The third sub-surface is connected to the second bottom surface, and a second obtuse angle is located between the third sub-surface and the fourth sub-surface. The underfill adhesive layer is located between the first semiconductor device and the second semiconductor device, between the first semiconductor device and the redistribution structure, and between the second semiconductor device and the redistribution structure. The encapsulation body encapsulates the first semiconductor device, the second semiconductor device, and the bottom filler layer.

[0004] According to an embodiment of the present invention, a semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill adhesive layer, and an encapsulator. The first semiconductor device is disposed on and electrically connected to the redistribution structure, wherein the first semiconductor device includes a first portion and a second portion stacked on the first portion along a first direction, the first portion having a first inclined side surface, the second portion having a second inclined side surface connected to the first inclined side surface, and the slope of the first inclined side surface being less than the slope of the second inclined side surface. The second semiconductor device is disposed adjacent to the first semiconductor device and electrically connected to the redistribution structure, wherein the second semiconductor device includes a third portion and a fourth portion stacked on the third portion along the first direction, the third portion having a third inclined side surface, the fourth portion having a fourth inclined side surface connected to the third inclined side surface, a space located between the first semiconductor device and the second semiconductor device and formed and sandwiched by the first inclined side surface, the second inclined side surface, the third inclined side surface, and the fourth inclined side surface, and the slope of the third inclined side surface being less than the slope of the fourth inclined side surface. The underfill adhesive layer fills the space between the first semiconductor device and the second semiconductor device. The encapsulation body encapsulates the first semiconductor device, the second semiconductor device, and the bottom filler layer.

[0005] According to an embodiment of the present invention, a method of forming a semiconductor package includes at least the following steps: Providing a first semiconductor device having a first side surface connected to a first bottom surface and a first top surface, wherein the first side surface includes a first sub-surface and a second sub-surface interconnected, the first sub-surface being connected to the first bottom surface, and a first obtuse angle located between the first sub-surface and the second sub-surface. Providing a second semiconductor device having a second side surface connected to a second bottom surface and a second top surface, wherein the second side surface includes a third sub-surface and a fourth sub-surface interconnected, the third sub-surface being connected to the second bottom surface, and a second obtuse angle located between the third sub-surface and the fourth sub-surface. Forming a redistribution structure. Bonding the first semiconductor device and the second semiconductor device to the redistribution structure such that the first side surface faces the second side surface. Forming an underfill adhesive layer between the first semiconductor device and the second semiconductor device, between the first semiconductor device and the redistribution structure, and between the second semiconductor device and the redistribution structure. Encapsulating the first semiconductor device, the second semiconductor device, and the underfill adhesive layer with an encapsulator. Attached Figure Description

[0006] The aspects of this disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 This is a schematic cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

[0008] Figure 2A yes Figure 1 A magnified view of the area R1 within the dashed line region.

[0009] Figure 2B yes Figure 1 A magnified view of the area R2 within the dashed line region.

[0010] Figure 3 This is a simplified top view of a semiconductor package according to some embodiments of the present disclosure.

[0011] Figures 4A to 4E This is a schematic cross-sectional view illustrating the manufacturing process of a semiconductor device according to some embodiments of the present disclosure.

[0012] Figures 5A to 5C This is a schematic cross-sectional view illustrating the manufacturing process of a semiconductor device according to some embodiments of the present disclosure.

[0013] Figures 6A to 6F This is a schematic cross-sectional view illustrating a manufacturing process for a semiconductor package according to some embodiments of the present disclosure.

[0014] Figure 7 It is shown Figure 6C A schematic top view of the intermediate stage during the formation of the underfill layer in the process.

[0015] Figure 8 This is a schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the present disclosure.

[0016] Figure 9 This is a schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the present disclosure.

[0017] Figure 10 This is a schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the present disclosure.

[0018] Figure 11A yes Figure 10 A magnified view of the area R1 within the dashed line region.

[0019] Figure 11B yes Figure 10A magnified view of the area R2 within the dashed line region.

[0020] Figure 12 This is a schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the present disclosure.

[0021] Figure 13 This is a schematic cross-sectional view illustrating the application of a semiconductor structure according to some embodiments of the present disclosure.

[0022] Explanation of icon numbers

[0023] 100, 200, 300, 400, 500: Semiconductor packaging;

[0024] 110: Rewiring structure;

[0025] 110a: First surface;

[0026] 110b: Second surface;

[0027] 112: Dielectric layer;

[0028] 114: Conductive layer;

[0029] 120, 130: Semiconductor devices;

[0030] 120B, 130B: Rear surface;

[0031] 120F, 130F: Front surface;

[0032] 120P1, 120P2, 130P1, 130P2: Partial list;

[0033] 120S1, 120S2, 120S3, 120S4, 130S1, 130S2, 130S3, 130S4: side surfaces;

[0034] 120S11, 120S12, 120S13, 120S14, 120S15, 120S16, 120S31, 120S32, 120S33, 120S34, 120S35, 120S36, 130S11, 130S12, 130S13, 130S14, 130S15: Sub-surfaces;

[0035] 122, 132: Connection structure;

[0036] 122a, 132a: Conductive connectors;

[0037] 122b, 132b: Solder cap;

[0038] 140. UF: Bottom filler adhesive layer;

[0039] 150: Encapsulation body;

[0040] 160: Electrical terminal;

[0041] B1, B2: Blade;

[0042] BS1, BS2: Joint structure;

[0043] C: Carrier;

[0044] C1: First component;

[0045] C2: Second component;

[0046] CT: Terminal;

[0047] D1, D3: Maximum distance;

[0048] D2, D4: Minimum distance;

[0049] DB: Peeling layer;

[0050] DD: Distance difference;

[0051] P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15: Virtual planes;

[0052] R1, R2: Dashed area;

[0053] S1, S2: Space;

[0054] SC: Component Assembly;

[0055] T1, T2, T3, T4: Thickness;

[0056] TP: Tape frame;

[0057] W1, W2: Width;

[0058] X, Z: Direction;

[0059] θ1, θ2, θ3, θ4, θ5, θ6, θ7, θ8, θ9, θa, θb, θc, θd, θe, θf, θg, θh, θi, θj, θk: included angle;

[0060] θ10, θ11: sharp angles. Detailed Implementation

[0061] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features so that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, define a relationship between the various embodiments and / or configurations discussed.

[0062] Additionally, for ease of description, spatially relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms may be used to describe the relationship between one element or feature and another, as shown in the figures. Besides the orientations depicted in the figures, the spatially relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0063] Other features and processes may also be included. For example, test structures may be included to aid in the verification testing of three-dimensional (3D) packaged or three-dimensional integrated circuit (3DIC) devices. These test structures may include, for example, test pads formed in redistribution layers or on a substrate, to enable testing of 3D packages or 3DICs using probes and / or probe cards. Verification testing can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with test methods that include intermediate verification of known good dies to improve yield and reduce costs.

[0064] Figure 1 This is a schematic cross-sectional view of a semiconductor package 100 according to some embodiments of the present disclosure. Figure 2A yes Figure 1 A magnified view of the area R1 within the dashed line region. Figure 2B yes Figure 1 A magnified view of the area R2 within the dashed line region. Figure 3 This is a simplified top view of a semiconductor package 100 according to some embodiments of the present disclosure. For simplicity and clarity, Figure 3Some components are omitted in the simplified top view, and these components may not be in the same plane. Semiconductor package 100 may be an integrated fan-out (“InFO”) package.

[0065] refer to Figure 1 , Figure 2A , Figure 2B and Figure 3 Semiconductor package 100 includes a redistribution structure 110, semiconductor devices 120, a plurality of semiconductor devices 130, an underfill adhesive layer 140, and an encapsulation body 150. In some embodiments, semiconductor package 100 further includes a plurality of electrical terminals 160. Semiconductor devices 120 are disposed on and electrically connected to the redistribution structure 110. Figure 1 As shown, semiconductor device 120 is electrically connected to redistribution structure 110 via multiple bonding structures BS1. Semiconductor device 130 is disposed on and electrically connected to redistribution structure 110. Figure 1 As shown, each semiconductor device 130 is disposed next to semiconductor device 120. Specifically, as Figure 1 As shown, one of the plurality of semiconductor devices 130 has a side surface 130S1 facing the side surface 120S1 of the semiconductor device 120, and another of the plurality of semiconductor devices 130 has a side surface 130S1 facing the side surface 120S3 of the semiconductor device 120, and side surfaces 120S1 and 120S3 are opposite to each other. That is, the plurality of semiconductor devices 130 are disposed on opposite sides of the semiconductor device 120. Furthermore, as... Figure 1 As shown, semiconductor devices 130 are electrically connected to redistribution structure 110 via multiple bonding structures BS2. Underfill adhesive layer 140 is located between semiconductor devices 120 and each semiconductor device 130, between semiconductor devices 120 and redistribution structure 110, and between each semiconductor device 130 and redistribution structure 110. Figure 1 , Figure 2A , Figure 2B and Figure 3As shown, semiconductor device 120 is partially encapsulated by underfill adhesive layer 140, and each semiconductor device 130 is also partially encapsulated by underfill adhesive layer 140. That is, underfill adhesive layer 140 covers a portion of each of the side surfaces 120S1, 120S2, 120S3, and 120S4 of semiconductor device 120, and a portion of each of the side surfaces 130S1, 130S2, 130S3, and 130S4 of each semiconductor device 130. Furthermore, underfill adhesive layer 140 surrounds each bonding structure BS1 and each bonding structure BS2. Due to underfill adhesive layer 140, the bonding strength between semiconductor device 120 and redistribution structure 110, and between each semiconductor device 130 and redistribution structure 110, is enhanced, thereby improving the reliability of semiconductor package 100. Encapsulation body 150 encapsulates semiconductor device 120, each semiconductor device 130, and underfill adhesive layer 140. Electrical terminals 160 are disposed on the redistribution structure 110 and opposite to semiconductor devices 120 and 130. That is, electrical terminals 160 are disposed on the side of the redistribution structure 110 opposite to the side where semiconductor devices 120 and 130 are located. Furthermore, electrical terminals 160 are electrically connected to the redistribution structure 110. In other words, in some embodiments, electrical terminals 160 are electrically connected to semiconductor devices 120 and 130 via the redistribution structure 110.

[0066] In some embodiments, each of semiconductor device 120 and the plurality of semiconductor devices 130 is a logic die, a memory die, an application-specific integrated circuit (ASIC) die, a sensor die, a wireless and radio frequency die, an analog die, a voltage regulator die, an integrated passive device (IPD), or any other suitable device. In some embodiments, semiconductor device 120 is a system-on-a-chip (SoC), and semiconductor device 130 is a high bandwidth memory (HBM) die. In some embodiments, the plurality of semiconductor devices 130 have the same functions and characteristics (e.g., both are HBM dies). However, this disclosure is not limited thereto. In some alternative embodiments, the plurality of semiconductor devices 130 may have different functions and characteristics.

[0067] like Figure 1 , Figure 2A , Figure 2B and Figure 3As shown, although two semiconductor devices 130 are presented around the semiconductor device 120 in the semiconductor package 100 for illustrative purposes, those skilled in the art will understand that the number of semiconductor devices 130 may be more or less. Figure 1 , Figure 2A , Figure 2B and Figure 3 As depicted herein, and can be specified based on requirements and / or design layout. It is worth noting that when the semiconductor package 100 includes more than two semiconductor devices 130 surrounding the semiconductor device 120, more than two side surfaces of the semiconductor device 120 may face the semiconductor device 130. Further, as... Figure 1 As shown, although the semiconductor package 100 is illustrated using four bonding structures BS1 and two bonding structures BS2 as examples, those skilled in the art will understand that the number of bonding structures BS1 and the number of bonding structures BS2 may be more or less than [the number of bonding structures BS1 and BS2]. Figure 1 As described herein, and can be specified according to requirements and / or design layout.

[0068] like Figure 1 and Figure 3 As shown, the width W1 of semiconductor device 120 is greater than the width W2 of each semiconductor device 130. However, this disclosure is not limited thereto. In some alternative embodiments, the width W1 of semiconductor device 120 may be equal to or less than the width W2 of each semiconductor device 130. Furthermore, as... Figure 1 and Figure 3 As shown, the width W2 of the plurality of semiconductor devices 130 is the same as that of each other. However, this disclosure is not limited thereto. In some alternative embodiments, the width W2 of the plurality of semiconductor devices 130 is different from that of each other.

[0069] like Figure 1 , Figure 2A , Figure 2B and Figure 3 As shown, each of the side surfaces 120S1, 120S2, 120S3, and 120S4 of the semiconductor device 120 is connected to the front surface 120F (i.e., the bottom surface shown) and the rear surface 120B (i.e., the top surface shown), respectively, of the semiconductor device 120. The side surface 120S1 of the semiconductor device 120 includes interconnected sub-surfaces 120S11 and 120S12. Specifically, as... Figure 1As shown, sub-surface 120S11 is connected to the front surface 120F, and sub-surface 120S12 is connected to the rear surface 120B. That is, the side surface 120S1 of the semiconductor device 120 is composed of only two sub-surfaces (i.e., sub-surface 120S11 and sub-surface 120S12). However, this disclosure is not limited thereto. In some alternative embodiments, the side surface 120S1 of the semiconductor device 120 may be composed of more than two sub-surfaces. From another perspective, the sub-surface 120S11 connected to the front surface 120F is closer to the redistribution structure 110 than the sub-surface 120S12 connected to the rear surface 120B.

[0070] In some embodiments, sub-surface 120S11 and sub-surface 120S12 form an obtuse angle. For example... Figure 2A As shown, the angle θ1 between sub-surface 120S11 and sub-surface 120S12 is an obtuse angle. In some embodiments, the angle θ1 ranges from greater than 91° to less than 180°. In some embodiments, such as Figure 2A As shown, sub-surfaces 120S11 and 120S12 are inclined side surfaces. Specifically, angle θ2 lies between sub-surface 120S11 and a virtual plane P1 parallel to direction Z, and angle θ3 lies between sub-surface 120S12 and a virtual plane P2 parallel to direction Z, wherein direction Z is perpendicular to direction X and perpendicular to the rear surface 120B. In some embodiments, as Figure 2A As shown, the angle θ2 between sub-surface 120S11 and virtual plane P1 is greater than the angle θ3 between sub-surface 120S12 and virtual plane P2. That is, as... Figure 2A As shown, in semiconductor device 120, the slope of sub-surface 120S11 connected to front surface 120F is less than the slope of sub-surface 120S12 connected to sub-surface 120S11. With this configuration, the uniformity of the flow field of underfill adhesive layer 140 is improved during the formation process of underfill adhesive layer 140.

[0071] The side surface 120S3 of the semiconductor device 120 includes interconnected sub-surfaces 120S31 and 120S32. Specifically, as... Figure 2B As shown, sub-surface 120S31 is connected to the front surface 120F, and sub-surface 120S32 is connected to the rear surface 120B. That is, the side surface 120S3 of the semiconductor device 120 is composed of only two sub-surfaces (i.e., sub-surface 120S31 and sub-surface 120S32). However, this disclosure is not limited thereto. In some alternative embodiments, the side surface 120S3 of the semiconductor device 120 may be composed of more than two sub-surfaces. From another perspective, sub-surface 120S31, connected to the front surface 120F, is closer to the redistribution structure 110 than sub-surface 120S32, connected to the rear surface 120B.

[0072] In some embodiments, sub-surface 120S31 and sub-surface 120S32 form an obtuse angle. For example... Figure 2B As shown, the angle θ4 between sub-surface 120S31 and sub-surface 120S32 is an obtuse angle. In some embodiments, the angle θ4 ranges from greater than 91° to less than 180°. In some embodiments, such as Figure 2B As shown, sub-surfaces 120S31 and 120S32 are inclined side surfaces. Specifically, the included angle θ5 lies between sub-surface 120S31 and the virtual plane P3 parallel to the Z direction, and the included angle θ6 lies between sub-surface 120S32 and the virtual plane P4 parallel to the Z direction. In some embodiments, as... Figure 2B As shown, the angle θ5 between sub-surface 120S31 and virtual plane P3 is greater than the angle θ6 between sub-surface 120S32 and virtual plane P4. That is, as... Figure 2B As shown, in semiconductor device 120, the slope of sub-surface 120S31 connected to front surface 120F is less than the slope of sub-surface 120S32 connected to sub-surface 120S31. With this configuration, the uniformity of the flow field of underfill adhesive layer 140 is improved during the formation process of underfill adhesive layer 140.

[0073] like Figure 1 , Figure 2A and Figure 2B As shown, the included angle θ4 of side surface 120S3 is the same as the included angle θ1 of side surface 120S1. However, this disclosure is not limited thereto. In some alternative embodiments, reference is made to... Figure 8 In semiconductor package 200, the included angle θ4 of side surface 120S3 is different from the included angle θ1 of side surface 120S1. From another perspective, as... Figure 1 As shown, the included angles θ2 and θ5 are the same, and the included angles θ3 and θ6 are the same. However, this disclosure is not limited thereto. In some alternative embodiments, the included angle θ2 is different from the included angle θ5, and / or the included angle θ3 is different from the included angle θ6. For example, as... Figure 8 As shown in the embodiment, the included angle θ2 is different from the included angle θ5, while the included angle θ3 is the same as the included angle θ6.

[0074] In some embodiments, such as Figure 1 , Figure 2A , Figure 2B and Figure 3As shown, the side surfaces 120S2 and 120S4 of the semiconductor device 120 that do not face any other semiconductor device are perpendicular side surfaces. That is, side surfaces 120S2 and 120S4 extend substantially along the direction Z. In other words, the extension direction of each of side surfaces 120S2 and 120S4 has an angular offset of less than 1° from the direction Z.

[0075] In some embodiments, such as Figure 1 , Figure 2A and Figure 2B As shown, the semiconductor device 120 includes a portion 120P1 and a portion 120P2 stacked on the portion 120P1 along the Z direction. The portion 120P1 has sub-surfaces 120S11 and 120S31, and the portion 120P2 has sub-surfaces 120S12 and 120S32. That is, the portion 120P1 is closer to the redistribution structure 110 than the portion 120P2. In some embodiments, such as... Figure 1 As shown, the bonding structure BS1 is in contact with a portion 120P1 of the first semiconductor device 120.

[0076] In some embodiments, such as Figure 1 , Figure 2A and Figure 2B As shown, along direction Z, the thickness T1 of portion 120P1 is less than the thickness T2 of portion 120P2. In Figure 1 , Figure 2A and Figure 2B In this configuration, each of the included angles θ2, θ3, θ5, and θ6 is less than 45 degrees and greater than or equal to 1 degree. However, this disclosure is not limited thereto. In some alternative embodiments, along the Z direction, the thickness T1 of portion 120P1 may be equal to or greater than the thickness T2 of portion 120P2, and each of the included angles θ2, θ3, θ5, and θ6 is less than 30 degrees and greater than or equal to 1 degree. With the configuration where each of the included angles θ2, θ3, θ5, and θ6 is less than 45 degrees and greater than 0 degrees or less than 30 degrees and greater than 0 degrees, the circuit structure and electrical components of the semiconductor device 120 can avoid damage due to the formation processes of surfaces 120S11, 120S12, 120S31, and 120S32.

[0077] like Figure 1 , Figure 2A and Figure 2B As shown, portion 120P1 has a constant thickness (i.e., thickness T1), while portion 120P2 has a constant thickness (i.e., thickness T2). However, this disclosure is not limited thereto. In some alternative embodiments, reference is made to... Figure 8In the semiconductor package 200, the thickness of a portion of 120P1 varies continuously along the X direction, and the thickness of a portion of 120P2 varies continuously along the X direction.

[0078] like Figure 1 , Figure 2A , Figure 2B and Figure 3 As shown, each of the side surfaces 130S1, 130S2, 130S3, and 130S4 of the semiconductor device 130 is connected to the front surface 130F (i.e., the bottom surface shown) and the rear surface 130B (i.e., the top surface shown), respectively, of the semiconductor device 130. The side surface 130S1 of the semiconductor device 130 includes interconnected sub-surfaces 130S11 and 130S12. Specifically, as... Figure 1 , Figure 2A , Figure 2B As shown, sub-surface 130S11 is connected to the front surface 130F, and sub-surface 130S12 is connected to the rear surface 130B. That is, the side surface 130S1 of the semiconductor device 130 is composed of only two sub-surfaces (i.e., sub-surface 130S11 and sub-surface 130S12). However, this disclosure is not limited thereto. In some alternative embodiments, the side surface 130S1 of the semiconductor device 130 may be composed of more than two sub-surfaces. From another perspective, sub-surface 130S11, connected to the front surface 130F, is closer to the redistribution structure 110 than sub-surface 130S12, connected to the rear surface 130B.

[0079] In some embodiments, sub-surface 130S11 and sub-surface 130S12 form an obtuse angle. For example... Figure 1 , Figure 2A and Figure 2B As shown, the angle θ7 between sub-surface 130S11 and sub-surface 130S12 is an obtuse angle. In some embodiments, the angle θ7 ranges from greater than 91° to less than 180°. In some embodiments, such as Figure 1 , Figure 2A and Figure 2B As shown, sub-surfaces 130S11 and 130S12 are inclined side surfaces. Specifically, the included angle θ8 lies between sub-surface 130S11 and the virtual plane P5 parallel to the Z direction, and the included angle θ9 lies between sub-surface 130S12 and the virtual plane P6 parallel to the Z direction. In some embodiments, as... Figure 1 , Figure 2A and Figure 2B As shown, the angle θ8 between sub-surface 130S11 and virtual plane P5 is greater than the angle θ9 between sub-surface 130S12 and virtual plane P6. That is, as... Figure 1 , Figure 2A and Figure 2BAs shown, in semiconductor device 130, the slope of sub-surface 130S11 connected to front surface 130F is less than the slope of sub-surface 130S12 connected to sub-surface 130S11. With this configuration, the uniformity of the flow field of underfill adhesive layer 140 is improved during the formation process of underfill adhesive layer 140.

[0080] like Figure 1 , Figure 2A and Figure 2B As shown, the included angles θ7, θ8, and θ9 of the two semiconductor devices 130 are the same. However, this disclosure is not limited thereto. In some alternative embodiments, the included angles θ7, θ8, and θ9 of the two semiconductor devices 130 are different from each other. For example, refer to... Figure 9 In the semiconductor package 300, the included angle θ9 of the two semiconductor devices 130 is the same, while the included angle θ7 of the two semiconductor devices 130 is different, and the included angle θ8 of the two semiconductor devices 130 is different.

[0081] From another perspective, such as Figure 1 , Figure 2A and Figure 2B As shown, the included angle θ7 of each semiconductor device 130 is the same as the included angles θ1 and θ4 of semiconductor device 120, the included angle θ8 of each semiconductor device 130 is the same as the included angles θ2 and θ5 of semiconductor device 120, and the included angle θ9 of each semiconductor device 130 is the same as the included angles θ3 and θ6 of semiconductor device 120. However, this disclosure is not limited thereto. In some alternative embodiments, the included angle θ7 of semiconductor device 130 may be different from the included angles θ1 and / or θ4 of semiconductor device 120, the included angle θ8 of semiconductor device 130 may be different from the included angles θ2 and / or θ5 of semiconductor device 120, and / or the included angle θ9 of semiconductor device 130 may be different from the included angles θ3 and / or θ6 of semiconductor device 120. For example, as Figure 8 As shown in the embodiment, the included angles θ7, θ8, and θ9 of one of the plurality of semiconductor devices 130 are the same as the included angles θ4, θ5, and θ6 of semiconductor device 120, respectively, while the included angles θ7 and θ8 of another of the plurality of semiconductor devices 130 are different from the included angles θ1 and θ2 of semiconductor device 120, respectively, and the included angle θ9 of the other of the plurality of semiconductor devices 130 is the same as the included angle θ3 of semiconductor device 120. For example, as... Figure 9As shown in the embodiment, the included angles θ7, θ8 and θ9 of one of the plurality of semiconductor devices 130 are the same as the included angles θ1, θ2 and θ3 of semiconductor device 120, respectively, while the included angles θ7 and θ8 of another of the plurality of semiconductor devices 130 are different from the included angles θ4 and θ5 of semiconductor device 120, respectively, and the included angle θ9 of another of the plurality of semiconductor devices 130 is the same as the included angle θ6 of semiconductor device 120.

[0082] In some embodiments, such as Figure 1 , Figure 2A , Figure 2B and Figure 3 As shown, the side surfaces 130S2, 130S3, and 130S4 of the semiconductor device 130 that do not face any other semiconductor device are vertical side surfaces. That is, the side surfaces 130S2, 130S3, and 130S4 extend substantially along the direction Z. In other words, the extension direction of each of the side surfaces 130S2, 130S3, and 130S4 has an angular offset of less than 1° from the direction Z.

[0083] In some embodiments, such as Figure 1 , Figure 2A and Figure 2B As shown, each semiconductor device 130 includes a portion 130P1 and a portion 130P2 stacked on the portion 130P1 along the Z direction. The portion 130P1 has a sub-surface 130S11, and the portion 130P2 has a sub-surface 130S12. That is, the portion 130P1 is closer to the redistribution structure 110 than the portion 130P2. In some embodiments, such as Figure 1 As shown, the bonding structure BS2 is in contact with a portion 130P1 of the semiconductor device 130.

[0084] In some embodiments, such as Figure 1 , Figure 2A and Figure 2B As shown, along direction Z, the thickness T3 of portion 130P1 is less than the thickness T4 of portion 130P2. In Figure 1 , Figure 2A and Figure 2B In this configuration, both included angles θ8 and θ9 are less than 45 degrees and greater than or equal to 1 degree. However, this disclosure is not limited thereto. In some alternative embodiments, along direction Z, the thickness T3 of portion 130P1 may be equal to or greater than the thickness T4 of portion 130P2, and both included angles θ8 and θ9 are less than 30 degrees and greater than or equal to 1 degree. With the configuration where both included angles θ8 and θ9 are less than 45 degrees and greater than or equal to 1 degree or less than 30 degrees and greater than or equal to 1 degree, the circuit structure and electrical components of semiconductor device 130 can avoid damage to the formation process of sub-surface 130S11 and sub-surface 130S12.

[0085] like Figure 1 , Figure 2A and Figure 2B As shown, the thickness T3 of portions 130P1 in the two semiconductor devices 130 is the same, and the thickness T4 of portions 130P2 in the two semiconductor devices 130 is the same. However, this disclosure is not limited thereto. In some alternative embodiments, reference is made to... Figure 9 In the semiconductor package 300, the thickness T3 of a portion 130P1 in one of the plurality of semiconductor devices 130 is different from the thickness T3 of a portion 130P1 in another of the plurality of semiconductor devices 130, and the thickness T4 of one of the plurality of semiconductor devices 130 is different from the thickness T4 of a portion 130P2 in another of the plurality of semiconductor devices 130.

[0086] In some embodiments, such as Figure 1 , Figure 2A , Figure 2B and Figure 3 As shown, semiconductor device 130 and semiconductor device 120 are separated laterally. That is, semiconductor device 130 and semiconductor device 120 are spaced apart along direction X. In other words, along direction X, the side surface 120S1 of semiconductor device 120 is spaced apart from the corresponding side surface 130S1 of semiconductor device 130, and the side surface 120S3 of semiconductor device 120 is spaced apart from the corresponding side surface 130S1 of semiconductor device 130. Specifically, as... Figure 1 , Figure 2A , Figure 2B and Figure 3 As shown, along direction X, the sub-surface 120S11 of semiconductor device 120 is separated from the corresponding sub-surface 130S11 of semiconductor device 130 by a maximum distance D1, the sub-surface 120S31 of semiconductor device 120 is separated from the corresponding sub-surface 130S11 of semiconductor device 130 by a maximum distance D3, the sub-surface 120S12 of semiconductor device 120 is separated from the corresponding sub-surface 130S12 of semiconductor device 130 by a minimum distance D2, and the sub-surface 120S32 of semiconductor device 120 is separated from the corresponding sub-surface 130S12 of semiconductor device 130 by a minimum distance D4.

[0087] In some embodiments, such as Figure 1 , Figure 2A , Figure 2B and Figure 3As shown, since the front surfaces 120F and 130F are coplanar and the rear surfaces 120B and 130B are coplanar, the maximum distance D1 between sub-surfaces 120S11 and 130S11 is the minimum distance between the front surfaces 120F and 130F; the maximum distance D3 between sub-surfaces 120S31 and 130S11 is the minimum distance between the front surfaces 120F and 130F; the minimum distance D2 between sub-surfaces 120S12 and 130S12 is the minimum distance between the rear surfaces 120B and 130B; and the minimum distance D4 between sub-surfaces 120S32 and 130S12 is the minimum distance between the rear surfaces 120B and 130B. However, this disclosure is not limited thereto. In some alternative embodiments, when the current surface 130F is higher than the front surface 120F (i.e., the front surface 120F and the front surface 130F are not coplanar), the maximum distance D1 between sub-surface 120S11 and sub-surface 130S11 can be the minimum distance between the front surface 130F and sub-surface 120S11 along the X direction. Similarly, in some alternative embodiments, when the rear surface 120B is higher than the rear surface 130B (i.e., the rear surface 120B and the rear surface 130B are not coplanar), the maximum distance D2 between sub-surface 120S12 and sub-surface 130S12 can be the minimum distance between the rear surface 130B and sub-surface 120S12 along the X direction.

[0088] From another perspective, such as Figure 1 , Figure 2A , Figure 2B and Figure 3 As shown, the maximum distance D1 between sub-surfaces 120S11 and 130S11 and the minimum distance D2 between sub-surfaces 120S12 and 130S12 are the bottom and top lateral dimensions of the space S1 between semiconductor devices 120 and 130, respectively, defined by sub-surfaces 120S11, 130S11, 120S12, and 130S12. Similarly, the maximum distance D3 between sub-surfaces 120S31 and 130S11 and the minimum distance D4 between sub-surfaces 120S32 and 130S12 are the bottom and top lateral dimensions of the space S2 between semiconductor devices 120 and 130, respectively, defined by sub-surfaces 120S31, 130S11, 120S32, and 130S12.

[0089] In some embodiments, both the minimum distance D2 and the minimum distance D4 are less than 400 μm. In some embodiments, the maximum distance D1 between sub-surface 120S11 and sub-surface 130S11 is greater than the minimum distance D2 between sub-surface 120S12 and sub-surface 130S12, and the maximum distance D3 between sub-surface 120S31 and sub-surface 130S11 is greater than the minimum distance D4 between sub-surface 120S32 and sub-surface 130S12. That is, the lateral dimension of space S1 continuously decreases along a direction parallel to the Z direction, from the front surface 120F of semiconductor device 120 to the rear surface 120B of semiconductor device 120. Furthermore, the lateral dimension of space S2 continuously decreases along a direction parallel to the Z direction, from the front surface 120F of semiconductor device 120 to the rear surface 120B of semiconductor device 120. In other words, the minimum lateral distance separating the side surface 120S1 of semiconductor device 120 from the corresponding side surface 130S1 of semiconductor device 130 is the minimum distance D2 between sub-surface 120S12 and sub-surface 130S12, and the minimum lateral distance separating the side surface 120S3 of semiconductor device 120 from the corresponding side surface 130S1 of semiconductor device 130 is the minimum distance D4 between sub-surface 120S32 and sub-surface 130S12. In some embodiments, the maximum distance D1 between sub-surface 120S11 and sub-surface 130S11 is greater than 1.25 times the minimum distance D2 between sub-surface 120S12 and sub-surface 130S12, and the maximum distance D3 between sub-surface 120S31 and sub-surface 130S12 is greater than 1.25 times the minimum distance D4 between sub-surface 120S32 and sub-surface 130S12.

[0090] In conventional cases where the space between two semiconductor devices has a constant lateral dimension of less than 400 μm, the flow field uniformity of the underfill layer is poor during the formation process, making it easy for voids to form in the underfill layer and reducing the mechanical stability of the semiconductor package. Therefore, by arranging the space (e.g., space S1 or space S2) between the two semiconductor devices (e.g., semiconductor devices 120, 130) such that its lateral dimension continuously decreases along the direction from the front surface (e.g., front surface 120F, 130F) to the rear surface (e.g., rear surface 120B, 130B) of the two semiconductor devices and has a minimum lateral dimension of less than 400 μm, the flow field uniformity of the underfill layer (e.g., underfill layer 140) is improved, making it possible to eliminate the void problem seen in conventional underfill layers, thereby improving the mechanical stability of the semiconductor package (e.g., semiconductor package 100).

[0091] The following will refer to Figures 4A to 6FA method for forming semiconductor package 100 is described in detail. Figures 4A to 4E This is a schematic cross-sectional view illustrating the manufacturing process of a semiconductor device 120 according to some embodiments of the present disclosure. Figures 5A to 5C This is a schematic cross-sectional view illustrating the manufacturing process of a semiconductor device 130 according to some embodiments of the present disclosure.

[0092] refer to Figure 4A At least one semiconductor device 120 is provided. At this stage, the side surfaces 120S1 and 120S3 of the semiconductor device 120 are vertical side surfaces, such as... Figure 4A As shown. In some embodiments, the semiconductor device 120 includes a plurality of connection structures 122 disposed on a front surface 120F. In some embodiments, the connection structure 122 is a microbump including a conductive connector 122a and a solder cap 122b on the conductive connector 122a. However, this disclosure is not limited thereto. In some alternative embodiments, the connection structure 122 may be other conductive structures, such as solder bumps, gold bumps, or copper bumps. In some embodiments, the conductive connector 122a is a copper pillar, copper post, copper pad, etc.

[0093] Semiconductor devices 120 can be formed in a semiconductor wafer (not shown). For example, the semiconductor wafer is processed to include multiple device regions, and then, after formation, the semiconductor wafer can be tested. For example, each device region of the semiconductor wafer is probed and its functionality and performance are tested, and devices known to be good are selected for subsequent processing. In some embodiments, the semiconductor wafer is attached to a temporary carrier or a frame including tape, and then the semiconductor wafer is diced along multiple dicing lines (not shown) to form individual semiconductor devices 120. For example, a tape frame TP is used to hold the semiconductor wafer in place during a monomerization process. Figure 4A As shown, the rear surface 120B of the semiconductor device 120 is attached to the tape frame TP. In some embodiments, a monomerization process is performed along multiple dicing paths (not shown) using a laser cutting process. It should be noted that, although... Figure 4A For simplicity, only one semiconductor device 120 is shown, but this disclosure is not limited to the embodiments or drawings shown herein, and those skilled in the art will understand that multiple semiconductor devices 120 arranged in an array are provided on a tape frame TP.

[0094] refer to Figure 4BA post-cut process is performed to cut the semiconductor device 120, thereby forming a sub-surface 120S11 at the side surface 120S1. In some embodiments, the post-cut process for forming the sub-surface 120S11 is performed using a mechanical cutting process with a blade. That is, the sub-surface 120S11 is formed by a contact cutting process. Specifically, as... Figure 4B As shown, a blade B1 with a taper angle θ10 is used to form the sub-surface 120S11. In some embodiments, the taper angle θ10 is greater than or equal to 1° to less than 45°. In some alternative embodiments, the taper angle θ10 is greater than or equal to 1° to less than 30°.

[0095] refer to Figure 4C After forming the sub-surface 120S11, another post-dicing process is performed to dicing the semiconductor device 120, thereby forming the sub-surface 120S12 at the side surface 120S1. In some embodiments, the post-dicing process for forming the sub-surface 120S12 is performed using a mechanical dicing process with a blade. That is, the sub-surface 120S11 is formed by a contact dicing process. Specifically, as... Figure 4C As shown, a blade B2 with a sharp angle θ11 is used to form the sub-surface 120S12. In some embodiments, as... Figure 4B and Figure 4C As shown, the tip angle θ11 of blade B2 is smaller than the tip angle θ10 of blade B1. That is, the side surface 120S1 with sub-surfaces 120S11 and 120S12 is formed by different post-cutting processes using different blades (e.g., blades B1, B2). In some embodiments, the tip angle θ11 is greater than 0° and less than 45°. In some alternative embodiments, the tip angle θ11 is greater than 0° and less than 30°.

[0096] refer to Figure 4D After forming the side surface 120S1 with sub-surfaces 120S11 and 120S12, a post-cutting process is performed using blade B1 to cut the semiconductor device 120, thereby forming the sub-surface 120S31 at the side surface 120S3. That is, by using the same blade B1, the post-cutting process for forming the sub-surface 120S31 is the same as the post-cutting process for forming the sub-surface 120S11, because the angle θ2 between the sub-surface 120S11 and the virtual plane P1 is equal to the angle θ5 between the sub-surface 120S31 and the virtual plane P3, as shown below. Figure 4D As shown.

[0097] refer to Figure 4EAfter forming sub-surface 120S31, a post-cutting process using blade B2 is performed to cut semiconductor device 120, thereby forming sub-surface 120S32 at side surface 120S3. That is, using the same blade B2, the post-cutting process for forming sub-surface 120S32 is the same as the post-cutting process for forming sub-surface 120S12, because the angle θ3 between sub-surface 120S12 and virtual plane P2 is equal to the angle θ6 between sub-surface 120S32 and virtual plane P4, as shown below. Figure 4E As shown. From another perspective, as Figure 4E As shown, after forming sub-surface 120S32, a portion 120P1 of the semiconductor device 120 and a portion 120P2 located below portion 120P1 are formed. Thus, a semiconductor device 120 with an inclined side surface for forming the semiconductor package 100 has been formed. Furthermore, as will be discussed later... Figures 6A to 6B As described in detail, the semiconductor device 120 with the tilted side surface can be bonded to the redistribution structure 110 in a subsequent process.

[0098] exist Figures 4A to 4E In the illustrated embodiment, a side surface 120S1 having sub-surfaces 120S11 and 120S12 is formed, followed by the formation of sub-surface 120S31. However, this disclosure is not limited thereto. In some alternative embodiments, sub-surfaces 120S11 and 120S31, formed using the same blade B1, may be formed, followed by sub-surfaces 120S12 and 120S32, formed using the same blade B2. Further, according to Figures 4A to 4E From the description, it can be deduced that in embodiments where included angles θ2 and θ3 differ from included angles θ5 and θ6, sub-surfaces 120S11, 120S12, 120S31, and 120S32 are formed using different post-cutting processes with different blades having different sharp angles. Furthermore, in Figures 4A to 4E In the illustrated embodiments, the mechanical blade cutting process for forming sub-surfaces 120S11, 120S12, 120S31, and 120S32 is performed after a monomerization process performed by a laser cutting process. However, this disclosure is not limited thereto. In embodiments where each of the side surfaces 120S1, 120S2, 120S3, and 120S4 of the semiconductor device 120 has at least two tilted sub-surfaces, the monomerization process for separating individual semiconductor devices 120 is performed by a mechanical cutting process using at least two blades.

[0099] refer to Figure 5A At least one semiconductor device 130 is provided. At this stage, the side surface 130S1 of the semiconductor device 130 is a vertical side surface, such as... Figure 5AAs shown. In some embodiments, the semiconductor device 130 includes a plurality of connection structures 132 disposed on the front surface 130F. In some embodiments, the connection structure 132 is a microbump including a conductive connector 132a and a solder cap 132b on the conductive connector 132a. However, this disclosure is not limited thereto. In some alternative embodiments, the connection structure 132 may be other conductive structures, such as solder bumps, gold bumps, or copper bumps. In some embodiments, the conductive connector 132a is a copper pillar, copper rod, copper pad, etc.

[0100] Semiconductor devices 130 can be formed in a semiconductor wafer (not shown). For example, the semiconductor wafer is processed to include multiple device regions, and then, after formation, the semiconductor wafer can be tested. For example, each device region of the semiconductor wafer is probed and its functionality and performance are tested, and devices known to be of good quality are selected for subsequent processing. In some embodiments, the semiconductor wafer is attached to a temporary carrier or a frame including tape, and then the semiconductor wafer is diced along multiple dicing lines (not shown) to form individual semiconductor devices 130. For example, a tape frame TP is used to hold the semiconductor wafer in place during a monomerization process. Figure 5A As shown, the rear surface 130B of the semiconductor device 130 is attached to the tape frame TP. In some embodiments, a monomerization process is performed along multiple dicing paths (not shown) using a laser cutting process. It should be noted that, although... Figure 5A For simplicity, only one semiconductor device 130 is shown, but this disclosure is not limited to the embodiments or drawings shown herein, and those skilled in the art will understand that multiple semiconductor devices 130 arranged in an array are provided on a tape frame TP.

[0101] According to Figure 1 , Figure 2A , Figure 2B , Figure 3 and Figures 4A to 4E As described above, those skilled in the art should understand that the above combination Figure 4B and Figure 4C The described post-dicing process can be applied to form sub-surfaces 130S11 and 130S12 of semiconductor device 130. Specifically, as... Figure 5B As shown, blade B1 is used to form sub-surface 130S11, and then as... Figure 5C As shown, blade B2 is used to form sub-surface 130S12. Thus, a semiconductor device 130 with a tilted side surface for forming semiconductor package 100 has been formed. Furthermore, as will be discussed later... Figures 6A to 6B As described in detail, the semiconductor device 130 with the tilted side surface can be bonded to the redistribution structure 110 in a subsequent process.

[0102] Figures 6A to 6F This is a schematic cross-sectional view illustrating the manufacturing process of a semiconductor package 100 according to some embodiments of the present disclosure. In exemplary embodiments, the following manufacturing process is part of a wafer-level packaging process. Specifically, one semiconductor package is shown to represent multiple semiconductor packages obtained after the manufacturing process. That is, Figures 6A to 6F A single package area is shown, and the semiconductor package 100 (see...) Figure 1 It is formed in the encapsulation area shown.

[0103] refer to Figure 6A A carrier C is provided on which a release layer DB is formed. In some embodiments, the carrier C is a glass substrate. However, other materials may also be suitable for the carrier C, as long as the material can withstand subsequent processes while supporting the encapsulation structure formed thereon. In some embodiments, the release layer DB is a light-to-heat conversion (LTHC) release layer formed on the glass substrate. The release layer DB allows structures formed on the carrier C in subsequent processes to be peeled off from the carrier C.

[0104] A redistribution structure 110 is then formed on the carrier C and the release layer DB. The redistribution structure 110 has a first surface 110a and a second surface 110b opposite to the first surface 110a. In some embodiments, the second surface 110b faces the carrier C. In some embodiments, the second surface 110b is attached to the release layer DB.

[0105] In some embodiments, the method of forming the redistribution structure 110 includes sequentially and alternately forming a plurality of dielectric layers 112 and a plurality of conductive layers 114 along a direction Z parallel to the normal direction of the carrier C. For example... Figure 6A As shown, multiple conductive layers 114 are sandwiched between multiple dielectric layers 112, but the top surface of the top layer of the multiple conductive layers 114 is exposed by the top layer of the multiple dielectric layers 112, and the bottom layer of the multiple conductive layers 114 is exposed by the bottom layer of the dielectric layers 112. The exposed top layer of the multiple conductive layers 114 serves to electrically connect to semiconductor device 120 and multiple semiconductor devices 130. In some embodiments, the exposed top layer of the multiple conductive layers 114 includes multiple under-bump metallurgy patterns. In some embodiments, the exposed top layer of the multiple conductive layers 114 includes multiple pads. The pads may include redistribution pads (wiring pads) and / or bump pads. In some embodiments, the exposed top layer of the multiple conductive layers 114 includes multiple microbumps. The exposed bottom layer of the multiple conductive layers 114 serves to electrically connect to multiple electrical terminals 160 subsequently formed. In some embodiments, the exposed bottom layer of the multiple conductive layers 114 includes multiple under-bump metallurgy patterns.

[0106] It should be noted that, although Figure 6A The diagram shows four conductive layers 114 and four dielectric layers 112, but this disclosure does not limit the number of these layers. In some alternative embodiments, depending on the circuit design, the redistribution structure 110 may consist of more or fewer conductive layers 114 and dielectric layers 112.

[0107] In some embodiments, the conductive layer 114 is made of aluminum, titanium, copper, nickel, tungsten, and / or alloys thereof. The conductive layer 114 can be formed, for example, by electroplating, deposition, and / or photolithography and etching. In some embodiments, the dielectric layer 112 is made of polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymer dielectric material. The dielectric layer 112 can be formed using suitable manufacturing techniques, such as spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc.

[0108] refer to Figure 6B Semiconductor device 120 and multiple semiconductor devices 130 are mounted to the redistribution structure 110 using a flip-chip bonding method. That is, semiconductor device 120 and multiple semiconductor devices 130 are each inverted, such that the front surface 120F of semiconductor device 120 and the front surface 130F of each semiconductor device 130 face the carrier C. More specifically, as... Figure 6B As shown, a plurality of connection structures 122 of semiconductor device 120 are bonded to corresponding portions (e.g., pads, microbumps) of the exposed top layer of a plurality of conductive layers 114 to form a plurality of bonding structures BS1, and a plurality of connection structures 132 of each semiconductor device 130 are bonded to other corresponding portions (e.g., pads, microbumps) of the exposed top layer of the plurality of conductive layers 114 to form a plurality of bonding structures BS2. In some embodiments, semiconductor device 120 and the plurality of semiconductor devices 130 are bonded to redistribution structure 110 by a reflow process or other suitable process. In some embodiments, flux (not shown) may be applied to connection structures 122 and / or connection structures 132 to obtain better adhesion. Furthermore, in some embodiments, redistribution structure 110 is referred to as an organic interposer. However, this disclosure is not limited thereto. In some alternative embodiments, redistribution structure 110 may be an inorganic interposer.

[0109] exist Figures 6A to 6BIn the illustrated embodiment, the top exposed layer of the plurality of conductive layers 114 used to connect semiconductor device 120 and the plurality of semiconductor devices 130 is solderless. However, this disclosure is not limited thereto. In some alternative embodiments, a solder cap layer may be formed on top of the top exposed layer of the plurality of conductive layers 114. The solder cap layer may be formed by an electroplating process. Furthermore, in Figures 6A to 6B In the illustrated embodiment, the connection structure 122 of the semiconductor device 120 includes a solder cap 122b on the conductive connector 122a, and the connection structure 132 of the semiconductor device 130 includes a solder cap 132b on the conductive connector 132a. However, this disclosure is not limited thereto. In some alternative embodiments, the connection structure 122 of the semiconductor device 120 includes a conductive connector 122a without a solder cap, and the connection structure 132 of the semiconductor device 130 includes a conductive connector 132a without a solder cap.

[0110] refer to Figure 6A and Figure 6B The redistribution structure 110 is formed before the semiconductor devices 120 and 130 are placed; therefore, the above process is considered a "redistribution-first method (RDL first method)". By using the RDL first method to form the redistribution structure 110 and semiconductor devices 120 and 130 on the carrier C, the subsequently formed semiconductor package 100 is not limited by the fan-out ratio (i.e., the ratio of die area to package area). Furthermore, since the semiconductor devices 120 and 130 are coupled to the first surface 110a of the redistribution structure 110 via flip-chip bonding, the use of die attach film (DAF) or film on wire (FOW) used in conventional packaging structures for bonding semiconductor devices is eliminated. Therefore, the overall thickness of the subsequently formed semiconductor package 100 can be effectively reduced.

[0111] refer to Figure 6C After the semiconductor device 120 and the plurality of semiconductor devices 130 are connected to the redistribution structure 110, an underfill adhesive layer 140 is formed on the redistribution structure 110. In some embodiments, such as Figure 6CAs shown, an underfill adhesive layer 140 is formed to fill the spaces S1 between semiconductor devices 120 and 130, S2 between semiconductor devices 120 and 130, the space between semiconductor device 120 and redistribution structure 110, and the space between semiconductor device 130 and redistribution structure 110, to cover the front surface 120F of semiconductor device 120, the front surface 130F of each semiconductor device 130, and the top portion of the plurality of conductive layers 114, and to surround the plurality of bonding structures BS1 and BS2. In some embodiments, the underfill adhesive layer 140 comprises a polymer, such as epoxy resin. In some embodiments, the underfill adhesive layer 140 is formed by a capillary flow process after the semiconductor devices 120 and the plurality of semiconductor devices 130 are attached. That is, the underfill adhesive layer 140 is drawn by capillary action through spaces S1, S2, the space between semiconductor device 120 and redistribution structure 110, and the space between each semiconductor device 130 and redistribution structure 110.

[0112] like Figure 6C As shown, since the space S1 sandwiched between semiconductor devices 120 and 130 and formed by side surfaces 120S1 and 130S1 has a lateral dimension that continuously decreases along the direction from the front surface 120F to the rear surface 120B, and the space S2 sandwiched between semiconductor devices 120 and 130 and formed by side surfaces 120S3 and 130S1 has a lateral dimension that continuously decreases along the direction from the front surface 120F to the rear surface 120B, the capillary driving force caused by side surfaces 120S1 and 130S1 and the capillary driving force caused by side surfaces 120S3 and 130S1 are reduced. Therefore, during the formation process of the underfill adhesive layer 140, the uniformity of the flow field of the underfill adhesive layer 140 is improved, and void problems in the underfill adhesive layer 140 can be prevented, thereby improving the mechanical stability of the semiconductor package 100.

[0113] In embodiments where the maximum distance D1 (i.e., the maximum lateral dimension of space S1) is greater than the minimum distance D2 (i.e., the minimum lateral dimension of space S1), the maximum distance D3 (i.e., the maximum lateral dimension of space S2) is greater than the minimum distance D4 (i.e., the minimum lateral dimension of space S2), and both the minimum distances D2 and D4 are less than 400 μm, the distance difference DD at the flow front of the bottom filling adhesive layer 140 is less than 5 mm. Figure 7As shown. That is, during the formation process of the bottom filling adhesive layer 140, the bottom filling adhesive layer 140 has a uniform flow front velocity. In another embodiment, where the maximum distance D1 (i.e., the maximum lateral dimension of space S1) is greater than 1.25 times the minimum distance D2 (i.e., the minimum lateral dimension of space S1), the maximum distance D3 (i.e., the maximum lateral dimension of space S2) is greater than 1.25 times the minimum distance D4 (i.e., the minimum lateral dimension of space S2), and both the minimum distance D2 and the minimum distance D4 are less than 400 μm, the distance difference DD at the flow front of the bottom filling adhesive layer 140 is less than 4.5 mm.

[0114] refer to Figure 6D An encapsulation 150 is formed on the redistribution structure 110 to encapsulate the semiconductor device 120, multiple semiconductor devices 130, and the underfill adhesive layer 140. At this stage, the semiconductor device 120 and multiple semiconductor devices 130 are completely encapsulated by the encapsulation 150 without exposing the rear surface 120B of the semiconductor device 120 and the rear surface 130B of the multiple semiconductor devices 130. Figure 6D As shown. That is, at this stage, semiconductor device 120 and the plurality of semiconductor devices 130 are not exposed and are well protected by encapsulation 150. In some embodiments, encapsulation 150 is a molding compound formed by an over-molding process. In some alternative embodiments, the material of encapsulation 150 includes epoxy resin or other suitable resin.

[0115] refer to Figure 6D and Figure 6E The encapsulation 150 is planarized until the rear surface 120B of the semiconductor device 120 and the rear surfaces 130B of the plurality of semiconductor devices 130 are exposed. In some embodiments, such as Figure 6E As shown, after the planarization process, the illustrated top surface of the encapsulation 150 is substantially coplanar with the rear surfaces 120B of the semiconductor device 120 and 130B of the semiconductor device 130. The encapsulation 150 can be planarized by, for example, a grinding process or a chemical mechanical polishing (CMP) process. After the planarization or grinding process, a cleaning step can be selectively performed to remove any residues generated. However, the invention is not limited thereto, and the planarization process can be performed by any other suitable method.

[0116] After the encapsulation 150 is planarized to expose the semiconductor device 120 and the plurality of semiconductor devices 130, the redistribution structure 110 is separated from the carrier C, thereby exposing the second surface 110b of the redistribution structure 110. Details are as follows... Figure 6EAs shown, the bottom layer of the plurality of conductive layers 114 for connection to the subsequently formed plurality of electrical terminals 160 is exposed. In some embodiments, the release layer DB is an LTHC release layer. The release layer DB and the carrier C can be peeled off and removed from the overlying structure when irradiated with a UV laser. It should be noted that the peeling process is not limited to this. Other suitable methods can be used in some alternative embodiments. In some embodiments, a frame tape (not shown) is attached to the rear surface 120B of the semiconductor device 120 and the rear surface 130B of the plurality of semiconductor devices 130 before the carrier C is removed.

[0117] refer to Figure 6F Multiple electrical terminals 160 are formed on and electrically connected to the bottom layer of multiple conductive layers 114 of the redistribution structure 110. In some embodiments, the electrical terminals 160 are, for example, controlled collapse chip connection (C4) bumps. The electrical terminals 160 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or combinations thereof. In some embodiments, the electrical terminals 160 are formed by initially forming a solder layer through vapor deposition, electroplating, printing, solder transfer, balling, etc. Once the solder layer has been formed on the structure, a reflow process can be performed to shape the material into the desired bump shape. In another embodiment, the electrical terminals 160 include metal pillars (e.g., copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The metal pillars may be solderless and have substantially vertical sidewalls. In some embodiments, a metal caplayer is formed on top of the metal pillars. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or combinations thereof, and may be formed by an electroplating process. In some embodiments, after the plurality of electrical terminals 160 are formed, the frame tape (not shown) remains attached to the rear surface 120B of the semiconductor device 120 and the rear surface 130B of the semiconductor device 130. However, this disclosure is not limited thereto. In some alternative embodiments, after the plurality of electrical terminals 160 are formed, the frame tape (not shown) is separated from the semiconductor device 120 and the semiconductor device 130.

[0118] After forming multiple electrical terminals 160, a monomerization process is performed along multiple dicing regions between adjacent package areas to... Figure 6F The entire structure shown is cut into multiple semiconductor packages 100. As mentioned above, the above manufacturing process is part of a wafer-level packaging process, although... Figure 1A single-unitized semiconductor package 100 is shown, but those skilled in the art will understand that multiple semiconductor packages 100 are obtained after the unitization process. In some embodiments, the unitization process is performed to cut through the redistribution structure 110 and the encapsulation 150, such as... Figure 6F and Figure 1 As shown. The monomerization process can be a blade cutting process or a laser cutting process. In some embodiments, the frame tape (not shown) attached to the rear surface 120B of semiconductor device 120 and the rear surface 130B of semiconductor device 130 is removed after the monomerization process. In subsequent processes, the monomerized semiconductor package 100 may be disposed on a circuit substrate or other components, for example, as needed.

[0119] Although the steps of the described method are shown and illustrated as a series of actions or events, it should be understood that the order in which such actions or events are shown should not be construed as limiting. Furthermore, not all of the shown processes or steps are required to implement one or more embodiments of this disclosure.

[0120] exist Figure 1 In the semiconductor package 100 shown, each of the side surfaces 120S1, 120S3, and 130S1 has two inclined sub-surfaces. However, this disclosure is not limited thereto. In some alternative embodiments, the side surfaces 120S1, 120S3, and 130S1 may each have at least two inclined sub-surfaces. Reference will be made below to... Figure 10 , Figure 11A and Figure 11B Other embodiments are described.

[0121] Figure 10 This is a schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the present disclosure. Figure 11A yes Figure 10 A magnified view of the area R1 within the dashed line region. Figure 11B yes Figure 10 A magnified view of the area R2 within the dashed line region. Figure 10 The semiconductor package 400 shown is Figure 1 The semiconductor package 100 shown is similar to the semiconductor package 100, therefore the same or similar parts are indicated by the same reference numerals and will not be described again here. The differences between semiconductor package 400 and semiconductor package 100 will be described below.

[0122] refer to Figure 10 and Figure 11A In the semiconductor package 400, the side surface 120S1 of the semiconductor device 120 includes sub-surfaces 120S13, 120S14, 120S15, and 120S16. Specifically, as... Figure 10 and Figure 11AAs shown, sub-surface 120S13 is located between and connected to front surface 120F and sub-surface 120S14; sub-surface 120S14 is located between and connected to sub-surface 120S13 and sub-surface 120S15; sub-surface 120S15 is located between and connected to sub-surface 120S14 and sub-surface 120S16; and sub-surface 120S16 is located between and connected to sub-surface 120S15 and rear surface 120B. In other words, in the semiconductor package 400, the side surface 120S1 of the semiconductor device 120 is composed of four sub-surfaces (i.e., sub-surfaces 120S13, 120S14, 120S15, and 120S16). From another perspective, as... Figure 10 and Figure 11A As shown, the sub-surface 120S13 connected to the front surface 120F is closest to the rewiring structure 110, while the sub-surface 120S16 connected to the rear surface 120B is farthest from the rewiring structure 110.

[0123] In some embodiments, such as Figure 10 and Figure 11A As shown, sub-surfaces 120S13, 120S14, 120S15, and 120S16 are inclined side surfaces. Specifically, the included angle θa lies between sub-surface 120S13 and the virtual plane P5 parallel to the Z direction, the included angle θb lies between sub-surface 120S14 and the virtual plane P6 parallel to the Z direction, the included angle θc lies between sub-surface 120S15 and the virtual plane P7 parallel to the Z direction, and the included angle θd lies between sub-surface 120S16 and the virtual plane P8 parallel to the Z direction. In some embodiments, such as Figure 10 and Figure 11AAs shown, the angle θa between sub-surface 120S13 and virtual plane P5 is greater than the angle θb between sub-surface 120S14 and virtual plane P6; the angle θb between sub-surface 120S14 and virtual plane P6 is greater than the angle θc between sub-surface 120S15 and virtual plane P7; and the angle θc between sub-surface 120S15 and virtual plane P7 is greater than the angle θd between sub-surface 120S16 and virtual plane P8. That is, among angles θa, θb, θc, and θd, the angle closer to the rewiring structure 110 is greater than the angle farther from the rewiring structure 110. In some embodiments, each of the angles θa, θb, θc, and θd is less than 45 degrees and greater than 0 degrees. From another perspective, the slope of sub-surface 120S13 connected to the front surface 120F is less than the slope of sub-surface 120S14 connected to sub-surface 120S13, the slope of sub-surface 120S14 connected to sub-surface 120S14 is less than the slope of sub-surface 120S15 connected to sub-surface 120S14, and the slope of sub-surface 120S15 connected to sub-surface 120S14 is less than the slope of sub-surface 120S16 connected to sub-surface 120S15.

[0124] In some embodiments, such as Figure 10 and Figure 11B As shown, the side surface 120S3 of the semiconductor device 120 includes sub-surfaces 120S33, 120S34, 120S35, and 120S36. Specifically, as... Figure 10 and Figure 11B As shown, sub-surface 120S33 is located between and connected to front surface 120F and sub-surface 120S34; sub-surface 120S34 is located between and connected to sub-surface 120S33 and sub-surface 120S35; sub-surface 120S35 is located between and connected to sub-surface 120S34 and sub-surface 120S36; and sub-surface 120S36 is located between and connected to sub-surface 120S35 and rear surface 120B. In other words, in semiconductor package 400, the side surface 120S3 of semiconductor device 120 is composed of four sub-surfaces (i.e., sub-surfaces 120S33, 120S34, 120S35, and 120S36). From another perspective, such as Figure 10 and Figure 11B As shown, the sub-surface 120S33 connected to the front surface 120F is closest to the rewiring structure 110, while the sub-surface 120S36 connected to the rear surface 120B is farthest from the rewiring structure 110.

[0125] In some embodiments, such as Figure 10 and Figure 11B As shown, sub-surfaces 120S33, 120S34, 120S35, and 120S36 are inclined side surfaces. Specifically, the included angle θe is located between sub-surface 120S33 and the virtual plane P9 parallel to the Z direction, the included angle θf is located between sub-surface 120S34 and the virtual plane P10 parallel to the Z direction, the included angle θg is located between sub-surface 120S35 and the virtual plane P11 parallel to the Z direction, and the included angle θh is located between sub-surface 120S36 and the virtual plane P12 parallel to the Z direction. In some embodiments, such as Figure 10 and Figure 11B As shown, the angle θe between sub-surface 120S33 and virtual plane P9 is greater than the angle θf between sub-surface 120S34 and virtual plane P10; the angle θf between sub-surface 120S34 and virtual plane P10 is greater than the angle θg between sub-surface 120S35 and virtual plane P11; and the angle θg between sub-surface 120S35 and virtual plane P11 is greater than the angle θh between sub-surface 120S36 and virtual plane P12. That is, among the angles θe, θf, θg, and θh, the angle closer to the rewiring structure 110 is greater than the angle farther from the rewiring structure 110. In some embodiments, each of the angles θe, θf, θg, and θh is less than 45 degrees and greater than 0 degrees. From another perspective, the slope of sub-surface 120S33 connected to the front surface 120F is less than the slope of sub-surface 120S34 connected to sub-surface 120S33, the slope of sub-surface 120S34 connected to sub-surface 120S34 is less than the slope of sub-surface 120S35 connected to sub-surface 120S34, and the slope of sub-surface 120S35 connected to sub-surface 120S35 is less than the slope of sub-surface 120S36 connected to sub-surface 120S35.

[0126] In some embodiments, such as Figure 10 , Figure 11A and Figure 11B As shown, the side surface 130S1 of each semiconductor device 130 includes sub-surface 130S13, sub-surface 130S14, and sub-surface 130S15. Specifically, as... Figure 10 , Figure 11A and Figure 11BAs shown, sub-surface 130S13 is located between and connected to front surface 130F and sub-surface 130S14. Sub-surface 130S14 is located between and connected to sub-surface 130S13 and sub-surface 130S15. Sub-surface 130S15 is located between and connected to sub-surface 130S13 and sub-surface 130S15. Sub-surface 130S15 is located between and connected to sub-surface 130S14 and rear surface 130B. In other words, in the semiconductor package 400, the side surface 130S1 of each semiconductor device 130 is composed of three sub-surfaces (i.e., sub-surfaces 130S13, 130S14, and 130S15). From another perspective, as... Figure 10 , Figure 11A and Figure 11B As shown, the sub-surface 130S13 connected to the front surface 130F is closest to the rewiring structure 110, while the sub-surface 130S15 connected to the rear surface 130B is farthest from the rewiring structure 110.

[0127] In some embodiments, such as Figure 10 , Figure 11A and Figure 11B As shown, sub-surfaces 130S13, 130S14, and 130S15 are inclined side surfaces. Specifically, the included angle θi is located between sub-surface 130S13 and the virtual plane P13 parallel to the Z direction, the included angle θj is located between sub-surface 130S14 and the virtual plane P14 parallel to the Z direction, and the included angle θk is located between sub-surface 130S15 and the virtual plane P15 parallel to the Z direction. In some embodiments, such as Figure 10 , Figure 11A and Figure 11B As shown, the angle θi between sub-surface 130S13 and virtual plane P13 is greater than the angle θj between sub-surface 130S14 and virtual plane P14, and the angle θj between sub-surface 130S14 and virtual plane P14 is greater than the angle θk between sub-surface 130S15 and virtual plane P15. That is, among the angles θi, θj, and θk, the angle closer to the redistribution structure 110 is greater than the angle farther from the redistribution structure 110. In some embodiments, each of the angles θi, θj, and θk is less than 45 degrees and greater than 0 degrees. From another perspective, the slope of sub-surface 130S13 connected to the front surface 130F is less than the slope of sub-surface 130S14 connected to sub-surface 130S13, and the slope of sub-surface 130S14 connected to sub-surface 130S15 connected to sub-surface 130S14 is less than the slope of sub-surface 130S15 connected to sub-surface 130S14.

[0128] exist Figure 1In the semiconductor package 100 shown, each of the sub-surfaces 120S11, 120S12, 120S31, 120S32, 130S11, and 130S12 is a substantially flat or planar surface. However, this disclosure is not limited thereto. In some alternative embodiments, some sub-surfaces may be curved surfaces. Reference will be made below. Figure 12 Other embodiments are described.

[0129] Figure 12 This is a schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the present disclosure. Figure 12 The semiconductor package 500 shown is Figure 1 The semiconductor package 100 shown is similar to the semiconductor package 100, therefore identical or similar parts are indicated by the same reference numerals and will not be described again here. The semiconductor package 500 differs from the semiconductor package 100 in that the sub-surfaces 120S11 of side surface 120S1, 120S31 of side surface 120S3, and 130S11 of side surface 130S1 are curved surfaces. For example, when the number of multiple sub-surfaces connecting sub-surface 120S12 and front surface 120F is infinite, the multiple sub-surfaces connecting sub-surface 120S12 and front surface 120F can be collectively referred to as sub-surface 120S11, wherein sub-surface 120S11 exhibits a curved profile. Similarly, in some embodiments, when the number of multiple sub-surfaces connecting sub-surface 120S32 and front surface 120F is infinite, the multiple sub-surfaces connecting sub-surface 120S32 and front surface 120F can be collectively referred to as curved sub-surface 120S31. In addition, in some embodiments, when the number of multiple sub-surfaces connected between sub-surface 130S12 and front surface 130F is infinite, the multiple sub-surfaces connected between sub-surface 130S12 and front surface 130F can be collectively referred to as curved sub-surface 130S11.

[0130] Figure 13 This is a schematic cross-sectional view illustrating the application of a semiconductor structure according to some embodiments of the present disclosure. Reference Figure 13A component assembly SC is provided, comprising a first component C1 and a second component C2 disposed on the first component C1. The first component C1 may be or may include a packaging substrate, a printed circuit board (PCB), a printed circuit board, and / or other carrier capable of carrying an integrated circuit. In some embodiments, the second component C2 mounted on the first component C1 is similar to one of the semiconductor packages 100 to 500 described above. For example, one of the semiconductor packages 100 to 500 may be electrically coupled to the first component C1 via a plurality of terminals CT. The terminals CT may be the electrical terminals 160 described above. In some embodiments, an underfill adhesive layer UF is formed between the space of the first component C1 and the second component C2 to cover the plurality of terminals CT at least laterally. Alternatively, the underfill adhesive layer UF is omitted.

[0131] Other packaging technologies can be used to form the component assembly SC, and this invention is not limited thereto. For example, the component assembly SC is formed using wafer-level packaging (WLP), chip-on-wafer-on-substrate (CoWoS) processes, chip-on-chip-on-substrate (CoCoS) processes, etc. The component assembly SC can be part of an electronic system used for, for example, computers (e.g., high-performance computers), computing devices used in conjunction with artificial intelligence systems, wireless communication devices, computer-related peripherals, entertainment devices, etc. Component assemblies SC incorporating the semiconductor structures discussed herein can provide high-bandwidth data communication. It should be noted that other electronic applications are also possible.

[0132] According to some embodiments, a semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor, an underfill adhesive layer, and an encapsulator. The first semiconductor device is disposed on and electrically connected to the redistribution structure. The first semiconductor device has a first bottom surface, a first top surface, and a first side surface connected to the first bottom surface and the first top surface. The first side surface includes a first sub-surface and a second sub-surface connected to each other. The first sub-surface and the first bottom surface are connected, and a first obtuse angle is located between the first sub-surface and the second sub-surface. The second semiconductor device is disposed on and electrically connected to the redistribution structure. The second semiconductor device has a second bottom surface, a second top surface, and a second side surface connected to the second bottom surface and the second top surface. The second side surface faces the first side surface. The second side surface includes a third sub-surface and a fourth sub-surface connected to each other. The third sub-surface is connected to the second bottom surface, and a second obtuse angle is located between the third sub-surface and the fourth sub-surface. The underfill adhesive layer is located between the first semiconductor device and the second semiconductor device, between the first semiconductor device and the redistribution structure, and between the second semiconductor device and the redistribution structure. The encapsulator encapsulates the first semiconductor device, the second semiconductor device, and the underfill adhesive layer. In some embodiments, a first minimum distance between the first bottom surface and the second bottom surface is greater than a second minimum distance between the first top surface and the second top surface. In some embodiments, the first minimum distance between the first bottom surface and the second bottom surface is greater than 1.25 times the second minimum distance between the first top surface and the second top surface. In some embodiments, the second minimum distance between the first top surface and the second top surface is less than 400 μm. In some embodiments, a first angle between the first sub-surface and a first virtual plane perpendicular to the first top surface is greater than a second angle between the second sub-surface and a second virtual plane perpendicular to the first top surface; and a third angle between the third sub-surface and a third virtual plane perpendicular to the second top surface is greater than a fourth angle between the fourth sub-surface and a fourth virtual plane perpendicular to the second top surface. In some embodiments, the first angle, the second angle, the third angle, and the fourth angle are all less than 45 degrees and greater than 0 degrees. In some embodiments, the first obtuse angle is the same as the second obtuse angle. In some embodiments, the first obtuse angle is different from the second obtuse angle.

[0133] According to some embodiments, a semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill adhesive layer, and an encapsulation body. The first semiconductor device is disposed on and electrically connected to the redistribution structure, wherein the first semiconductor device includes a first portion and a second portion stacked on the first portion along a first direction. The first portion has a first inclined side surface, and the second portion has a second inclined side surface connected to the first inclined side surface. The slope of the first inclined side surface is less than the slope of the second inclined side surface. The second semiconductor device is disposed adjacent to the first semiconductor device and electrically connected to the redistribution structure, wherein the second semiconductor device includes a third portion and a fourth portion stacked on the third portion along a first direction. The third portion has a third inclined side surface, and the fourth portion has a fourth inclined side surface connected to the third inclined side surface. A space is located between the first and second semiconductor devices and is formed and sandwiched by the first, second, third, and fourth inclined side surfaces, wherein the slope of the third inclined side surface is less than the slope of the fourth inclined side surface. The underfill adhesive layer fills the space between the first and second semiconductor devices. The encapsulation body encapsulates the first semiconductor device, the second semiconductor device, and the underfill adhesive layer. In some embodiments, a first angle between the first inclined side surface and a first virtual plane parallel to the first direction is greater than a second angle between the second inclined side surface and a second virtual plane parallel to the first direction; and a third angle between the third inclined side surface and a third virtual plane parallel to the first direction is greater than a fourth angle between the fourth inclined side surface and a fourth virtual plane parallel to the first direction. In some embodiments, along the first direction, the thickness of the first portion is equal to or greater than the thickness of the second portion, the thickness of the third portion is equal to or greater than the thickness of the fourth portion, and each of the first angle, the second angle, the third angle, and the fourth angle is less than 30 degrees and greater than 0 degrees. In some embodiments, along the first direction, the thickness of the first portion is less than the thickness of the second portion, the thickness of the third portion is less than the thickness of the fourth portion, and each of the first angle, the second angle, the third angle, and the fourth angle is less than 45 degrees and greater than 0 degrees. In some embodiments, the first angle is the same as the third angle, and the second angle is the same as the fourth angle. In some embodiments, the first inclined side surface and the third inclined side surface are spaced apart by a maximum distance along a second direction perpendicular to the first direction, and the second inclined side surface and the fourth inclined side surface are spaced apart by a minimum distance along the second direction, wherein the minimum distance is less than 400 μm and the maximum distance is greater than 1.25 times the minimum distance.In some embodiments, the semiconductor package further includes: a plurality of first bonding structures contacting the first portion of the first semiconductor device; and a plurality of second bonding structures contacting the third portion of the second semiconductor device. In some embodiments, the semiconductor package further includes: a plurality of electrical terminals disposed on the redistribution structure, opposite to the first semiconductor device and the second semiconductor device, and electrically connected to the redistribution structure.

[0134] According to some embodiments, a method for forming a semiconductor package is provided, the method comprising at least the following steps: Providing a first semiconductor device having a first side surface connected to a first bottom surface and a first top surface, wherein the first side surface includes a first sub-surface and a second sub-surface interconnected, the first sub-surface being connected to the first bottom surface, and a first obtuse angle located between the first sub-surface and the second sub-surface. Providing a second semiconductor device having a second side surface connected to a second bottom surface and a second top surface, wherein the second side surface includes a third sub-surface and a fourth sub-surface interconnected, the third sub-surface being connected to the second bottom surface, and a second obtuse angle located between the third sub-surface and the fourth sub-surface. Forming a redistribution structure. Bonding the first semiconductor device and the second semiconductor device to the redistribution structure such that the first side surface faces the second side surface. Forming an underfill adhesive layer between the first semiconductor device and the second semiconductor device, between the first semiconductor device and the redistribution structure, and between the second semiconductor device and the redistribution structure. Encapsulating the first semiconductor device, the second semiconductor device, and the underfill adhesive layer by an encapsulator. In some embodiments, the first side surface of the first semiconductor device is formed by a first blade cutting process using two blades with different sharp angles, and the second side surface of the second semiconductor device is formed by a second blade cutting process using two blades with different sharp angles. In some embodiments, the first blade cutting process is the same as the second blade cutting process. In some embodiments, the first blade cutting process is different from the second blade cutting process.

[0135] The foregoing summary of features of several embodiments enables those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for achieving the same purposes and / or benefits as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor package, comprising: Rewiring structure; A first semiconductor device is disposed on and electrically connected to the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface, and a first side surface connected to the first bottom surface and the first top surface. The first side surface includes a first sub-surface and a second sub-surface connected to each other. The first sub-surface is connected to the first bottom surface, and the second sub-surface is connected to the first top surface. A first obtuse angle is located between the first sub-surface and the second sub-surface. The first sub-surface and the second sub-surface are inclined surfaces. A first acute angle is located between the first sub-surface and the first bottom surface, and a second acute angle is located between the second sub-surface and the first top surface. A second semiconductor device is disposed on and electrically connected to the redistribution structure, wherein the second semiconductor device has a second bottom surface, a second top surface, and a second side surface connected to the second bottom surface and the second top surface. The second side surface faces the first side surface. The second side surface includes a third sub-surface and a fourth sub-surface connected to each other. The third sub-surface is connected to the second bottom surface, and the fourth sub-surface is connected to the second top surface. A second obtuse angle is located between the third sub-surface and the fourth sub-surface. The third sub-surface and the fourth sub-surface are inclined surfaces. A third acute angle is located between the third sub-surface and the second bottom surface, and a fourth acute angle is located between the fourth sub-surface and the second top surface. A bottom filler adhesive layer is located between the first semiconductor device and the second semiconductor device, between the first semiconductor device and the redistribution structure, and between the second semiconductor device and the redistribution structure; as well as An encapsulation body encapsulates the first semiconductor device, the second semiconductor device, and the bottom filler layer.

2. The semiconductor package of claim 1, wherein the first minimum distance between the first bottom surface and the second bottom surface is greater than the second minimum distance between the first top surface and the second top surface.

3. The semiconductor package of claim 2, wherein the first minimum distance between the first bottom surface and the second bottom surface is greater than 1.25 times the second minimum distance between the first top surface and the second top surface.

4. The semiconductor package of claim 3, wherein the second minimum distance between the first top surface and the second top surface is less than 400 μm.

5. The semiconductor package according to claim 1, wherein The first angle between the first sub-surface and the first virtual plane perpendicular to the first top surface is greater than the second angle between the second sub-surface and the second virtual plane perpendicular to the first top surface; and The third angle between the third sub-surface and the third virtual plane perpendicular to the second top surface is greater than the fourth angle between the fourth sub-surface and the fourth virtual plane perpendicular to the second top surface.

6. The semiconductor package according to claim 5, wherein the first included angle, the second included angle, the third included angle and the fourth included angle are all less than 45 degrees and greater than 0 degrees.

7. The semiconductor package of claim 1, wherein the first obtuse angle is the same as the second obtuse angle.

8. The semiconductor package of claim 1, wherein the first obtuse angle is different from the second obtuse angle.

9. A semiconductor package, comprising: Rewiring structure; A first semiconductor device is disposed on and electrically connected to the redistribution structure, wherein the first semiconductor device includes a first portion and a second portion stacked on the first portion along a first direction, the first portion having a first inclined side surface, the second portion having a second inclined side surface connected to the first inclined side surface, the slope of the first inclined side surface being less than the slope of the second inclined side surface, the first surface of the first portion being connected to the first inclined side surface and being the top surface of the first semiconductor device; the second surface of the second portion being connected to the second inclined side surface and being the bottom surface of the first semiconductor device, and a first acute angle being located between the second inclined side surface and the second surface; A second semiconductor device is disposed next to the first semiconductor device and electrically connected to the redistribution structure. The second semiconductor device includes a third portion and a fourth portion stacked on the third portion along the first direction. The third portion has a third inclined side surface, and the fourth portion has a fourth inclined side surface connected to the third inclined side surface. A space is located between the first semiconductor device and the second semiconductor device and is formed and sandwiched by the first inclined side surface, the second inclined side surface, the third inclined side surface, and the fourth inclined side surface. The slope of the third inclined side surface is less than the slope of the fourth inclined side surface. The third surface of the third portion is connected to the first inclined side surface and is the top surface of the second semiconductor device; the fourth surface of the fourth portion is connected to the fourth inclined side surface and is the bottom surface of the second semiconductor device; and a second acute angle is located between the fourth inclined side surface and the fourth surface. A bottom filler adhesive layer fills the space between the first semiconductor device and the second semiconductor device; as well as An encapsulation body encapsulates the first semiconductor device, the second semiconductor device, and the bottom filler layer.

10. The semiconductor package of claim 9, wherein The first angle between the first inclined side surface and the first virtual plane parallel to the first direction is greater than the second angle between the second inclined side surface and the second virtual plane parallel to the first direction; and The third angle between the third inclined side surface and the third virtual plane parallel to the first direction is greater than the fourth angle between the fourth inclined side surface and the fourth virtual plane parallel to the first direction.

11. The semiconductor package of claim 10, wherein along the first direction, the thickness of the first portion is equal to or greater than the thickness of the second portion, the thickness of the third portion is equal to or greater than the thickness of the fourth portion, and each of the first included angle, the second included angle, the third included angle, and the fourth included angle is less than 30 degrees and greater than 0 degrees.

12. The semiconductor package of claim 10, wherein along the first direction, the thickness of the first portion is less than the thickness of the second portion, the thickness of the third portion is less than the thickness of the fourth portion, and each of the first included angle, the second included angle, the third included angle, and the fourth included angle is less than 45 degrees and greater than 0 degrees.

13. The semiconductor package of claim 10, wherein the first included angle is the same as the third included angle, and the second included angle is the same as the fourth included angle.

14. The semiconductor package of claim 9, wherein the first inclined side surface and the third inclined side surface are spaced apart by a maximum distance along a second direction perpendicular to the first direction, the second inclined side surface and the fourth inclined side surface are spaced apart by a minimum distance along the second direction, the minimum distance is less than 400 μm, and the maximum distance is greater than 1.25 times the minimum distance.

15. The semiconductor package according to claim 9, further comprising: Multiple first bonding structures are in contact with the first portion of the first semiconductor device; as well as Multiple second bonding structures are in contact with the third portion of the second semiconductor device.

16. The semiconductor package according to claim 9, further comprising: Multiple electrical terminals are disposed on the redistribution structure, opposite to the first semiconductor device and the second semiconductor device, and electrically connected to the redistribution structure.

17. A method for forming a semiconductor package, comprising: A first semiconductor device is provided having a first side surface connected to a first bottom surface and a first top surface, wherein the first side surface includes a first sub-surface and a second sub-surface connected to each other, the first sub-surface being connected to the first bottom surface, the second sub-surface being connected to the first top surface, and a first obtuse angle being located between the first sub-surface and the second sub-surface, wherein the first sub-surface and the second sub-surface are inclined surfaces, and a first acute angle being located between the first sub-surface and the first bottom surface; A second semiconductor device is provided having a second side surface connected to a second bottom surface and a second top surface, wherein the second side surface includes a third sub-surface and a fourth sub-surface connected to each other, the third sub-surface being connected to the second bottom surface, the fourth sub-surface being connected to the second top surface, and a second obtuse angle being located between the third sub-surface and the fourth sub-surface, wherein the third sub-surface and the fourth sub-surface are inclined surfaces, and a second acute angle being located between the third sub-surface and the second bottom surface; Forming a rewiring structure; The first semiconductor device and the second semiconductor device are bonded to the redistribution structure such that the first side surface faces the second side surface; An underfill adhesive layer is formed between the first semiconductor device and the second semiconductor device, between the first semiconductor device and the redistribution structure, and between the second semiconductor device and the redistribution structure; as well as The first semiconductor device, the second semiconductor device, and the bottom filler layer are encapsulated by an encapsulation body.

18. The method of forming a semiconductor package according to claim 17, wherein the first side surface of the first semiconductor device is formed by a first blade cutting process using two blades with different sharp angles, and the second side surface of the second semiconductor device is formed by a second blade cutting process using two blades with different sharp angles.

19. The method of forming a semiconductor package according to claim 18, wherein the first blade cutting process is the same as the second blade cutting process.

20. The method of forming a semiconductor package according to claim 18, wherein the first blade cutting process is different from the second blade cutting process.

Images