Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same. The semiconductor structure includes a substrate having first type deep trenches and second type deep trenches. The first type deep trenches and the second type deep trenches have lengthwise sidewalls extending laterally along different directions. The semiconductor structure includes a capacitor structure having a layer stack including at least three metal electrode layers interleaved with at least two node dielectric layers. Each layer within the layer stack includes a horizontally extending portion overlying a top surface of the substrate and a plurality of vertically extending portions projecting downward into respective ones of the first type deep trenches and the second type deep trenches. The different orientations of the lengthwise of the deep trenches reduce deformation of the semiconductor structure. Stress relief structures are formed in corner regions of the capacitor structure to provide structural reinforcement.

Description

Technical Field

[0001] This disclosure relates to a semiconductor structure and a method for forming the same. Background Technology

[0002] Capacitors are used in semiconductor wafers for many applications, such as power supply stabilization. However, a considerable amount of device area is often used to manufacture such capacitors. Therefore, there is a desire for capacitors that can provide high capacitance within a small device footprint. Summary of the Invention

[0003] According to some embodiments of this disclosure, a semiconductor structure includes a substrate and a capacitor structure. The substrate includes a plurality of first-type deep trenches and a plurality of second-type deep trenches, wherein the first-type deep trenches include a plurality of first-length-direction sidewalls extending laterally along a first horizontal direction, and the second-type deep trenches include a plurality of second-length-direction sidewalls extending laterally along a second horizontal direction different from the first horizontal direction. The plurality of clusters of subsets of the first-type deep trenches and the plurality of clusters of subsets of the second-type deep trenches alternate laterally along at least one direction selected from the first horizontal direction and the second horizontal direction. The capacitor structure includes a stacked layer comprising at least three metal electrode layers interleaved with at least two node dielectric layers. Each layer within the stack includes a horizontally extending portion covering a top surface of the substrate and a plurality of vertically extending portions protruding downward into a corresponding deep trench of the first-type deep trenches and the second-type deep trenches.

[0004] According to some embodiments of this disclosure, a semiconductor structure includes a first semiconductor die, the first semiconductor die including a substrate and a deep trench capacitor embedded within the substrate. The deep trench capacitor includes a plurality of deep trenches stacked and arranged in a two-dimensional array. The two-dimensional array includes a first two-dimensional periodic array of a plurality of first-type deep trenches located in the substrate and a second two-dimensional periodic array of a plurality of second-type deep trenches located in the substrate and interspersed with the first two-dimensional periodic array, wherein the first-type deep trenches have a plurality of first length-direction sidewalls extending laterally along a first horizontal direction and the second-type deep trenches have a plurality of second length-direction sidewalls extending laterally along a second horizontal direction different from the first horizontal direction. The stacked layer includes at least three metal electrode layers interspersed with at least two node dielectric layers, wherein each layer in the stack includes a horizontally extending portion covering a top surface of the substrate and a plurality of vertically extending portions protruding downward into a corresponding deep trench of the first-type deep trenches and the second-type deep trenches.

[0005] According to some embodiments of this disclosure, a method for forming a semiconductor structure includes the following steps: Forming a plurality of first-type deep trenches and a plurality of second-type deep trenches in an upper portion of a substrate, wherein the first-type deep trenches have a plurality of first-length-direction sidewalls extending laterally along a first horizontal direction, and the second-type deep trenches have a plurality of second-length-direction sidewalls extending laterally along a second horizontal direction different from the first horizontal direction, and wherein a plurality of clusters of subsets of the first-type deep trenches and a plurality of clusters of subsets of the second-type deep trenches alternate laterally along at least one direction selected from the first horizontal direction and the second horizontal direction. A capacitor structure is formed by depositing and patterning a layer stack including at least three metal electrode layers interleaved with at least two node dielectric layers, wherein each layer within the layer stack includes a horizontally extending portion covering a top surface of the substrate and a plurality of vertically extending portions protruding downward into a corresponding deep trench of the first-type deep trenches and the second-type deep trenches. Attached Figure Description

[0006] The features disclosed herein will be best understood from the following detailed description when read in conjunction with the accompanying drawings. Please note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1A This is a vertical cross-sectional view of a first exemplary structure after the formation of a deep trench, according to an embodiment of the present disclosure, wherein the inset shows an enlarged view of a region of the first configuration of the exemplary structure;

[0008] Figure 1B For along Figure 1A A vertical cross-sectional view of a region of the first exemplary structure in the vertical plane B–B';

[0009] Figure 2 This is a vertical cross-sectional view of a region of a first exemplary structure after the formation of a layer stack according to an embodiment of the present disclosure, the layer stack including at least three metal electrode layers interleaved with at least two node dielectric layers;

[0010] Figure 3 A vertical cross-sectional view of the peripheral region of a first exemplary structure after patterning the layer stack, according to an embodiment of the present disclosure;

[0011] Figure 4 This is a vertical cross-sectional view of a region of a first exemplary structure after the formation of a planarized dielectric layer and a plurality of contact via structures, according to an embodiment of the present disclosure.

[0012] Figure 5A top-down view of a second exemplary structure after the formation of a deep trench, according to an embodiment of the present disclosure;

[0013] Figure 6A A top-down view of a second exemplary structure after patterning of the layer stack and formation of the contact level dielectric layer, according to an embodiment of the present disclosure;

[0014] Figure 6B For along Figure 6A A vertical cross-sectional view of a region of the second exemplary structure in the vertical plane B–B';

[0015] Figure 7 A top-down view of a third exemplary structure according to an embodiment of the present disclosure;

[0016] Figure 8 A top-down view of a fourth exemplary structure according to an embodiment of the present disclosure;

[0017] Figure 9 A top-to-bottom view of a fifth exemplary structure according to an embodiment of the present disclosure;

[0018] Figure 10 A top-to-bottom view of a sixth exemplary structure according to an embodiment of the present disclosure;

[0019] Figure 11 A vertical cross-sectional view of an exemplary wafer assembly containing semiconductor grains with deep trench capacitors, according to an embodiment of the present disclosure.

[0020] Figure 12 A flowchart illustrating the general processing steps of the method disclosed herein.

[0021] [Symbol Explanation]

[0022] 6: Dielectric lining

[0023] 8:Substrate

[0024] 9, 9A, 9B: Deep trenches

[0025] 10A, 10B, 20A, 20B: Metal electrode layer, metal material layer

[0026] 15: Node dielectric layer

[0027] 19,499: Fictitious deep trench

[0028] 30: Layer stacking

[0029] 32: Encapsulating dielectric material layer

[0030] 34: Dielectric filler layer

[0031] 39: Cavity

[0032] 70: Contact-level dielectric layer

[0033] 80, 80A, 80B, 80C, 80D, 80E: Contact through-hole structure

[0034] 90: Interconnect-level dielectric layer

[0035] 90A, 90B: Cluster

[0036] 91: Sidewall in the first length direction

[0037] 92: Second length direction sidewall

[0038] 300: Deep trench capacitor / capacitor structure

[0039] 400,400': Stress-relief structure

[0040] 1000: First semiconductor die

[0041] 1210, 1220: Steps

[0042] 2000: Second Semiconductor Die

[0043] 1500, 2500: Solder balls

[0044] 3000: Integrated Fan-Out Stacked Package Diode

[0045] B–B',VP,VP1,VP2: Perpendicular plane

[0046] GC: Geometric Center

[0047] hd1: First horizontal direction

[0048] hd2: Second horizontal direction

[0049] LS1: First straight line segment

[0050] LS2: Second line segment

[0051] P1: First periodic spacing

[0052] P2: Second periodic spacing

[0053] TLS: Slanted Line Segmentation Detailed Implementation

[0054] The following disclosure provides numerous different embodiments or instances of various features for implementing the provided subject matter. Specific examples of components and configurations will be described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0055] Furthermore, for the convenience of describing the relationship between one element or feature as illustrated in the figures and another element or feature, spatially related terms such as "below," "under," "lower," "above," "upper," and similar terms are used herein. Spatially related terms are intended to cover different orientations of elements during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein can be interpreted similarly.

[0056] This disclosure relates to semiconductor devices, and more specifically to a deformation-resistant deep trench capacitor structure and its formation method. Deep trench capacitors can be used as integrated passive devices for providing large capacitance. Such large-capacitance capacitors can be used to stabilize power supplies and act as noise filters in handheld devices. The deep trench capacitor can be formed in a first semiconductor die as a component of a power supply circuit. The first semiconductor die can then be bonded to a second semiconductor die, which can be a system-on-a-chip (SoC) semiconductor die. Generally, processing the first semiconductor die after the deep trench capacitor has been formed in the first semiconductor die introduces mechanical stress into the first semiconductor die and may damage the deep trench capacitor.

[0057] According to one embodiment of this disclosure, the longitudinal orientation of the deep trench capacitor can be alternated along at least one horizontal direction to reduce deformation of the semiconductor grains including the deep trench capacitor. Furthermore, stress relief structures can be disposed around the array of deep trenches to reduce the effect of external stresses applied to the deep trench capacitor and prevent semiconductor grain warping. Various embodiments of this disclosure will now be described with reference to the accompanying drawings.

[0058] Figure 1A This is a vertical cross-sectional view of a first exemplary structure after the formation of a deep trench, according to an embodiment of this disclosure. The illustration shows an enlarged view of a region of the first configuration of this exemplary structure. Figure 1BFor along Figure 1A A vertical cross-sectional view of a region of the first exemplary structure in the vertical plane B–B'. (Reference) Figure 1A and Figure 1B The illustration shows a first exemplary structure according to an embodiment of the present disclosure, the first exemplary structure comprising a substrate 8 having a flat top surface. The substrate 8 may be a semiconductor substrate comprising a semiconductor material and may have a thickness of at least 10 micrometers. In one embodiment, the substrate 8 may comprise a commercially available semiconductor wafer that can be diced into semiconductor dies after deep trench formation. For example, the substrate 8 may comprise a semiconductor substrate comprising monocrystalline silicon and having a thickness in the range of 500 micrometers to 1,500 micrometers, although thicker or thinner substrates may be used.

[0059] Deep trenches 9 extending vertically into the substrate 8 can be formed by forming a patterned etch mask layer on the front surface of the substrate 8. The pattern in the patterned etch mask layer can be transferred to the upper portion of the substrate 8. An optional pad dielectric layer (not shown), such as a silicon oxide pad, can be formed on the front surface (i.e., the top surface) of the substrate 8 prior to the formation of the patterned etch mask layer. In one exemplary embodiment, the pad dielectric layer may comprise a silicon oxide layer with a thickness ranging from 20 nm to 100 nm, although thicker or thinner pad dielectric layers may be used.

[0060] The patterned etch mask layer may comprise a silicon nitride layer or a borosilicate glass (BSG) layer with a thickness ranging from 200 nm to 600 nm, although different materials and / or smaller or larger thicknesses may also be used for the optional pad dielectric layer and the patterned etch mask layer. The patterned etch mask layer may be formed by depositing a blanket etch mask layer, forming a photoresist layer with photolithography patterning on top of the blanket etch mask layer, and transferring the pattern from the photoresist layer into the blanket etch mask layer using an anisotropic etching process such as reactive ion etching.

[0061] An anisotropic etching process can be performed to transfer the patterned pattern in the etch mask layer into the upper portion of the substrate 8 to form deep trenches 9. For example, a reactive ion etching process using a gas combination including HBr, NF3, O2, and SF6 can be used to form deep trenches 9. The depth of the deep trenches 9 can range from 2 micrometers to 20 micrometers (such as 3 micrometers to 10 micrometers), although deeper or shallower trenches can be used. The horizontal cross-sectional shape of each deep trench 9 can have the following shapes: circular, elliptical, rectangular, rounded rectangle, annular bands with various shapes of inner and outer peripheries, or any two-dimensional shape defining a closed volume. Generally, at least one deep trench 9 extending downward from the top surface of the substrate can be formed in the substrate 8. At least one deep trench 9 may comprise a plurality of deep trenches 9 with a depth greater than 2 micrometers.

[0062] In one embodiment, each of the deep trenches 9 may extend laterally with a uniform width. The dominant portion of each deep trench 9 (such as greater than 50% of the entire area) may have a width sufficient to accommodate vertical extensions of all subsequently formed metal electrode layers and at least two node dielectric layers. For example, the dominant portion of each deep trench 9 may have a width sufficient to accommodate vertical extensions of at least three metal electrode layers and at least two node dielectric layers. In an illustrative example, the dominant portion of each deep trench 9 may have a width in the range of 50 nm to 1,000 nm, although smaller or larger widths may also be used.

[0063] In one embodiment, a first-type deep trench 9A and a second-type deep trench 9B may be formed in the upper portion of the substrate 8. The first-type deep trench 9A may have a plurality of first-length-direction sidewalls 91 extending laterally along a first horizontal direction hd1, and the second-type deep trench 9B may have a plurality of second-length-direction sidewalls 92 extending laterally along a second horizontal direction hd2 different from the first horizontal direction hd1. In one embodiment, the second horizontal direction hd2 may be perpendicular to the first horizontal direction hd1.

[0064] In one embodiment, each of the first type deep trench 9A and the second type deep trench 9B may have a length-to-width ratio in the range of 3 to 30. In one embodiment, each of the first type deep trench 9A and the second type deep trench 9B has a depth-to-width ratio in the range of 10 to 200. In one embodiment, each of the first type deep trench 9A and the second type deep trench 9B has a depth in the range of 2 micrometers to 20 micrometers.

[0065] In one embodiment, clusters 90A of a subset of first-type deep trenches 9A and clusters 90B of a subset of second-type deep trenches 9B alternate laterally along at least one direction selected from a first horizontal direction hd1 and a second horizontal direction hd2. The second horizontal direction hd2 may be perpendicular to the first horizontal direction hd1. In one embodiment, clusters 90A of the subset of first-type deep trenches 9A and clusters 90B of the subset of second-type deep trenches 9B alternate laterally along the first horizontal direction hd1 and along the second horizontal direction hd2. In the illustrated example, each cluster of the subset of first-type deep trenches 9A includes six first-type deep trenches 9A, and each cluster of the subset of second-type deep trenches 9B includes six second-type deep trenches 9B.

[0066] In one embodiment, the first type deep trench 9A and the second type deep trench 9B comprise a plurality of deep trenches 9 arranged in a two-dimensional array, wherein the first type deep trench 9A is configured as a first two-dimensional periodic array and the second type deep trench 9B is configured as a second two-dimensional periodic array interleaved with the first two-dimensional periodic array. In one embodiment, each of the first two-dimensional periodic array and the second two-dimensional periodic array has a first periodic spacing P1 along a first horizontal direction hd1 and a second periodic spacing hd2 along a second horizontal direction hd2. In one embodiment, the second two-dimensional periodic array may be laterally offset by half of the first periodic spacing P1 along the first horizontal direction hd1 and by half of the second periodic spacing P2 along the second horizontal direction hd2.

[0067] The photoresist layer can be removed before the anisotropic etching process forming the deep trench 9, or it can be consumed during the anisotropic etching process forming the deep trench 9. The patterned etch mask layer and the optional dielectric pad layer can then be removed, for example, by a corresponding isotropic etching process such as a wet etching process.

[0068] Figure 2 This is a vertical cross-sectional view of a region of a first exemplary structure after layer stacking has been formed, according to an embodiment of this disclosure. The layer stack includes at least three metal electrode layers interleaved with at least two node dielectric layers. (Reference) Figure 2The dielectric liner 6 may be formed on the solid exposed surface of the semiconductor substrate 8, including the top surface of the semiconductor substrate 8, and on the sidewalls of the deep trench 9. The dielectric liner 6 may include a dielectric material that provides electrical isolation between the deep trench capacitor subsequently formed and the substrate 8. For example, the dielectric liner 6 may include silicon oxide, silicon nitride, silicon oxynitride, and / or a dielectric metal oxide. Other suitable materials within the scope of this disclosure may also be used. In an illustrative example, the dielectric liner 6 may include a silicon oxide layer formed by thermal oxidation of multiple surface portions of the substrate 8, including silicon. The thickness of the dielectric liner 6 may range from 4 nm to 100 nm, although smaller and larger thicknesses may also be used.

[0069] An alternating stack 30 of metal electrode layers (10A, 20A, 10B, 20B) and node dielectric layers 15 is formed by a corresponding conformal deposition process. The alternating stack 30 includes at least three metal electrode layers (20A, 20B) that are interleaved with at least two node dielectric layers 15 and extend continuously above the top surface of the semiconductor substrate 8 into each of at least one deep trench 9. The alternating stack 30 may extend continuously into each deep trench 9. A cavity may exist in the unfilled volume of each deep trench 9. Generally, at least three metal electrode layers (10A, 20A, 10B, 20B) and at least two node dielectric layers 15 are deposited by a corresponding conformal deposition process.

[0070] Each of the metal electrode layers (10A, 20A, 10B, 20B) may include a metallic material, which may comprise a conductive metal nitride, an elemental metal, or an intermetallic alloy, and / or be substantially composed of a conductive metal nitride, an elemental metal, or an intermetallic alloy. In one embodiment, each metal electrode layer (10A, 20A, 10B, 20B) comprises a conductive metal nitride material, and / or is substantially composed of a composition of conductive metal nitride materials, which may be a metal diffusion barrier material. For example, each metal electrode layer (10A, 20A, 10B, 20B) may include a conductive metal nitride material such as TiN, TaN, or WN, and / or may be substantially composed of such conductive metal nitride material. Other suitable materials within the intended scope of the disclosure may also be used.

[0071] Using metal diffusion barrier materials for the metal electrode layers (10A, 20A, 10B, 20B) is advantageous because metal element diffusion through the node dielectric layer 15 and / or through the dielectric liner 6 can lead to a poisoning effect in deep trench capacitors. Each metal electrode layer (10A, 20A, 10B, 20B) can be formed by conformal deposition processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of each metal electrode layer (10A, 20A, 10B, 20B) can range from 5 nm to 50 nm (e.g., 10 nm to 30 nm), although smaller and larger thicknesses are also possible. In one embodiment, each metal electrode layer (10A, 20A, 10B, 20B) may have the same material composition and the same thickness. In another embodiment, each metal electrode layer (10A, 20A, 10B, 20B) may have the same material composition but with varying thicknesses. In yet another embodiment, each metal electrode layer (10A, 20A, 10B, 20B) may have a different material composition and the same thickness.

[0072] Each of the node dielectric layers 15 may include a node dielectric material, which may be a dielectric metal oxide material with a dielectric constant greater than 7.9 (the dielectric constant of silicon nitride), i.e., a "high-k" dielectric metal oxide material, or may include silicon nitride. For example, the node dielectric layer 15 may include a dielectric metal oxide material such as alumina, hafnium oxide, zirconia, tantalum oxide, lanthanum oxide, their alloys or silicates, and / or their layer stacks. In one embodiment, the node dielectric layer 15 may include an amorphous alumina layer, which may be annealed to a polycrystalline alumina material after the contact via structure is formed. Other suitable materials within the scope of the disclosure may also be used.

[0073] Each node dielectric layer 15 can be formed using a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of each node dielectric layer 15 can range from 1 nm to 20 nm (e.g., 3 nm to 12 nm), although smaller and larger thicknesses are also possible. In one embodiment, each node dielectric layer 15 may have the same material composition and the same thickness. In another embodiment, each node dielectric layer 15 may have the same material composition but with varying thicknesses. In yet another embodiment, each node dielectric layer 15 may have different material compositions and the same thickness. In yet another embodiment, each node dielectric layer 15 may have different material compositions and different thicknesses. For example, in one embodiment, the first node dielectric layer 15 may be thinner than the second node dielectric layer 15.

[0074] The total number of metal electrode layers (10A, 20A, 10B, 20B) can range from 3 to 16 (e.g., 4 to 8). The total number of node dielectric layers 15 can be one less than the total number of metal electrode layers (10A, 20A, 10B, 20B).

[0075] Although this disclosure is described using an embodiment of an alternating stack 30 of metal electrode layers (10A, 20A, 10B, 20B) and node dielectric layers 15 comprising four metal electrode layers (10A, 20A, 10B, 20B) and three node dielectric layers 15, embodiments in which different numbers of metal electrode layers (10A, 20A, 10B, 20B) and different numbers of node dielectric layers 15 may be used within the alternating stack 30 are explicitly contemplated herein. Generally, the alternating stack 30 may include at least three metal electrode layers (10A, 20A, 10B, 20B) interleaved with at least two node dielectric layers 15, which may be formed in and above at least one deep trench 9 formed in a substrate 8.

[0076] The metal electrode layers (10A, 20A, 10B, 20B) can be numbered sequentially according to the deposition order. For example, the metal electrode layers (10A, 20A, 10B, 20B) may include a first metal electrode layer 10A, a second metal electrode layer 20A, a third metal electrode layer 10B, a fourth metal electrode layer 20B, etc. Multiple patterned portions of each odd-numbered metal electrode layer (10A, 10B) can then be used to form a main electrode assembly serving as a primary node (i.e., a first node) of a deep trench capacitor, and the patterned portions of even-numbered metal electrode layers (20A, 20B) can then be used to form supplementary electrode assemblies serving as supplementary nodes (i.e., second nodes) of a deep trench capacitor. The total number of metal electrode layers (10A, 20A, 10B, 20B), the thickness of the metal electrode layers (10A, 20A, 10B, 20B), and the width of the deep trench 9 can be selected such that the dominant portion (i.e., greater than 50%) of the entire volume of each deep trench 9 can be filled with alternating layer stacks 30, rather than completely filling the deep trench 9.

[0077] The capping dielectric layer 32 and the dielectric filler layer 34 may be deposited over the alternating layer stack 30, as appropriate. The capping dielectric layer 32 may include the same dielectric material as the node dielectric layer 15 and may have a thickness in the range of 1 nm to 20 nm (such as 3 nm to 12 nm), although smaller and larger thicknesses may also be used.

[0078] The dielectric filling material layer 34 may be deposited on the capping dielectric material layer 32 or on the alternating layer stack 30 to fill the volume of the cavity retained in the deep trench 9. In one embodiment, the dielectric filling material layer 34 comprises undoped silicate glass or doped silicate glass, and / or is substantially composed of undoped silicate glass or doped silicate glass.

[0079] Figure 3 This is a vertical cross-sectional view of the peripheral region of a first exemplary structure after patterning a layer stack, according to an embodiment of this disclosure. (See also:) Figure 3 A trimmable masking layer may be applied over the dielectric filler layer 34 and can be patterned using photolithography to cover the area of ​​the deep trench 9. The entire periphery of the trimmable masking layer may be located outside the area of ​​the deep trench 9. A first set of etching processes may be performed to etch the dielectric filler layer 34, the optionally capped dielectric layer 32, and the unmasked portion of the topmost layer selected from the metal electrode layers (10A, 10B, 20A, 20B). The first set of etching processes may include a set of wet etching processes.

[0080] Subsequently, the trimmable masking layer can be trimmed to make the periphery of the trimmable masking layer laterally recessed and to increase the unmasked area of ​​the trimmable masking layer. A second set of etching processes can be performed to etch the unmasked portion of the dielectric filling material layer 34, the unmasked portion of the optional capping dielectric material layer 32, the unmasked portion of the topmost layer of the node dielectric layer 15, and the unmasked underlying portion of the metal electrode layers (10A, 10B, 20A, 20B).

[0081] The trimming and etching process of the trimmable mask layer and additional groups can be repeated to provide a stepped surface for the metal electrode layers (10A, 10B, 20A, 20B). The trimmable mask layer can then be removed, for example, by ashing or by dissolving it in a solvent.

[0082] Figure 4 This is a vertical cross-sectional view of a region of a first exemplary structure after the formation of a planarized dielectric layer and a plurality of contact via structures, according to an embodiment of this disclosure. (See reference...) Figure 4 A planarizable dielectric material or a self-planarizing dielectric material may be deposited over alternating layer stacks (10A, 10B, 20A, 20B) and dielectric filler layer 34 to form a contact-level dielectric layer 70. The contact-level dielectric layer 70 may have a thickness in the range of 100 nm to 2,000 nm, although smaller and larger thicknesses may also be used.

[0083] Contact via structures (80A, 80B) can be formed through contact-level dielectric layers 70 on corresponding layers in the metal electrode layers (10A, 10B, 20A, 20B). Each of at least three metal electrode layers (10A, 10B, 20A, 20B) can be contacted by a corresponding contact via structure (80A, 80B) embedded in the contact-level dielectric layer 70, which overlays a horizontal extension of the dielectric filler layer 34.

[0084] As known in the art, additional dielectric material layers (not shown) and additional metal interconnect structures (not shown) may be formed over the contact-level dielectric layer 70 and the contact via structures (80A, 80B). Bonding structures such as copper bonding pads and / or copper bonding pillars may be formed over the metal interconnect structures, as known in the art. Subsequently, the first exemplary structure may be diced into a plurality of semiconductor dies, which may be capacitor dies that can be attached to another semiconductor die. Each semiconductor die may include a deep trench capacitor 300.

[0085] The capacitor structure in the first exemplary structure includes at least one lateral alternating sequence of clusters 90A of a first type of deep trench 9A and clusters 90B of a second type of deep trench 9B. The first type of deep trench 9A has longitudinal sidewalls extending laterally along a first horizontal direction hd1, and the second type of deep trench 9B has longitudinal sidewalls extending laterally along a second horizontal direction hd2. The alternation of the longitudinal directions of the deep trenches 9 can homogenize the mechanical stress generated by the vertical extensions of the alternating layer stack 30 along different orientation directions (i.e., along the horizontal direction), and thus reduce stress-induced deformation of the semiconductor grains of the deep trench capacitor including the first exemplary structure. In one embodiment, each layer within the alternating layer stack 30 includes a horizontal extension overlying the top surface of the substrate 8 and a plurality of vertical extensions protruding downward into the corresponding deep trenches of the first type of deep trench 9A and the second type of deep trench 9B.

[0086] Figure 5 This is a top-down view of a second exemplary structure after the deep trench has been formed, according to one embodiment of this disclosure. (See reference...) Figure 5 A second exemplary structure according to an embodiment of this disclosure can be achieved by forming an additional deep trench while forming the deep trench 9. Figure 1A and Figure 1B The first exemplary structure illustrated is produced. These additional deep trenches may be formed in areas not used to form deep trench capacitors and are referred to herein as dummy deep trenches 19. In one embodiment, the dummy deep trenches 19 may be formed in corner regions of a two-dimensional array of deep trenches 9. Each of the dummy deep trenches 19 may extend vertically within the substrate 8.

[0087] In an illustrative example, the dummy deep trench 19 may comprise at least four sets of at least one dummy deep trench 19, the four sets being configured to have mirror symmetry about a vertical plane perpendicular to the geometric center GC of the two-dimensional array passing through the deep trench 9. As used herein, the geometric center of an element refers to a point having Cartesian coordinates that are the average of all Cartesian coordinates of the entire volume of the element. For example, the vertical plane may be a first vertical plane VP1 passing through the geometric center GC and parallel to a first horizontal direction hd1, or a second vertical plane VP2 passing through the geometric center GC and parallel to a second horizontal direction hd2.

[0088] In one embodiment, the second horizontal direction hd2 may be perpendicular to the first horizontal direction hd1, and each of at least one dummy deep trench 19 includes an inclined straight line segment TLS extending laterally along a corresponding horizontal direction, which forms an angle greater than 0 degrees and less than 90 degrees relative to the first horizontal direction hd1. In one embodiment, the inclination angle may be in the range of 30 degrees to 60 degrees, such as 45 degrees. In one embodiment, each of at least one dummy deep trench 19 includes: a first straight line segment LS1, which is connected to the inclined straight line segment TLS and extends laterally along the first horizontal direction hd1; and a second straight line segment LS2, which is connected to the inclined straight line segment TLS and extends laterally along the second horizontal direction hd2.

[0089] Figure 6A This is a top-down view of a second exemplary structure after the alternating layer stack 30 has been patterned and the contact level dielectric layer 70 has been formed, according to an embodiment of the present disclosure. Figure 6B For along Figure 6A A vertical cross-sectional view of a region of the second exemplary structure in the vertical plane B–B'. (See reference) Figure 6A and Figure 6B Executable Figures 2 to 4 The processing steps to form the deep trench capacitor 300 modify the pattern of the trimmable masking layer so that the regions of the dummy deep trenches 19 are covered by the trimmable masking layer. A portion of the alternating layer stack 30 remains above each region of at least one set of dummy deep trenches 19. In this embodiment, each patterned portion of the alternating layer stack 30 may have a stepped surface. Alternatively, a patterned dielectric etch masking layer (not shown) may be used to mask each portion of the alternating layer stack 30. In this embodiment, the sidewalls of the various layers within the patterned portions of the alternating layer stack 30 may be vertically aligned, i.e., may be located in the same vertical plane. Each patterned portion of the alternating layer stack 30, the optional capping dielectric material layer 32, and the optional dielectric filler material layer 34 filling or covering at least one set of dummy deep trenches 19 in the corner region of the deep trench capacitor 300 includes a stress relief structure 400 that protects the deep trench capacitor 300 from mechanical deformation when external mechanical stress is applied to the deep trench capacitor 300.

[0090] In one embodiment, the alternating layer stack 30 of the deep trench capacitor 300 and the stress relief structure 400 can be formed by depositing a continuous layer stack in each of a first type deep trench 9A, a second type deep trench 9B, and a dummy deep trench 19, the continuous layer stack including at least three continuous metal electrode layers (10A, 10B, 20A, 20B) interleaved with at least two continuous node dielectric layers 15; and subsequently patterning the continuous layer stack into the alternating layer stack 30 of the deep trench capacitor 300 and into additional alternating layer stacks 30 within the stress relief structure 400.

[0091] In one embodiment, the stress relief structure 400 may be formed at a corner region of a two-dimensional array of deep trenches 19 of the deep trench capacitor 300. In one embodiment, each of the stress relief structures 400 includes: a corresponding set of at least one additional deep trench (such as at least one dummy deep trench 19) extending vertically within the substrate 8; and a corresponding additional layer stack 30 comprising at least three metal material layers (10A, 10B, 20A, 20B) interleaved with at least two node dielectric layers 15. In one embodiment, each of the metal material layers (10A, 10B, 20A, 20B) within the stress relief structure 400 may be electrically isolated from at least three metal electrode layers (10A, 10B, 20A, 20B) within the capacitor structure 300.

[0092] In one embodiment, the stress relief structure 400 comprises four stress relief structures 400 configured to have mirror symmetry with respect to a vertical plane (VP1 or VP2) about the geometric center GC of the two-dimensional array passing through the deep trench 9. In one embodiment, the second horizontal direction hd2 is perpendicular to the first horizontal direction hd1, and each of the at least one additional deep trench (i.e., at least one dummy deep trench 19) comprises an inclined straight line segment TLS extending laterally along a corresponding horizontal direction, which forms an angle greater than 0 degrees and less than 90 degrees with respect to the first horizontal direction hd1. In one embodiment, each of the at least one additional deep trench comprises: a first straight line segment LS1, which is connected to the inclined straight line segment TLS and extends laterally along the first horizontal direction hd1; and a second straight line segment LS2, which is connected to the inclined straight line segment TLS and extends laterally along the second horizontal direction hd2.

[0093] refer to Figure 7 According to a third exemplary structure of the disclosure, it can be achieved through... Figure 6A and Figure 6BThe second exemplary structure generates additional stress relief structures 400' around the periphery of the deep trench capacitor 300, formed between the four stress relief structures 400. In this embodiment, the additional stress relief structures 400' may include a plurality of straight segments parallel to a first horizontal direction hd1 or a second horizontal direction hd2, and located within a corresponding set of at least one dummy deep trench 19.

[0094] refer to Figure 8 According to the fourth exemplary structure disclosed herein, it can be automatically configured through the following operations. Figure 6A and Figure 6B The second exemplary structure is generated by forming dummy deep trenches 19, such that each dummy deep trench 19 includes an inclined straight segment TLS, but does not include, as in Figures 5 to 7 Any lining segments (LS1, LS2) extending laterally along a first horizontal direction hd1 or along a second horizontal direction hd2 in the previously disclosed embodiments illustrated.

[0095] refer to Figure 9 According to the fifth exemplary structure disclosed herein, it can be automatically configured through the following operations. Figure 6A and Figure 6B The second exemplary structure is generated by eliminating the inclined straight segment TLS, such that each dummy deep trench 19 includes a first straight segment LS1 and a second straight segment LS2 directly connected to the first straight segment LS1. Each first straight segment LS1 may be parallel to a first horizontal direction hd1, and each second straight segment LS2 may be parallel to a second horizontal direction hd2.

[0096] refer to Figure 10 According to the sixth exemplary structure disclosed herein, it can be self-operated through the following operations. Figure 6A and Figure 6B The second exemplary structure illustrated results in a two-dimensional array of discrete dummy deep trenches 499 formed in each corner region of the deep trench capacitor 300, replacing the elongated and / or segmented dummy deep trenches 19. In this embodiment, each set of at least one additional deep trench comprises a two-dimensional array of additional deep trenches (i.e., a two-dimensional array of dummy deep trenches 19), which has a first periodicity along a first horizontal direction hd1 and a second periodicity along a second horizontal direction hd2. In a non-limiting illustrative example, each dummy deep trench 19 may have a horizontal cross-sectional shape of: a circle, a square, a rounded square, or a rounded rectangle with a length-to-width ratio not greater than 2.

[0097] refer to Figure 11 The illustrations are derived from non-limiting illustrative applications of various exemplary semiconductor die structures. In one embodiment, the first semiconductor die 1000 can be diced... Figure 4 , Figure 5 , Figure 6A and Figure 6B , Figure 7 , Figure 8 , Figure 9 or Figure 10 The first semiconductor die 1000 is formed from a substrate 8 of any of the exemplary structures. The first semiconductor die 1000 includes a cut portion of the substrate 8, a capacitor structure 300, and a stress relief structure 400 (if present).

[0098] Generally, it is available and has Figure 4 , Figure 5 , Figure 6A and Figure 6B , Figure 7 , Figure 8 , Figure 9 or Figure 10 The first semiconductor die 1000 is one of the exemplary structures. The first semiconductor die 1000 may be attached to the bottom side of the second semiconductor die 2000. For example, the first semiconductor die 1000 may be bonded to the second semiconductor die 2000, which includes a semiconductor device. The capacitor structure 300 is partially electrically connected to the semiconductor device via bonding pads or solder material.

[0099] For example, the second semiconductor die 2000 may be a system-on-a-chip (SoC) die 2000, which may be bonded to an integrated fan-out package-on-package (InFO PoP) die 3000 via an array of solder balls 2500. The second semiconductor die 2000 may be bonded to another module, such as a printed circuit board (PCB), via another array of solder balls 1500. Deep trench capacitors in semiconductor die 1000 may be used to stabilize the power supply system in the second semiconductor die 2000.

[0100] Referring to all the accompanying drawings and various embodiments according to the present disclosure, a semiconductor structure is provided, the semiconductor structure comprising: a substrate 8 in which a first type of deep trench 9A and a second type of deep trench 9B are included, wherein the first type of deep trench 9A has a first length direction sidewall 91 extending laterally along a first horizontal direction hd1, and the second type of deep trench 9B has a second length direction sidewall 92 extending laterally along a second horizontal direction hd2 different from the first horizontal direction hd1, and wherein a plurality of clusters 90A of a plurality of subsets of the first type of deep trench 9A and a second type of deep trench 9B are provided. Multiple clusters 90B of multiple subsets of type deep trench 9B are laterally alternating along at least one direction selected from a first horizontal direction hd1 and a second horizontal direction hd2; and a capacitor structure 300 including a layer stack 30 comprising at least three metal electrode layers (10A, 10B, 20A, 20B) interleaved with at least two node dielectric layers 15, wherein each layer within the layer stack 30 includes a horizontal extension overlying the top surface of the substrate 8 and multiple vertical extensions protruding downward into a corresponding deep trench in a first type deep trench 9A and a second type deep trench 9B.

[0101] In one embodiment, the first type deep trench 9A and the second type deep trench 9B include a plurality of deep trenches 9 arranged in a two-dimensional array, wherein the first type deep trench 9A is configured as a first two-dimensional periodic array and the second type deep trench 9B is configured as a second two-dimensional periodic array interleaved with the first two-dimensional periodic array, and wherein each of the first two-dimensional periodic array and the second two-dimensional periodic array has a first periodic spacing P1 along a first horizontal direction hd1 and a second periodic spacing P2 along a second horizontal direction hd2.

[0102] In one embodiment, the semiconductor structure includes stress relief structures 400 located in corner regions of a two-dimensional array of deep trenches 9, wherein each of the stress relief structures 400 includes: a corresponding set of at least one additional deep trench 19 extending vertically within the substrate 8; and a corresponding additional layer stack 30 including at least three metal material layers (10A, 10B, 20A, 20B) interleaved with at least two node dielectric layers 15.

[0103] In one embodiment, each of the metal material layers (10A, 10B, 20A, 20B) within the stress relief structure 400 is electrically isolated from at least three metal electrode layers (10A, 10B, 20A, 20B) within the capacitor structure 300. In one embodiment, the stress relief structure 400 comprises four stress relief structures 400 configured to be arranged in a mirror-symmetric arrangement across a vertical plane (VP1 or VP2) of the geometric center GC of the two-dimensional array of deep trenches 9.

[0104] In one embodiment, the second horizontal direction hd2 is perpendicular to the first horizontal direction hd1. In one embodiment, each of at least one additional deep trench 19 includes a segment of inclined straight line TLS extending laterally along a corresponding horizontal direction, which forms an angle greater than 0 degrees and less than 90 degrees relative to the first horizontal direction hd1, such as... Figure 7 and Figure 8 As shown in the diagram.

[0105] In one embodiment, each of the at least one additional deep trench 19 includes: a first straight segment LS1, which is connected to an inclined straight segment LS and extends laterally along a first horizontal direction hd1; and a second straight segment LS2, which extends laterally along a second horizontal direction hd2, such as Figure 7 and Figure 9 As illustrated. In one embodiment, the second straight segment LS2 may be connected to the inclined straight segment TLS, as shown. Figure 7 As shown in the diagram.

[0106] In one embodiment, a corresponding set of at least one additional deep trench 19 comprises a corresponding two-dimensional array of two-dimensional deep trenches 19 having a first periodicity P1 along a first horizontal direction hd1 and a second periodicity P2 along a second horizontal direction hd2.

[0107] In one embodiment, each of the first type deep trench 9A and the second type deep trench 9B has a length-to-width ratio in the range of 3 to 30; each of the first type deep trench 9A and the second type deep trench 9B has a depth-to-width ratio in the range of 10 to 200; and each of the first type deep trench 9A and the second type deep trench 9B has a depth in the range of 2 micrometers to 20 micrometers.

[0108] In one embodiment, at least three metal electrode layers (10A, 10B, 20A, 20B) comprise conductive metal nitrides, elemental metals, or intermetallic alloys; at least two node dielectric layers 15 comprise dielectric metal oxides or silicon nitride; and the substrate 8 comprises a semiconductor substrate.

[0109] In one embodiment, the semiconductor structure includes: a contact-level dielectric layer 70 overlying a capacitor structure 300; and contact via structures (80A, 80B) extending vertically through the contact-level dielectric layer 70 and contacting corresponding of at least three metal electrode layers (10A, 10B, 20A, 20B).

[0110] According to another embodiment of this disclosure, a semiconductor structure is provided. The semiconductor structure includes a first semiconductor die 1000. The first semiconductor die 1000 includes a substrate 8 and a deep trench capacitor 300 embedded in the substrate 8. The deep trench capacitor 300 includes: a plurality of deep trenches 9 arranged in a two-dimensional array, the two-dimensional array including a first two-dimensional periodic array of first type deep trenches 9A and a second two-dimensional periodic array of second type deep trenches 9B located in the substrate 8, the second two-dimensional periodic array being located in the substrate 8 and interleaved with the first two-dimensional periodic array, wherein the first type deep trenches 9A have a plurality of first length direction sidewalls 91 extending laterally along a first horizontal direction hd1, and the second type deep trenches 9B have a plurality of second length direction sidewalls 92 extending laterally along a second horizontal direction hd2 different from the first horizontal direction hd1; and a layer stack 30 including at least three metal electrode layers (10A, 10B, 20A, 20B) interleaved with at least two node dielectric layers 15, wherein each layer in the layer stack 30 includes a horizontally extending portion covering the top surface of the substrate 8 and a plurality of vertically extending portions protruding downward into the corresponding deep trenches in the first type deep trenches 9A and the second type deep trenches 9B.

[0111] In one embodiment, the semiconductor structure includes a second semiconductor die 2000 bonded to a first semiconductor die 1000 and containing a plurality of semiconductor devices, wherein a deep trench capacitor 300 is electrically connected to the semiconductor devices via a plurality of bonding pads or a plurality of solder material portions.

[0112] In one embodiment, the first semiconductor die 1000 includes a stress relief structure 400 located in a corner region of a two-dimensional array of deep trenches 9. In one embodiment, each of the stress relief structures 400 includes: a corresponding set of at least one additional deep trench 19 extending vertically within the substrate 8; and a corresponding additional layer stack 30 including at least three metal material layers (10A, 10B, 20A, 20B) interleaved with at least two node dielectric layers 15.

[0113] Figure 12 This is a flowchart illustrating the general processing steps of the method disclosed herein. Refer to steps 1210 and... Figures 1A to 10A plurality of first-type deep trenches 9A and a plurality of second-type deep trenches 9B can be formed in the upper portion of the substrate 8. The first-type deep trenches 9A have a plurality of first-length-direction sidewalls 91 extending laterally along a first horizontal direction hd1, and the second-type deep trenches 9B have a plurality of second-length-direction sidewalls 92 extending laterally along a second horizontal direction hd2 different from the first horizontal direction hd1. Clusters 90A of subsets of the first-type deep trenches 9A and clusters 90B of subsets of the second-type deep trenches 9B alternate laterally along at least one direction selected from the first horizontal direction hd1 and the second horizontal direction hd2.

[0114] Refer to steps 1220 and Figures 1A to 10 The capacitor structure 300 can be formed by depositing and patterning a layer stack 30, which includes at least three metal electrode layers (10A, 10B, 20A, 20B) interleaved with at least two node dielectric layers 15. Each layer in the layer stack 30 includes a horizontal extension overlying the top surface of the substrate 8 and a plurality of vertical extensions protruding downward into corresponding deep trenches of the first type deep trench 9A and the second type deep trench 9B.

[0115] Various embodiments of this disclosure provide a deformation-resistant deep trench capacitor 300 by providing a transversely alternating sequence of deep trenches with different length orientations. Furthermore, a stress-relief structure 400 may be formed around the deep trench capacitor 300. The stress-relief structure 400 can absorb mechanical stress to prevent warping during the handling of a first semiconductor die 1000 including the deep trench capacitor 300 (such as bonding the first semiconductor die 1000 to a second semiconductor die 2000).

[0116] According to one embodiment of the present disclosure, a semiconductor structure includes a substrate and a capacitor structure. The substrate includes a plurality of first-type deep trenches and a plurality of second-type deep trenches, wherein the first-type deep trenches include a plurality of first-length-direction sidewalls extending laterally along a first horizontal direction, and the second-type deep trenches include a plurality of second-length-direction sidewalls extending laterally along a second horizontal direction different from the first horizontal direction. The plurality of clusters of subsets of the first-type deep trenches and the plurality of clusters of subsets of the second-type deep trenches alternate laterally along at least one direction selected from the first horizontal direction and the second horizontal direction. The capacitor structure includes a stacked layer comprising at least three metal electrode layers interleaved with at least two node dielectric layers. Each layer within the stack includes a horizontally extending portion covering a top surface of the substrate and a plurality of vertically extending portions protruding downward into a corresponding deep trench of the first-type deep trenches and the second-type deep trenches.

[0117] In some embodiments, the first type deep trenches and the second type deep trenches comprise a plurality of deep trenches arranged in a two-dimensional array, wherein the first type deep trenches are configured as a first two-dimensional periodic array and the second type deep trenches are configured as a second two-dimensional periodic array interleaved with the first two-dimensional periodic array, and wherein each of the first two-dimensional periodic array and the second two-dimensional periodic array has a first periodic spacing along the first horizontal direction and a second periodic spacing along the second horizontal direction. In some embodiments, the semiconductor structure further comprises a plurality of stress relief structures located at corner regions of the two-dimensional array of the deep trenches, wherein each of the stress relief structures comprises: a corresponding set of at least one additional deep trench extending vertically within the substrate; and a corresponding additional layer stack comprising at least three metal material layers interleaved with at least two node dielectric layers. In some embodiments, each of the metal material layers within the stress relief structures is electrically isolated from the at least three metal electrode layers within the capacitor structure. In some embodiments, the stress relief structures comprise four stress relief structures configured to be arranged in a mirror-symmetric arrangement on a vertical plane passing through a geometric center of the two-dimensional array of the deep trenches. In some embodiments, the second horizontal direction is perpendicular to the first horizontal direction; and each of the at least one additional deep trench includes an inclined straight line segment extending laterally along a corresponding horizontal direction, the corresponding horizontal direction forming an angle greater than 0 degrees and less than 90 degrees with respect to the first horizontal direction. In some embodiments, each of the at least one additional deep trench includes: a first straight line segment connected to the inclined straight line segment and extending laterally along the first horizontal direction; and a second straight line segment connected to the inclined straight line segment and extending laterally along the second horizontal direction. In some embodiments, the second horizontal direction is perpendicular to the first horizontal direction; and each of the at least one additional deep trench includes a first straight line segment extending laterally along the first horizontal direction, and a second straight line segment connected to the first straight line segment and extending laterally along the second horizontal direction. In some embodiments, the corresponding set of at least one additional deep trench comprises a corresponding two-dimensional array of two-dimensional deep trenches having a first periodicity along the first horizontal direction and a second periodicity along the second horizontal direction. In some embodiments, each of the first-type deep trenches and the second-type deep trenches has a length-to-width ratio in the range of 3 to 30; and each of the first-type deep trenches and the second-type deep trenches has a depth-to-width ratio in the range of 10 to 200; and each of the first-type deep trenches and the second-type deep trenches has a depth in the range of 2 micrometers to 20 micrometers.In some embodiments, the at least three metal electrode layers comprise a conductive metal nitride, an elemental metal, or an intermetallic alloy; the at least two node dielectric layers comprise a dielectric metal oxide or silicon nitride; and the substrate comprises a semiconductor substrate. In some embodiments, the semiconductor structure further comprises: a contact-level dielectric layer covering the capacitor structure; and a plurality of contact via structures extending vertically through the contact-level dielectric layer and contacting a corresponding metal electrode layer among the at least three metal electrode layers.

[0118] According to another embodiment of this disclosure, a semiconductor structure includes a first semiconductor die. The first semiconductor die includes a substrate and a deep trench capacitor embedded in the substrate; and the deep trench capacitor includes: a plurality of deep trenches stacked and arranged in a two-dimensional array. The two-dimensional array includes a first two-dimensional periodic array of a plurality of first-type deep trenches located in the substrate and a second two-dimensional periodic array of a plurality of second-type deep trenches located in the substrate and interspersed with the first two-dimensional periodic array, wherein the first-type deep trenches have a plurality of first length direction sidewalls extending laterally along a first horizontal direction and the second-type deep trenches have a plurality of second length direction sidewalls extending laterally along a second horizontal direction different from the first horizontal direction; the stacked layer includes at least three metal electrode layers interspersed with at least two node dielectric layers, wherein each layer in the stack includes a horizontally extending portion covering a top surface of the substrate and a plurality of vertically extending portions protruding downward into a corresponding deep trench of the first-type deep trenches and the second-type deep trenches.

[0119] In some embodiments, the semiconductor structure further includes: a second semiconductor die bonded to the first semiconductor die and containing a plurality of semiconductor devices, wherein the deep trench capacitor is electrically connected to the semiconductor devices via a plurality of bonding pads or a plurality of solder material portions. In some embodiments, the first semiconductor die includes a plurality of stress relief structures located at corner regions of the two-dimensional array of the deep trenches; and each of the stress relief structures includes: a corresponding set of at least one additional deep trench extending vertically within the substrate, and a corresponding additional layer stack comprising at least three metal material layers interleaved with at least two node dielectric layers.

[0120] According to another aspect of this disclosure, a method for forming a semiconductor structure includes the following steps: forming a plurality of first-type deep trenches and a plurality of second-type deep trenches in an upper portion of a substrate, wherein the first-type deep trenches have a plurality of first-length-direction sidewalls extending laterally along a first horizontal direction and the second-type deep trenches have a plurality of second-length-direction sidewalls extending laterally along a second horizontal direction different from the first horizontal direction, and wherein a plurality of clusters of a plurality of subsets of the first-type deep trenches and a plurality of clusters of a plurality of subsets of the second-type deep trenches alternate laterally along at least one direction selected from the first horizontal direction and the second horizontal direction; and forming a capacitor structure by depositing and patterning a layer stack including at least three metal electrode layers interleaved with at least two node dielectric layers, wherein each layer in the layer stack includes a horizontally extending portion covering a top surface of the substrate and a plurality of vertically extending portions protruding downward into a corresponding deep trench of the first-type deep trenches and the second-type deep trenches.

[0121] In some embodiments, the first type deep trenches and the second type deep trenches comprise a plurality of deep trenches arranged in a two-dimensional array, wherein the first type deep trenches are configured as a first two-dimensional periodic array and the second type deep trenches are configured as a second two-dimensional periodic array interleaved with the first two-dimensional periodic array, and wherein each of the first two-dimensional periodic array and the second two-dimensional periodic array has a first periodic spacing along the first horizontal direction and a second periodic spacing along the second horizontal direction. In some embodiments, the method further comprises the step of forming a plurality of stress relief structures at corner regions of the two-dimensional array of the deep trenches, wherein each of the stress relief structures comprises: a corresponding set of at least one additional deep trench extending vertically within the substrate; and a corresponding additional layer stack comprising at least three metal material layers interleaved with at least two node dielectric layers. In some embodiments, each of the layer stack and the additional layer stacks is formed by the following steps: depositing a continuous layer stack in each of the first type deep trenches, the second type deep trenches, and the additional deep trenches, the continuous layer stack including at least three continuous metal electrode layers interleaved with at least two continuous node dielectric layers; and patterning the continuous layer stack into the layer stack including the at least three metal electrode layers and the at least two node dielectric layers and into the additional layer stacks. In some embodiments, the method further includes the steps of: forming a first semiconductor die by dicing the substrate, wherein the first semiconductor die includes a diced portion of the substrate and the capacitor structure; and bonding the first semiconductor die to a second semiconductor die, the second semiconductor die including a plurality of semiconductor devices, wherein the capacitor structure is electrically connected to the semiconductor devices via a plurality of bonding pads or a plurality of solder material portions.

[0122] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can readily serve as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure includes: A substrate includes a plurality of first-type deep trenches and a plurality of second-type deep trenches, wherein the first-type deep trenches include a plurality of first-length-direction sidewalls extending laterally along a first horizontal direction and the second-type deep trenches include a plurality of second-length-direction sidewalls extending laterally along a second horizontal direction different from the first horizontal direction, and wherein a plurality of clusters of a plurality of subsets of the first-type deep trenches and a plurality of clusters of a plurality of subsets of the second-type deep trenches alternate laterally along at least one direction selected from the first horizontal direction and the second horizontal direction, and the first-type deep trenches and the second-type deep trenches include a plurality of deep trenches arranged in a two-dimensional array; A capacitor structure comprising a stack of layers, the stack including at least three metal electrode layers interleaved with at least two node dielectric layers, wherein each layer within the stack includes a horizontally extending portion covering a top surface of the substrate and a plurality of vertically extending portions protruding downward into a corresponding deep trench of a first type deep trench and a second type deep trench; and Multiple stress-relief structures are located in the corner regions of the two-dimensional array of deep trenches, wherein each of the stress-relief structures comprises: A corresponding set of at least one additional deep trench extending vertically within the substrate; and A corresponding additional layer stack includes at least three metal material layers interleaved with at least two node dielectric layers, and includes at least one vertical extension portion of a corresponding deep trench extending vertically into the at least one additional deep trench and a horizontal extension portion covering a top surface of the substrate.

2. The semiconductor structure as described in claim 1, characterized in that, In the two-dimensional array, the first type of deep trenches are configured as a first two-dimensional periodic array and the second type of deep trenches are configured as a second two-dimensional periodic array interleaved with the first two-dimensional periodic array, wherein each of the first two-dimensional periodic array and the second two-dimensional periodic array has a first periodic spacing along the first horizontal direction and a second periodic spacing along the second horizontal direction.

3. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes an additional stress relief structure comprising a plurality of straight segments parallel to the first horizontal direction or the second horizontal direction.

4. The semiconductor structure as described in claim 1, characterized in that, Each of the metal material layers within the stress relief structures is electrically isolated from the at least three metal electrode layers within the capacitor structure.

5. The semiconductor structure as described in claim 1, characterized in that, The stress relief structures comprise four stress relief structures configured to be arranged in a mirror-symmetric arrangement on a vertical plane passing through a geometric center of the two-dimensional array of the deep trenches.

6. The semiconductor structure as described in claim 1, characterized in that, in: The second horizontal direction is perpendicular to the first horizontal direction; and Each of the at least one additional deep trench includes a sloping straight line segment extending laterally along a corresponding horizontal direction, which forms an angle greater than 0 degrees and less than 90 degrees relative to the first horizontal direction.

7. The semiconductor structure as described in claim 6, characterized in that, Each of the at least one additional deep trench contains: A first straight line segment, the first straight line segment connecting to the inclined straight line segment and extending laterally along the first horizontal direction; and A second straight line segment, which connects to the inclined straight line segment and extends laterally along the second horizontal direction.

8. The semiconductor structure as described in claim 3, characterized in that, in: The second horizontal direction is perpendicular to the first horizontal direction; and Each of the at least one additional deep trench includes a first straight segment extending laterally along the first horizontal direction, and a second straight segment connected to the first straight segment and extending laterally along the second horizontal direction.

9. The semiconductor structure as described in claim 3, characterized in that, The corresponding set of at least one additional deep trench includes a corresponding two-dimensional array of two-dimensional deep trenches having a first periodicity along the first horizontal direction and a second periodicity along the second horizontal direction.

10. The semiconductor structure as claimed in claim 1, characterized in that, Each of the first type deep trenches and the second type deep trenches has a length-to-width ratio in the range of 3 to 30; Each of the first type deep trenches and the second type deep trenches has a depth-to-width ratio in the range of 10 to 200; and Each of the first-type deep trenches and the second-type deep trenches has a depth in the range of 2 micrometers to 20 micrometers.

11. The semiconductor structure as claimed in claim 1, characterized in that, The at least three metal electrode layers comprise a conductive metal nitride, an elemental metal, or an intermetallic alloy. The at least two node dielectric layers comprise a dielectric metal oxide or silicon nitride; and The substrate includes a semiconductor substrate.

12. The semiconductor structure as claimed in claim 1, characterized in that, Further includes: A contact-level dielectric layer is applied over the capacitor structure; and Multiple contact via structures extend vertically through the contact dielectric layer and contact a corresponding metal electrode layer among the at least three metal electrode layers.

13. A semiconductor structure, characterized in that, It includes a first semiconductor die, wherein: The first semiconductor die includes a substrate and a deep trench capacitor embedded in the substrate; and This deep trench capacitor includes: A plurality of deep trenches arranged in a two-dimensional array, the two-dimensional array comprising a first two-dimensional periodic array of a plurality of first-type deep trenches located in the substrate and a second two-dimensional periodic array of a plurality of second-type deep trenches located in the substrate and intersecting with the first two-dimensional periodic array, wherein the first-type deep trenches have a plurality of first-length-direction sidewalls extending laterally along a first horizontal direction and the second-type deep trenches have a plurality of second-length-direction sidewalls extending laterally along a second horizontal direction different from the first horizontal direction; A stack comprising at least three metal electrode layers interleaved with at least two node dielectric layers, wherein each layer in the stack includes a horizontal extension overlying a top surface of the substrate and a plurality of vertical extensions projecting downward into a corresponding deep trench of the first type deep trenches and the second type deep trenches; and Multiple stress-relief structures are located in the corner regions of the two-dimensional array of deep trenches, wherein each of the stress-relief structures comprises: A corresponding set of at least one additional deep trench extending vertically within the substrate; and A corresponding additional layer stack includes at least three metal material layers interleaved with at least two node dielectric layers, and includes at least one vertical extension portion of a corresponding deep trench extending vertically into the at least one additional deep trench and a horizontal extension portion covering a top surface of the substrate.

14. The semiconductor structure as described in claim 13, characterized in that, Further includes: A second semiconductor die is bonded to the first semiconductor die and contains a plurality of semiconductor devices, wherein the deep trench capacitor is electrically connected to the semiconductor devices via a plurality of bonding pads or a plurality of solder material portions.

15. The semiconductor structure as described in claim 13, characterized in that, The stress relief structures comprise four stress relief structures configured to be arranged in a mirror-symmetric arrangement on a vertical plane passing through a geometric center of the two-dimensional array of the deep trenches.

16. A method for forming a semiconductor structure, characterized in that, The method includes the following steps: A plurality of first-type deep trenches and a plurality of second-type deep trenches are formed in an upper portion of a substrate, wherein the first-type deep trenches have a plurality of first-length-direction sidewalls extending laterally along a first horizontal direction and the second-type deep trenches have a plurality of second-degree-direction sidewalls extending laterally along a second horizontal direction different from the first horizontal direction, and wherein a plurality of clusters of a plurality of subsets of the first-type deep trenches and a plurality of clusters of a plurality of subsets of the second-type deep trenches alternate laterally along at least one direction selected from the first horizontal direction and the second horizontal direction, and the first-type deep trenches and the second-type deep trenches comprise a plurality of deep trenches arranged in a two-dimensional array; A capacitor structure is formed by depositing and patterning a stack of layers, the stack including at least three metal electrode layers interleaved with at least two node dielectric layers, wherein each layer in the stack includes a horizontal extension overlying a top surface of the substrate and a plurality of vertical extensions protruding downward into a corresponding deep trench of the first type deep trenches and the second type deep trenches; and Multiple stress-relief structures are formed in the corner regions of the two-dimensional array of these deep trenches, each of which comprises: A corresponding set of at least one additional deep trench extending vertically within the substrate; and A corresponding additional layer stack includes at least three metal material layers interleaved with at least two node dielectric layers, and includes at least one vertical extension portion extending vertically into a corresponding deep trench of the at least one additional deep trench and a horizontal extension portion covering a top surface of the substrate.

17. The method as described in claim 16, characterized in that, In the two-dimensional array, the first type deep trenches are configured as a first two-dimensional periodic array and the second type deep trenches are configured as a second two-dimensional periodic array interleaved with the first two-dimensional periodic array, wherein each of the first two-dimensional periodic array and the second two-dimensional periodic array has a first periodic spacing along the first horizontal direction and a second periodic spacing along the second horizontal direction.

18. The method as described in claim 16, characterized in that, The stress relief structures comprise four stress relief structures configured to be arranged in a mirror-symmetric arrangement on a vertical plane passing through a geometric center of the two-dimensional array of the deep trenches.

19. The method as described in claim 16, characterized in that, The following steps are used to form this layer stack and each of these additional layer stacks: A continuous layer stack is deposited in each of the first type deep trenches, the second type deep trenches, and the additional deep trenches, the continuous layer stack comprising at least three continuous metal electrode layers interleaved with at least two continuous node dielectric layers; and The continuous layer stack is patterned into the layer stack including the at least three metal electrode layers and the at least two node dielectric layers, as well as into the additional layer stack.

20. The method as described in claim 17, characterized in that, Further steps include: A first semiconductor die is formed by cutting the substrate, wherein the first semiconductor die includes a cut portion of the substrate and the capacitor structure; and The first semiconductor die is bonded to a second semiconductor die, the second semiconductor die containing a plurality of semiconductor devices, wherein the capacitor structure is electrically connected to the semiconductor devices via a plurality of bonding pads or a plurality of solder material portions.

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