Semiconductor packages including semiconductor wafer stacks

Abstract

This application relates to a semiconductor package including a semiconductor wafer stack. One semiconductor package includes a lower semiconductor wafer and an upper semiconductor wafer offsetly stacked in a first direction, wherein the lower semiconductor wafer includes a plurality of lower pads arranged in a second direction perpendicular to the first direction, and wherein the upper semiconductor wafer includes a plurality of upper pads arranged in the second direction. The semiconductor package further includes bent wiring that electrically connects the lower pads of the lower semiconductor wafer to the upper pads of the upper semiconductor wafer in the first direction. The semiconductor package also includes vertical wiring such that the vertical wiring is disposed on either the lower pad or the upper pad in each pad pair electrically connected by the bent wiring.

Description

Technical Field

[0001] This disclosure relates to semiconductor wafer stacks and semiconductor packages including the semiconductor wafer stacks, and more specifically, to semiconductor wafer stacks having curved wiring and vertical wiring and semiconductor packages including the semiconductor wafer stacks. Background Technology

[0002] Fan-out semiconductor packages with vertical wiring have been proposed to electrically connect stacked semiconductor wafer stacks to redistribution layers. Summary of the Invention

[0003] Some embodiments of this disclosure relate to semiconductor wafer stacks including curved wiring and vertical wiring, and fan-out semiconductor packages.

[0004] Some embodiments of this disclosure relate to semiconductor wafer stacks and fan-out semiconductor packages that reduce electrical interference between vertical wirings.

[0005] According to embodiments of this disclosure, a semiconductor package may include a lower semiconductor wafer and an upper semiconductor wafer stacked in a stepped configuration offset in a first direction, wherein the lower semiconductor wafer includes a plurality of lower pads arranged in a second direction perpendicular to the first direction, and the upper semiconductor wafer includes a plurality of upper pads arranged in the second direction. The semiconductor package may further include bent wiring that electrically connects at least one of the lower pads of the lower semiconductor wafer to at least one of the upper pads of the upper semiconductor wafer in pairs in the first direction. The semiconductor package may further include vertical wiring disposed on either the lower pads and the upper pads electrically connected by the bent wiring.

[0006] According to embodiments of the present disclosure, a semiconductor package may include a semiconductor wafer stack comprising: a lower semiconductor wafer including a first lower pad and a second lower pad, and an upper semiconductor wafer including a first upper pad and a second upper pad stacked on the lower semiconductor wafer; a first bent wiring electrically connecting the first lower pad and the first upper pad in a first direction; a second bent wiring electrically connecting the second lower pad and the second upper pad in a first direction; a first vertical wiring disposed on either the first lower pad and the first upper pad; and a second vertical wiring disposed on either the second lower pad and the second upper pad.

[0007] According to embodiments of this disclosure, a semiconductor package may include a semiconductor wafer stack comprising a lower semiconductor wafer and an upper semiconductor wafer stacked in a stepped configuration offset in a first direction, wherein the lower semiconductor wafer includes a plurality of lower pads arranged in a second direction perpendicular to the first direction, and wherein the upper semiconductor wafer includes a plurality of upper pads arranged in the second direction. The semiconductor wafer stack further includes: bent wiring electrically connecting at least one of the lower pads of the lower semiconductor wafer to at least one of the upper pads of the upper semiconductor wafer in the first direction; and vertical wiring disposed on at least one lower pad of at least every other pair of pads electrically connected in the first direction by the bent wiring.

[0008] According to some embodiments of this disclosure, because the vertical wirings are configured to be spaced apart from each other, electrical signal interference between the vertical wirings can be reduced. Attached Figure Description

[0009] Figures 1A to 1C These are, respectively, a perspective view, a top view, and a partial enlarged view of a semiconductor wafer stack according to embodiments of the present disclosure.

[0010] Figure 1D This is a side view illustrating a semiconductor package including a semiconductor wafer stack according to an embodiment of the present disclosure.

[0011] Figure 2A and Figure 2B This is a perspective view illustrating a semiconductor wafer stack according to an embodiment of the present disclosure.

[0012] Figure 3A This is a perspective view illustrating a semiconductor wafer stack according to an embodiment of the present disclosure.

[0013] Figure 3B This is a side view illustrating a semiconductor package including a semiconductor wafer stack according to an embodiment of the present disclosure.

[0014] Figure 4A and Figure 4B These are a perspective view and a top view illustrating a semiconductor wafer stack according to an embodiment of the present disclosure.

[0015] Figure 5A and Figure 5B These are a perspective view and a top view illustrating a semiconductor wafer stack according to an embodiment of the present disclosure.

[0016] Figure 6A and Figure 6B These are a perspective view and a top view illustrating a semiconductor wafer stack according to an embodiment of the present disclosure.

[0017] Figures 7A to 7C This is a perspective view illustrating a semiconductor wafer stack according to an embodiment of the present disclosure.

[0018] Figure 8A and Figure 8B This is a perspective view illustrating a semiconductor wafer stack according to an embodiment of the present disclosure.

[0019] Figure 9A This is a perspective view illustrating a semiconductor wafer stack according to an embodiment of the present disclosure.

[0020] Figure 9B This is a side view illustrating a semiconductor package including a semiconductor wafer stack according to an embodiment of the present disclosure. Detailed Implementation

[0021] Various embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. The drawings are not necessarily drawn to scale, and in some cases, the scale may have been exaggerated to clearly illustrate the features of the embodiments. When a multilayer structure with two or more layers is disclosed in the drawings or detailed description, the relative positions or arrangement order of the layers shown only reflects a particular embodiment, and therefore the present disclosure is not limited thereto. The present disclosure may include relative positions or arrangement orders different from those shown in the embodiments. Furthermore, the drawings or detailed description of a multilayer structure may not reflect all layers present in a particular multilayer structure (e.g., one or more additional layers may exist between the two layers shown). For example, when a multilayer structure is illustrated in the drawings or detailed description as including a first layer on a second layer or substrate, it refers not only to the case where the first layer is formed directly on the second layer or directly on the substrate, but also to the case where there is one or more other layers between the first and second layers or between the first layer and the substrate.

[0022] Figures 1A to 1C These are, respectively, a perspective view, a top view, and a partial enlarged view illustrating a semiconductor wafer stack 101 according to an embodiment of the present disclosure.

[0023] Reference Figure 1A and Figure 1B The semiconductor wafer stack 101 according to embodiments of the present disclosure may include a lower semiconductor wafer 10, an upper semiconductor wafer 20, a curved wiring 50, and a vertical wiring 60.

[0024] The lower semiconductor wafer 10 and the upper semiconductor wafer 20 may be stacked in a stepped manner in the first direction D1 or staggered in the first direction D1. The lower semiconductor wafer 10 may include a plurality of lower pads 15 arranged in a straight line parallel to the second direction D2, and the upper semiconductor wafer 20 may include a plurality of upper pads 25 arranged in a straight line parallel to the second direction D2.

[0025] The lower pad 15 and the upper pad 25 can be arranged in a straight line parallel to the second direction D2. The lower pad 15 and the upper pad 25 can be respectively disposed in regions closer to the edges of the lower semiconductor wafer 10 and the upper semiconductor wafer 20. The lower pad 15 and the upper pad 25 can respectively protrude from the surfaces of the lower semiconductor wafer 10 and the upper semiconductor wafer 20. In an embodiment, the lower pad 15 and the upper pad 25 can be respectively disposed in recesses below the surfaces of the lower semiconductor wafer 10 and the upper semiconductor wafer 20. The lower pad 15 and the upper pad 25 may comprise metal.

[0026] The curved wiring 50 can electrically connect the lower pad 15 of the lower semiconductor wafer 10 and the upper pad 25 of the upper semiconductor wafer 20, which are arranged adjacent to each other along the first direction D1, in a cascaded manner.

[0027] Vertical traces 60 can be positioned on some of the pads in the lower pad 15 and / or upper pad 25 to stand vertically in the third direction D3. Each vertical trace 60 can be selectively positioned on either the lower pad 15 and the upper pad 25 connected by a corresponding curved trace 50. The vertical traces 60 can be arranged in a zigzag shape or pattern in the second direction D2. That is, the vertical traces 60 can be alternately positioned on the lower pad 15 and the upper pad 25 in the second direction D2. Vertical traces 60 can be positioned on every other pad in the lower pad 15 or the upper pad 25. The curved traces 50 and the vertical traces 60 can be bonded traces including gold (Au) or silver (Ag).

[0028] The lower semiconductor wafer 10 and the upper semiconductor wafer 20 may include semiconductor memory devices. For example, the lower semiconductor wafer 10 and the upper semiconductor wafer 20 may each include one of a memory device such as DRAM, SRAM, ReRAM, MRAM, PCRAM, NVM, or NAND flash memory. In one embodiment, the lower semiconductor wafer 10 and the upper semiconductor wafer 20 may be the same type of semiconductor memory device. Therefore, it is assumed and shown that the lower pad 15 of the lower semiconductor wafer 10 and the upper pad 25 of the upper semiconductor wafer 20 are arranged identically. In another embodiment, either the lower semiconductor wafer 10 or the upper semiconductor wafer 20 may be a logic semiconductor device including a microprocessor.

[0029] Reference Figure 1CEach lower pad 15 and each upper pad 25 can be spaced apart from each other along a first direction D1 with a first pitch P1. The lower pads 15 can be spaced apart from each other along a second direction D2 with a second pitch P2. The upper pads 25 can be spaced apart from each other along a second direction D2 with a second pitch P2. The vertical wiring 60 can be spaced and arranged diagonally relative to the first direction D1 and the second direction D2. Therefore, the spacing distance d between the vertical wiring 60 can be greater than the first pitch P1 and the second pitch P2. In an embodiment, the spacing distance d, the first pitch P1, and the second pitch P2 can be described by the following formula.

[0030] d 2 =P1 2 +P2 2

[0031] Figure 1D This is a side view illustrating a semiconductor package 201 including a semiconductor wafer stack 101 according to an embodiment of the present disclosure.

[0032] Reference Figure 1D The semiconductor package 201 may include a semiconductor wafer stack 101 and a redistribution layer 90. The semiconductor package 201 may also include a molding material 98 surrounding the semiconductor wafer stack 101. The semiconductor package 201 may also include a support substrate 99 for supporting the semiconductor wafer stack 101. The semiconductor package 201 may also include bumps 97 disposed on the redistribution layer 90.

[0033] The redistribution layer 90 may include a lower via 91, a lower interconnect layer 92, an upper via 93, an upper interconnect layer 94, a bump pad 95, and an insulating layer 96.

[0034] The lower via 91 can be electrically connected to the vertical wiring 60 through direct contact. The lower interconnect layer 92 and the upper interconnect layer 94 can extend in the lateral direction to transmit electrical signals in the lateral direction. The upper via 93 can electrically connect the lower interconnect layer 92 to the upper interconnect layer 94. The bump pad 95 can electrically connect the upper interconnect layer 94 to the bump 97 in the vertical direction. The lower via 91, lower interconnect layer 92, upper via 93, and upper interconnect layer 94 can include metals such as copper (Cu), aluminum (Al), tungsten (W), or titanium (Ti). The bump pad 95 can include metals such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), nickel (Ni), or tin (Sn). An insulating layer 96 can cover the lower via 91, lower interconnect layer 92, upper via 93, upper interconnect layer 94, and bump pad 95. The insulating layer 96 can include silicon oxide, silicon nitride, or other insulating materials.

[0035] The redistribution layer 90 may not include a lower pad. The lower pad can be formed with vertical sidewalls using photolithography and electroplating processes such as copper. In contrast, unlike the lower pad, the lower via 91 can be formed with sloping sidewalls using etching processes such as etching. Therefore, the lower via 91 should be formed with a wider gap and a larger pitch than the lower pad.

[0036] When vertical wiring 60 is placed on all the lower pads 15 and upper pads 25, lower pads 15 are absolutely necessary because the distance between the vertical wiring 60 is small. However, in this embodiment, because the vertical wiring 60 is arranged diagonally, the gap between the vertical wiring 60 is large enough. Therefore, the electrical connection between the redistribution layer 90 and the vertical wiring 60 can be achieved solely through the lower via 91 without the need for lower pads. That is, at least one photolithography and etching process can be skipped.

[0037] Bump 97 may be disposed on bump pad 95 of redistribution layer 90. Bump 97 may include solder balls or metal bumps. Molding material 98 may include epoxy molding compound. Molding material 98 may cover lower semiconductor wafer 10, upper semiconductor wafer 20, bent wiring 50, and vertical wiring 60. Support substrate 99 may include glass, plastic, ceramic, silicon, graphene, or metal. Support substrate 99 may be disposed below the lower surface of lower semiconductor wafer 10.

[0038] Figure 2A and Figure 2B This is a perspective view illustrating semiconductor wafer stacks 102 and 103 according to embodiments of the present disclosure. (Refer to...) Figure 2A and Figure 2B The semiconductor wafer stacks 102 and 103 may include a lower semiconductor wafer 10 and an upper semiconductor wafer 20 stacked in a stepped configuration with horizontal offset, a bent wiring 50, and a vertical wiring 60. The lower semiconductor wafer 10 may include a lower pad 15 arranged in a straight line in a second direction D2 on a surface region near its edge. The upper semiconductor wafer 20 may include an upper pad 25 arranged in a straight line in the second direction D2 on a surface region near its edge. The bent wiring 50 may cascade the lower pad 15 and the upper pad 25 in a first direction D1. The vertical wiring 60 may be selectively disposed on either the lower pad 15 or the upper pad 25 electrically connected by the bent wiring 50.

[0039] Reference Figure 2ASome of the vertical traces 60 can be arranged adjacent to each other along the second direction D2. Specifically, some of the vertical traces 60 can be located on lower pads 15 or upper pads 25 adjacent to each other in the second direction D2. For example, adjacent vertical traces 60 can transmit power or DC signals. Because power or DC signals are less affected by interference or coupling, the vertical traces 60, lower pads 15, and upper pads 25 that transmit power or DC signals can be arranged adjacent to each other. Vertical traces 60, lower pads 15, and upper pads 25 that transmit pulse-type or AC signals such as clock signals, command signals, address signals, etc., can be arranged spaced apart.

[0040] Reference Figure 2B Some of the curved wiring 50 can be removed or omitted. For example, some of the adjacent lower pads 15 and upper pads 25 in the first direction D1 may not be electrically connected. The lower pads 15 and upper pads 25 that independently transmit electrical signals to the lower semiconductor wafer 10 or the upper semiconductor wafer 20 may not be connected to each other. The vertical wiring 60 can be respectively provided on the lower pads 15 and upper pads 25 that are not connected to each other.

[0041] Reference Figure 2A and Figure 2B The described technical features can be combined. For example, some of the vertical wiring 60 can be arranged adjacent to each other, and some of the curved wiring 50 can be omitted.

[0042] Figure 3A This is a perspective view illustrating a semiconductor wafer stack 104 according to an embodiment of the present disclosure. (Refer to...) Figure 3A The semiconductor wafer stack 104 may include a lower semiconductor wafer 10, an upper semiconductor wafer 20, bent wiring 50, vertical wiring 60, and metal pillars 70. The vertical wiring 60 may be disposed on the lower pad 15 of the lower semiconductor wafer 10. The metal pillars 70 may be disposed on the upper pad 25 of the upper semiconductor wafer 20. Figure 1AThe vertical wiring 60 on the upper pad 25 of the upper semiconductor wafer 20 of the semiconductor wafer stack 101 shown can be replaced by metal pillars 70. Metal pillars 70 can be disposed on every other pad of the upper pad 25. Vertical wiring 60 can be disposed on every other pad of the lower pad 15. Therefore, the metal pillars 70 and vertical wiring 60 can be arranged in a zigzag shape or pattern in the second direction D2. Alternatively, the metal pillars 70 and vertical wiring 60 can be exclusively alternately disposed on the upper pad 25 and lower pad 15 in the second direction D2. That is, the metal pillars 70 and vertical wiring 60 may not be electrically connected via bent wiring 50. The metal pillars 70 can include a metal such as copper (Cu). Each vertical wiring 60 is formed and disposed by a separate process, but multiple metal pillars 70 can be disposed simultaneously by a single process. That is, the metal pillars 70 can provide higher throughput or bandwidth than the vertical wiring 60. Components and technical features not described can be understood with reference to other accompanying drawings.

[0043] Figure 3B This is a side view illustrating a semiconductor package 202 including a semiconductor wafer stack 104 according to an embodiment of the present disclosure. (Refer to...) Figure 3B ,and Figure 1D In contrast, the semiconductor package 202 may also include metal pillars 70 disposed on the upper pads 25 of the upper semiconductor wafer 20. The metal pillars 70 can electrically connect the upper pads 25 of the upper semiconductor wafer 20 and the lower vias 91 of the redistribution layer 90.

[0044] Additionally, refer to Figure 2A and Figure 2B The features described in this disclosure can be compared with Figure 3A and Figure 3B The semiconductor wafer stack 104 and the semiconductor package 202 are combined. That is, some of the metal pillars 70 or vertical wirings 60 can be arranged adjacent to each other in the second direction D2, and some of the curved wirings 50 can be omitted.

[0045] Figure 4A and Figure 4B These are perspective and top views illustrating a semiconductor wafer stack 105 according to an embodiment of the present disclosure. (Refer to...) Figure 4A and Figure 4BThe semiconductor wafer stack 105 may include a lower semiconductor wafer 10, an intermediate semiconductor wafer 30, an upper semiconductor wafer 20, bent wiring 50, and vertical wiring 60. The lower semiconductor wafer 10, intermediate semiconductor wafer 30, and upper semiconductor wafer 20 may be stacked in a stepped manner or arranged in layers in the first direction D1. The lower semiconductor wafer 10 may include a lower pad 15 arranged in a straight line parallel to the second direction D2. The intermediate semiconductor wafer 30 may include an intermediate pad 35 arranged in a straight line parallel to the second direction D2. The upper semiconductor wafer 20 may include an upper pad 25 arranged in a straight line in the second direction D2. The bent wiring 50 may be electrically connected in a cascaded manner to the lower pad 15, intermediate pad 35, and upper pad 25 aligned in the first direction D1. The vertical wiring 60 may be selectively disposed on any one of the cascaded lower pad 15, intermediate pad 35, and upper pad 25. The vertical wiring 60 may be configured to not be adjacent to each other in the first direction D1 and the second direction D2. For example, the vertical wiring 60 can be arranged to be aligned in a diagonal direction. In an embodiment, the vertical wiring 60 can be arranged randomly.

[0046] Figure 5A and Figure 5B These are perspective and top views illustrating a semiconductor wafer stack 106 according to an embodiment of the present disclosure. (Refer to...) Figure 5A and Figure 5B The semiconductor wafer stack 106 may include a lower semiconductor wafer 10, an intermediate semiconductor wafer 30, and an upper semiconductor wafer 20, a curved wiring 50, and a vertical wiring 60. The lower semiconductor wafer 10, intermediate semiconductor wafer 30, and upper semiconductor wafer 20 may be stacked in a stepped configuration along a first direction D1. The lower semiconductor wafer 10, intermediate semiconductor wafer 30, and upper semiconductor wafer 20 may each include a lower pad 15, an intermediate pad 35, and an upper pad 25. The lower pad 15, intermediate pad 35, and upper pad 25 may be arranged in a straight line parallel to a second direction D2. The curved wiring 50 may be electrically connected in a cascaded configuration to the lower pad 15, intermediate pad 35, and upper pad 25 aligned along the first direction D1. The vertical wiring 60 may be selectively disposed on either the lower pad 15 or the upper pad 25 among the cascaded lower pad 15, intermediate pad 35, and upper pad 25. For example, the vertical wiring 60 may not be disposed on the intermediate pad 35 of the intermediate semiconductor wafer 30. and Figure 4A and Figure 4BCompared to the semiconductor wafer stack 105, the spacing between vertical wirings 60 can be larger. Therefore, signal interference and coupling between vertical wirings 60 can be reduced. In another embodiment, the vertical wirings 60 can be selectively disposed on either the middle pad 35 or the upper pad 25 among the lower pad 15, middle pad 35, and upper pad 25 connected in a cascaded manner. For example, the vertical wirings 60 may not be disposed on the lower pad 15 of the lower semiconductor wafer 10. In another embodiment, the vertical wirings 60 can be selectively disposed on both the lower pad 15 and the middle pad 35 among the lower pad 15, middle pad 35, and upper pad 25 connected in a cascaded manner. For example, the vertical wirings 60 may not be disposed on the upper pad 25 of the upper semiconductor wafer 20.

[0047] Figure 6A and Figure 6B These are perspective and top views illustrating a semiconductor wafer stack 107 according to an embodiment of the present disclosure. (Refer to...) Figure 6A and Figure 6B When with Figure 5A and Figure 5B Compared to the semiconductor wafer stack 106 shown, the vertical wiring 60 can be selectively disposed on two of the lower pad 15, intermediate pad 35, and upper pad 25 that are cascaded together in the semiconductor wafer stack 107 according to embodiments of the present disclosure. For example, the vertical wiring 60 can be disposed on both the lower pad 15 of the lower semiconductor wafer 10 and the corresponding upper pad 25 of the upper semiconductor wafer 20. The vertical wiring 60 can be arranged in a Z-shape or pattern. For example, the vertical wiring 60 can be arranged in a diagonal direction, such as... Figure 6A and Figure 6B As shown.

[0048] Figures 7A to 7C This is a perspective view illustrating a semiconductor wafer stack 108 to 110 according to an embodiment of the present disclosure. (Refer to...) Figure 7AThe semiconductor wafer stack 108 may include a lower semiconductor wafer 10, an intermediate semiconductor wafer 30, an upper semiconductor wafer 20, bent wiring 50, vertical wiring 60, and metal pillars 70. The lower semiconductor wafer 10, the intermediate semiconductor wafer 30, and the upper semiconductor wafer 20 may be stacked in a stepped configuration in a first direction D1. The vertical wiring 60 may be selectively disposed on the lower pad 15 of the lower semiconductor wafer 10 and the intermediate pad 35 of the intermediate semiconductor wafer 30. The metal pillars 70 may be selectively disposed on the upper pad 25 of the upper semiconductor wafer 20. The metal pillars 70 and the vertical wiring 60 may not be electrically connected. That is, the vertical wiring 60 or the metal pillars 70 may be selectively disposed on any of the corresponding upper pad 25, corresponding intermediate pad 35, and corresponding lower pad 15 electrically connected by the bent wiring 50. In another embodiment, the metal pillars 70 may be selectively disposed on the lower pad 15 of the lower semiconductor wafer 10.

[0049] Reference Figure 7B ,and Figure 7A Compared to the semiconductor wafer stack 108 shown, the semiconductor wafer stack 109 may include an upper pad 25a that is not connected to the curved wiring 50. That is, the upper pad 25a on which the metal pillar 70 is disposed can be isolated. The upper pad 25b on which the metal pillar 70 is not disposed can be connected to the curved wiring 50. This facilitates the process of disposing of the metal pillar 70 on the upper pad 25a.

[0050] Reference Figure 7C ,and Figure 7A and Figure 7B Compared to the semiconductor wafer stacks 108 and 109 shown, the semiconductor wafer stack 110 may optionally include a lower pad 16, an upper pad 26, and an intermediate pad 36 on which no metal pillars 70, curved wiring 50, or vertical wiring 60 are provided.

[0051] Figure 8A and Figure 8B This is a perspective view illustrating semiconductor wafer stacks 111 and 112 according to embodiments of the present disclosure. (Refer to...) Figure 8AThe semiconductor wafer stack 111 may include a lower semiconductor wafer 10, a lower intermediate semiconductor wafer 30a, an upper intermediate semiconductor wafer 30b, an upper semiconductor wafer 20, bent wiring 50, and vertical wiring 60. The lower semiconductor wafer 10, lower intermediate semiconductor wafer 30a, upper intermediate semiconductor wafer 30b, and upper semiconductor wafer 20 may be stacked in a stepped configuration along a first direction D1. Each bent wiring 50 may be electrically connected to each of the lower pad 15, lower intermediate pad 35a, upper intermediate pad 35b, and upper pad 25 arranged along the first direction D1. The lower pad 15, lower intermediate pad 35a, upper intermediate pad 35b, and upper pad 25 may be cascaded on the lower semiconductor wafer 10, lower intermediate semiconductor wafer 30a, upper intermediate semiconductor wafer 30b, and upper semiconductor wafer 20, respectively.

[0052] In another embodiment, according to reference Figure 2B The described technical features may optionally omit some of the bent traces 50. For example, some of the pads 15, 25, 35a, and 35b adjacent in the first direction D1 may not be electrically connected. That is, only some of the pads 15, 25, 35a, and 35b aligned in the first direction D1 may be electrically connected. Alternatively, all the pads 15, 25, 35a, and 35b aligned in the first direction D1 may not be electrically connected. The vertical traces 60 may optionally be provided on any one of the pads 15, 25, 35a, and 35b electrically connected by the bent traces 50. The vertical traces 60 may be arranged diagonally and not on the pads 15, 25, 35a, and 35b adjacent to each other in the second direction D2.

[0053] In another embodiment, according to reference Figure 5B The described technical feature is that the vertical wiring 60 can be selectively disposed on any one of the lower pad 15 or the upper pad 25 among the lower pad 15, lower intermediate pad 35a, upper intermediate pad 35b, and upper pad 25 of the electrical connection. For example, the vertical wiring 60 may not be disposed on the lower intermediate pad 35a of the lower intermediate semiconductor wafer 30a and the corresponding upper intermediate pad 35b of the upper intermediate semiconductor wafer 30b.

[0054] In another embodiment, the vertical wiring 60 may be selectively disposed on any one of the corresponding lower pad 15, corresponding lower intermediate pad 35a, or corresponding upper pad 25 among the lower pad 15, lower intermediate pad 35a, upper intermediate pad 35b, and upper pad 25 of the electrical connection. For example, the vertical wiring 60 may not be disposed on the upper intermediate pad 35b of the upper intermediate semiconductor wafer 30b.

[0055] In another embodiment, the vertical wiring 60 may be selectively disposed on any one of the lower pad 15, the corresponding upper pad 35b, or the corresponding upper pad 25 among the lower pad 15, lower intermediate pad 35a, upper intermediate pad 35b, and upper pad 25 of the electrical connection. For example, the vertical wiring 60 may not be disposed on the lower intermediate pad 35a of the lower intermediate semiconductor wafer 30a.

[0056] In another embodiment, some of the vertical wiring 60 can be replaced with metal pillars 70. For example, see reference... Figure 3A The vertical wiring 60 on the upper pad 25 of the upper semiconductor wafer 20 can be replaced by a metal pillar 70.

[0057] Reference Figure 8B The semiconductor wafer stack 112 may include a lower semiconductor wafer 10, a lower intermediate semiconductor wafer 30a, an upper intermediate semiconductor wafer 30b, an upper semiconductor wafer 20, bent wiring 50, and vertical wiring 60. The lower semiconductor wafer 10, lower intermediate semiconductor wafer 30a, upper intermediate semiconductor wafer 30b, and upper semiconductor wafer 20 may be stacked in a stepped configuration along a first direction D1. The vertical wiring 60 may be selectively disposed on two of the pads 15, 25, 35a, and 35b electrically connected by the bent wiring 50. The vertical wiring 60 may be arranged diagonally, such as... Figure 8B As shown. Vertical wiring 60 can be arranged in a zigzag shape or a pattern.

[0058] Figure 9A This is a perspective view illustrating a semiconductor wafer stack 113 according to an embodiment of the present disclosure. (Refer to...) Figure 9A The semiconductor wafer stack 113 may include a lower semiconductor wafer stack 100a and an upper semiconductor wafer stack 100b that is offset from the lower semiconductor wafer stack 100a in a first direction D1. The lower semiconductor wafer stack 100a may include a lower semiconductor wafer 10a and an upper semiconductor wafer 20a stacked in a stepped manner in the first direction D1. The upper semiconductor wafer stack 100b may include a lower semiconductor wafer 10b and an upper semiconductor wafer 20b stacked in a stepped manner in a direction opposite to the first direction D1.

[0059] Lower semiconductor wafers 10a and 10b may each include lower pads 15a and 15b on their surfaces. Upper semiconductor wafers 20a and 20b may each include upper pads 25a and 25b on their surfaces.

[0060] The bent wiring 50 can be cascaded to connect the lower pad 15a of the lower semiconductor wafer 10a of the lower semiconductor wafer stack 100a to the upper pad 25a of the upper semiconductor wafer 20a of the lower semiconductor wafer stack 100a, and / or the bent wiring 50 can be cascaded to connect the lower pad 15b of the lower semiconductor wafer 10b of the upper semiconductor wafer stack 100b to the upper pad 25b of the upper semiconductor wafer 20b of the upper semiconductor wafer stack 100b.

[0061] Vertical routing 60 can be selectively disposed on one of the lower pad 15a and the upper pad 25a and one of the lower pad 15b and the upper pad 25b, which are electrically connected by bent routing 50.

[0062] Figure 9B This is a side view illustrating a semiconductor package 203 including a semiconductor wafer stack 113 according to an embodiment of the present disclosure. (Refer to...) Figure 9B The semiconductor package 203 may include Figure 9A The semiconductor wafer stack 113 and redistribution layer 90 are shown. The semiconductor package 203 may further include a molding material 98 surrounding the semiconductor wafer stack 113 and a support substrate 99 supporting the semiconductor wafer stack 113. The semiconductor package 203 may also include a support structure 89 disposed between the exposed lower surface of the lower semiconductor wafer 10b of the upper semiconductor wafer stack 100b and the support substrate 99. The support structure 89 may be vertically aligned with the lower pad 15b of the lower semiconductor wafer 10b of the upper semiconductor wafer stack 100b. The support structure 89 may include a portion of a metal, plastic, ceramic, silicon pillar, wafer such as a dummy semiconductor wafer, or other structures capable of supporting the lower semiconductor wafer 10b. The support structure 89 may support the lower semiconductor wafer 10b and upper semiconductor wafer 20b of the upper semiconductor wafer stack 100b during the process of forming bent wiring 50 and vertical wiring 60 on the lower semiconductor wafer 10b and upper semiconductor wafer 20b of the upper semiconductor wafer stack 100b.

[0063] Although not specifically described, it will be understood that the technical features described with reference to this specification and the accompanying drawings can be combined in various ways.

[0064] While the technical features of this disclosure have been shown and described with reference to specific embodiments thereof, it should be noted that this disclosure is not limited to the embodiments described herein. Furthermore, those skilled in the art will understand that various modifications and variations can be made thereto without departing from the scope of this disclosure.

[0065] Cross-reference of related applications

[0066] This application claims priority to Korean Patent Application No. 10-2021-0073742, filed on June 7, 2021, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor package comprising: A lower semiconductor wafer and an upper semiconductor wafer are stacked in a stepped configuration with an offset in a first direction, wherein... The lower semiconductor wafer includes a plurality of lower pads arranged in a second direction perpendicular to the first direction, and The upper semiconductor wafer includes a plurality of upper pads arranged in the second direction; A curved wiring, wherein the curved wiring electrically connects, in pairs in the first direction, at least one of the plurality of lower pads of the lower semiconductor wafer to at least one of the plurality of upper pads of the upper semiconductor wafer; and Vertical wiring, wherein the vertical wiring is disposed on either the lower pad or the upper pad that is electrically connected by the curved wiring. The distance between the vertical wirings of adjacent pad pairs is greater than the pitch between the upper pads of adjacent pad pairs.

2. The semiconductor package according to claim 1, wherein, The vertical wiring is arranged in a Z-shaped pattern in the second direction.

3. The semiconductor package according to claim 1, wherein, The vertical wiring is arranged diagonally relative to the first direction and the second direction.

4. The semiconductor package according to claim 1, wherein, The distance between the vertical traces of adjacent pad pairs is greater than the pitch between the upper and lower pads of the pad pair along the first direction.

5. The semiconductor package according to claim 1, wherein, At least one vertical wiring is disposed on at least one of the plurality of upper pads, and At least one vertical wiring is provided on at least one of the plurality of lower pads.

6. The semiconductor package of claim 1, further comprising a metal pillar disposed on the upper pad, one of the lower pad and the upper pad electrically connected by the curved wiring.

7. The semiconductor package according to claim 6, wherein, Pad pairs with vertical wiring located on the lower pad and pad pairs with metal pillars located on the upper pad are arranged alternately in the second direction.

8. The semiconductor package according to claim 1, wherein, Some of the lower and upper pads arranged in the first direction are not connected by the curved wiring.

9. The semiconductor package according to claim 8, wherein, The vertical wiring is disposed on the lower pad and the upper pad that are not connected by the curved wiring.

10. The semiconductor package of claim 1, further comprising an intermediate semiconductor wafer located between the lower semiconductor wafer and the upper semiconductor wafer, wherein, The intermediate semiconductor wafer includes intermediate pads. The intermediate pad, together with the lower pad and the upper pad, is arranged along the first direction, and The lower pad, the middle pad, and the upper pad arranged in the first direction are electrically connected in a cascaded manner via the curved wiring.

11. The semiconductor package of claim 10, wherein, The vertical wiring is disposed on any one of the lower pad, the middle pad, and the upper pad that are electrically connected by the curved wiring.

12. The semiconductor package of claim 10, wherein, The vertical wiring is disposed on either the lower pad or the upper pad that are electrically connected by the curved wiring, but not on the intermediate pad.

13. The semiconductor package of claim 1, further comprising a redistribution layer, wherein, The redistribution layer includes a lower via, a lower interconnect layer, an upper via, and an upper interconnect layer, and The lower via is electrically connected to at least one of the vertical cablings, and the upper via is electrically connected to the lower interconnect layer and the upper interconnect layer.

14. A semiconductor package comprising a semiconductor wafer stack, the semiconductor wafer stack comprising: A lower semiconductor wafer and an upper semiconductor wafer, the lower semiconductor wafer including a first lower pad and a second lower pad, and the upper semiconductor wafer stacked on the lower semiconductor wafer and including a first upper pad and a second upper pad; A first curved wiring, which electrically connects the first lower pad and the first upper pad in a first direction; The second curved wiring is electrically connected to the second lower pad and the second upper pad in the first direction; A first vertical routing is disposed on either the first lower pad or the first upper pad; as well as The second vertical routing is disposed on either the second lower pad or the second upper pad. The first lower pad and the first upper pad are aligned in the first direction. The second lower pad and the second upper pad are aligned in the first direction. The first lower pad and the second lower pad are aligned in a second direction, which is perpendicular to the first direction. Wherein, the first upper pad and the second upper pad are aligned in the second direction, and The first vertical wiring and the second vertical wiring are arranged diagonally relative to the first direction and the second direction.

15. The semiconductor package of claim 14, wherein, The first lower pad and the first upper pad are spaced apart by a first pitch in the first direction, and The distance between the first vertical wiring and the second vertical wiring is greater than the first pitch.

16. The semiconductor package of claim 15, wherein, The first lower pad and the second lower pad are spaced apart by a second pitch in a second direction, the second direction being perpendicular to the first direction, and The distance between the first vertical wiring and the second vertical wiring is greater than the second pitch.

17. A semiconductor package comprising a semiconductor wafer stack, the semiconductor wafer stack comprising: A lower semiconductor wafer and an upper semiconductor wafer are stacked in a stepped configuration with an offset in a first direction; as well as Metal pillar, The lower semiconductor wafer includes a plurality of lower pads arranged in a second direction, which is perpendicular to the first direction. The upper semiconductor wafer includes a plurality of upper pads arranged in the second direction. In this configuration, the bent wiring electrically connects at least one of the plurality of lower pads of the lower semiconductor wafer to at least one of the plurality of upper pads of the upper semiconductor wafer in the first direction. Wherein, at least every other pad connected by the curved wiring in the first direction is provided on one of the plurality of lower pads. Wherein, the metal pillar is disposed on the lower pad at least every other pad connected by the bent wiring, and The metal pillars and the vertical wiring are alternately arranged on the pad pairs in the second direction.

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