Semiconductor device and method for forming a wiring structure avoiding short circuits thereof

Abstract

The present application relates to semiconductor devices and methods for forming wiring structures that avoid shorting thereof. A semiconductor device includes a substrate; a memory cell region over the substrate; a peripheral region over the substrate, the peripheral region adjacent to the memory cell region; and a plurality of first and second word lines extending across the memory cell region and the peripheral region; wherein the plurality of first word lines and the plurality of second word lines are arranged alternately with each other; and wherein a length of the first word lines in the peripheral region is longer than a length of the second word lines in the peripheral region.

Description

Technical Field

[0001] This application relates to semiconductor devices, and more specifically, to semiconductor devices and methods for forming wiring structures to prevent short circuits therein. Background Technology

[0002] For example, in semiconductor devices such as Dynamic Random Access Memory (DRAM), there is a pursuit of further miniaturization to increase data storage capacity. For instance, the repeatability of the interconnects between DRAM word lines and bit lines is reduced, and the distances between word lines and bit lines are shortened. However, when forming contact electrodes that connect to word lines and bit lines, if the positioning relative to the word lines and bit lines is misaligned, a contact electrode that should be connected to a specific word line may become connected to an adjacent word line, or a contact electrode that should be connected to a specific word line may become connected to an adjacent bit line. Summary of the Invention

[0003] One aspect of this disclosure provides a semiconductor device comprising: a substrate; a memory cell region above the substrate; a peripheral region above the substrate, the peripheral region being adjacent to the memory cell region; and a plurality of first and second word lines extending across the memory cell region and the peripheral region; wherein the plurality of first word lines and the plurality of second word lines are arranged alternately to each other; and wherein the length of the first word lines in the peripheral region is longer than the length of the second word lines in the peripheral region.

[0004] Another aspect of this disclosure provides a semiconductor device comprising: a substrate; a memory cell region above the substrate; a peripheral region above the substrate, the peripheral region being adjacent to the memory cell region; and a plurality of first and second bit lines extending across the memory cell region and the peripheral region; wherein the plurality of first bit lines and the plurality of second bit lines are arranged alternately to each other; and wherein the length of the first bit line in the peripheral region is longer than the length of the second bit line in the peripheral region.

[0005] Another aspect of this disclosure provides a method comprising: forming a repeat of four linear mask patterns extending across a memory cell region and a peripheral region provided above a substrate; forming a first resist pattern periodically disposed on the linear mask patterns to sandwich three of the linear mask patterns in the middle; forming a second resist pattern periodically disposed on the linear mask patterns to sandwich one of the linear mask patterns between the first resist pattern and the second resist pattern; and transferring an interlaced pattern to a component disposed below the linear mask patterns, using the linear mask patterns, the first resist pattern, and the second resist pattern as masks to form the interlaced pattern from the linear mask patterns, the first resist pattern, and the second resist pattern. Attached Figure Description

[0006] Figure 1 This is a plan view illustrating a portion of the memory cell region of a semiconductor device according to an embodiment. Figure 2 This is a plan view illustrating the schematic configuration of the storage pad;

[0007] Figure 3A This is a plan view layout illustrating a schematic arrangement of the memory cell regions of a semiconductor device according to an embodiment, and is Figure 2 An enlarged view of the end region A1 of the memory pad;

[0008] Figure 3B This is a plan view layout illustrating a schematic arrangement of the memory cell regions of a semiconductor device according to an embodiment, and is Figure 2 An enlarged view of the end region A2 of the memory pad;

[0009] Figure 4A This is a schematic longitudinal section of the memory cell region and peripheral region of a semiconductor device according to an embodiment, and it illustrates the arrangement along... Figure 3A A schematic configuration of the line BB section in the diagram;

[0010] Figure 4B This is a longitudinal section illustrating the schematic arrangement of the memory cell region and peripheral region of a semiconductor device according to an embodiment, and it illustrates the arrangement along... Figure 3A A schematic configuration of the CC section in the diagram;

[0011] Figure 5A This is a plan view layout illustrating a schematic arrangement of the memory cell regions of a semiconductor device according to an embodiment, and is Figure 2 Enlarged view of the end region A3 of the memory pad;

[0012] Figure 5BThis is a plan view layout illustrating a schematic arrangement of the memory cell regions of a semiconductor device according to an embodiment, and is Figure 2 Enlarged view of the end region A4 of the memory pad;

[0013] Figure 6A This is a longitudinal section illustrating the schematic arrangement of the memory cell region and peripheral region of a semiconductor device according to an embodiment, and it illustrates the arrangement along... Figure 5A A schematic configuration of the DD section in the diagram;

[0014] Figure 6B This is a longitudinal section illustrating the schematic arrangement of the memory cell region and peripheral region of a semiconductor device according to an embodiment, and it illustrates the arrangement along... Figure 5A A schematic configuration of the EE portion in the diagram;

[0015] Figure 7A , 7B Figures 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A, and 14B are diagrams illustrating a method of forming a semiconductor device according to an embodiment, and illustrating examples of illustrative configurations in exemplary process stages. Figure 7A , 8A Figures 9A, 10A, 11A, 12A, 13A, and 14A are plan views illustrating examples of illustrative configurations in exemplary process phases. Figure 7B , 8B 9B, 10B, 11B, 12B, 13B, and 14B are descriptions along... Figure 7A , 8A Longitudinal sections of the schematic configuration of the line FF portion in 9A, 10A, 11A, 12A, 13A and 14A;

[0016] Figure 15A , 15B Figures 15C and 15C are diagrams illustrating a method of forming a semiconductor device according to an embodiment, and illustrating an example of a schematic configuration in an exemplary processing stage. Figure 15A This is a floor plan illustrating an example of a schematic configuration in an exemplary processing phase. Figure 15B It means to explain along Figure 15A The schematic configuration of the longitudinal section of the line FF in the diagram. Figure 15C It means to explain along Figure 15A A schematic longitudinal section of the line GG portion in the diagram;

[0017] Figure 16A , 16B Figures 16C, 17A, 17B, and 17C are diagrams illustrating a method of forming a semiconductor device according to an embodiment, and illustrating examples of illustrative configurations in exemplary process stages. Figure 16A and 17A This is a floor plan illustrating an example of a schematic configuration in an exemplary process phase. Figure 16B and 17B It means to explain along Figure 16A and 17A The schematic configuration of the longitudinal section of line GG in the diagram. Figure 16C and 17C It means to explain along Figure 16A and 17A A schematic longitudinal section of the line HH portion in the diagram;

[0018] Figure 18A , 18B Figures 19A, 19B, 20A, 20B, 21A, 21B, 22A, 22B, 23A, 23B, 24A, 24B, 25A, and 25B are diagrams illustrating a method of forming a semiconductor device according to an embodiment, and illustrating examples of illustrative configurations in exemplary process stages. Figure 18A , 19A 20A, 21A, 22A, 23A, 24A, and 25A are examples illustrating illustrative configurations in exemplary process phases. Figure 18B , 19B 20B, 21B, 22B, 23B, 24B, and 25B are descriptions along... Figure 18A , 19A Longitudinal cross sections of the schematic configuration of line JJ in 20A, 21A, 22A, 23A, 24A and 25A;

[0019] Figure 26A , 26B Figures 26C, 27A, 27B, and 27C are diagrams illustrating a method of forming a semiconductor device according to an embodiment, and illustrating examples of illustrative configurations in exemplary process stages. Figure 26A and 27A This is a floor plan illustrating an example of a schematic configuration in an exemplary process phase. Figure 26B and 27B It means to explain along Figure 26A and 27A The schematic configuration of the longitudinal section of line JJ in the diagram. Figure 26C and 27C It means to explain along Figure 26A and 27A A schematic longitudinal section of the line KK portion;

[0020] Figure 28 This is a longitudinal section illustrating an example of the overall schematic configuration of a memory cell region in a semiconductor device according to an embodiment; and

[0021] Figure 29 This is a circuit diagram illustrating a schematic configuration of the equivalent circuit of a memory cell in a semiconductor device according to an embodiment. Detailed Implementation

[0022] Various embodiments of the invention will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which illustrate specific aspects and embodiments in which the invention can be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that other embodiments may be used and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0023] In the following text, reference will be made to Figures 1 to 29 A semiconductor device and a method of forming the same according to embodiments are described. A semiconductor device according to an embodiment will be described using DRAM as an example. In the description of the embodiments, common or related elements and substantially the same elements are labeled with the same symbols, and their descriptions are reduced or omitted. In the drawings mentioned below, the dimensions and aspect ratios of each unit in each drawing may not match the actual dimensions and aspect ratios in the embodiments. Furthermore, in the following description, the vertical direction refers to the vertical direction when the semiconductor substrate 10 is located on the bottom.

[0024] Figure 1 and 2 This is a diagram illustrating the planar layout of a semiconductor device according to an embodiment. For example... Figure 1 As described, the semiconductor device has multiple memory pads 2 in a matrix disposed on the surface of a semiconductor substrate. For example... Figure 2 As illustrated, in each of the memory pads 2, a plurality of word lines 4 are arranged in parallel, extending in the X direction of the diagram. Additionally, a plurality of bit lines 5 are arranged in parallel within the memory pad 2, orthogonal to the word lines 4, or in other words, extending in the Y direction of the diagram. The direction parallel to the word lines 4, or in other words, the X direction, is designated as the word line direction. The direction parallel to the bit lines 5, or in other words, the Y direction, is designated as the bit line direction.

[0025] End regions A1 and A2 of the memory pad are positioned in the peripheral portion in the word line direction of the memory pad 2. Each word line 4 is connected to a row decoder not described in the peripheral portion. The row decoder accepts input of the row address selected when reading / writing a memory cell from an undescribed row address buffer. Each of the multiple word lines 4 is paired with a corresponding one among the multiple memory cells and controls access to the corresponding memory cell among the multiple memory cells.

[0026] End regions A3 and A4 of the memory pad are positioned in the peripheral portion in the bitline direction of memory pad 2. Each bitline 5 is connected to a column decoder not described in the peripheral portion. The column decoder accepts input of the column address selected when reading / writing a memory cell from an undescribed column address buffer. Each of the multiple bitlines 5 is paired with a corresponding one among the multiple memory cells and controls access to the corresponding memory cell among the multiple memory cells.

[0027] Figure 3A yes Figure 2 An enlarged layout diagram of the end region A1 of the memory pad. Figure 3B yes Figure 2 An enlarged layout diagram of the end region A2 of the memory pad. Figure 4A It means to explain along Figure 3A The longitudinal section of line BB in the schematic configuration. Figure 4B It means to explain along Figure 3A The schematic configuration of the longitudinal section of line CC in the diagram. Figure 3B The layout described in the text is the same as Figure 3A The layout described is symmetrical, and the other configurations are the same. Figure 3B The cross section of the structure in the middle is Figure 4A and 4B The structure in the middle is reversed from left to right.

[0028] because Figure 3A and 3B The structures containing cross-sectional structures are basically the same, so the description of semiconductor devices will mainly refer to... Figure 3A , 4A and 4B and refer only when necessary Figure 3B Similarly, Figure 5A and 5B The structures containing cross-sectional structures are essentially the same, and therefore the description of semiconductor devices will primarily refer to... Figure 5A , 6A and 6B and refer only when necessary Figure 5B .

[0029] like Figure 3A As described, in the memory pad end region A1, the semiconductor device has a memory cell region M and a peripheral region N. In the memory cell region M, a plurality of word lines 4 arranged at equal intervals in the Y direction and a plurality of bit lines 5 arranged at equal intervals in the X direction are orthogonally arranged. An undescribed active region forming the memory cell is located at the intersection point between the word lines 4 and the bit lines 5. In the peripheral region N, peripheral circuitry, such as an undescribed row decoder and row address buffer, is provided.

[0030] exist Figure 3AIn this design, multiple word lines 4 are classified into multiple first word lines 401 and multiple second word lines 402. The first word lines 401 are designated as odd-numbered word lines 401, and the second word lines 402 are designated as even-numbered word lines 402. Each of the first word lines 401, i.e., each of the odd-numbered word lines 401, and each of the second word lines 402, i.e., each of the even-numbered word lines 402, are arranged alternately.

[0031] Word lines 4 are arranged to extend linearly in the X direction from memory cell region M across peripheral region N. In peripheral region N, word line contacts 7 are electrically connected to first word lines 401. In peripheral region N, each of the second word lines 402 not connected to word line contacts 7 is arranged adjacently between the first word lines 401 connected to word line contacts 7. Word line contacts 7 are connected to the first word lines 401 in edge portions 4a. Edge portions 4a correspond to the overlapping portion between the first word lines 401 and word line contacts 7. The width of the edge portion 4a of each first word line 401 is the same as the width of the portion of the first word line 401 excluding the edge portion 4a.

[0032] like Figure 4A and 4B As described, the semiconductor device has word lines 4, bit lines 5, and word line contacts 7. The semiconductor substrate 10 is divided into a memory cell region M and a peripheral region N. A plurality of memory cells (not described) are provided in the memory cell region M. A peripheral isolation 11 is provided in the peripheral region N. In the peripheral isolation 11, a first insulating film 12 and a second insulating film 14 are embedded in trenches provided in the semiconductor substrate 10. A third insulating film 16 is provided below the word lines 4, while a fourth insulating film 18 and a fifth insulating film 20 are provided above the word lines 4.

[0033] Multiple bit lines 5 and a seventh insulating film 22 are provided on top of the fifth insulating film 20. An eighth insulating film 24 is provided to cover the top of the second insulating film 14, the fifth insulating film 20, the bit lines 5, and the seventh insulating film 22. The top surface of the seventh insulating film 22 is further covered by a ninth insulating film 26.

[0034] exist Figure 4A In the middle, the character line contact point 7 is formed in the outer area N. Figure 4B In the middle, the word line contact 7 is not formed in the peripheral area N. In the peripheral area N, the word line contact 7 is provided so that it can reach the top surface of the word line 4 from the top surface of the ninth insulating film 26.

[0035] The first insulating film 12, the fourth insulating film 18, the fifth insulating film 20, the seventh insulating film 22, and the ninth insulating film 26 contain silicon nitride (SiN). The second insulating film 14, the third insulating film 16, and the eighth insulating film 24 contain silicon dioxide (SiO2). For example, the word line 4 contains a conductive material, such as layered titanium nitride (TiN) and polycrystalline silicon (polycrystalline Si). For example, the word line contact 7 contains a conductive material, such as tungsten (W).

[0036] like Figure 3A and 4A As explained, in the peripheral region N of the memory pad end region A1, the first word line 401 is longer than the second word line 402. The second word line 402 does not exist in the region adjacent to the edge portion 4a in the Y direction. Therefore, the side of each edge portion of the first word line 401 does not contain the second word line 402. Therefore, when the word line contact 7 is formed in the edge portion 4a of the first word line 401, the connection with the second word line 402 adjacent to the word line contact 7 is suppressed, or in other words, short-circuited, even if misalignment occurs during the photolithography step.

[0037] like Figure 3B and 4B As described, in the peripheral region N of the memory pad end region A2, the relationship between the first word line 401 and the second word line 402 is reversed. In the peripheral region N of the memory pad end region A2, the second word line 402 is longer than the first word line 401. A word line contact 7 is provided on the second word line 402. An edge portion 4b corresponds to the overlapping portion between the word line contact 7 and the second word line 402. The first word line 401 is not present in the region adjacent to the edge portion 4b in the Y direction. Therefore, the side of each edge portion of the second word line 402 does not contain the first word line 401. Therefore, as... Figure 3B and 4B As explained, when a word line contact 7 is formed in the edge portion 4b of the second word line 402, the connection with the first word line 401 adjacent to the word line contact 7 is suppressed, or in other words, short-circuited, even if misalignment occurs during the photolithography step. The width of the edge portion 4b of each second word line 402 is the same as the width of the portion of the second word line 402 excluding the edge portion 4b.

[0038] Figure 5A yes Figure 2 An enlarged layout diagram of the end region A3 of the memory pad. Figure 5B yes Figure 2 An enlarged layout diagram of the end region A4 of the memory pad. Figure 6A It means to explain along Figure 5A The schematic configuration of the longitudinal section of line DD in the diagram. Figure 6B It means to explain along Figure 5A The longitudinal section of the line EE in the schematic configuration. Figure 5BThe layout described in the text is the same as Figure 5A The layout described is symmetrical, and the other configurations are the same. Figure 5B The cross section of the structure in the middle is Figure 6A and 6B The structure in the middle is reversed from left to right. Figure 5A and 5B The structures containing cross-sectional structures are essentially the same, and therefore the description of semiconductor devices will primarily refer to... Figure 5A , 6A and 6B and refer only when necessary Figure 5B .

[0039] like Figure 5A As described, in the memory pad end region A3, the semiconductor device has a memory cell region M and a peripheral region N. In the peripheral region N, peripheral circuitry, such as a column decoder and a column address buffer (not described), is provided.

[0040] exist Figure 5A In this configuration, multiple bit lines 5 are classified into alternating first bit lines 501 and second bit lines 502. The first bit lines 501 are designated as odd-numbered bit lines 501, and the second bit lines 502 are designated as even-numbered bit lines 502. Each of the multiple first bit lines 501, i.e., each of the odd-numbered bit lines 501, and each of the multiple second bit lines 502, i.e., each of the even-numbered bit lines 502, are arranged alternately.

[0041] Bit line 5 is arranged to extend linearly in the Y direction from memory cell region M across peripheral region N. In peripheral region N, bit line contact 8 is electrically connected to first bit line 501. In peripheral region N, each of the second bit lines 502 not connected to bit line contact 8 is arranged adjacently between the first bit lines 501 connected to bit line contact 8. Bit line contact 8 is connected in the edge portion 5a of the first bit line 501. Edge portion 5a corresponds to the overlapping portion between the first bit line 501 and bit line contact 8. The width of the edge portion 5a of each first bit line 501 is the same as the width of the portion of the first bit line 501 excluding the edge portion 5a.

[0042] like Figure 6A and 6B As described, the semiconductor device has bit line 5 and bit line contact 8. A seventh insulating film 22, an eighth insulating film 24 and a ninth insulating film 26 are provided on top of bit line 5.

[0043] like Figure 5A and 6AAs explained, in the peripheral region N of the memory pad end region A3, the first bit line 501 is longer than the second bit line 502. The second bit line 502 does not exist in the region adjacent to the edge portion 5a in the X direction. Therefore, the side of each edge portion of the first bit line 501 does not contain the second bit line 502. Therefore, when the bit line contact 8 is formed in the edge portion 5a of the first bit line 501, the connection with the second bit line 502 adjacent to the bit line contact 8 is suppressed, or in other words, short-circuited, even if misalignment occurs during the photolithography step.

[0044] like Figure 5B and 6B As described, in the peripheral region N of the memory pad end region A4, the relationship between the second bit line 502 and the first bit line 501 is reversed. In the peripheral region N of the memory pad end region A4, the second bit line 502 is longer than the first bit line 501. Bit line contacts 8 are provided on the second bit line 502. Edge portions 5b correspond to the overlapping portion between the bit line contacts 8 and the second bit line 502. The width of the edge portion 5b of each second bit line 502 is the same as the width of the portion of the second bit line 502 excluding the edge portion 5b.

[0045] The first line 501 does not exist in the region adjacent to the second line 502 in the X direction. Therefore, the sides of each edge portion of the second line 502 do not contain the first line 501. Therefore, as Figure 5B and 6B As explained, when the bit line contact 8 is formed in the edge portion 5b of the second bit line 502, the connection with the first bit line 501 adjacent to the bit line contact 8 is suppressed, or in other words, short-circuited, even if misalignment occurs during the photolithography step.

[0046] Figure 28 This is a longitudinal section illustrating an example of the overall schematic configuration of a memory cell region in a semiconductor device according to an embodiment. For example... Figure 28 As described above, below capacitor 140, components included in DRAM memory cell 145 are provided, such as semiconductor substrate 112, shallow trench isolation 114, access transistor 142, and capacitor contacts 116. Capacitor 140 is provided on semiconductor substrate 112, in which components such as shallow trench isolation 114, access transistor 142, and capacitor contacts 116 are formed. Semiconductor substrate 112 corresponds to semiconductor substrate 10, which is described later.

[0047] Figure 28 The bottom electrode of the capacitor 140 described herein is electrically connected via capacitor contact 116 to one side of the source-drain region of the access transistor 142 formed in the active region of the semiconductor substrate 112. The bottom electrode of the capacitor 140 is connected to the semiconductor substrate 112. For example... Figure 2 , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A and Figure 6B In the diagram, the gate electrode of access transistor 142 corresponds to word line 4.

[0048] like Figure 28 As described, an upper portion comprising multiple upper wiring layers is provided above the capacitor 140, the upper wiring layers containing components such as interconnects 148, 149, 150, and 151. The upper portion is disposed above the memory cell 145. The top electrode of the capacitor 140 is disposed near the upper wiring layers containing components such as interconnects 148, 149, 150, and 151. Figure 28 The components 146, 147 and 152 described herein contain insulating material.

[0049] Similar to Figure 28 The configuration described herein, in Figure 4A , 4B The capacitor 140 and the upper layer are provided above the diagrams illustrated in 6A and 6B.

[0050] and, Figure 29 The equivalent circuit of a memory cell array of a semiconductor device according to an embodiment is described. A plurality of memory cells 145 are arranged in a matrix, wherein each memory cell 145 is connected to an intersection point orthogonal to a plurality of word lines 4 and a plurality of bit lines 5 disposed relative to each other. A single memory cell 145 includes a pair of access transistors 142 and a capacitor 140.

[0051] For example, access transistor 142 includes a metal-oxide-semiconductor field-effect transistor (MOSFET). The gate electrode of access transistor 142 serves as DRAM word line 4. Word line 4 serves as a control line controlling the selection of the corresponding memory cell. One of the source and drain of access transistor 142 is connected to one of the bit lines 5, while the other is connected to capacitor 140. Capacitor 140 includes a capacitor and stores data by retaining accumulated charge in the capacitor.

[0052] When data is written to one of the memory cells 145, the potential of the access transistor 142 is applied to word line 4, and a low or high potential corresponding to the "0" or "1" of the data to be written is applied to bit line 5. When data is read from one of the memory cells 145, the potential of the access transistor 142 is applied to word line 4, and data determination is performed by causing a sense amplifier connected to bit line 5 to sense the potential drawn from capacitor 140 to bit line 5.

[0053] References from Figure 3A and 3B arrive Figure 27A , 27B The figures for 27C illustrate a method of forming a semiconductor device according to an embodiment. Figure 5A and 5B arrive Figure 17A , 17B The diagrams for 17C are explained in sequence. Figure 2 A schematic configuration of the end region A1 of the memory pad. (Source: [Insert Source Here]) Figure 18A and 18B arrive Figure 27A , 27B The diagrams for 27C are explained in sequence. Figure 2 Schematic configuration of the end region A3 of the memory pad.

[0054] like Figure 7A and 7B As described, the first sacrificial film 30 and the photoresist 31 are formed on the semiconductor substrate 10. The photoresist 31 is patterned in a line and spatial layout using known photolithography techniques.

[0055] For the semiconductor substrate 10, a single-crystal silicon substrate may be used, for example. For example, the first sacrificial film 30 contains an insulating material, such as silicon dioxide (SiO2). For example, the first sacrificial film 30 is formed by chemical vapor deposition (hereinafter referred to as "CVD"). The dimension of the resist 31 in the Y direction is approximately [missing information]. Figure 17A The dimension in the Y direction of the character line 4 described herein is three times that of the character line 4. The repeating spacing P2 of the resist 31 is... Figure 17A The repeating spacing P1 of the character line 4 described in the text is four times that of the character line 4.

[0056] Next, as Figure 8A and 8B As described herein, a second sacrificial film 32 is formed to cover the first sacrificial film 30 and the photoresist 31. For example, the second sacrificial film 32 contains an insulating material, such as silicon nitride (SiN). The second sacrificial film 32 is formed, for example, using low-temperature CVD and deposited, for example, at approximately room temperature. The thickness of the second sacrificial film 32 is set to be substantially the same as the width dimension of each word line 4 described subsequently.

[0057] Next, as Figure 9A and 9BAs described, the second sacrificial film 32 is etched back by performing anisotropic dry etching on the semiconductor substrate 10 on which it is deposited, and a pillar 321 is formed by leaving the second sacrificial film 32 on the sidewalls of the resist 31. The surface of the first sacrificial film 30 is exposed by the etch-back. A pillar 321 encapsulating the resist 31 is formed. Therefore, the ends of the pillar 321 are U-shaped. Thereafter, the resist 31 is removed. The Y-direction dimension of the pillar 321 is specified by the thickness of the second sacrificial film 32. Figure 9B As explained in the text, along Figure 9A In the cross-sectional view of line FF, support column 321 is arranged in a linear and spatial layout.

[0058] Next, as Figure 10A and 10B As described, a third sacrificial film 33 is formed to cover the first sacrificial film 30 and the pillar 321. The third sacrificial film 33 contains an insulating material. For example, the third sacrificial film 33 contains silicon nitride. For example, the third sacrificial film 33 is formed by CVD. The thickness of the third sacrificial film 33 is set to be substantially the same as the width dimension of each word line 4 described below.

[0059] Next, as Figure 11A and 11B As described, the third sacrificial film 33 is etched back by performing anisotropic dry etching on the semiconductor substrate 10 on which the third sacrificial film 33 is deposited, and the pillar 331 is formed by leaving the third sacrificial film 33 on the sidewall of the pillar 321. The surface of the first sacrificial film 30 is exposed by the etch-back. The pillar 331 enclosing the pillar 321 is formed. Therefore, the end of the pillar 331 is U-shaped. Thereafter, the pillar 321 is removed by performing dry etching under conditions that allow selective removal of the pillar 321.

[0060] The Y-direction dimension of the support 331 is specified by the thickness of the third sacrificial membrane 33. For example... Figure 11B As explained in the text, along Figure 11A In the cross-sectional view of line FF, support column 331 is arranged in a linear and spatial layout with repeating spacing P3. The repeating spacing P3 of support column 331 is... Figure 17A The repeating spacing P1 of the character line 4 described in the text is basically the same.

[0061] Next, as Figure 12A and 12B As described, a fourth sacrificial film 34 is formed to cover the first sacrificial film 30 and the pillars 331, and is also embedded between the plurality of pillars 331. For example, the fourth sacrificial film 34 contains an insulating material, such as silicon nitride. For example, the fourth sacrificial film 34 is formed by CVD.

[0062] Next, as Figure 13A and13B As described, the fourth sacrificial film 34 is etched until the top surface of the pillar 331 is exposed, and the pillar 331 is subsequently removed by performing dry etching under conditions that allow selective removal of the pillar 331. The structure remaining after this step is the pillar 341. The pillar 341 has a reverse pattern of the pillar 331. The corresponding areas of the removal of the plurality of pillars 331 become gaps 342 between the plurality of pillars 341. The gaps 342 form an opening pattern. Along Figure 13A In the cross-sectional view of line FF, the supports 341 are arranged in a linear and spatial layout. The repeating spacing P4 of the gaps 342 between the supports 341 is... Figure 17A The repeating spacing P1 of the character line 4 described in the text is basically the same.

[0063] Next, as Figure 14A and 14B As explained, a resist 35 is formed to fill some of the multiple gaps 342 in the peripheral region N, while leaving three unfilled gaps 342 in the Y direction. Figure 14B It means to explain along Figure 14A The longitudinal section of the line FF in the image. The resist 35 is patterned using a known photolithography technique. The resist 35 is formed to partially fill the gap 342 extending in the X direction. (As shown) Figure 14B As described, the gaps 342 are arranged in a repeating pattern of four gaps, from the first gap 342a to the fourth gap 342d. The pattern of the four gaps 342 forms four linear mask patterns extending linearly in the X direction. Thus, four repeating linear mask patterns are formed. The resist 35 is disposed in the portion on top of the first gap 342a. Next, for example, the resist 35 is cured by irradiation with ultraviolet light or by a baking process.

[0064] Next, as Figure 15A , 15B As described in 15C, resist 36 is formed in the peripheral region N. Resist 36 is patterned using known photolithography techniques. Resist 36 is formed that partially overlaps with resist 35. Because resist 35 has already cured, resist 35 remains after the formation of resist 36.

[0065] The resist 36 has an alternating or non-uniform shape. The resist 36 has a rectangular portion 361 and protruding portions 362. The rectangular portion 361 is positioned to cover the U-shaped portion of the support column 341. The protruding portions 362 are arranged parallel in the Y direction, centered between adjacent resists 35. The protruding portions 362 are arranged such that each protruding portion 362 has at least one gap 342 between it and the resist 35. If the resist 35 is positioned in the first gap 342a, the protruding portion 362 is positioned in the third gap 342c. Neither the resist 35 nor the protruding portions 362 are provided in the second gap 342b and the fourth gap 342d. Through the above steps, in the peripheral region N, the resists 35 and 36 are formed in an alternating arrangement, which is configured to cover the U-shaped portion of the support column 341. The resists 35 and 36 are arranged such that a gap 342 is present between them.

[0066] Next, as Figure 16A , 16B As described in 16C, anisotropic dry etching is performed on the first sacrificial film 30 using pillar 341, resist 35, and resist 36 as an etching mask. Anisotropic dry etching is performed under conditions where the etching rate of the first sacrificial film 30 is high and the etching rate of the semiconductor substrate 10 is sufficiently low. Through the anisotropic dry etching of the first sacrificial film 30, openings 301 and 302 are formed in the first sacrificial film 30. The top surface of the semiconductor substrate 10 is exposed in openings 301 and 302. Subsequently, pillar 341, resist 35, and resist 36 are removed. Through the above steps, alternating growth openings 301 and short-circuit openings 302 are formed in the first sacrificial film 30 in the peripheral region N.

[0067] Next, as Figure 17A , 17B As described in 17C, anisotropic dry etching is performed on the semiconductor substrate 10 using a first sacrificial film 30, in which openings 301 and 302 are formed, as an etching mask. The anisotropic dry etching is performed under conditions where the etching rate of the semiconductor substrate 10 is high and the etching rate of the first sacrificial film 30 is sufficiently low. Through the anisotropic dry etching of the semiconductor substrate 10, trenches obtained by the transfer of openings 301 and 302 are formed in the semiconductor substrate 10. The depth of the trenches is adjusted by controlling the duration of the anisotropic dry etching.

[0068] Subsequently, the first sacrificial film 30 is removed. For example, the first sacrificial film 30 is removed by dry etching or by using buffered hydrofluoric acid. Word lines 4 are formed by embedding conductive material into the lower portion of the trench. For example, word lines 4 contain layered titanium nitride (TiN) and polycrystalline silicon (polycrystalline Si). For example, titanium nitride and polycrystalline silicon are formed by CVD.

[0069] A fourth insulating film 18 and a fifth insulating film 20 are formed to cover the upper portion of the trench and the top surface of the semiconductor substrate 10. For example, the fourth insulating film 18 and the fifth insulating film 20 contain an insulating material, such as silicon nitride. For example, the fourth insulating film 18 and the fifth insulating film 20 are deposited by CVD. Through the above steps, a first word line 401 and a short second word line 402 are alternately formed in the peripheral region N.

[0070] By Figure 7A and 7B The resist 31 in the text is considered as the prototype and relative to Figure 9A and 9B The formation of pillar 321 and Figure 11A and 11B The formation of the pillar 331 employs a double-doubling process to form the letter line 4. In other words, the letter line 4 is formed using a quadruple patterning technique. Through this arrangement, Figure 17A The repeating spacing P1 of the word line 4 described in the text is Figure 7A The repeating interval P2 of the resist 31 described herein is one-quarter.

[0071] Next, as Figure 18A and 18B As described, a multilayer film containing a 10th insulating film 37, a conductive film 51, an 11th insulating film 38, a fifth sacrificial film 40, and a sixth sacrificial film 42 is formed on top of the fourth insulating film 18 and the fifth insulating film 20. Figure 18A , 18B In the following figures, the arrangement below the fourth insulating film 18, or in other words, the arrangement in the semiconductor substrate 10, is omitted from the illustrations.

[0072] The 10th insulating film 37, the 11th insulating film 38, the fifth sacrificial film 40, and the sixth sacrificial film 42 all contain insulating materials. For example, the 10th insulating film 37 and the 11th insulating film 38 contain silicon nitride. For example, the fifth sacrificial film 40 contains carbon. For example, the sixth sacrificial film 42 contains silicon oxynitride (SiON). For example, the conductive film 51 contains a metal such as tungsten. For example, the 10th insulating film 37, the conductive film 51, the 11th insulating film 38, the fifth sacrificial film 40, and the sixth sacrificial film 42 are formed by CVD.

[0073] Resist 44 is formed on top of the sixth sacrificial film 42. The resist 44 is patterned in a line and spatial layout using known photolithography techniques. The dimension of the resist 44 in the X direction is approximately [missing information]. Figure 27A The dimension of bit line 5 in the X direction is three times that described in the diagram. The repeating spacing P6 of resist 44 is... Figure 27A The repeating spacing P5 of bit line 5 is four times that described in the document.

[0074] Next, as Figure 19A and 19B As described herein, a seventh sacrificial film 46 is formed to cover the sixth sacrificial film 42 and the photoresist 44. For example, the seventh sacrificial film 46 contains an insulating film, such as silicon dioxide. The seventh sacrificial film 46 is formed, for example, using low-temperature CVD and deposited, for example, at approximately room temperature. The thickness of the seventh sacrificial film 46 is set to be substantially the same as the width dimension of each bit line 5 described subsequently.

[0075] Next, as Figure 20A and 20B As described, the seventh sacrificial film 46 is etched back by performing anisotropic dry etching on the semiconductor substrate 10 on which it is deposited, and a pillar 461 is formed by leaving the seventh sacrificial film 46 on the sidewalls of the resist 44. The surface of the sixth sacrificial film 42 is exposed by the etch-back. A pillar 461 encapsulating the resist 44 is formed. Therefore, the ends of the pillar 461 are U-shaped. Thereafter, the resist 44 is removed. The Y-direction dimension of the pillar 461 is specified by the thickness of the seventh sacrificial film 46. Figure 20B As explained in the text, along Figure 20A In the cross-sectional view of line JJ, support column 461 is arranged in a linear and spatial layout.

[0076] Next, as Figure 21A and 21B As described, anisotropic dry etching is performed on the sixth sacrificial film 42 and the fifth sacrificial film 40 using pillar 461 as an etching mask. Anisotropic dry etching is performed under conditions where the etching rates of the sixth sacrificial film 42 and the fifth sacrificial film 40 are high and the etching rates of pillar 461 and the 11th insulating film 38 are sufficiently low. Through anisotropic dry etching, pillar 40a is formed by transferring the pattern of pillar 461 to the fifth sacrificial film 40. Subsequently, pillar 461 and the sixth sacrificial film 42 are removed.

[0077] Next, as Figure 22A and 22B As described, an eighth sacrificial film 48 is formed to cover the eleventh insulating film 38 and the pillar 40a. The eighth sacrificial film 48 contains an insulating material. For example, the eighth sacrificial film 48 contains silicon dioxide. For example, the eighth sacrificial film 48 is formed by CVD. The thickness of the eighth sacrificial film 48 is set to be substantially the same as the width dimension of each word line 4 described later.

[0078] Next, as Figure 23A and 23BAs described, the eighth sacrificial film 48 is etched back by performing anisotropic dry etching on the semiconductor substrate 10 on which the eighth sacrificial film 48 is deposited, and the pillar 481 is formed by leaving the eighth sacrificial film 48 on the sidewall of the pillar 40a. The surface of the eleventh insulating film 38 is exposed by the etch back. The pillar 481 is linear. The pillar 481 is formed to enclose the pillar 40a. Therefore, the end of the pillar 481 is U-shaped.

[0079] Subsequently, pillar 40a is removed by performing anisotropic dry etching under conditions that allow selective removal of pillar 40a. The X-axis dimension of pillar 481 is specified by the thickness of the eighth sacrificial film 48. Figure 23B As explained in the text, along Figure 23A In the cross-sectional view of line JJ, support column 481 is arranged in a linear and spatial layout with repeating spacing P7. The repeating spacing P7 of support column 481 is... Figure 27A The repeating spacing P5 of bit line 5 described in the document is basically the same.

[0080] Next, as Figure 24A and 24B As explained, a resist 50 is formed to cover some of the multiple pillars 481 in the peripheral region N, while leaving three uncovered pillars 481 in the X direction. Figure 24B It means to explain along Figure 24A The longitudinal section of the portion of line JJ in the image. The resist 50 is patterned using a known photolithography technique. The resist 50 is formed to partially cover the bit line 5 along its extension in the Y direction. (Example: ...) Figure 24B As explained in the text, along Figure 24A In the section of line JJ, pillars 481 are arranged in a repeating pattern of four pillars, from the first pillar 481a to the fourth pillar 481d. The pattern of the four pillars 481 forms four linear mask patterns extending linearly in the Y direction. Resist 50 is placed on top of the first pillar 481a. Next, for example, the resist 50 is cured by irradiation with ultraviolet light or by a baking process.

[0081] Next, as Figure 25A and 25B As described, resist 52 is formed in portions of memory cell region M and peripheral region N. Resist 52 is patterned using known photolithography techniques. Resist 52 is formed that partially overlaps with resist 50. Because resist 50 has already cured, resist 50 remains after resist 52 is formed.

[0082] The resist 52 has an interlaced or non-uniform shape. The resist 52 has a rectangular portion 521 and a protruding portion 522. The rectangular portion 521 is positioned to cover portions of the memory cell region M and the peripheral region N, such that the U-shaped portion of the support 481 is exposed. The protruding portion 522 is arranged to protrude from the memory cell region M into the peripheral region N. The protruding portions 522 are arranged parallel in the X direction and centered between adjacent resists 50. The protruding portions 522 are arranged such that each protruding portion 522 has at least one support 481 between it and an adjacent resist 50.

[0083] With the resist 50 placed on top of the first pillar 481a, the protrusion 522 is placed on top of the third pillar 481c. In the peripheral region N, neither the resist 50 nor the protrusion 522 is provided on the second pillar 481b and the fourth pillar 481d. Through the above steps, in the peripheral region N, the resist 50 and resist 52 are formed by an alternating arrangement with a pillar 481 between them, and are configured to expose the U-shaped portion of the pillar 481.

[0084] Next, as Figure 26A , 26B As described in 26C, anisotropic dry etching is performed on the pillar 481 using resist 50 and resist 52 as etching masks. Anisotropic dry etching is performed under conditions where the etching rate of the pillar 481 is high and the etching rate of the 11th insulating film 38 is sufficiently low. Afterward, resist 50 and resist 52 are removed.

[0085] By anisotropic dry etching, the pillars 481 in the portions not covered by resist 50 and resist 52 are removed, and the remaining portions become pillars 482. Through the above steps, pillars 482a and short pillars 482b are alternately grown in the peripheral region N.

[0086] Next, as Figure 27A , 27B As described in 27C, anisotropic dry etching is performed on the 11th insulating film 38 and the conductive film 51 using pillar 482 as an etching mask. The anisotropic dry etching includes dry etching performed under conditions of high etching rate of the 11th insulating film 38, followed by dry etching performed under conditions of high etching rate of the conductive film 51 and sufficiently low etching rate of the 10th insulating film 37.

[0087] By dry etching, the pattern of the pillar 482 is transferred to the 11th insulating film 38 and the conductive film 51, and bit line 5 and a seventh insulating film 22 disposed on top of bit line 5 are formed. Through the above steps, a long first bit line 501 and a short second bit line 502 are formed in the peripheral region N. The long first bit line 501 and the short second bit line 502 are alternately arranged in the peripheral region N.

[0088] By Figure 18A and 18B The resist 44 in the middle is considered as the prototype and relative to Figure 20A and 20B The formation of pillar 461 and Figure 23A and 23B The formation of pillar 481 involves a double-doubling process to form bit line 5. In other words, bit line 5 is formed using a quadruple patterning technique. Through this arrangement, Figure 27A The repeating interval P5 of bit line 5 described in the document is Figure 18A The repeating interval of resist 44 described herein is one-quarter of that of P6.

[0089] After that, as Figure 4A and 4B and Figure 6A and 6B As described, an eighth insulating film 24 is formed covering the fifth insulating film 20, the bit line 5, and the seventh insulating film 22, and a ninth insulating film 26 is formed covering the eighth insulating film 24. For example, the eighth insulating film 24 contains silicon dioxide and is deposited by CVD. For example, the ninth insulating film 26 contains silicon nitride and is deposited by CVD.

[0090] Next, as Figure 4A and 4B As explained, word line contact holes are formed in the peripheral region N, extending from the ninth insulating film 26 to the top surface of the word line 4. The word line contacts 7 are formed by embedding a conductive material, such as tungsten, into the word line contact holes, for example, by CVD, and then performing an anisotropic dry etching.

[0091] Figure 3A and 3B and Figure 4A and 4B The word line contacts 7 described herein can also be formed by a photolithography step, which is different from the photolithography step used to form a contact hole in one of the adjacent word line contacts 7. This configuration allows sufficient distance to be provided between contact holes demarcated by a single photolithography step, thereby avoiding the inability to pattern contact holes due to resolution limitations below those of photolithography technology, and thus enabling precise formation of the word line contacts 7.

[0092] Next, as Figure 6A and 6B As explained, a bit line contact hole is formed in the peripheral region N, extending from the ninth insulating film 26 to the top surface of the bit line 5. The bit line contact 8 is formed by embedding a conductive material, such as tungsten, into the bit line contact hole, for example, by CVD, and then performing an etch-back process by anisotropic dry etching.

[0093] Figure 5A and5B and Figure 6A and 6B The bit line contacts 8 described herein can also be formed using a photolithography step, which is different from the photolithography step used to form a contact hole in one of the adjacent bit line contacts 8. This configuration allows sufficient distance to be provided between contact holes demarcated by a single photolithography step, thereby avoiding the inability to pattern contact holes due to resolution limitations below those of photolithography techniques, and thus enabling precise formation of the bit line contacts 8.

[0094] After that, as Figure 28 As described above, capacitor contacts 116, capacitor 140, insulating materials 146, 147 and 152, and interconnects 148, 149, 150 and 151 are formed. Through the above steps, a semiconductor device according to the embodiment can be formed.

[0095] As described above, in the peripheral region N of the memory pad end region A1, the first word line 401 is longer than the second word line 402. In other words, the word lines 4 have an interleaved arrangement. The second word line 402 is not present in the region adjacent to the edge portion 4a in the Y direction (the direction in which the word line 4 extends), the edge portion corresponding to the overlap between the first word line 401 and the word line contact 7.

[0096] By configuring the word line in this manner when forming the word line contact 7 in the edge portion 4a of the first word line 401, the word line contact 7 does not contact the adjacent second word line 402 at all, even if misalignment occurs during the photolithography step. Therefore, even if the word line contact 7 is misaligned, short circuits with adjacent word lines 402 can be avoided or suppressed. Thus, the manufacturing yield of semiconductor devices can be improved.

[0097] Furthermore, in the peripheral region N of the memory pad end region A3, the first bit line 501 is longer than the second bit line 502. In other words, through the staggered arrangement of the bit lines 5, the second bit line 502 does not exist in the region adjacent to the edge portion 5a in the X direction (the direction in which the bit line 5 extends), the edge portion corresponding to the overlap between the first bit line 501 and the bit line contact 8. Therefore, when the bit line contact 8 is formed in the edge portion 5a of the first bit line 501, connection to the second bit line 502 adjacent to the bit line contact 8 can be avoided or suppressed, or in other words, short circuits can be prevented even if misalignment occurs during the photolithography step. Therefore, the manufacturing yield of the semiconductor device can be improved.

[0098] Furthermore, as mentioned above, word lines 4 and bit lines 5 are formed using a double-doubling process, or in other words, a quadruple patterning technique. This configuration eliminates the need for patterning at or near the resolution limits of photolithography, thus allowing for precise formation of word lines 4 and bit lines 5. Consequently, the manufacturing yield of semiconductor devices can be improved.

[0099] As described above, DRAM is an example of a semiconductor device according to the embodiments, but the above description is merely an example and is not intended to limit it to DRAM. For example, other memory devices besides DRAM, such as static random access memory (SRAM), flash memory, erasable programmable read-only memory (EPROM), magnetoresistive random access memory (MRAM), and phase-change memory, can also be used as semiconductor devices.

[0100] Although the invention has been disclosed in the context of certain preferred embodiments and examples, those skilled in the art will understand that the invention extends beyond the specifically disclosed embodiments to other alternative embodiments and / or the use of the invention and its obvious modifications and equivalents. Furthermore, other modifications within the scope of the invention will be apparent to those skilled in the art based on this disclosure. Various combinations or sub-combinations of specific features and aspects of the embodiments are also contemplated and will still fall within the scope of the invention. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for each other to form variations of the disclosed invention. Therefore, it is intended that the scope of at least some of the invention disclosed herein should not be limited to the specific disclosed embodiments described above.

Claims

1. A semiconductor device comprising: Substrate; The memory cell region above the substrate; A peripheral region above the substrate, the peripheral region being adjacent to the memory cell region; An additional peripheral region above the substrate; as well as A plurality of first word lines and a plurality of second word lines extend across the memory cell region, the peripheral region and the additional peripheral region; The plurality of first letter lines and the plurality of second letter lines are arranged alternately with each other; The memory cell region is arranged between the peripheral region and the additional peripheral region; The length of each of the plurality of first character lines in the peripheral area is longer than the length of each of the plurality of second character lines in the peripheral area; and The length of each of the plurality of second word lines in the additional peripheral area is longer than the length of each of the plurality of first word lines in the additional peripheral area.

2. The semiconductor device of claim 1, further comprising a plurality of contacts, the contacts being respectively connected to edge portions of the plurality of first word lines in the peripheral region; The width of the edge portion of each first character line is the same as the width of the portion of the first character line excluding the edge portion; and The side of each of the edge portions of the plurality of first letter lines does not contain the second letter line.

3. The semiconductor device of claim 1, further comprising a plurality of contacts, the contacts being respectively connected to edge portions of the plurality of second word lines in the additional peripheral region; The width of the edge portion of each second character line is the same as the width of the portion of the second character line excluding the edge portion; and The side of each of the edge portions of the plurality of second letter lines does not contain the first letter line.

4. The semiconductor device of claim 1, wherein the memory cell region comprises a plurality of memory cells.

5. The semiconductor device of claim 2, further comprising a contact connected to the edge portion of the first word line in the peripheral region.

6. The semiconductor device of claim 3, further comprising a contact connected to the edge portion of the second word line in the additional peripheral region.

7. A semiconductor device comprising: Substrate; The memory cell region above the substrate; A peripheral region above the substrate, the peripheral region being adjacent to the memory cell region; An additional peripheral region above the substrate; as well as Multiple first bit lines and multiple second bit lines extend across the memory cell region, the peripheral region, and the additional peripheral region; The plurality of first bit lines and the plurality of second bit lines are arranged alternately with each other; The memory cell region is arranged between the peripheral region and the additional peripheral region; The length of each of the plurality of first lines in the peripheral region is longer than the length of each of the plurality of second lines in the peripheral region; and The length of each of the plurality of second bit lines in the additional peripheral region is longer than the length of each of the plurality of first bit lines in the additional peripheral region.

8. The semiconductor device of claim 7, further comprising a plurality of contacts, the contacts being respectively connected to edge portions of the plurality of first bit lines in the peripheral region; The width of the edge portion of each first bit line is the same as the width of the portion of the first bit line excluding the edge portion; and The side of each of the edge portions of the plurality of first bit lines does not contain the second bit line.

9. The semiconductor device of claim 7, further comprising a plurality of contacts respectively connected to edge portions of the plurality of second bit lines in the additional peripheral region; The width of the edge portion of each second bit line is the same as the width of the portion of the second bit line excluding the edge portion; and Each of the edge portions of the plurality of second bit lines does not contain the first bit line on its side.

10. The semiconductor device of claim 7, wherein the memory cell region comprises a plurality of memory cells.

11. The semiconductor device of claim 8, further comprising a contact connected to the edge portion of the first bit line in the peripheral region.

12. The semiconductor device of claim 9, further comprising a contact connected to the edge portion of the second bit line in the additional peripheral region.

13. A method of forming a semiconductor device, comprising: Forming a repeating of four linear mask patterns that extend across the memory cell region and peripheral region provided above the substrate; A first resist pattern is formed, which is periodically arranged on the linear mask pattern to sandwich three of the linear mask patterns in the middle; A second resist pattern is formed, which is periodically arranged on the linear mask pattern to sandwich one of the linear mask patterns between the first resist pattern and the second resist pattern; and The interlaced pattern is transferred to a component arranged below the linear mask pattern, and the interlaced pattern is formed by using the linear mask pattern, the first resist pattern, and the second resist pattern as a mask.

14. The method of claim 13, wherein the first resist pattern is cured prior to the formation of the second resist pattern.

15. The method according to claim 13, The linear mask pattern described therein is an opening. During the transfer process, the linear mask pattern is transferred to the component arranged below the linear mask pattern as a groove, and The method further includes forming wiring by embedding conductive material in the trench.

16. The method according to claim 13, The linear mask pattern is a line pattern, and During the transfer process, multiple wirings are formed by transferring the line pattern to the component arranged below the linear mask pattern.

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