Semiconductor memory device

Abstract

Embodiments of the present application provide a semiconductor memory device that can be manufactured well. The semiconductor memory device of the embodiments includes a substrate, a plurality of first conductive layers and a plurality of first insulating layers arranged alternately in a first direction intersecting the substrate, a first semiconductor layer extending in the first direction and facing the plurality of first conductive layers and the plurality of first insulating layers, a first charge storage layer provided between the plurality of first conductive layers and the first semiconductor layer, and a second semiconductor layer connected to one end portion of the first semiconductor layer in the first direction. At least a portion of the plurality of first insulating layers contains a first element, and the first element is at least one of phosphorus (P), arsenic (As), carbon (C), and argon (Ar).

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2021-103042 (filed on June 22, 2021). This application incorporates the entire contents of the said basic application by reference. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Technology

[0004] A semiconductor memory device is known, comprising: a plurality of first conductive layers and a plurality of first insulating layers, alternately arranged in a first direction; a first semiconductor layer extending in the first direction and facing the plurality of first conductive layers and the plurality of first insulating layers; and a first charge storage layer disposed between the plurality of first conductive layers and the first semiconductor layer. Summary of the Invention

[0005] The embodiment provides a semiconductor memory device that can be manufactured well.

[0006] A semiconductor memory device according to one embodiment includes: a substrate; a plurality of first conductive layers and a plurality of first insulating layers, alternately arranged in a first direction intersecting the substrate; a first semiconductor layer extending in the first direction and facing the plurality of first conductive layers and the plurality of first insulating layers; a first charge storage layer disposed between the plurality of first conductive layers and the first semiconductor layer; and a second semiconductor layer connected to one end of the first semiconductor layer in the first direction. At least a portion of the plurality of first insulating layers includes a first element, which is at least one of phosphorus (P), arsenic (As), carbon (C), and argon (Ar). Attached Figure Description

[0007] Figure 1 This is a schematic circuit diagram showing a portion of the semiconductor memory device according to the first embodiment.

[0008] Figure 2 This is a schematic top view showing a portion of the semiconductor memory device.

[0009] Figure 3 This is a schematic perspective view showing a portion of the semiconductor memory device.

[0010] Figure 4 This is a schematic top view showing a portion of the semiconductor memory device.

[0011] Figure 5 This is a schematic cross-sectional view showing a portion of the semiconductor memory device.

[0012] Figure 6 This is a schematic cross-sectional view showing a portion of the semiconductor memory device.

[0013] Figures 7 to 29 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device.

[0014] Figure 30 This is a schematic cross-sectional view showing a portion of a comparative example semiconductor memory device.

[0015] Figure 31 , Figure 32 This is a schematic cross-sectional view used to illustrate the manufacturing method of a comparative example semiconductor memory device.

[0016] Figure 33 This is a schematic cross-sectional view showing a portion of the semiconductor memory device according to the second embodiment.

[0017] Figures 34-37 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device.

[0018] Figure 38 This is a schematic cross-sectional view showing a portion of the semiconductor memory device according to the third embodiment.

[0019] Figure 39 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device. Detailed Implementation

[0020] Next, the semiconductor memory device according to embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the invention. Additionally, the following drawings are schematic, and for ease of explanation, some components may be omitted. Furthermore, common parts in multiple embodiments may be labeled with the same symbol, and descriptions may be omitted.

[0021] Additionally, in this specification, the term "semiconductor memory device" sometimes refers to a memory die, and sometimes to a memory system that includes a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). Furthermore, it sometimes also refers to a device that includes a host computer, such as a smartphone, tablet, or personal computer.

[0022] Furthermore, when this specification mentions that the first component is "connected" between the second and third components, it may mean that the first, second, and third components are connected in series, and the second component is connected to the third component via the first component.

[0023] In addition, in this specification, a specific direction parallel to the upper surface of the substrate is called the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and a direction perpendicular to the upper surface of the substrate is called the Z direction.

[0024] In addition, in this specification, the direction along a specific surface is sometimes referred to as the first direction, the direction along the specific surface that intersects the first direction is referred to as the second direction, and the direction that intersects the specific surface is referred to as the third direction. The first, second, and third directions may correspond to any one of the X, Y, and Z directions, or they may not correspond to each other.

[0025] Furthermore, in this specification, terms such as "upper" or "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction approaching the substrate along the Z direction is called "lower." Additionally, when a component is referred to as a lower surface or lower end, it means the surface or end of the component on the substrate side; when referred to as an upper surface or upper end, it means the surface or end of the component opposite to the substrate. Furthermore, a surface intersecting the X or Y direction is called a side surface, etc.

[0026] In addition, when referring to "width", "length" or "thickness" in a specific direction for components or parts in this specification, it sometimes means the width, length or thickness of a cross-section observed using SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy).

[0027] [First Implementation]

[0028] Figure 1 This is a schematic circuit diagram showing a portion of the configuration of the semiconductor memory device according to the first embodiment. The semiconductor memory device of the first embodiment includes a memory cell array (MCA) and peripheral circuitry (PC).

[0029] The memory cell array (MCA) comprises multiple memory blocks (BLK). Each memory block (BLK) comprises multiple string cells (SU). Each string cell (SU) comprises multiple memory strings (MS). One end of each memory string (MS) is connected to the peripheral circuit (PC) via a bit line (BL). The other end of each memory string (MS) is connected to the peripheral circuit (PC) via a common source line (SL).

[0030] The memory string (MS) includes a drain-side select transistor (STD), multiple memory cells (MCs) (memory transistors), and a source-side select transistor (STS). The STD, MCs, and STS are connected in series between the bit line (BL) and the source line (SL). Hereinafter, the STD and STS will sometimes be referred to simply as select transistors (STD, STS).

[0031] The memory cell MC is a field-effect transistor. The memory cell MC has a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film contains a charge storage film. The threshold voltage of the memory cell MC varies according to the amount of charge in the charge storage film. The memory cell MC stores one or more bits of data. Furthermore, the gate electrodes of multiple memory cells MC corresponding to one memory string MS are respectively connected to word lines WL. These word lines WL are all commonly connected to all memory strings MS in one memory block BLK.

[0032] Select transistors (STD, STS) are field-effect transistors. Each select transistor (STD, STS) has a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. Select gate lines (SGD, SGS) are connected to the gate electrodes of the select transistors (STD, STS). One drain-side select gate line (SGD) is connected to all memory strings (MS) within a single string cell (SU). One source-side select gate line (SGS) is connected to all memory strings (MS) within a single memory block (BLK).

[0033] The peripheral circuit PC includes, for example: a voltage generation circuit that generates an operating voltage; a voltage transmission circuit that transmits the generated operating voltage to the selected bit line BL, word line WL, source line SL, select gate line (SGD, SGS), etc.; an induction amplifier module connected to the bit line BL; and a sequencer that controls the components.

[0034] Figure 2 This is a schematic top view showing a portion of the configuration of the semiconductor memory device according to the first embodiment. The semiconductor memory device of this embodiment includes a semiconductor substrate 100. The semiconductor substrate 100 is a semiconductor substrate containing, for example, p-type silicon (Si) containing p-type impurities such as boron (B). In the illustrated example, four memory cell array regions R arranged in the X and Y directions are provided on the semiconductor substrate 100. MCA Additionally, in each memory cell array region R MCA It contains multiple memory blocks (BLK) arranged in the Y direction.

[0035] Figure 3This is a schematic perspective view showing a portion of the configuration of the semiconductor memory device according to the first embodiment. Figure 4 This is a schematic top view showing a portion of the configuration of the semiconductor memory device according to the first embodiment. Figure 5 It is cut along line BB′. Figure 4 The structure shown is a schematic cross-sectional view viewed in the direction of the arrow.

[0036] The semiconductor memory device of this embodiment is, for example, such as Figure 3 As shown, a transistor layer L is provided on the semiconductor substrate 100. TR , and set in transistor layer L TR The upper memory cell array layer L MCA .

[0037] [Transistor layer L] TR [Construction]

[0038] For example, Figure 3 As shown, a wiring layer GC is disposed on the upper surface of the semiconductor substrate 100, separated by an insulating layer (not shown). The wiring layer GC includes a plurality of electrodes gc facing the surface of the semiconductor substrate 100. Furthermore, each region of the semiconductor substrate 100 and the plurality of electrodes gc included in the wiring layer GC are respectively connected to a contact CS.

[0039] Multiple electrodes gc are respectively facing the surface of the semiconductor substrate 100, and function as the gate electrodes of multiple transistors Tr that constitute the peripheral circuit PC, and other electrodes of multiple capacitors.

[0040] Multiple contacts CS extend in the Z direction and are connected at their lower ends to the upper surface of the semiconductor substrate 100 or the electrode gc. An impurity region containing N-type or P-type impurities is provided at the connection point between the contacts CS and the semiconductor substrate 100. The contacts CS may also comprise, for example, a stacked film containing a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0041] Wiring layers D0, D1, and D2 each contain multiple wirings, which are electrically connected to at least one of the configurations in the memory cell array (MCA) and the peripheral circuitry (PC). These wirings may also include, for example, a stacked film containing a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0042] [Memory cell array layer L] MCA [Construction]

[0043] For example, Figure 3 and Figure 4 As shown, in the memory cell array layer L MCA It sets up multiple memory blocks (BLK) arranged in the Y direction.

[0044] Figure 4 In the example, the memory block BLK has one side from the Y direction ( Figure 4 The middle (positive side in the Y direction) is set to the other side in the Y direction ( Figure 4 Five serial units SUa to SUe (located on the negative side of the Y direction) are respectively connected to a reference. Figure 1 The description corresponds to the string unit SU. Between two adjacent string units SU in the Y direction, an inter-string unit insulating layer SHE, such as silicon oxide (SiO2), is provided. Between two adjacent memory blocks BLK in the Y direction, an inter-block structure ST is provided.

[0045] like Figure 3 and Figure 5 As shown, in the memory cell array layer L MCA In the memory block BLK, there is a memory cell array layer L. MCA1 , and set in the memory cell array layer L MCA1 The upper memory cell array layer L MCA2 Memory cell array layer L MCA1 and memory cell array layer L MCA2 It includes a plurality of conductive layers 110 arranged in the Z direction, a plurality of semiconductor layers 120 extending in the Z direction, and a plurality of gate insulating films 130 disposed between the plurality of conductive layers 110 and the plurality of semiconductor layers 120.

[0046] The conductive layer 110 is a generally plate-shaped conductive layer extending in the X direction. The conductive layer 110 may comprise a laminated film containing a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Alternatively, the conductive layer 110 may also comprise, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). At the X-direction ends of the plurality of conductive layers 110, contacts CC (…) are respectively provided. Figure 3 An insulating layer 101, such as silicon oxide (SiO2), is disposed between multiple conductive layers 110 arranged in the Z direction.

[0047] Below the plurality of conductive layers 110, a dielectric insulating layer 101 is provided with semiconductor layers 111, 113, and 112. A portion of a gate insulating film 130 is provided between semiconductor layers 111 and 112 and semiconductor layer 120. Semiconductor layer 113 is connected to the lower end of semiconductor layer 120.

[0048] The upper surface of semiconductor layer 113 is connected to semiconductor layer 111, and the lower surface is connected to semiconductor layer 112. Alternatively, a conductive layer 114 may be disposed on the lower surface of semiconductor layer 112. Semiconductor layers 111, 113, 112, and conductive layer 114 serve as the source line SL. Figure 1) to perform its function. Source line SL, for example, for memory cell array region R MCA ( Figure 2 All memory blocks (BLKs) contained therein are configured in a common manner. Semiconductor layers 111, 113, and 112 contain, for example, polysilicon containing impurities such as phosphorus (P) or boron (B). Conductive layer 114 may also contain, for example, a metal such as tungsten (W), a conductive layer such as tungsten silicide, or other conductive layers.

[0049] The bottommost conductive layer 110 among the multiple conductive layers 110 serves as the source-side selected gate line (SGS). Figure 1 ) and multiple source-side selection transistors (STS) connected to it. Figure 1 The gate electrode of the conductive layer 110 functions. The conductive layer 110 is electrically independent in each memory block BLK.

[0050] Additionally, multiple conductive layers 110 located above it serve as bit lines WL ( Figure 1 ) and multiple memory units MC connected to it Figure 1 The gate electrode of the memory block BLK functions. The plurality of conductive layers 110 are electrically independent in each memory block BLK.

[0051] Additionally, one or more conductive layers 110 located above it serve as drain-side selected gate lines (SGD). Figure 1 ) and multiple drain-side selection transistors STD connected thereto. Figure 1 The gate electrode of the conductive layer 110 functions as a gate electrode. The width of the multiple conductive layers 110 in the Y direction is smaller than that of the other conductive layers 110. In addition, an inter-cell insulating layer SHE is provided between two adjacent conductive layers 110 in the Y direction. The multiple conductive layers 110 are electrically independent in each string cell SU.

[0052] Semiconductor layer 120, for example Figure 3 and Figure 4 As shown, they are arranged in a specific pattern in the X and Y directions. Semiconductor layer 120 serves as a memory string (MS). Figure 5 The multiple memory cells (MCs) and the channel regions of the selection transistors (STDs, STSs) contained within the semiconductor layer 120 function as semiconductor layers, such as polysilicon (Si). Semiconductor layer 120 is, for example, a semiconductor layer such as... Figure 3 As shown, it has a roughly cylindrical shape with a bottom, and an insulating layer 125 such as silicon oxide is provided in the central part.

[0053] Semiconductor layer 120 Figure 5 As shown, it has a memory cell array layer L MCA1 Includes semiconductor region 120 L , and memory cell array layer L MCA2Includes semiconductor region 120 U Additionally, the semiconductor layer 120 has connections to the semiconductor region 120. L The upper end and semiconductor region 120 U The lower semiconductor region 120 J Connected to semiconductor region 120 L The lower end of the impurity region 122 and the connection to the semiconductor region 120 U The impurity region 121 at the upper end.

[0054] Semiconductor Area 120 L It is a roughly cylindrical region extending in the Z direction. Semiconductor region 120 L The outer periphery is composed of memory cell array layers L MCA1 It includes a plurality of conductive layers 110 surrounding it, and faces the plurality of conductive layers 110. Furthermore, the semiconductor region 120 L The lower end (e.g., located in the memory cell array layer L) MCA1 The radial width of the portion below the multiple conductive layers 110 is smaller than that of the semiconductor region 120. L The upper end (e.g., located in the memory cell array layer L) MCA1 The radial width of the portion above the multiple conductive layers 110 contained therein.

[0055] Semiconductor Area 120 U It is a roughly cylindrical region extending in the Z direction. Semiconductor region 120 U The outer periphery is composed of memory cell array layers L MCA2 It includes a plurality of conductive layers 110 surrounding it, and faces the plurality of conductive layers 110. Furthermore, the semiconductor region 120 U The lower end (e.g., located in the memory cell array layer L) MCA2 The radial width of the portion below the multiple conductive layers 110 is smaller than that of the semiconductor region 120. U The upper end (e.g., located in the memory cell array layer L) MCA2 The radial width of the portion above the multiple conductive layers 110 contained therein.

[0056] Semiconductor Area 120 J They are respectively set in the memory cell array layer L MCA1 It includes multiple conductive layers 110 above it, and is disposed above the memory cell array layer L. MCA2 Below the multiple conductive layers 110 contained therein. Additionally, the semiconductor region 120... J The radial width is greater than that of the semiconductor region 120. L 120 U Radial width.

[0057] Impurity region 122 includes region 122_A opposite to semiconductor layer 111, region 122_C opposite to semiconductor layer 112, and region 122_B disposed between the two regions and whose outer peripheral surface is connected to semiconductor layer 113. That is, region 122_C is disposed at the lower end of semiconductor layer 120. Furthermore, in semiconductor region 120... L Between region 122_C and region 122_B, region 122_B is located. Impurity region 122 contains, for example, N-type impurities such as phosphorus (P) or P-type impurities such as boron (B).

[0058] Impurity region 121 contains N-type impurities such as phosphorus (P). Impurity region 121 is connected via contact Ch and contact Vy ( Figure 3 Connected to bit line BL.

[0059] The gate insulating film 130 has a generally bottomed cylindrical shape covering the outer peripheral surface of the semiconductor layer 120. The gate insulating film 130 includes, for example, a tunnel insulating film, a charge storage film, and a bulk insulating film deposited between the semiconductor layer 120 and the conductive layer 110. The tunnel insulating film and the bulk insulating film are, for example, insulating films such as silicon oxide (SiO2). The charge storage film is, for example, a film capable of storing charge such as silicon nitride (Si3N4). The tunnel insulating film, the charge storage film, and the bulk insulating film have a generally cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120.

[0060] In addition, the gate insulating film 130 may also have a floating gate, such as polysilicon containing N-type or P-type impurities.

[0061] The inter-block structure ST is a structure that extends in the Z and X directions, and is divided along the Y direction into multiple insulating layers 101, multiple conductive layers 110, semiconductor layers 111 and 113, reaching the semiconductor layer 112. An example of the inter-block structure ST is... Figure 5 As shown, it may also include an insulating layer 170 such as silicon oxide (SiO2) and a conductive layer 110 such as tungsten. The lower end of the conductive layer 110 is connected to the semiconductor layer 112.

[0062] [Memory cell array layer L] MCA [Impurities contained in each component]

[0063] Figure 6 It is Figure 5 The memory cell array layer L shown MCA1 Region R in LMH and memory cell array layer L MCA2 Region R in UMH A schematic cross-sectional view shown in enlarged format.

[0064] like Figure 6As shown, in the memory cell array layer L MCA1 In the middle, the conductive layer 110 and the semiconductor region 120 L The opposing surface relative to the insulating layer 101 and the semiconductor region 120 L The width of the backslope of the opposite face D L1 And the settings. Additionally, in the memory cell array layer L... MCA2 In the middle, the conductive layer 110 and the semiconductor region 120 U The opposing surface relative to the insulating layer 101 and the semiconductor region 120 U The width of the backslope of the opposite face D U1 And set the width D. L1 、and width D U1 They are of the same degree.

[0065] Additionally, in the memory cell array layer L MCA1 In the process, insulating layer 101 includes region 101_C1 and region 101_C2. Region 101_C2 is disposed between region 101_C1 and semiconductor region 120. L The position between them. That is, region 101_C2 is set closer to semiconductor region 120 than region 101_C1. L The location. Region 101_C2 is a region containing at least one element selected from phosphorus (P), arsenic (As), carbon (C), and argon (Ar). The concentration of said element in region 101_C2 is greater than the concentration of said element in region 101_C1.

[0066] Additionally, in the memory cell array layer L MCA2 In the insulating layer 101, region 101_C3 is included. Region 101_C3 is positioned parallel to region 101_C2 in the Z direction. The concentration of at least one element among phosphorus (P), arsenic (As), carbon (C), and argon (Ar) in region 101_C3 is greater than the concentration of the element in region 101_C2.

[0067] In addition, for example, Figure 5 As shown, semiconductor layer 111 includes region 111_C1 and region 111_C2. Region 111_C2 is located between region 111_C1 and impurity region 122. That is, region 111_C2 is located closer to impurity region 122 than region 111_C1. Region 111_C2 contains at least one element selected from phosphorus (P), arsenic (As), carbon (C), and argon (Ar). The concentration of the element in region 111_C2 is greater than the concentration of the element in region 111_C1.

[0068] In addition, for example, Figure 5As shown, semiconductor layer 112 includes region 112_C1 and region 112_C2. Region 112_C2 is located between region 112_C1 and impurity region 122. That is, region 112_C2 is located closer to impurity region 122 than region 112_C1. Region 112_C2 contains at least one element selected from phosphorus (P), arsenic (As), carbon (C), and argon (Ar). The concentration of the element in region 112_C2 is greater than the concentration of the element in region 112_C1.

[0069] In addition, the concentrations of phosphorus (P), arsenic (As), carbon (C), and argon (Ar) in each region can be determined by EDS (Energy Dispersive X-ray Spectrometer).

[0070] [Manufacturing Method]

[0071] Next, refer to Figures 7 to 29 The manufacturing method of the semiconductor memory device according to the first embodiment will be described. Figures 7-9 , Figure 11 , Figures 13-18 ,and Figures 20-29 This is a schematic cross-sectional view used to illustrate the manufacturing method, showing the relationship with... Figure 5 The corresponding cross-section. Figure 10 and Figure 12 This is a schematic cross-sectional view used to illustrate the manufacturing method, and it is a schematic cross-sectional view of... Figure 9 and Figure 11 The area R shown LMH and region R SL The images are enlarged separately. Figure 19 This is a cross-sectional view used to illustrate the manufacturing method, and it shows... Figure 18 The area R shown UMH and region R LMH The image.

[0072] In manufacturing the semiconductor memory device of the first embodiment, a peripheral circuit PC is first formed on the semiconductor substrate 100. Figure 1 Additionally, an insulating layer 101 is formed above the peripheral circuit PC.

[0073] Next, for example, Figure 7As shown, a conductive layer 114, a semiconductor layer 112, a sacrificial layer 113A (such as silicon oxide), a sacrificial layer 113B (such as silicon nitride), a sacrificial layer 113C (such as silicon oxide), and a semiconductor layer 111 are formed on the insulating layer 101. Additionally, multiple insulating layers 101 and multiple sacrificial layers 110A are alternately formed to form an insulating layer 151 (such as silicon oxide). These steps are performed, for example, by a method such as CVD (Chemical Vapor Deposition).

[0074] Next, for example, Figure 8 As shown, in the semiconductor region 120 L At corresponding locations, multiple openings MHa are formed. The openings MHa extend in the Z direction, penetrating the insulating layer 151, multiple sacrificial layers 110A and multiple insulating layers 101, semiconductor layer 111, sacrificial layer 113C, sacrificial layer 113B, and sacrificial layer 113A, exposing the semiconductor layer 112. This step is performed, for example, by a method such as RIE (Reactive Ion Etching).

[0075] Next, for example, Figure 9 and Figure 10 As shown, regions 111_C and 112_C containing impurities such as phosphorus (P), arsenic (As), carbon (C), and argon (Ar) are formed inside semiconductor layers 111 and 112 via opening MHa. This step is performed, for example, by ion implantation. In the ion implantation step, impurities such as phosphorus (P), arsenic (As), carbon (C), and argon (Ar) are used as dopants.

[0076] Furthermore, in the steps described, such as Figure 10 As shown, impurities such as phosphorus (P), arsenic (As), carbon (C), and argon (Ar) are also implanted into region 101_C2 near the opening MHa in the insulating layer 101 and region 110A_C2 near the opening MHa in the sacrificial layer 110A. Similarly, impurities such as phosphorus (P), arsenic (As), carbon (C), and argon (Ar) are also implanted into regions 113A_C, 113B_C, and 113C_C near the opening MHa in the sacrificial layers 113A, 113B, and 113C_C, respectively. In this step, because the opening MHa has a shape that narrows as it approaches the lower opening, even when ion implantation is performed at an angle almost perpendicular to the substrate, impurities are simultaneously implanted into the sidewall regions near the opening MHa, such as region 101_C2. In addition, impurities are hardly implanted into the sidewall regions 101_C1, etc., far from the opening MHa.

[0077] Next, for example, Figure 11 and Figure 12As shown, in the portions of semiconductor layers 111 and 112 exposed at the opening MHa (regions 111_C and 112_C), insulating layers 111_D and 112_D, such as silicon oxide, are formed, respectively. This step is performed, for example, by thermal oxidation. Furthermore, regions 111_C and 112_C are subject to reference... Figure 9 and Figure 10 The ion implantation steps described herein result in regions with more crystal defects. The oxidation reactions in these regions 111_C and 112_C proceed at a higher speed compared to oxidation reactions in regions without more crystal defects.

[0078] In addition, such as Figure 12 As shown, region R LMH The portion of the sacrificial layer 110A exposed at the opening MHa is also locally oxidized to form an insulating layer 110A_D, such as silicon oxide. Furthermore, as described above, the oxidation reactions forming the insulating layers 111_D and 112_D proceed at a relatively high speed. Therefore, because the time required to complete the oxidation step is relatively short, the insulating layer 110A_D is formed relatively thin.

[0079] Next, for example, Figure 13 As shown, an amorphous silicon or other sacrificial layer 120A′ is formed inside the opening MHa. Furthermore, the upper surface of the sacrificial layer 120A′ is removed until it reaches a position between the upper and lower surfaces of the insulating layer 151. This process is performed, for example, by CVD and RIE.

[0080] Next, for example, Figure 14 As shown, after widening the opening at the upper end of the opening MHa, an amorphous silicon film is deposited to form a sacrificial layer 120A″. This step is performed, for example, by wet etching and CVD.

[0081] Next, for example, Figure 15 As shown, the upper surface of the sacrificial layer 120A″ is removed until it becomes the same as the upper surface of the insulating layer 151, thus forming the sacrificial layer 120A. This step is performed, for example, by a RIE (Residual Insulation Layer).

[0082] Next, for example, Figure 16 As shown, multiple sacrificial layers 110A and multiple insulating layers 101 are alternately formed on the insulating layer 151. The steps are performed, for example, by methods such as CVD.

[0083] Next, for example, Figure 17 As shown, in the semiconductor region 120 U At the corresponding locations, multiple openings MHb are formed. The openings MHb extend in the Z direction, penetrating multiple sacrificial layers 110A and multiple insulating layers 101, exposing the sacrificial layer 120A. This step is performed, for example, by methods such as RIE.

[0084] Next, for example, Figure 18 As shown, the sacrificial layer 120A is removed to form the opening MHc. This step is performed, for example, by wet etching. Furthermore, semiconductor layers 111 and 112 contain the same elements as those contained in the sacrificial layer 120A, namely silicon (Si). However, regarding semiconductor layers 111 and 112, insulating layers 111_D and 112_D serve as etch stop layers, protecting them. Therefore, semiconductor layers 111 and 112 are not etched in this step.

[0085] Next, for example, Figure 19 As shown, a portion of the sacrificial layer 110A is removed from the opening MHc. Consequently, the opening width of the sacrificial layer 110A in both the X and Y directions is increased by a specific amount relative to the opening width of the insulating layer 101. This step is performed, for example, by wet etching using phosphoric acid or the like.

[0086] Furthermore, in the aforementioned steps, region R LMH In the process, before etching the sacrificial layer 110A containing silicon nitride, etc., the insulating layer 110A_D containing silicon oxide, etc., is etched. Figure 12 Because the aforementioned step uses phosphoric acid, etching of silicon oxide and the like requires a relatively long time. However, as described above, because the thickness of the insulating layer 110A_D in this embodiment is relatively small, the etching is performed in a relatively short time. Therefore, in the aforementioned step, region R... UMH The width D of the sacrificial layer 110A retreats U1 and region R LMH The width D of the sacrificial layer 110A retreats L1 They are of the same degree.

[0087] Next, for example, Figure 20 As shown, a gate insulating film 130, a semiconductor layer 120, and an insulating layer 125 are formed on the upper surface of the uppermost insulating layer 101 and the inner peripheral surface of the opening MHc, forming a memory hole MH. During the formation of the semiconductor layer 120, a film is deposited using methods such as CVD, and an amorphous silicon film is formed inside the memory hole MH. Furthermore, the crystal structure of the amorphous silicon film is modified, for example, through annealing.

[0088] Next, for example, Figure 21 As shown, a portion of the insulating layer 125 and the semiconductor layer 120 is removed until the upper surface of the semiconductor layer 120, etc., becomes the position between the upper and lower surfaces of the uppermost insulating layer 101. This step is performed, for example, by a method such as RIE.

[0089] Next, for example, Figure 22As shown, a semiconductor layer 121A is formed near the upper end of the memory hole MH. The semiconductor layer 121A contains, for example, amorphous silicon containing N-type impurities such as phosphorus (P). This step is performed, for example, by a method such as CVD.

[0090] Next, for example, Figure 23 As shown, an impurity region 121 of the semiconductor layer 120 is formed near the upper end of the memory hole MH. In this step, a portion of the semiconductor layer 121A is removed, for example, by a method such as RIE, exposing the uppermost insulating layer 101.

[0091] Next, for example, Figure 24 As shown, a trench STA′ is formed. The trench STA′ extends in the Z and X directions, and multiple insulating layers 101 and sacrificial layers 110A are interrupted along the Y direction, exposing the semiconductor layer 111. This step is performed, for example, by a method such as RIE. In addition, an insulating layer 161 such as silicon oxide and a semiconductor layer 162 such as amorphous silicon are formed inside the trench STA′ by a method such as CVD.

[0092] Next, for example, Figure 25 As shown, a trench STA is formed. The trench STA is formed by further separating the semiconductor layer 162, insulating layer 161, semiconductor layer 111, and sacrificial layers 113C, 113B, and 113A along the Y direction from the bottom surface of the trench STA′, exposing the semiconductor layer 112. This step is performed, for example, by a re-emulation (RIE) process. Furthermore, the semiconductor layer 162 on the Y-direction side of the trench STA and a portion of the semiconductor layer 112 exposed on the bottom surface are oxidized to form insulating layers 163 and 164, such as silicon oxide. This step is performed, for example, by thermal oxidation.

[0093] Next, for example, Figure 26 As shown, sacrificial layer 113B is removed via trench STA, followed by the removal of sacrificial layers 113A and 113C, and a portion of gate insulating film 130 to form cavity CAV1, thereby exposing a portion of semiconductor layer 120. These steps are performed, for example, by wet etching.

[0094] Next, for example, Figure 27 As shown, a semiconductor layer 113 is formed in the location where the cavity CAV1 exists via a trench STA. This step is performed, for example, by methods such as epitaxial growth. Additionally, the semiconductor layer 162 and the insulating layer 161 in the Y-direction side of the trench STA are removed. This step is performed, for example, by methods such as wet etching.

[0095] Next, for example, Figure 28As shown, the sacrificial layer 110A is removed via trench STA to form multiple cavities CAV2. This creates a hollow structure comprising multiple insulating layers 101 arranged along the Z direction and a structure (semiconductor layer 120, gate insulating film 130, and insulating layer 125) within a memory hole MH supporting the insulating layers 101. This step is performed, for example, by a method such as wet etching.

[0096] Next, for example, Figure 29 As shown, a conductive layer 110 is formed within the cavity CAV2. This step is performed, for example, by a method such as CVD.

[0097] Next, an inter-block structure ST is formed within the trench STA, forming a junction Ch connecting to the impurity region 121, and an inter-string unit insulating layer SHE, etc., forming a reference. Figure 5 The structure described.

[0098] [Comparative Example]

[0099] Next, refer to Figures 30-32 The comparative example semiconductor memory device will be described. Figure 30 This is a schematic cross-sectional view used to illustrate a comparative example of a semiconductor memory device. Figure 31 and Figure 32 This is a schematic cross-sectional view used to illustrate the manufacturing method of a comparative example semiconductor memory device.

[0100] When manufacturing the comparative example semiconductor memory device, no reference is used. Figure 9 and Figure 10 The steps for implanting ions into the MHa opening are described. Therefore, the semiconductor memory device of the comparative example and the semiconductor memory device of the first embodiment (…) Figure 5 Unlike semiconductor layers 111 and 112, regions 111_C and 112_C are not included. Figure 30 ).

[0101] Furthermore, in manufacturing the comparative example semiconductor memory device, when... Figure 11 and Figure 12 In the corresponding oxidation step, such as Figure 31 As shown, insulating layers 111_Dx and 112_Dx, such as silicon oxide, are formed in the portions of semiconductor layers 111 and 112 exposed at the opening MHa. During the formation of these insulating layers 111_Dx and 112_Dx, because semiconductor layers 111 and 112 do not contain regions 111_C and 112_C, which are prone to crystal defects, the oxidation reaction proceeds relatively slowly. Therefore, in comparison with the reference... Figure 18In the steps described, a relatively long time is required to form the insulating layers 111_Dx and 112_Dx of the required thickness as the etch termination layer.

[0102] Here, as Figure 31 Region R LMH As shown, in the steps of forming insulating layers 111_Dx and 112_Dx, the portion of sacrificial layer 110A exposed at opening MHa is also locally oxidized, thereby forming an insulating layer 110A_Dx such as silicon oxide. As described above, when manufacturing the comparative example semiconductor memory device, because... Figure 11 and Figure 12 The corresponding oxidation step requires a relatively long time, therefore, it is similar to the insulating layer 110A_D of the semiconductor memory device in the first embodiment. Figure 12 Compared to the thickness of the insulating layer 110A_Dx, the insulation layer is formed thicker.

[0103] Furthermore, in manufacturing the comparative example semiconductor memory device, when... Figure 19 The corresponding step is the memory cell array layer L. MCA1 In the process, the insulating layer 110A_Dx is etched before the sacrificial layer 110A is etched. Figure 31 At this point, because the insulating layer 110A_Dx is relatively thick, removing it requires a relatively long time. Therefore, during this period, in the memory cell array layer L... MCA2 In this process, the sacrificial layer 110A is further etched. Therefore, in the steps described, as... Figure 32 As shown, memory cell array layer L MCA2 The width D of the sacrificial layer 110A retreats Ux Larger than memory cell array layer L MCA1 The width D of the sacrificial layer 110A retreats Lx .

[0104] In this case, at the memory cell array layer L MCA1 With memory cell array layer L MCA2 The construction of memory cells (MCs) varies considerably between different types of memory cells, which can sometimes lead to significant differences in the characteristics of the memory cells (MCs).

[0105] [Effects of the first embodiment]

[0106] For reference Figure 9 and Figure 10 This indicates that by performing the step of implanting ions into the open MHa, regions 111_C and 112_C are formed, enabling relatively high-speed reference processing. Figure 11 and 12The oxidation steps described herein. Therefore, the memory cell array layer L formed simultaneously by the aforementioned steps can be... MCA1 The thickness of the insulating layer 110A_D on the sidewall of the sacrificial layer 110A is kept relatively thin.

[0107] Therefore, in reference Figure 19 In the etching step of the sacrificial layer 110A described herein, in the memory cell array layer L MCA1 With memory cell array layer L MCA2 Between these layers, the setback amount of the sacrificial layer 110A can be set to the same level. This allows for the manufacture of memory cells MC with better uniform characteristics.

[0108] [Second Implementation]

[0109] Next, refer to Figure 33 The semiconductor memory device of the second embodiment will be described. Figure 33 This is a schematic cross-sectional view used to illustrate the semiconductor memory device of the second embodiment.

[0110] The semiconductor memory device of the second embodiment is configured substantially the same as that of the semiconductor memory device of the first embodiment. However, the semiconductor memory device of the second embodiment has semiconductor layers 111_2A and 111_2B above and below semiconductor layer 111, and semiconductor layer 112_2A above semiconductor layer 112. Semiconductor layers 111_2A, 111_2B, and 112_2A contain at least one element selected from, for example, phosphorus (P), arsenic (As), carbon (C), and argon (Ar). The concentration of the element in semiconductor layers 111_2A, 111_2B, and 112_2A is greater than the concentration of the element in regions other than 111_C and 112_C in semiconductor layers 111 and 112.

[0111] [Manufacturing Method]

[0112] Next, refer to Figures 34-37 The manufacturing method of the semiconductor memory device according to the second embodiment will be described. Figure 34 and Figure 35 This is a schematic cross-sectional view used to illustrate the manufacturing method, showing a representation of... Figure 33 The corresponding cross-section. Figure 36 and Figure 37 This is a schematic cross-sectional view used to illustrate the manufacturing method, and it is a schematic cross-sectional view of... Figure 35 The area R shown SL Enlarged image.

[0113] The semiconductor memory device of the second embodiment is manufactured in essentially the same manner as the semiconductor memory device of the first embodiment.

[0114] However, when manufacturing the semiconductor memory device of the second embodiment, in conjunction with Figure 7 In the corresponding steps, such as Figure 34 As shown, semiconductor layer 112_2A is formed on the upper layer of semiconductor layer 112, and semiconductor layer 111_2A and semiconductor layer 111_2B are formed on the upper and lower layers of semiconductor layer 111.

[0115] In addition, in relation to Figure 9 and Figure 10 In the corresponding ion implantation steps, such as Figure 35 and Figure 36 As shown, within the opening MHa, regions 111_C and 112_C containing impurities such as phosphorus (P), arsenic (As), carbon (C), and argon (Ar) are formed. Through this step, the upper surface, lower surface, and side surface of the semiconductor layer 111 on the opening MHa side are surrounded by regions containing, for example, at least one element selected from phosphorus (P), arsenic (As), carbon (C), and argon (Ar), namely semiconductor layers 111_2A, 111_2B, and region 111_2C. Furthermore, the upper surface of the semiconductor layer 112 and the side surface on the opening MHa side are also surrounded by the same regions, namely semiconductor layers 112_2A and region 112_C.

[0116] In addition, in relation to Figure 11 and Figure 12 In the corresponding oxidation step, such as Figure 37 As shown, in the portions of semiconductor layer 111 and semiconductor layer 112 exposed at the opening MHa (regions 111_C and 112_C), insulating layers such as silicon oxide 111_2D and insulating layer 112_2D are formed respectively.

[0117] Furthermore, as described above, oxidation proceeds relatively rapidly in regions 111_C and 112_C, which contain a greater number of crystal defects. Additionally, oxidation also proceeds relatively rapidly in regions with higher impurity concentrations, such as semiconductor layers 111_2A, 111_2B, and 112_2A. Therefore, near semiconductor layers 111_2A, 111_2B, and 112_2A, oxidation continues until it reaches a region relatively far from the opening MHa.

[0118] [Effects of the second implementation method]

[0119] Given as Figure 33 The area R shown COR In the oxidation process, the oxidation rate is relatively low at these locations, which correspond to the "corners" of the semiconductor layer, due to the stress caused by the volume expansion of silicon as it becomes silicon oxide. Therefore, there are cases where a longer oxidation step time is required to form insulating layers 111_2D and 112_2D with the thickness needed to protect the "corners".

[0120] Therefore, in this embodiment, in addition to the regions 111_C and 112_C formed by ion implantation, high-concentration impurity layers, namely semiconductor layers 111_2A, 111_2B, and 112_2A, are provided at the "corner" positions surrounding the semiconductor layer. In the semiconductor layer containing high-concentration impurities, due to the presence of more crystal defects, the oxidation rate increases, similar to that in the regions 111_C and 112_C formed by the ion implantation step. Therefore, by surrounding the "corner" with regions 111_C and 112_C and semiconductor layers 111_2A, 111_2B, and 112_2A, insulating layers 111_2D and 112_2D of a specific thickness can be formed relatively quickly even in the "corner" where the oxidation reaction is relatively slow.

[0121] Therefore, similar to the first embodiment, the memory cell array layer L formed simultaneously by the oxidation step can be... MCA1 The thickness of the insulating layer 110A_D on the sidewall of the sacrificial layer 110A is kept relatively thin. Therefore, in the reference... Figure 19 In the etching step described above that causes the sacrificial layer 110A to retract, in the memory cell array layer L... MCA1 With memory cell array layer L MCA2 Between these, the backoff amount can be set to the same level, which can better manufacture memory cells (MCs) with uniform characteristics.

[0122] [Third Implementation]

[0123] Next, refer to Figure 38 The semiconductor memory device of the third embodiment will be described. Figure 38 This is a schematic cross-sectional view used to illustrate the semiconductor memory device of the third embodiment.

[0124] The semiconductor memory device of the third embodiment is configured in essentially the same way as the semiconductor memory device of the second embodiment. However, the semiconductor memory device of the third embodiment has a diffusion suppression layer 111_3A below semiconductor layer 111_2A, a diffusion suppression layer 111_3B above semiconductor layer 111_2B, and a diffusion suppression layer 112_3A below semiconductor layer 112_2A. The diffusion suppression layers 111_3A, 111_3B, and 112_3A are, for example, layers containing carbon (C), or semiconductor layers containing carbon at a high concentration. The carbon concentration of the diffusion suppression layers 111_3A, 111_3B, and 112_3A is greater than the carbon concentration of semiconductor layers 111 and 112.

[0125] [Manufacturing Method]

[0126] Next, refer to Figure 39The manufacturing method of the semiconductor memory device according to the third embodiment will be described. Figure 39 This is a schematic cross-sectional view used to illustrate the manufacturing method, showing the relationship with... Figure 38 The corresponding cross-section.

[0127] The semiconductor memory device of the third embodiment is manufactured in essentially the same manner as the semiconductor memory device of the second embodiment. However, when manufacturing the semiconductor memory device of the third embodiment, in conjunction with... Figure 34 In the corresponding steps, such as Figure 39 As shown, a diffusion suppression layer 112_3A is formed below the semiconductor layer 112_2A, a diffusion suppression layer 111_3B is formed above the semiconductor layer 111_2B, and a diffusion suppression layer 111_3A is formed below the semiconductor layer 111_2A.

[0128] [Effects of the third embodiment]

[0129] When semiconductor layers 111_2A, 111_2B, and 112_2A contain at least one element, such as phosphorus (P), arsenic (As), carbon (C), and argon (Ar), in a high concentration, the element may diffuse into semiconductor layers 111 and 112 due to various thermal steps in the manufacturing process, thereby potentially reducing the effect of increasing the oxidation rate as described in the second embodiment.

[0130] Therefore, as in this embodiment, by providing diffusion suppression layers 111_3A, 111_3B, and 112_3A on the upper or lower surfaces of semiconductor layers 111_2A, 111_2B, and 112_2A, it is possible to suppress the diffusion of impurities from semiconductor layers 111_2A, 111_2B, and 112_2A to semiconductor layers 111 and 112.

[0131] [other]

[0132] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. The novel embodiments can be implemented in various other ways, with various omissions, substitutions, and modifications possible without departing from the spirit of the invention. The embodiments or variations thereof are included within the scope or spirit of the invention, and are also included within the scope of the invention as described in the claims and its equivalents.

[0133] [Explanation of Symbols]

[0134] MCA: Memory Cell Array

[0135] BLK: Memory Block

[0136] SU: Serial Unit

[0137] 110: Conductive layer

[0138] 120: Semiconductor layer

[0139] 130: Gate insulating film.

Claims

1. A semiconductor memory device comprising: Substrate; Multiple first conductive layers and multiple first insulating layers are alternately arranged in a first direction intersecting the substrate; A first semiconductor layer extends in the first direction and faces the plurality of first conductive layers and the plurality of first insulating layers; A first charge storage layer is disposed between the plurality of first conductive layers and the first semiconductor layer; and A second semiconductor layer is connected to one end of the first semiconductor layer in the first direction; and At least a portion of the plurality of first insulating layers contains a first element; The first element is at least one of phosphorus (P), arsenic (As), carbon (C), and argon (Ar); When one of the plurality of first insulating layers is designated as a second insulating layer... The second insulating layer comprises: Area 1; and The second region is disposed between the first region and the first semiconductor layer; and The concentration of the first element in the second region is greater than the concentration of the first element in the first region.

2. The semiconductor memory device according to claim 1, comprising: A plurality of second conductive layers and a plurality of third insulating layers are separated from the plurality of first conductive layers and a plurality of first insulating layers in the first direction and are alternately arranged in the first direction; A third semiconductor layer extends in the first direction, faces the plurality of second conductive layers and the plurality of third insulating layers, and is connected to the first semiconductor layer; and A second charge storage layer is disposed between the plurality of second conductive layers and the third semiconductor layer; and When one of the plurality of third insulating layers is designated as a fourth insulating layer, the fourth insulating layer includes a third region arranged side-by-side with the second region in the first direction; and The concentration of the first element in the third region is greater than the concentration of the first element in the second region.

3. A semiconductor memory device comprising: Substrate; Multiple first conductive layers and multiple first insulating layers are alternately arranged in a first direction intersecting the substrate; A first semiconductor layer extends in the first direction and faces the plurality of first conductive layers and the plurality of first insulating layers; A charge storage layer is disposed between the plurality of first conductive layers and the first semiconductor layer; and A second semiconductor layer, wherein one end of the first semiconductor layer in the first direction extends inside the second semiconductor layer, and the second semiconductor layer is in contact with the sidewall of the first semiconductor layer; and The second semiconductor layer contains the first element. The first element is at least one of P, arsenic (As), carbon (C), and argon (Ar). One end of the charge storage layer in the first direction extends inside the second semiconductor layer. The second semiconductor layer comprises: Area 4; and A fifth region is disposed between the fourth region and the charge storage layer; and The concentration of the first element in the fifth region is greater than the concentration of the first element in the fourth region.

4. The semiconductor memory device according to claim 3, wherein The second semiconductor layer comprises: Area 6; and The seventh region is disposed between the sixth region and the substrate; and The concentration of the first element in the sixth region is greater than the concentration of the first element in the seventh region.

5. The semiconductor memory device according to claim 4, comprising: The eighth region is located between the sixth region and the seventh region; and The carbon (C) concentration in the 8th region is greater than that in the 6th and 7th regions.

6. The semiconductor memory device according to any one of claims 1 to 5, wherein The first semiconductor layer comprises: The 9th region is opposite to the plurality of first conductive layers and the plurality of first insulating layers; The 10th region is located at one end in the first direction; and Region 11 is located between Region 9 and Region 10 and is connected to the second semiconductor layer.

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