Thin-film transistors and electronic devices with vertical structure
By employing a stacked conductive ohmic contact layer in a vertical thin-film transistor, the stability problem caused by doped ion diffusion is solved, achieving a thin-film transistor with high aperture ratio and high performance, suitable for high-resolution and high-refresh-rate display products.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WUHAN CHINA STAR OPTOELECTRONICS TECH CO LTD
- Filing Date
- 2022-09-27
- Publication Date
- 2026-06-16
AI Technical Summary
In existing vertical thin-film transistors, doped ions in the ohmic contact region tend to diffuse into the channel, resulting in poor stability of the thin-film transistor.
The structure employs a stacked configuration of a first ohmic contact layer, a channel layer, and a second ohmic contact layer. The second ohmic contact layer is made of a conductive material with a sheet resistance of less than or equal to 10,000 ohms/square, thus preventing doped ions from diffusing into the channel layer.
The realization of polycrystalline silicon thin-film transistors with extremely small channel lengths improves the aperture ratio and device stability of display panels, making them suitable for the development of high-resolution and high-refresh-rate products.
Smart Images
Figure CN115513300B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and in particular to a vertically structured thin-film transistor and electronic device. Background Technology
[0002] With the development of display technology, existing display devices need to reduce the size and area of thin-film transistors (TFTs) to achieve narrow bezels, high aperture ratios, high brightness, and high resolution. However, polycrystalline silicon TFTs have relatively low mobility. To improve the mobility of TFTs, the channel length needs to be reduced, which means increasing the area occupied by the active layer. Furthermore, the channel length is limited by process constraints, resulting in a limited reduction in the shrinkage rate. This makes it impossible for display devices to simultaneously achieve both high mobility and small size of TFTs. To address this issue, existing display devices have designed a vertical TFT structure. By using the thickness of the active layer as the channel length, this design is not limited by process constraints and can achieve TFTs with extremely small channel lengths. However, during the fabrication of vertical TFT structures, because the ohmic contact regions are located on the top and bottom sides of the channel region, doped ions from the ohmic contact regions can easily diffuse into the channel, leading to decreased device stability.
[0003] Therefore, existing vertical thin-film transistors have the technical problem that doped ions in the ohmic contact region can easily diffuse into the channel, resulting in poor stability of the thin-film transistor. Summary of the Invention
[0004] This application provides a vertically structured thin-film transistor and electronic device to alleviate the technical problem that doped ions in the ohmic contact region of existing vertically structured thin-film transistors easily diffuse into the channel, resulting in poor stability of the thin-film transistor.
[0005] This application provides a vertically structured thin-film transistor, which includes:
[0006] Insulating substrate;
[0007] An active layer is disposed on one side of the insulating substrate, and the active layer includes a first ohmic contact layer, a channel layer and a second ohmic contact layer stacked together.
[0008] The second ohmic contact layer is disposed on the side of the channel layer away from the insulating substrate, and the material of the second ohmic contact layer includes a conductive material. The sheet resistance of the second ohmic contact layer is less than or equal to 10,000 ohms / square.
[0009] In some embodiments, when ions diffuse from the second ohmic contact layer into the channel layer, the diffusion depth of the ions in the second ohmic contact layer is less than or equal to one-quarter of the thickness of the channel layer.
[0010] In some embodiments, the material of the second ohmic contact layer includes at least one of indium tin oxide, indium gallium zinc oxide, indium zinc oxide, graphene, and carbon nanotubes.
[0011] In some embodiments, the material of the first ohmic contact layer includes N-type doped polycrystalline silicon.
[0012] In some embodiments, the material of the first ohmic contact layer includes a conductive material, and the sheet resistance of the first ohmic contact layer is less than or equal to 10,000 ohms / square.
[0013] In some embodiments, when ions diffuse from the second ohmic contact layer into the channel layer, the diffusion depth of the ions in the second ohmic contact layer is less than or equal to one-quarter of the thickness of the channel layer.
[0014] In some embodiments, the material of the first ohmic contact layer includes at least one of indium tin oxide, indium gallium zinc oxide, indium zinc oxide, graphene, and carbon nanotubes.
[0015] In some embodiments, the vertically structured thin-film transistor further includes:
[0016] An insulating layer is disposed on the side of the second ohmic contact layer away from the channel layer;
[0017] The source-drain layer is disposed on the side of the insulating layer away from the active layer;
[0018] The source and drain layers include a first electrode and a second electrode, the insulating layer includes a first via and a second via, the width of the first ohmic contact layer is greater than the width of the channel layer, the first via is disposed in the region of the first ohmic contact layer that extends beyond the channel layer, the first electrode is electrically connected to the first ohmic contact layer through the first via, and the second electrode is electrically connected to the second ohmic contact layer through the second via.
[0019] In some embodiments, the vertically structured thin-film transistor further includes:
[0020] A light-shielding layer is disposed between the insulating substrate and the active layer, wherein the orthographic projection of the light-shielding layer on the insulating substrate at least covers the orthographic projection of the channel layer on the insulating substrate;
[0021] A buffer layer is disposed between the light-shielding layer and the active layer;
[0022] A gate is disposed on the sidewall of the insulating layer, and the orthogonal projection of the gate onto the sidewall of the insulating layer covers the channel layer.
[0023] The gate is connected to the light-shielding layer.
[0024] Meanwhile, this application provides an electronic device including a thin-film transistor with a vertical structure as described in any of the above embodiments.
[0025] Beneficial effects: This application provides a vertically structured thin-film transistor and electronic device; the vertically structured thin-film transistor includes an insulating substrate and an active layer, the active layer being disposed on one side of the insulating substrate, the active layer including a first ohmic contact layer, a channel layer and a second ohmic contact layer stacked together; wherein, the second ohmic contact layer is disposed on the side of the channel layer away from the insulating substrate, the material of the second ohmic contact layer includes a conductive material, and the sheet resistance of the second ohmic contact layer is less than or equal to 10000 ohms / square. This application achieves a polycrystalline silicon thin-film transistor with an extremely small channel length by stacking a first ohmic contact layer, a channel layer, and a second ohmic contact layer. This reduces the projected area of the thin-film transistor, increases the aperture ratio of the display panel, and facilitates the development of high-resolution and high-refresh-rate products, even enabling the implementation of some chip functions. Furthermore, the material of the second ohmic contact layer includes conductive materials, and the sheet resistance of the second ohmic contact layer is less than or equal to 10,000 ohms / square. This eliminates the need to use polycrystalline silicon to form the second ohmic contact layer and eliminates the need for doping the second ohmic contact layer, preventing dopant ions from diffusing into the channel layer and reducing the number of ions diffusing from the second ohmic contact layer to the channel layer. In addition, the second ohmic contact layer has good conductivity, enabling the thin-film transistor to operate normally. Attached Figure Description
[0026] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.
[0027] Figure 1 This is a schematic diagram of the structure of an existing display device.
[0028] Figure 2 This is a schematic diagram of a vertically structured thin-film transistor provided in an embodiment of this application.
[0029] Figure 3 for Figure 2 A1-A2 cross-sectional view of the vertical structure of the thin-film transistor.
[0030] Figure 4 This is a first schematic diagram of the vertical thin-film transistor corresponding to each step in the fabrication method of the vertical thin-film transistor provided in the embodiments of this application.
[0031] Figure 5 This is a second schematic diagram of the vertical thin-film transistor corresponding to each step in the fabrication method of the vertical thin-film transistor provided in the embodiments of this application. Detailed Implementation
[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0033] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.
[0034] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0035] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.
[0036] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.
[0037] like Figure 1 As shown, a conventional display device includes a substrate 11, a light-shielding layer 12, a buffer layer 13, an active layer 14, a gate insulating layer 15, a gate layer 16, an interlayer insulating layer 17, a source / drain layer 18, a planarization layer 19, a first electrode layer 22, a passivation layer 21, and a second electrode layer 23. Figure 1 As can be seen, the active layer 14 includes an ohmic contact region 141 and a channel region 142. The ohmic contact region 141 includes a heavily doped region 141a and a lightly doped region 141b. Each region of the active layer is arranged horizontally, occupying a large area. Furthermore, due to limitations in exposure and etching precision, the channel length of the active layer is relatively small, resulting in low mobility of the thin-film transistor 10. To improve the mobility of thin-film transistors, existing display devices design vertically structured thin-film transistors, where the channel length of the active layer is equal to the thickness of the active layer, enabling the realization of thin-film transistors with extremely small channel lengths. However, during the fabrication of vertically structured thin-film transistors, because the ohmic contact regions are located on the upper and lower sides of the channel region, dopant ions from the ohmic contact regions easily diffuse into the channel, causing a decrease in device stability. Therefore, existing vertically structured thin-film transistors suffer from the technical problem of poor stability due to the easy diffusion of dopant ions from the ohmic contact regions into the channel.
[0038] This application provides a vertically structured thin-film transistor and electronic device to address the aforementioned technical problems.
[0039] like Figure 2 , Figure 3 As shown, this application embodiment provides a vertically structured thin-film transistor 3, which includes:
[0040] Insulating substrate 31;
[0041] An active layer 34 is disposed on one side of the insulating substrate 31. The active layer 34 includes a first ohmic contact layer 341, a channel layer 342, and a second ohmic contact layer 343 stacked together.
[0042] The second ohmic contact layer 343 is disposed on the side of the channel layer 342 away from the insulating substrate 31. The material of the second ohmic contact layer 343 includes a conductive material, and the sheet resistance of the second ohmic contact layer 343 is less than or equal to 10,000 ohms / square.
[0043] This application provides a vertically structured thin-film transistor (TFT). This TFT, by stacking a first ohmic contact layer, a channel layer, and a second ohmic contact layer, can achieve a polycrystalline silicon TFT with an extremely small channel length. This reduces the projected area of the TFT, increases the aperture ratio of the display panel, and is beneficial for developing high-resolution and high-refresh-rate products, and even realizing some chip functions. Furthermore, the material of the second ohmic contact layer includes conductive materials, and the sheet resistance of the second ohmic contact layer is less than or equal to 10,000 ohms / square. This eliminates the need for polycrystalline silicon to form the second ohmic contact layer and avoids doping of the second ohmic contact layer, preventing dopant ions from diffusing into the channel layer and reducing the number of ions diffusing from the second ohmic contact layer to the channel layer. Additionally, the second ohmic contact layer has good conductivity, enabling the TFT to function normally.
[0044] Specifically, in existing thin-film transistors, doping polysilicon with doped ions is used to form ohmic contact regions. However, this design causes doped ions to diffuse into the channel, resulting in poor device stability. Furthermore, the sheet resistance of the doped polysilicon in this design is greater than 10,000 ohms / square. In this application, by using a conductive material for the second ohmic contact layer, and ensuring that the sheet resistance of the second ohmic contact layer is less than or equal to 10,000 ohms / square, it is not necessary to use doped polysilicon to form the ohmic contact layer. This avoids the diffusion of doped ions into the ohmic contact layer, improves device stability, and ensures that the second ohmic contact layer has good conductivity, enabling the thin-film transistor to function properly.
[0045] To address the issue of doped ions diffusing into the channel layer and causing performance degradation in thin-film transistors (TFTs), one embodiment specifies that when ions diffuse into the channel layer from the second ohmic contact layer, the diffusion depth of these ions is less than or equal to one-quarter of the channel layer's thickness. By ensuring that the diffusion depth of ions from the second ohmic contact layer is less than or equal to one-quarter of the channel layer's thickness when ions diffuse into the channel layer, excessive ion diffusion depth can prevent performance changes in the channel layer and avoid excessive leakage current in the TFT, thereby improving TFT performance.
[0046] This addresses the technical problem that using doped polycrystalline silicon as the ohmic contact region leads to doped ions diffusing into the channel region, thereby degrading the performance of thin-film transistors (TFTs). In one embodiment, the material of the second ohmic contact layer includes at least one of indium tin oxide (ITO), indium gallium zinc oxide (IGNOO), indium zinc oxide (IBO), graphene, and carbon nanotubes. By using at least one of these materials as the material for the second ohmic contact layer, ion doping of the second ohmic contact layer is unnecessary during its formation. This avoids doped ions diffusing into the channel layer, preventing excessive leakage current in the TFT and improving its performance. Even if ion diffusion occurs in the second ohmic contact layer, the diffusion is minimal due to the aforementioned materials, and the diffusion depth does not exceed one-quarter of the channel layer thickness, thus preventing excessive leakage current and improving TFT performance.
[0047] In one embodiment, the second ohmic contact layer comprises two different materials, such as indium tin oxide and indium gallium zinc oxide. By using two materials with different sheet resistances to form the second ohmic contact layer, the second ohmic contact layer can form a structure similar to lightly doped and heavily doped portions, further reducing the leakage current of the thin-film transistor and improving the performance of the thin-film transistor.
[0048] In one embodiment, when the material of the second ohmic contact layer is indium tin oxide, indium gallium zinc oxide, or indium zinc oxide, the thickness of the second ohmic contact layer ranges from 10 nanometers to 100 nanometers; when the material of the second ohmic contact layer is graphene or carbon nanotubes, the thickness of the second ohmic contact layer ranges from 0.5 nanometers to 10 nanometers.
[0049] In one embodiment, the thickness of the channel layer ranges from 10 nanometers to 100 nanometers.
[0050] In one embodiment, the material of the first ohmic contact layer includes N-type doped polysilicon. Since the channel layer is disposed on the first ohmic contact layer, the first ohmic contact layer is prepared before the channel layer when the active layer is formed. During ion diffusion, fewer ions diffuse from the first ohmic contact layer to the channel layer. Therefore, N-type doped polysilicon can be used to form the first ohmic contact layer.
[0051] Specifically, the first ohmic contact layer includes a lightly doped layer and a heavily doped layer. The lightly doped layer is disposed between the channel layer and the heavily doped layer, and the dopant concentration of the lightly doped layer is lower than that of the heavily doped layer. By making the dopant concentration of the heavily doped portion greater than that of the lightly doped portion, the first ohmic contact layer has a stacked structure with a heavily doped bottom layer and a lightly doped top layer. This forces electrons to pass through both the heavily doped and lightly doped portions during movement, reducing the leakage current of the thin-film transistor and improving its performance.
[0052] This addresses the technical problem that using doped polysilicon for the first ohmic contact layer can lead to dopant ions diffusing into the channel layer, resulting in degraded thin-film transistor performance. In one embodiment, the first ohmic contact layer is made of a conductive material, and its sheet resistance is less than or equal to 10,000 ohms / square. By including a conductive material in the first ohmic contact layer, and ensuring its sheet resistance is less than or equal to 10,000 ohms / square, polysilicon is not required to form the first ohmic contact layer. This eliminates the need for doping the first ohmic contact layer, preventing dopant ions from diffusing into the channel layer, reducing the number of ions diffusing from the first ohmic contact layer to the channel layer, and improving the conductivity of the first ohmic contact layer, thus enabling the thin-film transistor to function properly.
[0053] Specifically, during laser annealing and crystallization of the channel layer, there is a certain amount of ion diffusion between the channel layer and the first ohmic contact layer, causing doped ions to diffuse into the channel layer. Therefore, an undoped material is used to form the first ohmic contact layer to prevent doped ions from the first ohmic contact layer from diffusing into the channel layer, thereby improving the performance of the thin film transistor. In addition, the sheet resistance of the first ohmic contact layer is small, which improves the conductivity of the first ohmic contact layer and enables the thin film transistor to work normally.
[0054] To address the issue of doped ions diffusing into the channel layer and causing performance degradation in thin-film transistors (TFTs), one embodiment specifies that when ions diffuse from the first ohmic contact layer into the channel layer, the diffusion depth of these ions is less than or equal to one-quarter of the channel layer's thickness. By ensuring that the diffusion depth of ions from the first ohmic contact layer into the channel layer is less than or equal to one-quarter of the channel layer's thickness, excessive ion diffusion depth can prevent performance changes in the channel layer and avoid excessive leakage current in the TFT, thereby improving TFT performance.
[0055] This addresses the technical problem that using doped polycrystalline silicon as the ohmic contact region leads to the diffusion of doped ions into the channel region, thereby degrading the performance of thin-film transistors (TFTs). In one embodiment, the material of the first ohmic contact layer includes at least one of indium tin oxide (ITO), indium gallium zinc oxide (IGNOO), indium zinc oxide (IGNOO), graphene, and carbon nanotubes. By using at least one of these materials as the material for the first ohmic contact layer, ion doping of the first ohmic contact layer is unnecessary during its formation. This avoids the diffusion of doped ions into the channel layer, preventing excessive leakage current in the TFT and improving its performance. Even if ion diffusion occurs in the first ohmic contact layer, the diffusion is minimal due to the aforementioned materials, and the diffusion depth does not exceed one-quarter of the channel layer thickness, thus preventing excessive leakage current and improving TFT performance.
[0056] In one embodiment, the first ohmic contact layer comprises two different materials, such as indium tin oxide and indium gallium zinc oxide. By using two materials with different sheet resistances to form the first ohmic contact layer, the first ohmic contact layer can form a structure similar to lightly doped and heavily doped portions, further reducing the leakage current of the thin-film transistor and improving the performance of the thin-film transistor.
[0057] In one embodiment, when the material of the first ohmic contact layer is indium tin oxide, indium gallium zinc oxide, or indium zinc oxide, the thickness of the first ohmic contact layer ranges from 10 nanometers to 100 nanometers; when the material of the first ohmic contact layer is graphene or carbon nanotubes, the thickness of the first ohmic contact layer ranges from 0.5 nanometers to 10 nanometers.
[0058] In one embodiment, such as Figure 3 As shown, the vertically structured thin-film transistor 3 further includes:
[0059] An insulating layer 35 is disposed on the side of the second ohmic contact layer 343 away from the channel layer 342;
[0060] The source-drain layer 38 is disposed on the side of the insulating layer 35 away from the active layer 34;
[0061] The source / drain layer 38 includes a first electrode 381 and a second electrode 382. The insulating layer 35 includes a first via 371 and a second via 372. The width of the first ohmic contact layer 341 is greater than the width of the channel layer 342. The first via 371 is located in the region of the first ohmic contact layer 341 that extends beyond the channel layer 342. The first electrode 381 is electrically connected to the first ohmic contact layer 341 through the first via 371, and the second electrode 382 is electrically connected to the second ohmic contact layer 343 through the second via 372. By making the width of the first ohmic contact layer greater than the width of the channel layer and placing the first via in the region of the first ohmic contact layer that extends beyond the channel layer, the first electrode can be connected to the first ohmic contact layer through the first via, avoiding poor contact or short circuits between the first electrode and the first ohmic contact layer. This ensures proper connection between the source / drain layer and the active layer, allowing the thin-film transistor to function normally.
[0062] Specifically, the difference between the width of the first ohmic contact layer and the width of the second ohmic contact layer ranges from 2 micrometers to 5 micrometers. By making the difference between the width of the first ohmic contact layer and the width of the second ohmic contact layer range from 2 micrometers to 5 micrometers, the first ohmic contact layer has a certain width to connect with the first electrode, and the width of the portion of the first ohmic contact layer that extends beyond the second ohmic contact layer is not too large, thereby reducing the projected area of the thin-film transistor and increasing the aperture ratio of the display panel.
[0063] This addresses the technical problem of insufficient control capability when the gate is disposed on the side of the active layer. In one embodiment, such as... Figure 3 As shown, the vertically structured thin-film transistor 3 further includes:
[0064] A light-shielding layer 32 is disposed between the insulating substrate 31 and the active layer 34, and the orthogonal projection of the light-shielding layer 32 on the insulating substrate 31 at least covers the orthogonal projection of the channel layer 342 on the insulating substrate 31.
[0065] A buffer layer 33 is disposed between the light-shielding layer 32 and the active layer 34;
[0066] A gate 36 is disposed on the sidewall of the insulating layer 35, and the orthographic projection of the gate 36 on the sidewall of the insulating layer 35 covers the channel layer 342.
[0067] The gate 36 is connected to the light-shielding layer 32. By ensuring that the orthogonal projection of the light-shielding layer on the insulating substrate at least covers the orthogonal projection of the channel layer on the insulating substrate, the light-shielding layer can prevent external light from shining into the channel portion, thus preventing the active layer from being exposed to light and causing performance degradation. By connecting the gate to the light-shielding layer, the active layer can be semi-enclosed, improving the control capability of the gate.
[0068] In one embodiment, the material of the light-shielding layer includes molybdenum, titanium, tungsten, or a stack thereof.
[0069] In one embodiment, the material of the buffer layer includes silicon oxide, silicon nitride, silicon oxynitride, or a stack thereof.
[0070] In one embodiment, the insulating layer 35 includes a gate insulating layer 351 and an interlayer insulating layer 352.
[0071] In one embodiment, the material of the gate insulating layer includes silicon oxide, silicon nitride, silicon oxynitride, or a stack thereof.
[0072] In one embodiment, the thickness of the gate insulating layer ranges from 30 nanometers to 200 nanometers.
[0073] In one embodiment, the gate material includes molybdenum, titanium, tungsten, or a stack thereof.
[0074] In one embodiment, the thickness of the gate ranges from 0.1 micrometers to 1 micrometer.
[0075] In one embodiment, the interlayer insulating layer is made of a stack of silicon oxide and silicon nitride.
[0076] In one embodiment, the source and drain layers are made of molybdenum, titanium, tungsten, aluminum, copper, or a stack thereof.
[0077] Meanwhile, this application provides a method for fabricating a vertically oriented thin-film transistor. This method fabricates a thin-film transistor as described in any of the above embodiments, and includes:
[0078] An insulating substrate is provided, and a light-shielding layer is formed on the insulating substrate; the structure of the vertical thin-film transistor corresponding to this step is as follows. Figure 4 As shown in (a) in the middle;
[0079] Specifically, metal can be deposited on an insulating substrate and then exposed and etched to form a light-shielding layer.
[0080] A buffer layer and a first ohmic contact layer are deposited on the light-shielding layer; the structure of the corresponding vertical thin-film transistor is as follows. Figure 4 As shown in (b);
[0081] Specifically, when the material of the first ohmic contact layer is indium tin oxide, indium gallium zinc oxide, or indium zinc oxide, the corresponding target material is used for sputtering to form a film in physical vapor deposition; when the material of the first ohmic contact layer is graphene or carbon nanotubes, carbon source gases such as methane or ethane are introduced into the chemical vapor deposition to form a film, and then the first ohmic contact layer is patterned by exposure etching.
[0082] A channel layer and a second ohmic contact layer are deposited on the first ohmic contact layer; the structure of the thin-film transistor corresponding to this step is as follows. Figure 4 As shown in (c);
[0083] Specifically, when forming the channel layer, an amorphous silicon layer can be deposited, and the amorphous silicon can be converted into polycrystalline silicon by laser annealing.
[0084] Specifically, when forming the second ohmic contact layer, if the material of the second ohmic contact layer is indium tin oxide, indium gallium zinc oxide, or indium zinc oxide, the corresponding target material is used for sputtering to form a film in physical vapor deposition; if the material of the second ohmic contact layer is graphene or carbon nanotubes, carbon source gas such as methane or ethane is introduced into the chemical vapor deposition to form a film, and then the second ohmic contact layer is patterned by exposure etching.
[0085] A gate insulating layer is formed on the second ohmic contact layer; the structure of the corresponding vertical thin-film transistor is as follows. Figure 4 As shown in (d);
[0086] Specifically, inorganic materials can be deposited on the second ohmic contact layer, and then exposed and etched through vias to form a gate insulating layer.
[0087] A gate is formed on the gate insulating layer; the structure of the corresponding vertical thin-film transistor is as follows: Figure 5 As shown in (a) in the middle;
[0088] Specifically, metal can be deposited on the gate insulating layer and then exposed and etched to form the gate.
[0089] An interlayer insulating layer is formed on the gate insulating layer, and the interlayer insulating layer is etched to obtain a first via and a second via; the structure of the vertical thin-film transistor corresponding to this step is as follows. Figure 5 As shown in (b);
[0090] Specifically, inorganic materials can be deposited on the gate insulating layer, and hydrogen activation, exposure, and via etching can be performed to form an interlayer insulating layer.
[0091] A source / drain layer is formed on the interlayer insulating layer; the structure of the corresponding vertical thin-film transistor is as follows: Figure 3 As shown.
[0092] Specifically, after depositing metal on the interlayer insulating layer, the source and drain layers can be formed by exposure etching.
[0093] This application provides a method for fabricating a vertically structured thin-film transistor (TFT). This method fabricates a TFT with a vertical structure by stacking a first ohmic contact layer, a channel layer, and a second ohmic contact layer. This enables the fabrication of a polycrystalline silicon TFT with an extremely small channel length, reducing the projected area of the TFT, increasing the aperture ratio of the display panel, and facilitating the development of high-resolution and high-refresh-rate products, even enabling the implementation of some chip functions. Furthermore, the second ohmic contact layer is made of conductive material, and its sheet resistance is less than or equal to 10,000 ohms / square. This eliminates the need for polycrystalline silicon to form the second ohmic contact layer and avoids doping of the second ohmic contact layer, preventing dopant ions from diffusing into the channel layer and reducing the number of ions diffusing from the second ohmic contact layer to the channel layer. The second ohmic contact layer also exhibits good conductivity, enabling the TFT to function properly.
[0094] Meanwhile, this application provides an electronic device including a thin-film transistor with a vertical structure as described in any of the above embodiments.
[0095] As can be seen from the above embodiments:
[0096] This application provides a vertically structured thin-film transistor and electronic device. The vertically structured thin-film transistor includes an insulating substrate and an active layer. The active layer is disposed on one side of the insulating substrate and includes a first ohmic contact layer, a channel layer, and a second ohmic contact layer stacked together. The second ohmic contact layer is disposed on the side of the channel layer away from the insulating substrate. The material of the second ohmic contact layer includes a conductive material, and the sheet resistance of the second ohmic contact layer is less than or equal to 10,000 ohms / square. This application achieves a polycrystalline silicon thin-film transistor with an extremely small channel length by stacking a first ohmic contact layer, a channel layer, and a second ohmic contact layer. This reduces the projected area of the thin-film transistor, increases the aperture ratio of the display panel, and facilitates the development of high-resolution and high-refresh-rate products, even enabling the implementation of some chip functions. Furthermore, the material of the second ohmic contact layer includes conductive materials, and the sheet resistance of the second ohmic contact layer is less than or equal to 10,000 ohms / square. This eliminates the need to use polycrystalline silicon to form the second ohmic contact layer and eliminates the need for doping the second ohmic contact layer, preventing dopant ions from diffusing into the channel layer and reducing the number of ions diffusing from the second ohmic contact layer to the channel layer. In addition, the second ohmic contact layer has good conductivity, enabling the thin-film transistor to operate normally.
[0097] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0098] The foregoing has provided a detailed description of a vertically structured thin-film transistor and electronic device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A vertically oriented thin-film transistor, characterized in that, include: Insulating substrate; An active layer is disposed on one side of the insulating substrate. The active layer includes a first ohmic contact layer, a channel layer, and a second ohmic contact layer stacked together. The channel layer is made of polycrystalline silicon. The second ohmic contact layer is disposed on the side of the channel layer away from the insulating substrate, and the material of the second ohmic contact layer includes a conductive material. The sheet resistance of the second ohmic contact layer is less than or equal to 10,000 ohms / square. The vertically structured thin-film transistor further includes a source-drain layer, and the material of the second ohmic contact layer is different from that of the source-drain layer; the material of the second ohmic contact layer is different from that of the channel layer; the material of the second ohmic contact layer is an undoped conductive material; The second ohmic contact layer comprises two different materials.
2. The thin-film transistor with a vertical structure as described in claim 1, characterized in that, When ions diffuse from the second ohmic contact layer into the channel layer, the diffusion depth of the ions in the second ohmic contact layer is less than or equal to one-quarter of the thickness of the channel layer.
3. The thin-film transistor with a vertical structure as described in claim 2, characterized in that, The material of the second ohmic contact layer includes at least one of indium tin oxide, indium gallium zinc oxide, indium zinc oxide, graphene, and carbon nanotubes.
4. The thin-film transistor with a vertical structure as described in claim 1, characterized in that, The material of the first ohmic contact layer includes N-type doped polycrystalline silicon.
5. The thin-film transistor with a vertical structure as described in claim 1, characterized in that, The material of the first ohmic contact layer includes a conductive material, and the sheet resistance of the first ohmic contact layer is less than or equal to 10,000 ohms / square.
6. The thin-film transistor with a vertical structure as described in claim 5, characterized in that, When ions diffuse from the second ohmic contact layer into the channel layer, the diffusion depth of the ions in the second ohmic contact layer is less than or equal to one-quarter of the thickness of the channel layer.
7. The thin-film transistor with a vertical structure as described in claim 6, characterized in that, The material of the first ohmic contact layer includes at least one of indium tin oxide, indium gallium zinc oxide, indium zinc oxide, graphene, and carbon nanotubes.
8. The thin-film transistor with a vertical structure as described in claim 1, characterized in that, The vertically structured thin-film transistor also includes: An insulating layer is disposed on the side of the second ohmic contact layer away from the channel layer; The source and drain layers are disposed on the side of the insulating layer away from the active layer; The source and drain layers include a first electrode and a second electrode, the insulating layer includes a first via and a second via, the width of the first ohmic contact layer is greater than the width of the channel layer, the first via is disposed in the region of the first ohmic contact layer that extends beyond the channel layer, the first electrode is electrically connected to the first ohmic contact layer through the first via, and the second electrode is electrically connected to the second ohmic contact layer through the second via.
9. The thin-film transistor with a vertical structure as described in claim 8, characterized in that, The vertically structured thin-film transistor also includes: A light-shielding layer is disposed between the insulating substrate and the active layer, wherein the orthographic projection of the light-shielding layer on the insulating substrate at least covers the orthographic projection of the channel layer on the insulating substrate; A buffer layer is disposed between the light-shielding layer and the active layer; A gate is disposed on the sidewall of the insulating layer, and the orthogonal projection of the gate onto the sidewall of the insulating layer covers the channel layer. The gate is connected to the light-shielding layer.
10. An electronic device, characterized in that, The electronic device includes a thin-film transistor with a vertical structure as described in any one of claims 1 to 9.