Back contact solar cell and method for preparing the same

Abstract

The present invention discloses a back-contact solar cell and a method for preparing the same. The back-contact solar cell comprises: a semiconductor substrate, the semiconductor substrate having a first surface and a second surface opposite to each other, the first surface comprising a plurality of non-grooved areas and a plurality of grooved areas, the non-grooved areas and the grooved areas being alternately arranged on the first surface; a tunneling oxide layer and an N-type doped crystalline silicon layer; a first intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer; an isolation structure, the isolation structure comprising an isolation layer and an isolation groove. The present invention not only increases the preparation process window of the back-contact solar cell and reduces the process difficulty, but also improves the surface passivation effect of the P region, so that the performance of the solar cell can reach an effect comparable to that of the existing HBC battery structure.

Description

Technical Field

[0001] The present invention belongs to the technical field of solar cells, and in particular relates to a back contact solar cell and a preparation method thereof. Background Art

[0002] Selective passivation contact technology separates metal from semiconductor, avoiding serious recombination caused by direct contact between metal and semiconductor. At the same time, this selective passivation structure has obvious selectivity for the passage of specific carriers. One carrier can pass effectively while shielding the other carrier, avoiding the recombination of the two carriers in the electrode collection area, thereby effectively improving the photoelectric conversion efficiency of solar cell devices. Typical representatives of this selective passivation contact structure in solar energy technology are tunnel oxide passivated contact solar cells (TOPCon) and heterojunction solar cells (HIT). Both of these cell structures are double-sided electrode structures, and the common efficiency bottleneck is that the shading caused by the front metal cannot be avoided. For the TOPCon structure, the front side is still in direct contact between the metal and the silicon base. In addition to shading, the problem of serious metal recombination still exists; for the HIT structure, although the front metal recombination is effectively suppressed, the parasitic absorption of the incident light by the amorphous silicon / ITO layer causes a serious loss of short-circuit current density.

[0003] Interdigitated back contact (IBC) cell technology moves the front electrode of the cell to the back, thereby avoiding shading and recombination of the front metal, effectively improving the conversion efficiency of the cell. The TBC (Tunnel oxide Back Contact) or HBC (Hetero-Junction Back Contact) technology, which combines IBC technology with TOPCon or HJT technology, further reduces the recombination of the back metal of IBC. In 2017, Kaneka announced a HBC cell conversion efficiency of up to 26.7%, showing the powerful efficiency advantage of this structure.

[0004] The back n-region and p-region of the traditional HBC battery structure use i / n a-Si:H and i / p a-Si:H to form a cross-finger pattern. During the manufacturing process, the damage of the laser to the n-region and p-region needs to be strictly controlled, especially for the n-region. The laser process window is narrow, which increases the difficulty of the process. HBC batteries also have the following shortcomings in the manufacturing process: a large number of masks and mask removal technologies are used to form patterns, such as the photolithography technology commonly used in the semiconductor field, which has high production costs and difficult process control; in terms of equipment fixed investment, the CVD equipment for depositing amorphous silicon thin films is expensive and has low production capacity. These aspects restrict the efficiency improvement and cost reduction of HBC batteries and limit its industrial application.

[0005] Since the TOPCon battery process is mature, the TBC battery that absorbs the key technical processes of the TOPCon battery has become the most cost-effective IBC battery process route. SunPower and domestic companies that have tried to mass-produce IBC batteries have transformed to this technical route. On the basis of the IBC battery structure, TBC replaces the n-region and p-region structures on the back of the IBC from phosphorus diffusion and boron diffusion doped substrate silicon to SiOx / n+poly Si and SiOx / p+poly Si structures. This structure solves the serious metal recombination of the n and p regions. In addition, this tunneling oxide layer passivation contact structure also effectively suppresses the serious Auger recombination problem caused by direct doping of impurities in the substrate in the traditional IBC structure. However, TBC batteries have the following disadvantages: the preparation process route is long, and the high-temperature preparation of p poly and n poly leads to serious concentric circles of silicon wafers, among which p poly is passivated at 10fa, and n poly can be 4fa; after the interdigitated structure on the back is completed, the P region and N region need to be isolated separately, and the preparation process is relatively complicated. Summary of the invention

[0006] The present invention aims to solve at least one of the technical problems in the related art to a certain extent. To this end, the purpose of the present invention is to provide a back-contact solar cell and a method for preparing the same. The present invention not only increases the preparation process window of the back-contact solar cell and reduces the process difficulty, but also improves the surface passivation effect of the P region, so that the energy conversion efficiency Eta, open circuit voltage Uoc, short circuit current Isc, fill factor FF, and parallel resistance Rsh of the solar cell can all achieve the same effect as the existing HBC battery structure.

[0007] In one aspect of the present invention, the present invention provides a back-contact solar cell. According to an embodiment of the present invention, the back-contact solar cell comprises:

[0008] A semiconductor substrate, wherein the semiconductor substrate has a first surface and a second surface opposite to each other, wherein the first surface includes a plurality of non-recessed areas and a plurality of recessed areas, and the non-recessed areas and the recessed areas are alternately arranged on the first surface;

[0009] A tunneling oxide layer and an N-type doped crystalline silicon layer, wherein the tunneling oxide layer is on the non-recessed area, and the N-type doped crystalline silicon layer is on a surface of the tunneling oxide layer away from the semiconductor substrate;

[0010] A first intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer, the N-type doped crystalline silicon layer and the P-type doped amorphous silicon layer have opposite conductivity types, the first intrinsic amorphous silicon layer is on the groove region and extends on a portion of the surface of the N-type doped crystalline silicon layer away from the tunneling oxide layer, and the P-type doped amorphous silicon layer is on a surface of the first intrinsic amorphous silicon layer away from the semiconductor substrate, forming an interlaced overlapping region of the first intrinsic amorphous silicon layer and the P-type doped amorphous silicon layer, the tunneling oxide layer, and the P-type doped polycrystalline silicon layer;

[0011] An isolation structure, wherein the isolation structure comprises an isolation layer and an isolation groove, wherein the isolation layer is between the first intrinsic amorphous silicon layer and the N-type doped crystalline silicon layer in the staggered overlapping region, and the isolation groove penetrates the P-type doped amorphous silicon layer and the first intrinsic amorphous silicon layer in the staggered overlapping region.

[0012] According to the back contact solar cell of the embodiment of the present invention, compared with the HBC cell structure in the prior art, the present invention adopts a tunneling oxide layer + n-poly-Si layer passivation contact to replace the intrinsic a-si:H + a-si:H(N) film passivation in the existing HBC cell structure. Since the tunneling oxide layer + n-poly-Si layer is relatively less sensitive to laser thermal damage, the influence on the passivation effect of the N region can be reduced during the laser film opening process, further increasing the process window and reducing the process difficulty. Compared with the TBC cell structure in the prior art, the present invention adopts an intrinsic amorphous silicon layer ia-Si + pa-Si layer passivation contact to replace the SiO in the existing TBC cell structure. x +p-poly-Si, avoiding the problem of serious concentric circles of silicon wafers caused by high-temperature preparation of p poly and n poly in TBC cells, thereby improving the surface passivation effect of the P region and improving the electrical performance of solar cells. Therefore, the present invention not only increases the preparation process window of back-contact solar cells, reduces the process difficulty, but also improves the surface passivation effect of the P region, so that the energy conversion efficiency Eta, open circuit voltage Uoc, short circuit current Isc, fill factor FF, and parallel resistance Rsh of solar cells can all achieve the same effect as the existing HBC battery structure.

[0013] In addition, the back contact solar cell according to the above embodiment of the present invention may also have the following additional technical features:

[0014] In some embodiments of the present invention, the non-groove area is a velvet structure; and / or the groove area is a velvet structure; and / or the second surface is a velvet structure; and / or the edge of the groove area in contact with the non-groove area is inclined.

[0015] In some embodiments of the present invention, the back-contact solar cell also includes: a first electrode layer and a second electrode layer, the first electrode layer is on one side of the isolation groove, and the first electrode layer covers the P-type doped amorphous silicon layer, and the second electrode layer is on the other side of the isolation groove, and the second electrode layer covers the P-type doped amorphous silicon layer and the N-type doped crystalline silicon layer.

[0016] In some embodiments of the present invention, the first electrode layer and the second electrode layer are transparent conductive layers, and the materials of the first electrode layer and the second electrode layer are independently selected from at least one of indium tin oxide, aluminum zinc oxide, indium hydroxide-doped indium and indium tungsten oxide.

[0017] In some embodiments of the present invention, the isolation layer includes an insulating layer, and the insulating layer is between the first intrinsic amorphous silicon layer and the N-type doped crystalline silicon layer;

[0018] Alternatively, the isolation layer includes a silicon nitride layer and a PSG layer, the PSG layer is on a surface of the N-type doped crystalline silicon layer away from the tunnel oxide layer, and the silicon nitride layer is on a surface of the PSG layer away from the N-type doped crystalline silicon layer.

[0019] In some embodiments of the present invention, the thickness of the silicon nitride layer is 50-110 nm; and / or the thickness of the PSG layer is 25-35 nm.

[0020] In some embodiments of the present invention, the back-contact solar cell also includes a passivation layer, which includes a second intrinsic amorphous silicon layer and a silicon nitride passivation layer, the second intrinsic amorphous silicon layer is arranged on the second surface, and the silicon nitride passivation layer is arranged on the surface of the second intrinsic amorphous silicon layer away from the semiconductor substrate.

[0021] In some embodiments of the present invention, the semiconductor substrate is an N-type semiconductor substrate, and the size of the groove region in the width direction is greater than the size of the non-groove region in the width direction;

[0022] Alternatively, the semiconductor substrate is a P-type semiconductor substrate, and the dimension of the groove region in the width direction is smaller than the dimension of the non-groove region in the width direction.

[0023] In some embodiments of the present invention, the tunneling oxide layer is a tunneling SiO2 layer; and / or the thickness of the tunneling oxide layer is 1 to 4 nm, preferably 1 to 1.8 nm; and / or the thickness of the N-type doped crystalline silicon layer is 30 to 250 nm, preferably 40 to 200 nm; and / or the phosphorus doping concentration in the N-type doped crystalline silicon layer is 8E19 to 5E20 cm -3 , preferably 3~9E20cm -3 ; and / or, the thickness of the first intrinsic amorphous silicon layer is 10 to 20 nm; and / or, the thickness of the P-type doped amorphous silicon layer is 5 to 45 nm, preferably 10 to 20 nm; and / or, the boron doping concentration in the P-type doped amorphous silicon layer is 10e20 cm -3 ~10e21cm -3 .

[0024] In another aspect of the present invention, the present invention provides a method for preparing a back-contact solar cell. According to an embodiment of the present invention, the method comprises:

[0025] Providing a semiconductor substrate, the semiconductor substrate having a first surface and a second surface opposite to each other, the first surface comprising a plurality of first regions and second regions arranged alternately;

[0026] forming a tunneling oxide layer, an N-type doped crystalline silicon layer and an isolation layer in sequence on the first surface;

[0027] Using laser to open the isolation layer in the second region to expose the semiconductor substrate in the second region, and the remaining tunnel oxide layer and the N-type doped crystalline silicon layer are in the first region;

[0028] sequentially forming a first intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer on a surface of the prepared intermediate member away from the second surface;

[0029] removing a portion of the first intrinsic amorphous silicon layer, the P-type doped amorphous silicon layer and the isolation layer away from one end of the second region, and the remaining first intrinsic amorphous silicon layer, the P-type doped amorphous silicon layer, the tunneling oxide layer and the N-type doped crystalline silicon layer are alternately arranged to form an alternate overlapping region;

[0030] The staggered overlapping region is grooved to form an isolation groove, wherein the isolation groove penetrates the P-type doped amorphous silicon layer and the first intrinsic amorphous silicon layer in the staggered overlapping region so as to separate the staggered overlapping region into a first staggered overlapping region and a second staggered overlapping region.

[0031] According to the method of the embodiment of the present invention, compared with the preparation process of HBC batteries in the prior art, the method adopts a tunneling oxide layer + n-poly-Si layer passivation contact to replace the intrinsic a-si:H + a-si:H(N) film layer passivation in the existing HBC battery structure. Since the tunneling oxide layer + n-poly-Si layer is relatively less sensitive to laser thermal damage, the influence on the passivation effect of the N region can be reduced during the laser film opening process, further increasing the process window and reducing the process difficulty. Compared with the preparation process of TBC batteries in the prior art, the method adopts an intrinsic amorphous silicon layer ia-Si + pa-Si layer passivation contact to replace the SiO in the existing TBC battery structure. x +p-poly-Si, avoiding the problem of serious concentric circles of silicon wafers caused by high-temperature preparation of p poly and n poly in TBC cells, thereby improving the surface passivation effect of the P region and improving the electrical performance of solar cells. Therefore, the method combines the passivation of the tunneling oxide layer + n-poly-Si layer with the passivation of the intrinsic amorphous silicon layer ia-Si + pa-Si layer, which not only increases the preparation process window of the back contact solar cell and reduces the process difficulty, but also improves the surface passivation effect of the P region, so that the energy conversion efficiency Eta, open circuit voltage Uoc, short circuit current Isc, fill factor FF, and parallel resistance Rsh of the solar cell can all achieve the same effect as the existing HBC battery structure. In addition, the method combines the texturing process with local etching, saving the previous texturing process.

[0032] In addition, the method according to the above embodiment of the present invention may also have the following technical solutions:

[0033] In some embodiments of the present invention, the method further comprises: performing alkali texturing on the semiconductor substrate after exposing the second region, so as to form a pyramid-like textured structure on the second surface and the second region.

[0034] In some embodiments of the present invention, after the pyramid-like velvet structure is formed on the second surface and the second region, a second intrinsic amorphous silicon layer and a silicon nitride passivation layer are sequentially formed on the second surface.

[0035] In some embodiments of the present invention, after grooving the staggered overlapping areas, a first electrode layer is formed on one side of the isolation groove, and the first electrode layer covers the P-type doped amorphous silicon layer, and a second electrode layer is formed on the other side of the isolation groove, and the second electrode layer covers the P-type doped amorphous silicon layer and the N-type doped crystalline silicon layer.

[0036] In some embodiments of the present invention, a first gate line is formed on a portion of the surface of the first electrode layer, and a second gate line is formed on a portion of the surface of the second electrode layer.

[0037] In some embodiments of the present invention, the tunnel oxide layer and the N-type doped crystalline silicon layer are deposited by LPCVD.

[0038] In some embodiments of the present invention, the isolation layer comprises an insulating layer;

[0039] Alternatively, the isolation layer includes a silicon nitride layer and a PSG layer, the PSG layer is formed on a surface of the N-type doped crystalline silicon layer away from the tunnel oxide layer, and the silicon nitride layer is formed on a surface of the PSG layer away from the N-type doped crystalline silicon layer.

[0040] In some embodiments of the present invention, a laser is used to remove a portion of the first intrinsic amorphous silicon layer and the P-type doped amorphous silicon layer away from one end of the second region, and the power of the laser is 6-15W.

[0041] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0043] Figure 1 A schematic structural diagram of a back-contact solar cell according to an embodiment of the present invention;

[0044] Figure 2 A schematic diagram of the structure of an intermediate component in a process of preparing a back-contact solar cell according to an embodiment of the present invention;

[0045] Figure 3 A schematic diagram of the structure of an intermediate component in a process of preparing a back-contact solar cell according to an embodiment of the present invention;

[0046] Figure 4 A schematic diagram of the structure of an intermediate component in a process of preparing a back-contact solar cell according to an embodiment of the present invention;

[0047] Figure 5 A schematic diagram of the structure of an intermediate component in a process of preparing a back-contact solar cell according to an embodiment of the present invention;

[0048] Figure 6 A schematic diagram of the structure of an intermediate component in a process of preparing a back-contact solar cell according to an embodiment of the present invention;

[0049] Figure 7 A schematic diagram of the structure of an intermediate component in a process of preparing a back-contact solar cell according to an embodiment of the present invention;

[0050] Figure 8A schematic diagram of the structure of an intermediate component in a process of preparing a back-contact solar cell according to an embodiment of the present invention;

[0051] Fig. 9 It is a schematic structural diagram of an intermediate component in the process of preparing a back-contact solar cell according to an embodiment of the present invention.

[0052] Figure annotation:

[0053] 1-silicon nitride passivation layer, 2-second intrinsic amorphous silicon layer, 3-semiconductor substrate, 3-1-first surface, 3-2-second surface, 4-tunneling oxide layer, 5-N-type doped crystalline silicon layer, 6-second electrode layer, 7-second gate line, 8-first intrinsic amorphous silicon layer, 9-P-type doped amorphous silicon layer, 10-first gate line, 11-PSG layer, 12-insulating layer, 13-isolation groove, 14-first electrode layer, B-non-groove area, C-groove area, A-interlaced overlapping area, A1-first interlaced overlapping area, A2-second interlaced overlapping area. DETAILED DESCRIPTION

[0054] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0055] In one aspect of the present invention, the present invention provides a back contact solar cell. Figure 1The back-contact solar cell comprises: a semiconductor substrate 3, the semiconductor substrate 3 has a first surface 3-1 and a second surface 3-2 opposite to each other, the first surface 3-1 comprises a plurality of non-grooved regions (B regions) and a plurality of grooved regions (C regions), the non-grooved regions (B regions) and the grooved regions (C regions) are alternately arranged on the first surface 3-1, and the distance between the non-grooved regions and the center line of the semiconductor substrate along the width direction is greater than the distance between the grooved regions and the center line of the semiconductor substrate along the width direction; a tunneling oxide layer 4 and an N-type doped crystalline silicon layer 5, the tunneling oxide layer 4 is on the non-grooved region (B region), and the N-type doped crystalline silicon layer 5 is on the surface of the tunneling oxide layer 4 away from the semiconductor substrate 3; a first intrinsic amorphous silicon layer 8 and a P-type doped The amorphous silicon layer 9, the N-type doped crystalline silicon layer 5 and the P-type doped amorphous silicon layer 9 have opposite conductivity types, the first intrinsic amorphous silicon layer 8 is on the groove area (C area) and extends on the partial surface of the N-type doped crystalline silicon layer 5 away from the tunneling oxide layer 4, and the P-type doped amorphous silicon layer 9 is on the surface of the first intrinsic amorphous silicon layer 8 away from the semiconductor substrate 3, forming an interlaced overlapping area of ​​the first intrinsic amorphous silicon layer 8 and the P-type doped amorphous silicon layer 9 and the tunneling oxide layer 4 and the P-type doped polycrystalline silicon layer; an isolation structure, the isolation structure includes an isolation layer and an isolation groove 13, the isolation layer is between the first intrinsic amorphous silicon layer 8 and the N-type doped crystalline silicon layer 5 in the interlaced overlapping area, and the isolation groove 13 runs through the P-type doped amorphous silicon layer 9 and the first intrinsic amorphous silicon layer 8 in the interlaced overlapping area. Therefore, compared with the HBC battery structure in the prior art, the present invention adopts a tunneling oxide layer + n-poly-Si layer passivation contact to replace the intrinsic a-si:H + a-si:H(N) film layer passivation in the existing HBC battery structure. Since the tunneling oxide layer + n-poly-Si layer is relatively less sensitive to laser thermal damage, the influence on the passivation effect of the N region can be reduced during the laser film opening process, further increasing the process window and reducing the process difficulty. Compared with the TBC battery structure in the prior art, the present invention adopts an intrinsic amorphous silicon layer ia-Si + pa-Si layer passivation contact to replace the SiO in the existing TBC battery structure. x +p-poly-Si, avoiding the problem of serious concentric circles of silicon wafers caused by high-temperature preparation of p poly and n poly in TBC cells, thereby improving the surface passivation effect of the P region and improving the electrical performance of solar cells. Therefore, the present application not only increases the preparation process window of back-contact solar cells and reduces the process difficulty, but also improves the surface passivation effect of the P region, so that the energy conversion efficiency Eta, open circuit voltage Uoc, short circuit current Isc, fill factor FF, and parallel resistance Rsh of solar cells can all achieve the same effect as the existing HBC battery structure.

[0056] In an embodiment of the present invention, the distance between the non-groove area and the center line of the semiconductor substrate along the width direction is greater than the distance between the groove area and the center line of the semiconductor substrate along the width direction, that is, the groove area (area C) is recessed into the non-groove area (area B), and the reason for this is that during the preparation of the back contact solar cell, the groove area (area C) is subjected to texturing etching, thereby forming a depression in the groove area (area C), so that the boundary area between the groove area (area C) and the non-groove area (area B) is discontinuous, for example, the groove area (area C) and the non-groove area (area B) are misaligned up and down. And the interface between the groove area (area C) and the non-groove area (area B) is an inclined intersection (that is, the edge of the groove area that contacts the non-groove area is inclined), and the reason for this is that a wet method is used for local texturing, which causes the laser area to be recessed and form a velvet surface.

[0057] It should be explained that the back contact solar cell includes a plurality of non-groove regions (B regions) and a plurality of groove regions (C regions), and the non-groove regions (B regions) and the groove regions (C regions) are alternately arranged on the first surface. Figure 1 Only a non-groove area (area B) and a groove area (area C) are schematically drawn.

[0058] In the embodiment of the present invention, the material of the semiconductor substrate 3 can be selected from materials such as silicon (Si) or germanium (Ge) or materials such as gallium arsenide (GaAs). It should be noted that the first surface 3-1 of the semiconductor substrate 3 refers to the backlight surface, and the second surface 3-2 of the semiconductor substrate 3 refers to the light-facing surface.

[0059] In the embodiment of the present invention, the specific type of the tunneling oxide layer 4 is not particularly limited. As a specific example, the tunneling oxide layer 4 is a tunneling SiO2 layer. According to some specific embodiments of the present invention, the thickness of the tunneling oxide layer 4 is 1 to 4 nm (for example, 1 / 1.8 / 2 / 3 / 4 nm), preferably 1 to 1.8 nm. Therefore, the thickness of the tunneling oxide layer 4 is limited to the above range, which can further ensure a better surface passivation effect and ensure the multi-sub tunneling effect.

[0060] According to some further specific embodiments of the present invention, the thickness of the N-type doped crystalline silicon layer 5 is 30 to 250 nm (for example, 30 / 50 / 100 / 150 / 200 / 250 nm), preferably 40 to 200 nm. Thus, the thickness of the N-type doped crystalline silicon layer 5 is limited within the above range, while ensuring a better field passivation effect, the poly thickness is reduced as much as possible to reduce parasitic absorption.

[0061] According to some specific embodiments of the present invention, the phosphorus doping concentration in the N-type doped crystalline silicon layer 5 is 8E19-5E20cm -3(For example, it can be 8E19 / 9E19 / 1E20 / 2E20 / 3E20 / 4E20 / 5E20cm -3 ), preferably 3 to 9E20cm -3 Thus, the phosphorus doping concentration in the N-type doped crystalline silicon layer 5 is limited to the above range, which ensures a good field passivation effect while also improving the contact performance between the subsequent metal paste and the poly.

[0062] According to some further specific embodiments of the present invention, the thickness of the first intrinsic amorphous silicon layer 8 is 10 to 20 nm, for example, it can be 10 / 11 / 12 / 13 / 14 / 15 / 16 / 17 / 18 / 19 / 20 nm. Therefore, the thickness of the first intrinsic amorphous silicon layer 8 is limited within the above range, which has a better passivation effect on the silicon-based surface.

[0063] According to some other specific embodiments of the present invention, the thickness of the P-type doped amorphous silicon layer 9 is 5 to 45 nm (for example, 5 / 10 / 20 / 30 / 40 / 45 nm), preferably 10 to 20 nm. Therefore, the thickness of the P-type doped amorphous silicon layer 9 is limited within the above range, which is beneficial to matching the subsequent laser and cleaning steps.

[0064] According to some specific embodiments of the present invention, the boron doping concentration in the P-type doped amorphous silicon layer 9 is 10e20cm -3 ~10e21cm -3 ; (for example, it can be 1 / 2 / 3 / 4 / 5 / 6 / 7 / 8 / 9 / 10e21cm -3 ), thereby limiting the boron doping concentration in the P-type doped amorphous silicon layer 9 to within the above range, while taking into account the passivation effect and having good contact performance.

[0065] According to some further specific embodiments of the present invention, the semiconductor substrate is an N-type semiconductor substrate, and the size of the groove region in the width direction is greater than the size of the non-groove region in the width direction; or, the semiconductor substrate is a P-type semiconductor substrate, and the size of the groove region in the width direction is smaller than the size of the non-groove region in the width direction. Thus, the series resistance of the back contact solar cell is further reduced, and the fill factor of the back contact solar cell is made larger.

[0066] According to some other specific embodiments of the present invention, the isolation layer includes an insulating layer 12, and the insulating layer 12 is between the first intrinsic amorphous silicon layer and the N-type doped crystalline silicon layer. In some examples, the insulating layer 12 can be a mask protection layer, and the isolation groove 13 penetrates the first intrinsic amorphous silicon layer 8 and the P-type doped amorphous silicon layer 9 to the mask protection layer. The mask protection layer serves as a laser energy absorption layer, which has the function of reducing the influence of the laser film opening process on the passivation effect of the doping area corresponding to the non-groove area, and also has the function of providing a hydrogen source to further passivate the polysilicon and the substrate, thereby improving the passivation effect and protecting the N-type doped crystalline silicon layer 5 from being corroded by alkali during the texturing process. It should be noted that the isolation groove may penetrate the above-mentioned insulating layer 12, or may not penetrate the above-mentioned insulating layer 12.

[0067] According to some other specific embodiments of the present invention, the isolation layer includes an insulating layer 12 (e.g., a silicon nitride layer) and a PSG layer 11, the PSG layer 11 is on the surface of the N-type doped crystalline silicon layer away from the tunneling oxide layer, and the insulating layer 12 is on the surface of the PSG layer 11 away from the N-type doped crystalline silicon layer. In some examples, the isolation layer includes at least one of a silicon nitride layer, an aluminum nitride layer, a silicon oxide layer, and a PSG layer. It should be noted that the PSG layer 11 is naturally formed under the action of oxygen during the phosphorus doping process of the N-type doped crystalline silicon layer 5, has a thickness of 25 to 35 nm, and is composed of phosphorus-doped silicon oxide. Similarly, the isolation groove may penetrate the insulating layer 12 and the PSG layer 11, or may not penetrate the insulating layer 12 and the PSG layer 11.

[0068] In the embodiments of the present invention, the specific type of the mask protection layer is not particularly limited. As some specific examples, the mask protection layer can be a SiNx layer. In some examples, the thickness of the mask protection layer can be 50 to 110 nm, thereby further ensuring the above effect of the mask protection layer. In some examples, the refractive index of the mask protection layer can be 1.8 to 2.6%, preferably 2.2 to 2.4%, thereby further ensuring the above effect of the mask protection layer.

[0069] Further, see Attachment Figure 1 The back contact solar cell further includes: a first electrode layer 14 and a second electrode layer 6, wherein the first electrode layer 14 is on one side of the isolation groove and covers the P-type doped amorphous silicon layer, and the second electrode layer 6 is on the other side of the isolation groove and covers the P-type doped amorphous silicon layer and the N-type doped crystalline silicon layer. The first electrode layer 14 enhances the conductivity between the P-type doped amorphous silicon layer 9 and the first gate line 10, and the second electrode layer 6 enhances the conductivity between the N-type doped crystalline silicon layer 5 and the second gate line 7.

[0070] In the embodiment of the present invention, the first electrode layer 14 and the second electrode layer 6 are transparent conductive layers. The specific materials of the first electrode layer 14 and the second electrode layer 6 are not particularly limited. As some specific examples, the materials of the first electrode layer 14 and the second electrode layer 6 are independently selected from at least one of indium tin oxide, aluminum zinc oxide, indium hydroxide-doped indium and indium tungsten oxide. In some examples, the thickness of the first electrode layer 14 and the second electrode layer 6 can be independently 50 to 110 nm.

[0071] Further, see Attachment Figure 1 , the back contact solar cell also includes: a passivation layer, the passivation layer includes a second intrinsic amorphous silicon layer 2 and a silicon nitride passivation layer 1, the second intrinsic amorphous silicon layer 2 is arranged on the second surface 3-2, and the silicon nitride passivation layer 1 is arranged on the surface of the oxide passivation layer away from the semiconductor substrate 3. The silicon nitride passivation layer 1 has the function of being a reflection prevention film and a protective film, and also has the function of being a passivation film that inhibits the recombination of photocarriers. The second intrinsic amorphous silicon layer 2 has the function of inhibiting the recombination of photocarriers at the bonding interface with the second surface 3-2. In some examples, at least part of the second surface 3-2 is provided with a velvet structure, that is, at least part of the second surface 3-2 is provided with a lot of pyramids, thereby increasing the light receiving surface of the second surface 3-2. In some other examples, the non-groove area is a velvet structure; and / or, the groove area is a velvet structure, and the velvet structure on the non-groove area and the groove area is formed in the cleaning step of the preparation process of the back contact solar cell.

[0072] In another aspect of the present invention, the present invention provides a method for preparing a back-contact solar cell. According to an embodiment of the present invention, the method comprises:

[0073] S100: Provide semiconductor substrate

[0074] In this step, a semiconductor substrate 3 is provided. The semiconductor substrate 3 has a first surface 3-1 and a second surface 3-2 opposite to each other. The first surface includes a plurality of first regions and second regions arranged alternately. Figure 2 As shown. The first surface 3-1 of the semiconductor substrate 3 refers to the backlight surface, and the second surface 3-2 of the semiconductor substrate 3 refers to the light-facing surface. In the embodiment of the present invention, the material of the semiconductor substrate 3 can be selected from materials such as silicon (Si) or germanium (Ge) or materials such as gallium arsenide (GaAs).

[0075] In order to ensure the cleanliness of the semiconductor substrate 3, in some examples, the semiconductor substrate 3 can be polished and cleaned. Specifically, the semiconductor substrate 3 is placed in a tank polishing and cleaning machine for polishing, the cutting damage layer on the surface of the semiconductor substrate 3 is removed, and the double-sided microscopic morphology preparation is completed. The size of the polishing block is controlled by controlling the concentration, temperature and cleaning time of the cleaning solution (generally an alkaline solution, such as potassium hydroxide / sodium hydroxide solution).

[0076] S200: forming a tunneling oxide layer, an N-type doped crystalline silicon layer and an isolation layer in sequence on the first surface

[0077] In this step, low pressure chemical vapor deposition furnaces such as LPCVD, PECVD, PVD, PEALD, etc. can be used to prepare the tunneling oxide layer 4 and the intrinsic or in-situ doped poly Si. Preferably, LPCVD is used to deposit the back tunneling oxide layer 4 and the polysilicon (poly) layer at a high temperature of 600-800°C. The deposition of the intrinsic a-si:H+a-si:H(N) film layer in the existing HBC battery structure mostly uses expensive CVD equipment, while the present application uses inexpensive LPCVD equipment to replace the expensive CVD equipment, effectively reducing the equipment investment cost.

[0078] Then, the intermediate after the deposition of the polysilicon (poly) layer is placed in a tubular diffusion furnace, and a phosphorus-containing compound (such as phosphorus oxychloride) is introduced to convert the polysilicon into an N-type doped crystalline silicon layer 5 at a high temperature of 750-880°C. It should be noted that during the phosphorus doping process of poly-Si, a PSG layer 11 is naturally formed under the action of oxygen, and its thickness is about 25 to 35 nm. The PSG layer 11 has the effect of enhancing the mask. In some examples, the phosphorus doping concentration in the N-type doped crystalline silicon layer 5 is 8E19 to 5E20 cm -3 (For example, it can be 8E19 / 9E19 / 1E20 / 2E20 / 3E20 / 4E20 / 5E20cm -3 ), preferably 3 to 9E20cm -3 In some examples, the thickness of the N-type doped crystalline silicon layer 5 is 30 to 250 nm, preferably 40 to 200 nm. In some examples, the thickness of the tunnel oxide layer 4 is 1 to 4 nm, preferably 1 to 1.8 nm.

[0079] In the embodiment of the present invention, the specific type of the tunneling oxide layer 4 is not particularly limited. For example, the tunneling oxide layer 4 is a tunneling SiO 2 layer.

[0080] Finally, an insulating layer is formed on the surface of the PSG layer. In some examples, the insulating layer can be a mask protection layer. The mask protection layer is deposited at a temperature of 400-600°C using PECVD equipment. The mask protection layer acts as a laser energy absorption layer, which has the function of reducing the effect of the laser film opening process on the passivation effect of the N region, and also has the function of providing a hydrogen source to further passivate the polysilicon and the substrate, thereby improving the passivation effect and protecting the N-type doped crystalline silicon layer 5 from being corroded by alkali during the texturing process. The structure of the intermediate component prepared in S200 is shown in the attached figure. Figure 3 shown.

[0081] In the embodiment of the present invention, the specific type of the mask protection layer is not particularly limited. For example, the mask protection layer can be SiN x In some examples, the thickness of the mask protection layer can be 50-110 nm, thereby further ensuring the above effect of the mask protection layer 12. In some examples, the refractive index of the mask protection layer can be 1.8-2.6%, preferably 2.2-2.4%, thereby further ensuring the above effect of the mask protection layer.

[0082] S300: Use laser to open the isolation layer in the second area

[0083] In this step, the isolation layer in the second region is opened by laser to expose the semiconductor substrate in the second region, and the remaining tunnel oxide layer and the N-type doped crystalline silicon layer are in the first region. The structure is as shown in the attached figure. Figure 4 As shown. Since the tunneling oxide layer 4+n-poly-Si layer passivation contact is used in the present application to replace the intrinsic a-si:H+a-si:H(N) film layer passivation in the existing HBC battery structure, and the tunneling oxide layer 4+n-poly-Si layer is relatively less sensitive to laser thermal damage, the laser process can be directly used to open the film in this step. The laser film opening process can reduce the impact on the passivation effect of the N region, further increase the process window, and reduce the process difficulty. In the existing HBC battery structure, this step generally uses a large number of mask and de-mask technologies to form a pattern, which has high production costs and great difficulty in process control. The present invention saves the steps of mask and de-mask in the process of laser film opening in this step, thereby improving production efficiency.

[0084] S400: forming a first intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer in sequence on a surface of the intermediate member prepared in step S300 away from the second surface

[0085] In this step, a first intrinsic amorphous silicon layer 8 and a P-type doped amorphous silicon layer 9 are sequentially formed on the surface of the intermediate member prepared in step S300 away from the second surface 3-2 by using a CVD device at 220-300°C. The present application adopts an intrinsic amorphous silicon layer ia-Si + pa-Si layer passivation contact to replace the SiO2 in the existing TBC battery structure. x +p-poly-Si, improves the surface passivation effect of the P region, thereby improving the electrical performance of the solar cell. In some examples, the thickness of the first intrinsic amorphous silicon layer 8 is 10 to 20 nm. In some examples, the thickness of the P-type doped amorphous silicon layer 9 is 5 to 45 nm, preferably 10 to 20 nm.

[0086] According to a specific embodiment of the present invention, step S400 further includes: forming a second intrinsic amorphous silicon layer and a silicon nitride passivation layer 1 on the second surface 3-2 in sequence, and the prepared intermediate member is as shown in the attached figure. Figure 6 The silicon nitride passivation layer 1 has the function of an anti-reflection film and a protective film, and also has the function of a passivation film for suppressing photocarrier recombination. The second intrinsic amorphous silicon layer 2 has the function of suppressing photocarrier recombination at the bonding interface with the second surface 3-2.

[0087] Furthermore, between steps S300 and S400, the method further includes: performing alkali texturing on the surface of the intermediate component prepared in step S300, so as to form a pyramid-like textured surface structure on the second surface and the second region, and removing the mask protection layer, tunnel oxide layer 4 or N-type doped crystalline silicon layer 5 remaining in the second region after laser. The cleaning solution may be an acid solution, such as hydrofluoric acid. Specifically, the intermediate piece after step S300 is placed in a hydrofluoric acid tank-texturing tank-SC1 cleaning tank-CP rounding tank-SC2 cleaning tank-pickling tank in sequence. The function of the hydrofluoric acid tank is to remove the mask protection layer 12, tunneling oxide layer 4 or N-type doped crystalline silicon layer 5 remaining in the second area after the laser. The function of the texturing tank is to complete the texturing in the laser area and the second surface 3-2 area at the same time. The function of the SC1 cleaning tank is mainly to remove contamination and chemical residues on the surface of the intermediate piece. The function of the CP rounding tank is to round the top and bottom of the pyramid to prevent epitaxial growth of amorphous silicon deposition. The function of the SC2 cleaning tank is to remove metal residues on the silicon wafer. The function of the pickling tank is to complete chemical passivation of the intermediate piece and form a hydrophobic structure. Therefore, this step not only completes the removal of residues in the second area after the laser, but also completes the texturing of the second area, making the laser area concave and forming a velvet surface, and also completes the texturing of the second surface 3-2, as shown in the attached figure. Figure 5 The second area after texturing is the groove area, and the first area is the non-groove area.

[0088] In some examples, the preparation of the silicon nitride passivation layer 1 can be the preparation of a multi-layer silicon nitride passivation layer 1. For example, the multi-layer silicon nitride passivation layer 1 can be designed to have a first layer thickness of 20±3nm and a refractive index of 2.4%, a second layer thickness of 15±5nm and a refractive index of 2.2%, a third layer thickness of 40±5nm and a refractive index of 2.0%; and a fourth sacrificial layer thickness of 80±10nm and a refractive index of 2.4%. The role of the fourth sacrificial layer is that the intermediate component prepared in step S300 will inevitably consume the above-mentioned sacrificial layer during the alkali texturing process, and the total thickness of the remaining first layer, second layer and third layer is the thickness of the silicon nitride passivation layer 1 finally formed.

[0089] S500: removing a portion of the first intrinsic amorphous silicon layer, the P-type doped amorphous silicon layer and the isolation layer away from one end of the second region

[0090] In this step, part of the first intrinsic amorphous silicon layer, the P-type doped amorphous silicon layer and the isolation layer away from one end of the second region are removed, and the remaining first intrinsic amorphous silicon layer, the P-type doped amorphous silicon layer, the tunneling oxide layer and the N-type doped crystalline silicon layer are alternately arranged to form an alternating overlapping region.

[0091] Specifically, a laser is first used to remove a portion of the first intrinsic amorphous silicon layer and the P-type doped amorphous silicon layer away from one end of the second region to expose the isolation layer. In some examples, this can be accomplished using a 532nm green nanosecond picosecond or a 355nm ultraviolet nanosecond picosecond laser. In some examples, the power of the laser is 6-15W. An acid solution (such as an HF solution) is then used to remove the exposed isolation layer to expose the remaining N-type doped crystalline silicon layer 5. The remaining first intrinsic amorphous silicon layer 8, the P-type doped amorphous silicon layer 9 are staggered with the tunneling oxide layer 4, and the N-type doped crystalline silicon layer 5 to form an staggered overlapping region (region A), in which the structure of the intermediate member is as shown in the attached figure. Figure 7 The purpose of step S500 is to expose a portion of the N-type doped crystalline silicon layer 5 in the grooved area, so as to facilitate the subsequent steps of preparing the second electrode layer and the second gate line.

[0092] S600: Slotting the overlapping areas

[0093] In this step, the laser ablation technology is used to groove the staggered overlapping area (area A) to expose part of the isolation layer to form an isolation groove 13. The isolation groove 13 divides the stacking area (area A) into a first staggered overlapping area (area A1) and a second staggered overlapping area (area A2). The structure of the intermediate member is as shown in the attached figure. Fig. 9 In some examples, the width of the isolation trench 13 is 20-200 μm, preferably 80-120 μm.

[0094] Furthermore, after the staggered overlapping regions are grooved, the method further includes: forming a first electrode layer on one side of the isolation groove, and the first electrode layer covers the P-type doped amorphous silicon layer, and forming a second electrode layer on the other side of the isolation groove, and the second electrode layer covers the P-type doped amorphous silicon layer and the N-type doped crystalline silicon layer. The first electrode layer is used to enhance the conductivity between the P-type doped amorphous silicon layer 9 and the first gate line 10, and the second electrode layer is used to enhance the conductivity between the N-type doped crystalline silicon layer 5 and the second gate line 7. In some embodiments, an electrode layer may also be first formed on the surface of the P-type doped amorphous silicon layer (the structure of the intermediate member is as shown in the attached figure). Figure 8 ), and then grooves are cut in the staggered overlapping areas.

[0095] In an embodiment of the present invention, the first electrode layer and the second electrode layer are transparent conductive layers. The specific materials of the first electrode layer and the second electrode layer are not particularly limited. As some specific examples, the materials of the first electrode layer and the second electrode layer are independently selected from at least one of indium tin oxide, aluminum zinc oxide, indium hydroxide-doped indium and indium tungsten oxide. In some examples, the thickness of the first electrode layer and the second electrode layer can be independently 50 to 110 nm.

[0096] Furthermore, the method further includes: forming a first gate line 10 on a partial surface of the first electrode layer 14, and forming a second gate line 7 on a partial surface of the second electrode layer 6. Specifically, the first gate line can be formed on a partial surface of the first electrode layer, and the second gate line can be formed on a partial surface of the second electrode layer by screen printing, inkjet printing, laser transfer, chemical plating, electroplating or PVD.

[0097] According to the method of the embodiment of the present invention, compared with the preparation process of HBC batteries in the prior art, this method uses a tunneling oxide layer + n-poly-Si layer passivation contact to replace the intrinsic a-si:H + a-si:H(N) film layer passivation in the existing HBC battery structure, and the tunneling oxide layer + n-poly-Si layer is relatively less sensitive to laser thermal damage. Therefore, in step S300, a laser process can be directly used to open the film. The laser film opening process can reduce the impact on the passivation effect of the N region, further increase the process window, and reduce the process difficulty. In the existing HBC battery structure, this step generally uses a large number of masks and demasking technologies to form patterns, which has high production costs and great process control difficulties. The present application directly uses lasers to form the formation area of ​​the first doped region. Compared with the preparation process of TBC batteries in the prior art, this method uses an intrinsic amorphous silicon layer ia-Si + pa-Si layer passivation contact to replace the SiO in the existing TBC battery structure. x+p-poly-Si, avoiding the problem of serious concentric circles of silicon wafers caused by high-temperature preparation of p poly and n poly in TBC cells, thereby improving the surface passivation effect of the P region and improving the electrical performance of solar cells. Therefore, the method combines the passivation of the tunneling oxide layer + n-poly-Si layer with the passivation of the intrinsic amorphous silicon layer ia-Si + pa-Si layer, which not only increases the preparation process window of the back contact solar cell, reduces the process difficulty, but also improves the surface passivation effect of the P region, so that the energy conversion efficiency Eta, open circuit voltage Uoc, short circuit current Isc, fill factor FF, and parallel resistance Rsh of the solar cell can all achieve the same effect as the existing HBC battery structure. In addition, in the deposition process of the tunneling oxide layer and the N-type doped crystalline silicon layer n-poly-Si, the expensive CVD equipment is replaced by the inexpensive LPCVD equipment, which effectively reduces the equipment investment cost. In addition, the method combines the texturing process with local etching, saving the previous texturing process.

[0098] The embodiments of the present invention are described in detail below. It should be noted that the embodiments described below are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0099] Example 1

[0100] This embodiment provides a solar cell, and the preparation method thereof is as follows:

[0101] 1) Provide an N-type 1.3Ωcm 166*166 silicon wafer with a thickness of 165μm.

[0102] 2) Polishing and cleaning: Put the above silicon wafer into a tank-type alkaline polishing machine for polishing and cleaning. The working volume of the tank of the cleaning machine is 360L. First, pre-clean the silicon wafer to remove organic and other contamination generated during the silicon wafer cutting and transportation process; this embodiment uses standard RCA cleaning liquid for cleaning to remove particles on the silicon wafer, and can oxidize and remove a small amount of organic matter and metal atomic pollution such as Au, Ag, Cu, Ni, Cd, Zn, Ca, Cr, etc. on the surface; after washing the residual chemicals with water, perform alkaline polishing treatment. The alkaline polishing formula is 5.97%wt KOH, the temperature is 80°C, and the alkaline polishing treatment time is 300s to remove damage and polish. Then perform SC1 cleaning, ozone cleaning, and finally acid washing and dehydration to complete polishing and cleaning.

[0103] 3) The polished silicon wafer is sent into a low-pressure vapor deposition LPCVD, and at a temperature of 640°C, a 1.4nm thick tunneling SiO2 and a 50nm thick intrinsic polysilicon poly Si are deposited.

[0104] 4) The intermediate after the deposition of the polycrystalline silicon (poly) layer is placed in a tubular diffusion furnace, and phosphorus oxychloride is introduced to dope the poly Si region with phosphorus at 870°C and complete the crystallization of the poly, with a doping concentration of 5E20cm -3 During this process, a PSG layer with a thickness of about 30 nm was formed.

[0105] 5) A SiNx single layer film with a thickness of 80 nm and a refractive index of 2.4% is deposited on the surface of the N-type doped crystalline silicon layer n-poly-Si by PECVD, and the SiNx single layer film is used as a mask layer.

[0106] 6) Use 532nm green nanosecond light and 15W laser power to open the SiNx film in the P area to expose the backlight side of the silicon wafer.

[0107] 7) Place the silicon wafer after laser treatment into the texturing machine. The working volume of the machine tank is 360L. Its main process and functions are as follows: ① The first functional tank uses 1%wt HF at a constant temperature of 25℃ to remove the residue. ② After cleaning, the silicon wafer enters the next texturing tank. The texturing liquid is 3.29%wt KOH solution, the texturing temperature is 82℃, and the texturing time is 570s. Thus, the texturing treatment of the front and back laser areas is completed. ③ Then perform high-efficiency SC1 cleaning. The cleaning liquid is NH4OH-H2O2-H2O. The volume ratio of the three is 1:1:5. The cleaning temperature is 65℃ and the cleaning time is 300s. ④ Use 50ppm O3 water plus HF for pyramid smoothing treatment. The hydrofluoric acid concentration is 0.31%wt. ⑤ Perform SC2 metal residue removal cleaning. The cleaning liquid is HCL-H2O2-H2O. The volume ratio of the three is 1:1:5. The cleaning temperature is 65℃ and the cleaning time is 200s. ⑥Finally, the surface is cleaned with 5% wt hydrofluoric acid to complete the texturing.

[0108] 8) Using CVD equipment at 250°C, 7nm thick a-si:H (i.e., the first intrinsic amorphous silicon layer ia-Si) and 15nm thick a-si:H(P) (i.e., the P-type doped amorphous silicon layer pa-Si) were sequentially deposited on the back side. Then, by flipping, 12nm thick a-si:H and 160nm thick SiNx were sequentially deposited on the front side, wherein the SiNx sacrificial layer was 80nm and the refractive index of the SiNx sacrificial layer was 2.4%.

[0109] 9) Using nanosecond laser to open one end of the P-type doped amorphous silicon layer pa-Si away from the P-doped region to expose the SiNx mask layer.

[0110] 10) The SiNx mask layer exposed in step 9) is cleaned with 8% wt hydrofluoric acid, thereby removing the SiNx mask layer and the PSG layer in the grooved area to expose the remaining portion of the N-type doped crystalline silicon layer n-poly-Si. At the same time, after the hydrofluoric acid treatment, the SiNx sacrificial layer on the front side is removed, and the thickness of the SiNx on the front side is retained to 80 nm.

[0111] 11) Deposit an ITO (indium tin oxide) layer on the back with a thickness of 50 nm.

[0112] 12) Use ultraviolet picosecond laser to open grooves to expose the SiNx mask layer and form isolation grooves to insulate the N region and P region to prevent leakage caused by the interconnection of the N / P regions. The insulation resistance of the test isolation region is >2MΩ, and the laser width is 100μm.

[0113] 13) The back metallization electrode is prepared by using metal silver through screen printing technology.

[0114] Example 2

[0115] This embodiment provides a solar cell. The difference between this embodiment and embodiment 1 is that:

[0116] 3) The polished silicon wafer is sent into a low-pressure vapor deposition LPCVD, and at a temperature of 640°C, a 1.4nm thick tunneling SiO2 and a 70nm thick intrinsic polysilicon poly Si are deposited.

[0117] The other steps are the same as those in Example 1.

[0118] Example 3

[0119] This embodiment provides a solar cell. The difference between this embodiment and embodiment 1 is that:

[0120] 3) The polished silicon wafer is sent into a low-pressure vapor deposition LPCVD, and at a temperature of 640°C, a 1.4nm thick tunneling SiO2 and a 90nm thick intrinsic polysilicon poly Si are deposited.

[0121] The other steps are the same as those in Example 1.

[0122] Example 4

[0123] This embodiment provides a solar cell. The difference between this embodiment and Embodiment 1 is that:

[0124] 6) Use 532nm green nanosecond light and 12W laser power to open the SiNx film in the P area to expose the backlight side of the silicon wafer.

[0125] Example 5

[0126] This embodiment provides a solar cell. The difference between this embodiment and Embodiment 1 is that:

[0127] 6) Use 532nm green nanosecond light and 10W laser power to open the SiNx film in the P area to expose the backlight side of the silicon wafer.

[0128] Example 6

[0129] This embodiment provides a solar cell. The difference between this embodiment and Embodiment 1 is that:

[0130] 6) Use 532nm green nanosecond light and 8W laser power to open the SiNx film in the P area to expose the backlight side of the silicon wafer.

[0131] Example 7

[0132] This embodiment provides a solar cell. The difference between this embodiment and Embodiment 1 is that:

[0133] 6) Use 532nm green nanosecond light and 6W laser power to open the SiNx film in the P area to expose the backlight side of the silicon wafer.

[0134] Comparative Example 1

[0135] This comparative example provides a method for preparing a HBC solar cell, comprising the following steps:

[0136] 1) Provide an N-type 1.3Ωcm 166*166 silicon wafer with a thickness of 165μm.

[0137] 2) Polishing and cleaning: Put the above silicon wafer into a tank-type alkaline polishing machine for polishing and cleaning. The working volume of the tank of the cleaning machine is 360L. First, pre-clean the silicon wafer to remove organic and other contamination generated during the silicon wafer cutting and transportation process; this embodiment uses standard RCA cleaning liquid for cleaning to remove particles on the silicon wafer, and can oxidize and remove a small amount of organic matter and metal atomic pollution such as Au, Ag, Cu, Ni, Cd, Zn, Ca, Cr, etc. on the surface; after washing the residual chemicals with water, perform alkaline polishing treatment. The alkaline polishing formula is 5.97%wt KOH, the temperature is 80°C, and the alkaline polishing treatment time is 300s to remove damage and polish. Then perform SC1 cleaning, ozone cleaning, and finally acid washing and dehydration to complete polishing and cleaning.

[0138] 3) Using PECVD equipment, a layer of SiNx mask with a thickness of 200nm and a refractive index of 2.4% is deposited on the back of the silicon wafer;

[0139] 4) In the tank cleaning machine, first put the silicon wafer into the HF tank, the mass concentration of the HF solution is 1%, and it is treated at room temperature for 30 seconds to remove the SiNx plated on the side and front of the battery. Then it enters the alkaline tank for texturing treatment. The texturing solution is a KOH+texturing additive solution with a mass concentration of 2.5%. The texturing temperature is 82°C and the texturing time is 780 seconds. Then it enters the HNO3 / HF tank for velvet smoothing treatment. The solution volume ratio HNO3:HF=1:100, the total etching amount is 1.8g, the reflectivity of the front side is 12%, and the velvet pyramid size is 4um. The large velvet microstructure, finally treated in the 8%wt HF tank at room temperature for 300 seconds, completely remove the SiNx mask remaining on the back.

[0140] 5) In a CVD device, 15 nm of intrinsic a-si:H, 25 nm of phosphorus-doped a-si:H(N), 200 nm of SiNx layer and 15 nm of intrinsic a-si:H are sequentially deposited on the back of the silicon wafer.

[0141] 6) Use a 532 laser with a power of 6W to groove the outermost layer of intrinsic a-si:H on the back side to create a P+ area, which is the area for deposition of intrinsic a-si:H and a-si:H(P) in subsequent steps. The grooved P+ area has the same width as the ungrooved N+ area along the arrangement direction.

[0142] 7) In a tank cleaning machine, the silicon wafer is first placed in an HF tank with an HF solution concentration of 8% and a treatment time of 200 seconds to remove SiNx from the laser grooved area; then it enters an alkaline tank for etching with a solution of 0.5wt% KOH plus 0.15wt% H2O2 solution at a solution temperature of 25°C and an etching time of 400 seconds to remove the residual intrinsic a-si:H and phosphorus-doped a-si:H(N) layers.

[0143] 8) In the CVD equipment, the back side of the silicon wafer is coated with 15nm thick intrinsic a-si:H and 25nm thick B-doped a-si:H(P) in sequence.

[0144] 9) In the CVD equipment, an intrinsic a-si:H layer with a thickness of 15 nm and a SiNx layer with a thickness of 85 nm are deposited on the front side of the silicon wafer in sequence.

[0145] 10) Use laser to etch the intrinsic a-si:H and a-si:H(P) in the back N+ region.

[0146] 11) The SiNx layer leaking out of the N+ region after laser treatment was removed using HF solution with a mass concentration of 8% for 400 seconds to expose the phosphorus-doped a-si:H(N) layer.

[0147] 12) Deposit an ITO (indium tin oxide) layer on the back with a thickness of 80nm.

[0148] 13) Use 355nm ultraviolet picosecond laser to open grooves to expose the SiNx mask layer and form isolation grooves to insulate the N region and P region to prevent leakage caused by the interconnection of the N / P regions. The insulation resistance of the test isolation region is >10MΩ, and the laser width is 100μm.

[0149] 14) Using metal silver through screen printing technology, the back metallization electrode is prepared, and then cured and annealed.

[0150] Comparative Example 2

[0151] The difference between Comparative Example 2 and Comparative Example 1 is that:

[0152] 6) Use 532 laser with a power of 8W to groove the outermost layer of intrinsic a-si:H on the back side to create a P+ area, which is the area for the deposition of intrinsic a-si:H and a-si:H(P) in subsequent steps.

[0153] Comparative Example 3

[0154] The difference between Comparative Example 3 and Comparative Example 1 is only that:

[0155] 6) Use a 532 laser with a power of 10W to groove the outermost layer of intrinsic a-si:H on the back side to create a P+ area, which is the area for the deposition of intrinsic a-si:H and a-si:H(P) in subsequent steps.

[0156] Comparative Example 4

[0157] The difference between Comparative Example 4 and Comparative Example 1 is only that:

[0158] 6) Use a 532 laser with a power of 12W to groove the outermost layer of intrinsic a-si:H on the back side to create a P+ area, which is the area for the deposition of intrinsic a-si:H and a-si:H(P) in subsequent steps.

[0159] The energy conversion efficiency Eta, open circuit voltage Uoc (volt, V), short circuit current Isc (ampere, A), fill factor FF (%), and series resistance Rsh (ohm, Ω) of the solar cells prepared in Examples 1-3 and Comparative Example 1 were performance tested, and the results are shown in Table 1.

[0160] Table 1

[0161]

[0162]

[0163] It can be seen that the mask and mask removal techniques are used multiple times in comparative examples 1-4 to form patterning, which has high production costs and great difficulty in process control, while in Example 1-7, the tunneling SiO2 layer + N-type crystalline silicon layer n-poly-Si passivation contact is used to replace the intrinsic a-si:H + a-si:H(N) film layer passivation in comparative example 1-4. Since the tunneling SiO2 layer + N-type crystalline silicon layer n-poly-Si in Example 1-7 is relatively less sensitive to laser thermal damage, the laser process can be directly used to open the film in this step, and there is no need to use the mask and mask removal techniques multiple times to form patterning. Specifically, comparative example 1-2 produces higher efficiency at lower laser power, but at higher laser power, comparative example 3-4 shows a significant decrease in efficiency. It can be seen that the tunneling SiO2 layer + N-type crystalline silicon layer n-poly-Si is relatively less sensitive to laser thermal damage, and the influence on the passivation effect of the corresponding doping area in the first region can be reduced during the laser film opening process. Examples 1-7 all have high efficiency at laser powers of 6-15 W, indicating that the preparation process window of the present invention is relatively wide. It can also be seen from Table 1 that compared with Comparative Examples 1-2, the energy conversion efficiency Eta, open circuit voltage Uoc, and fill factor FF of Examples 1-7 all reach levels comparable to those of Comparative Examples 1-2.

[0164] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0165] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A back contact solar cell, characterized in that: include: A semiconductor substrate, wherein the semiconductor substrate has a first surface and a second surface opposite to each other, the first surface includes a plurality of groove areas and a plurality of non-groove areas, the non-groove areas and the groove areas are alternately arranged on the first surface, the non-groove areas are polished surfaces, the groove areas are velvet surfaces, the polished surface includes a block-shaped structure, and the interface between the groove areas and the non-groove areas is obliquely intersected; A tunneling oxide layer and an N-type doped polysilicon layer, wherein the tunneling oxide layer is on the non-recessed area, and the N-type doped polysilicon layer is on a surface of the tunneling oxide layer away from the semiconductor substrate; A first intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer, the N-type doped polycrystalline silicon layer has a conductivity type opposite to that of the P-type doped amorphous silicon layer, the first intrinsic amorphous silicon layer is on the groove region and extends on a portion of the surface of the N-type doped polycrystalline silicon layer away from the tunneling oxide layer, and the P-type doped amorphous silicon layer is on a surface of the first intrinsic amorphous silicon layer away from the semiconductor substrate, forming an interlaced overlapping region of the first intrinsic amorphous silicon layer and the P-type doped amorphous silicon layer, the tunneling oxide layer, and the N-type doped polycrystalline silicon layer; An isolation structure, wherein the isolation structure comprises an isolation layer and an isolation groove, wherein the isolation layer is between the first intrinsic amorphous silicon layer and the N-type doped polysilicon layer in the staggered overlapping area, and the isolation groove penetrates the P-type doped amorphous silicon layer and the first intrinsic amorphous silicon layer in the staggered overlapping area.

2. The back contact solar cell according to claim 1, characterized in that: The second surface is a suede structure; And / or, the edge of the groove area that contacts the non-groove area is inclined.

3. The back contact solar cell according to claim 1, characterized in that: Also includes: A first electrode layer and a second electrode layer, wherein the first electrode layer is on one side of the isolation groove and covers the P-type doped amorphous silicon layer, and the second electrode layer is on the other side of the isolation groove and covers the P-type doped amorphous silicon layer and the N-type doped polysilicon layer.

4. The back contact solar cell according to claim 3, characterized in that: The first electrode layer and the second electrode layer are transparent conductive layers, and the materials of the first electrode layer and the second electrode layer are independently selected from at least one of indium tin oxide, aluminum zinc oxide, indium hydroxide-doped indium and indium tungsten oxide.

5. The back contact solar cell according to claim 1, characterized in that: The isolation layer comprises an insulating layer, and the insulating layer is between the first intrinsic amorphous silicon layer and the N-type doped polysilicon layer; Alternatively, the isolation layer includes a silicon nitride layer and a PSG layer, the PSG layer is on a surface of the N-type doped polysilicon layer away from the tunnel oxide layer, and the silicon nitride layer is on a surface of the PSG layer away from the N-type doped polysilicon layer.

6. The back contact solar cell according to claim 5, characterized in that: The thickness of the silicon nitride layer is 50-110 nm; and / or The thickness of the PSG layer is 25-35 nm.

7. The back contact solar cell according to claim 1, characterized in that: It also includes a passivation layer, which includes a second intrinsic amorphous silicon layer and a silicon nitride passivation layer. The second intrinsic amorphous silicon layer is arranged on the second surface, and the silicon nitride passivation layer is arranged on a surface of the second intrinsic amorphous silicon layer away from the semiconductor substrate.

8. The back contact solar cell according to claim 1, characterized in that: The semiconductor substrate is an N-type semiconductor substrate, and the size of the groove area in the width direction is greater than the size of the non-groove area in the width direction; Alternatively, the semiconductor substrate is a P-type semiconductor substrate, and the dimension of the groove region in the width direction is smaller than the dimension of the non-groove region in the width direction.

9. The back contact solar cell according to any one of claims 1 to 8, characterized in that: The tunneling oxide layer is a tunneling SiO2 layer; and / or The thickness of the tunnel oxide layer is 1-4 nm; and / or The thickness of the N-type doped polysilicon layer is 30-250 nm; and / or The phosphorus doping concentration in the N-type doped polysilicon layer is 8E19~5E20cm-3; and / or The thickness of the first intrinsic amorphous silicon layer is 10-20 nm; and / or The thickness of the P-type doped amorphous silicon layer is 5-45 nm; and / or The boron doping concentration in the P-type doped amorphous silicon layer is 10e20cm-3~10e21cm-3.

10. The back contact solar cell according to any one of claims 1 to 8, characterized in that: The thickness of the tunnel oxide layer is 1-1.8 nm; and / or The thickness of the N-type doped polysilicon layer is 40-200 nm; and / or The phosphorus doping concentration in the N-type doped polysilicon layer is 3-9E20 cm-3; and / or The thickness of the P-type doped amorphous silicon layer is 10-20 nm.

11. A method for preparing a back contact solar cell, characterized in that: include: A semiconductor substrate is provided, wherein the semiconductor substrate has a first surface and a second surface opposite to each other, wherein the first surface includes a plurality of first regions and second regions arranged alternately, wherein the first region is a polishing region, and wherein the polishing region includes a block-shaped structure; forming a tunneling oxide layer, an N-type doped polysilicon layer and an isolation layer in sequence on the first surface; The isolation layer in the second area is opened by laser to expose the semiconductor substrate in the second area, and the remaining tunnel oxide layer and the N-type doped polysilicon layer are in the first area. The second area is textured to form a groove texture area, and the interface between the groove texture area and the polishing area is obliquely connected; sequentially forming a first intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer on a surface of the prepared intermediate member away from the second surface; removing a portion of the first intrinsic amorphous silicon layer, the P-type doped amorphous silicon layer and the isolation layer away from one end of the second region, and the remaining first intrinsic amorphous silicon layer, the P-type doped amorphous silicon layer, the tunneling oxide layer and the N-type doped polysilicon layer are alternately arranged to form an alternate overlapping region; The staggered overlapping region is grooved to form an isolation groove, wherein the isolation groove penetrates the P-type doped amorphous silicon layer and the first intrinsic amorphous silicon layer in the staggered overlapping region so as to separate the staggered overlapping region into a first staggered overlapping region and a second staggered overlapping region.

12. The method according to claim 11, characterized in that Also includes: After exposing the second region, the semiconductor substrate is subjected to alkali texturing to form a pyramid-like textured surface structure on the second surface and the second region.

13. The method according to claim 12, characterized in that After the pyramid-like textured structure is formed on the second surface and the second region, a second intrinsic amorphous silicon layer and a silicon nitride passivation layer are sequentially formed on the second surface.

14. The method according to claim 11, characterized in that After grooving the staggered overlapping areas, a first electrode layer is formed on one side of the isolation groove, and the first electrode layer covers the P-type doped amorphous silicon layer, and a second electrode layer is formed on the other side of the isolation groove, and the second electrode layer covers the P-type doped amorphous silicon layer and the N-type doped polycrystalline silicon layer.

15. The method according to claim 14, characterized in that A first gate line is formed on a portion of the surface of the first electrode layer, and a second gate line is formed on a portion of the surface of the second electrode layer.

16. The method according to claim 11, characterized in that The tunnel oxide layer and the N-type doped polysilicon layer are deposited by LPCVD.

17. The method according to claim 11, characterized in that The isolation layer includes an insulating layer; Alternatively, the isolation layer includes a silicon nitride layer and a PSG layer, the PSG layer is formed on a surface of the N-type doped polysilicon layer away from the tunnel oxide layer, and the silicon nitride layer is formed on a surface of the PSG layer away from the N-type doped polysilicon layer.

18. The method according to claim 11, characterized in that A portion of the first intrinsic amorphous silicon layer and the P-type doped amorphous silicon layer away from one end of the second region is removed by using a laser, and the power of the laser is 6-15W.

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