Suppression of transient voltage spike coupling circuit and voltage conversion circuit

Abstract

Embodiments of this disclosure provide a transient voltage spike suppression circuit and a voltage conversion circuit. The transient voltage spike suppression circuit includes a switch isolation circuit and a low-pass filter circuit. The switch isolation circuit is configured to isolate the voltage node generating the voltage spike from the input terminal of the voltage receiving node during the occurrence of a voltage spike. The voltage spike is an instantaneous voltage spike caused by parasitic capacitance inside and / or outside the chip where the transient voltage spike suppression circuit is located. The low-pass filter circuit is configured to filter the high-frequency voltage spike generated by the switch isolation circuit during switching. This disclosure solves the problem of existing circuits experiencing abnormal operation due to parasitic capacitance interference, resulting in periodic operation in an open-loop state and excessive output ripple.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the field of integrated circuit technology, and more specifically, to a transient voltage spike coupling suppression circuit and a voltage conversion circuit. Background Technology

[0002] Due to the presence of parasitic capacitance inside the electronic chip or on the external PCB board, pulse signals in the circuit can couple to sensitive voltage nodes (such as feedback voltage nodes) and cause voltage spikes. Since sensitive nodes are generally high-impedance nodes, they cannot recover to steady-state voltage before the next voltage spike arrives. This will cause abnormal circuit operation, resulting in periodic operation in an open-loop state and excessive output ripple.

[0003] The common solution to the above problem is to add shielding lines parallel to the signal on both sides of the sensitive line corresponding to the chip layout. This way, the voltage spike interference will be absorbed by the shielding lines. However, due to the influence of power density, layout and other requirements, shielding lines are usually not added to the PCB board outside the chip. Therefore, the common solution can usually only suppress voltage spike interference caused by parasitic capacitance inside the chip, but cannot suppress voltage spike interference caused by parasitic capacitance on the PCB board outside the chip. Therefore, the circuit will still have the above-mentioned abnormal operation, and the problem of periodically operating in an open-loop state with large output ripple will still exist. Summary of the Invention

[0004] The embodiments described herein provide a transient voltage spike coupling suppression circuit and a voltage conversion circuit to solve the problem of existing circuits operating abnormally due to parasitic capacitance interference, resulting in periodic operation in an open-loop state and excessive output ripple.

[0005] The first aspect of this disclosure provides a transient voltage spike suppression circuit, characterized in that the transient voltage spike suppression circuit includes: a switch isolation circuit and a low-pass filter circuit; wherein, the switch isolation circuit is configured to isolate the voltage node that generates the voltage spike from the input terminal receiving the voltage of the voltage node during the occurrence of the voltage spike, the voltage spike being an instantaneous voltage spike caused by parasitic capacitance inside and / or outside the chip where the transient voltage spike suppression circuit is located; the low-pass filter circuit is configured to filter high-frequency voltage spikes generated by the switch isolation circuit during switching.

[0006] Optionally, the switch isolation circuit includes: a first transistor and a first operational amplifier; wherein, a first terminal and a second terminal of the first transistor are respectively connected to the low-pass filter circuit and the voltage node that generates the voltage spike, the control terminal of the first transistor receives a switch control signal, and the switch control signal is set according to the occurrence time of the voltage spike; the non-inverting input terminal of the first operational amplifier is connected to the first terminal of the first transistor, the negative-inverting input terminal of the first operational amplifier is connected to the output terminal of the first operational amplifier, and the output terminal of the first operational amplifier is connected to the substrate terminal of the first transistor.

[0007] Optionally, the switch isolation circuit includes: a second transistor, a third transistor, and a first capacitor; wherein, the second terminal of the second transistor is connected to the first terminal of the third transistor, the substrate terminal of the second transistor is connected to the substrate terminal of the third transistor, the first terminal of the second transistor is connected to the low-pass filter circuit, the second terminal of the third transistor is connected to the node that generates the voltage spike, the control terminals of the second transistor and the third transistor receive the same switch control signal, and the switch control signal is set according to the occurrence time of the voltage spike; one end of the first capacitor is connected to the ground terminal, and the other end of the first capacitor is connected to the node between the second terminal of the second transistor and the first terminal of the third transistor, and the node between the substrate terminal of the second transistor and the substrate terminal of the third transistor, respectively.

[0008] Optionally, the low-pass filter circuit includes: a first resistor and a second capacitor; wherein, one end of the first resistor is connected to the switch isolation circuit, the other end of the first resistor is connected to the second capacitor and the input terminal of the voltage receiving node, and the other end of the second capacitor is connected to the ground terminal.

[0009] Optionally, the switch control signal is low during the voltage spike and high at other times.

[0010] Optionally, the corresponding parameter values ​​of the first resistor and the second capacitor can be adjusted according to the rise rate of the voltage spike.

[0011] A second aspect of this disclosure provides a voltage conversion circuit, the voltage conversion circuit including the transient voltage spike suppression circuit described in any one of the first aspects above.

[0012] Optionally, the voltage conversion circuit can be any one of a low-dropout linear regulator circuit, a buck converter circuit, a boost converter circuit, a buck-boost converter circuit, or a switched-capacitor voltage converter circuit.

[0013] Optionally, the transient voltage spike suppression circuit is connected to the voltage feedback node and the input terminal receiving the voltage of the voltage feedback node.

[0014] Optionally, the voltage spike is a transient voltage spike generated by the voltage feedback node after being interfered with by pulse signal coupling under the condition of parasitic capacitance.

[0015] The transient voltage spike suppression circuit of this disclosure includes: a switch isolation circuit and a low-pass filter circuit; wherein, the switch isolation circuit is configured to isolate the voltage node generating the voltage spike from the input terminal of the voltage receiving node during the occurrence of a voltage spike, the voltage spike being an instantaneous voltage spike caused by parasitic capacitance inside and / or outside the chip where the transient voltage spike suppression coupling circuit is located; the low-pass filter circuit is configured to filter the high-frequency voltage spike generated by the switch isolation circuit during switching. It can be seen that the transient voltage spike suppression coupling circuit of this disclosure, by isolating the voltage node generating the voltage spike from the input terminal of the voltage receiving node during the occurrence of a voltage spike, can suppress the interference of voltage spikes caused by parasitic capacitance inside the chip to sensitive voltage nodes, as well as the interference of voltage spikes caused by parasitic capacitance on the external PCB board to sensitive voltage nodes. Therefore, compared with the existing method of adding shielding lines inside the chip, it can better suppress voltage spikes, thereby avoiding the problem of abnormal operation of the circuit due to parasitic capacitance interference, resulting in periodic operation in an open-loop state and excessive output ripple. Similarly, voltage conversion circuits that include transient voltage spike coupling suppression circuits can also suppress voltage spikes generated by parasitic capacitance from coupling to the input of the operational amplifier, ensuring stable output voltage and normal output ripple. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0017] Figure 1 This is a schematic diagram of a transient voltage spike coupling suppression circuit according to an embodiment of the present disclosure;

[0018] Figure 2 This is an example diagram of a switch isolation circuit according to an embodiment of the present disclosure;

[0019] Figure 3 This is a schematic diagram of an existing switching transistor;

[0020] Figure 4 This is an example diagram of another switch isolation circuit according to an embodiment of the present disclosure;

[0021] Figure 5 An exemplary circuit diagram of a low-dropout linear regulator circuit according to an embodiment of the present disclosure is shown;

[0022] Figure 6 This is a timing diagram of the signals corresponding to the low-dropout linear regulator circuit of an embodiment of this disclosure;

[0023] Figure 7 This is a waveform diagram of the corresponding signal for an existing low-dropout linear regulator circuit;

[0024] Figure 8 This is a waveform diagram of the corresponding signal of a low-dropout linear regulator circuit according to an embodiment of this disclosure.

[0025] The elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0027] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0028] In all embodiments of this disclosure, terms such as “first” and “second” are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0029] like Figure 1The diagram shown is an example of a transient voltage spike suppression circuit 100 provided in an embodiment of this disclosure. It includes a switch isolation circuit 110 and a low-pass filter circuit 120. The switch isolation circuit 110 is configured to isolate the voltage node Vs that generates the voltage spike from the input terminal A of the voltage receiving node Vs during the occurrence of a voltage spike. The voltage spike is an instantaneous voltage spike caused by parasitic capacitance inside and / or outside the chip where the transient voltage spike suppression circuit 100 is located. The low-pass filter circuit 120 is configured to filter the high-frequency voltage spike generated by the switch isolation circuit 110 during switching. The switch isolation circuit 110 and the low-pass filter circuit 120 are connected in series. In practical applications, the input terminal of the switch isolation circuit 110 is connected to the voltage node Vs that generates the voltage spike, and the output terminal of the low-pass filter circuit 120 is connected to the input terminal A of the voltage receiving node Vs. It should be noted that the switch isolation circuit 110 is an isolation circuit composed of a switching transistor. In this embodiment, the switching transistor in the switch isolation circuit 110 is a substrate-biased switching transistor. During the voltage spike, the switching transistor is turned off to suppress the interference of the spike voltage. The driving signal Vshoot of the switching transistor is low during the voltage spike and high at other times. The transient voltage spike suppression coupling circuit 100 can also maintain the stability of the voltage received at the input terminal A of the receiving voltage node through the low-pass filter circuit 120. Specifically, the low-pass filter circuit 120 includes a first resistor R1 and a second capacitor C. hold One end of the first resistor R1 is connected to the switch isolation circuit 110, and the other end of the first resistor R1 is connected to the second capacitor C. hold The voltage input terminal A of the receiving voltage node, and the second capacitor C. hold The other end is connected to the ground terminal. During circuit design, R1 and C in the low-pass filter circuit 120... hold The corresponding parameter values ​​are designed and adjusted according to the rise rate of the voltage spike.

[0030] Furthermore, Figure 2 An example diagram of a switch isolation circuit 110 provided in an embodiment of this disclosure is shown. The switch isolation circuit 110 includes: a first transistor M1 and a first operational amplifier 111; wherein, the first terminal S and the second terminal D of the first transistor M1 are respectively connected to a low-pass filter circuit 120 and a voltage node Vs that generates a voltage spike; the control terminal of the first transistor M1 receives a switch control signal (corresponding to the drive signal Vshoot of the switch transistor mentioned above), and the switch control signal Vshoot is set according to the occurrence time of the voltage spike; the non-inverting input terminal of the first operational amplifier 111 is connected to the first terminal S of the first transistor M1, the negative inverting input terminal of the first operational amplifier 111 is connected to the output terminal of the first operational amplifier 111, and the output terminal of the first operational amplifier 111 is connected to the substrate terminal B of the first transistor M1.

[0031] from Figure 2 As can be seen from the specific structure of the switch isolation circuit 110 in this embodiment, the switching transistor (i.e., the first transistor M1) in the switch isolation circuit 110 does not use a structure that connects the source terminal (S terminal) and bulk terminal (B terminal) of the MOSFET together. Figure 3 It is a typical switching transistor 200 structure, where the source and bulk terminals of the MOSFET are connected together. Instead, it is connected as a buffer through the first operational amplifier 111, and a separate substrate bias is applied to the B terminal of M1. Figure 3 In the structure described, when a negative voltage spike occurs at Vs, the parasitic diode 210 conducts. Even if the switching transistor drive signal Vshoot is low, a diode path is formed between the D and S terminals, making it impossible to suppress the negative voltage spike. Figure 2 The separate substrate biasing in the design prevents the B terminal and S terminal from being connected together. This prevents the parasitic diode between the D and B terminals from forming a diode path between the D and S terminals, thus suppressing negative voltage spikes.

[0032] Furthermore, Figure 4 An example diagram of another switch isolation circuit 110 provided in this embodiment of the present disclosure is shown. The switch isolation circuit 110 includes: a second transistor M2, a third transistor M3, and a first capacitor C1; wherein, the second terminal D of the second transistor M2 is connected to the first terminal S of the third transistor M3, the substrate terminal B of the second transistor M2 is connected to the substrate terminal B of the third transistor M3, the first terminal S of the second transistor M2 is connected to a low-pass filter circuit 120, the second terminal D of the third transistor M3 is connected to the node Vs that generates the voltage spike, the control terminals of the second transistor M2 and the third transistor M3 receive the same switch control signal Vshoot, and the switch control signal Vshoot is set according to the occurrence time of the voltage spike; one end of the first capacitor C1 is connected to the ground terminal, and the other end of the first capacitor C1 is connected to the node between the second terminal D of the second transistor M2 and the first terminal S of the third transistor M3, and the node between the substrate terminal B of the second transistor M2 and the substrate terminal B of the third transistor M3, respectively. The switch control signal Vshoot corresponds to the drive signal Vshoot of the aforementioned switch transistor, and is therefore set to be low during the occurrence of the voltage spike and high at other times.

[0033] from Figure 4 As can be seen from the specific structure of the switch isolation circuit 110 in this embodiment, the switching transistor (i.e., the second transistor M2) in the switch isolation circuit 110 does not use a structure that connects the source terminal (S terminal) and bulk terminal (B terminal) of the MOSFET together. Figure 3It is a typical MOSFET 200 structure (connecting the source and bulk terminals of the MOSFET together), but instead, it uses the first capacitor C1 and the third transistor M3 to create a separate substrate bias for the B terminal of M2. Figure 3 In the structure described, when a negative voltage spike occurs at Vs, the parasitic diode 210 conducts. Even if the switching transistor drive signal Vshoot is low, a diode path is formed between the D and S terminals, making it impossible to suppress the negative voltage spike. Figure 4 The separate substrate bias in the design prevents the base (B) and source (S) terminals of M2 from being connected together. This structure prevents the formation of a diode path between the source terminal of M2 and Vs when a negative voltage spike occurs at Vs, thus suppressing the negative voltage spike.

[0034] The above Figure 2 and Figure 4 Both types of switch isolation circuits 110 have a structure that separately biases the substrate of the switching transistor, so that the B terminal and the S terminal are not connected together. This prevents the parasitic body diode between the D terminal and the B terminal from forming a diode path between the D terminal and the S terminal, thus suppressing negative voltage spikes. It should be noted that in practical applications, the switch isolation circuit 110 can also be other switching transistor circuit structures that isolate the source terminal and the bulk terminal.

[0035] In summary, the transient voltage spike suppression coupling circuit 100 of this disclosure isolates the voltage node Vs that generates the voltage spike from the input terminal A of the receiving voltage node during the occurrence of the voltage spike. This method can suppress the interference of voltage spikes caused by parasitic capacitance inside the chip to sensitive voltage nodes, as well as the interference of voltage spikes caused by parasitic capacitance on the external PCB board of the chip to sensitive voltage nodes. Therefore, it can suppress voltage spikes better than the existing method of adding shielding lines inside the chip.

[0036] Regarding the application of the transient voltage spike suppression coupling circuit 100 described above, this disclosure also provides a voltage conversion circuit, which includes the aforementioned transient voltage spike suppression coupling circuit 100. Specifically, the voltage conversion circuit can be any one of a low dropout regulator (LDO), a buck converter, a boost converter, a buck-boost converter, or a switched capacitor voltage converter (charge pump). In all of the aforementioned voltage conversion circuits, transient voltage spikes are generated at the voltage feedback node due to interference from pulse signals coupled into the voltage conversion circuit caused by parasitic capacitance. By connecting the transient voltage spike suppression coupling circuit 100 between the voltage feedback node and the input terminal of the receiving voltage feedback node, transient voltage spikes can be effectively suppressed. The following detailed description uses the application of the transient voltage spike suppression coupling circuit 100 in a low dropout regulator circuit as an example.

[0037] like Figure 5 The diagram shows a schematic of a low-dropout linear regulator circuit 300 according to an embodiment of the present disclosure. The low-dropout linear regulator circuit 300 includes: a transient voltage spike suppression circuit 100, a second operational amplifier 310, a fourth transistor M4, a second resistor R2, a third resistor R3, a third capacitor Cout, and a first current source I. load In this configuration, the non-inverting input of the second operational amplifier 310 is connected to the node between the second resistor R2 and the third resistor R3 after passing through the transient voltage spike suppression coupling circuit 100. The negative-inverting input of the second operational amplifier 310 receives the reference voltage Vref, which is a reference voltage generated by the input voltage Vin through the bandgap reference circuit. The output of the second operational amplifier 310 is connected to the control terminal of the fourth transistor M4. The first terminal S of the fourth transistor M4 is connected to the negative voltage source terminal V. NEG negative voltage source terminal V NEG The input voltage Vin is a negative voltage generated by the switching power supply; the second terminal D of the fourth transistor M4 is connected to the output terminal of the output voltage Vout; the second resistor R2 and the third resistor R3 are connected in series between the output terminal and the ground terminal; the third capacitor Cout is connected in parallel between the output terminal and the ground terminal; the first current source I... load It is connected in parallel between the output terminal and the ground terminal. Figure 5 In the middle, the voltage feedback node is V FB(Corresponding to node Vs in the aforementioned embodiment), the input terminal of the voltage receiving voltage feedback node is the non-inverting input terminal of the second operational amplifier 310 (corresponding to terminal A in the aforementioned embodiment), and the transient voltage spike suppression coupling circuit 100 is connected between the two, with the voltage feedback suppression node being Vs. FB The resulting voltage spike enters the non-inverting input of the second operational amplifier 310.

[0038] Figure 5 In the chip 400, the transient voltage spike suppression circuit 100, the second operational amplifier 310, and the fourth transistor M4 are located inside the chip 400. The second resistor R2, the third resistor R3, the third capacitor Cout, and the first current source I are also present. load The capacitance is located outside the chip. The internal capacitance of the chip is C. p1 The parasitic capacitance on the external PCB of the chip is C. p2 The chip 400, which houses the low-dropout linear regulator circuit 300, also includes modules such as a switching power supply. Figure 5 The parasitic capacitance in the switching power supply is determined by the switching node voltage Vsw and the voltage feedback node V. FB Parasitic capacitance generated between nodes. When a switching power supply performs a switching action (at the rising and falling edges of the switching node voltage Vsw signal), due to the presence of parasitic capacitance, the node V... FB This will generate instantaneous voltage spikes, which, if not suppressed, will affect the voltage at the non-inverting input of the second operational amplifier 310. In this embodiment, transient voltage spike suppression coupling circuit 100 is added to suppress voltage spikes. Specifically, in the steady state of the low-dropout linear regulator circuit 300, when V... FB During the generation of voltage spikes, the switch isolation circuit 110 in the transient voltage spike suppression coupling circuit 100 is disconnected, thus blocking V FB Sensitive nodes (V) within the module INP The low-pass filter circuit 120 isolates the high-frequency voltage spikes generated by the switch isolation circuit 110 during switching, while the second capacitor C... hold This will also keep the voltage at V INP =V REF Unchanged. In V FB After the voltage returns to steady state, the drive signal Vshoot of the switching transistor in the switching isolation circuit 110 is high, the switching transistor is turned on, and V FB =V INP =V REF In other words, when the low-dropout linear regulator circuit is in steady state, the voltages at both input terminals of the second operational amplifier 310 are equal throughout the entire cycle, and the low-dropout linear regulator circuit 300 still operates in closed-loop mode. The output voltage Vout remains constant and the ripple is normal.Figure 6 The Vsw signal and V are shown in the figure. FB The timing diagram corresponding to the drive signal Vshoot of the switching transistor in the signal and switch isolation circuit 110 is as follows: Figure 6 As can be seen, during the arrival of the rising or falling edge of Vsw, V FB When a voltage spike occurs, the drive signal Vshoot of the switching transistor in the switch isolation circuit 110 is low during the period of the voltage spike, and the switching transistor in the switch isolation circuit 110 is off. At other times (V... FB During the period of recovery to a stable state, the voltage level is high, and the switching transistor in the switch isolation circuit 110 is turned on. It should also be noted that if there is a voltage spike when the low dropout linear regulator circuit has not yet entered a steady state, the transient voltage spike suppression coupling circuit 100 will also suppress it to ensure that the voltage at the non-inverting input terminal of the second operational amplifier 310 is not affected by the voltage spike.

[0039] As can be seen from the above analysis, the low-dropout linear regulator circuit 300 of this embodiment, compared with the existing low-dropout linear regulator circuit, adds a transient voltage spike suppression circuit 100 at the non-inverting input terminal of the second operational amplifier 310 to suppress voltage spike coupling. Any voltage spike affecting the voltage at the non-inverting input terminal of the second operational amplifier 310 can be suppressed, regardless of whether it is a parasitic capacitance C inside the chip 400. p1 The cause is still the parasitic capacitance C on the external PCB board of chip 400. p2 Caused by. Compared to existing sensitive lines corresponding to the chip layout (specifically referring to V in this disclosure embodiment). FB Adding shielding lines parallel to the signal on both sides of the line between the corresponding sampling node and the non-inverting input terminal of the second operational amplifier 310 can better ensure the normal operation of the circuit and avoid the problem of periodically operating in an open-loop state and having large output ripple.

[0040] To further illustrate the effect of the low-dropout linear regulator circuit 300 in the embodiments of this disclosure, simulation waveforms of the circuit are provided, such as... Figure 7 The image shows the waveform of the signal corresponding to a conventional low-dropout linear regulator circuit without the addition of a transient voltage spike suppression circuit 100. Figure 8 The image shown is a waveform diagram of the signal corresponding to the low-dropout linear regulator circuit with the added transient voltage spike suppression circuit 100 in this embodiment of the present disclosure. Figure 7 In the middle, V is shown SW V REF V INP Waveform diagram corresponding to the Vout signal; Figure 8 The diagram shows Vsw and V. shoot V INPV REF V FB Waveform diagram corresponding to the Vout signal. Figure 7 and Figure 8 The waveform diagram in the figure is under the same load, V SW This was obtained under the conditions of the same switching frequency and the same output voltage. Figure 7 As can be seen, without the addition of the transient voltage spike suppression circuit 100, V INP Coupled with voltage spikes, namely V FB The resulting voltage spike is directly coupled to the non-inverting input of the second operational amplifier 310. Because this node is a high-impedance node, its recovery is slow, causing a voltage spike across the second operational amplifier 310 to... REF ≠V INP This causes the second operational amplifier 310 to be out of the amplification region, the fourth transistor M4 to be turned off, and the LDO loop to open. The ripple of the output voltage Vout depends on I. load Periodically charge the capacitor, from Figure 7 From this, we can determine that the final output voltage ripple is 2.5mV. Figure 8 As can be seen, after adding the transient voltage spike suppression circuit 100, V FB Transient voltage spikes are greatly suppressed, and the signal V entering the non-inverting input of the second operational amplifier 310 is reduced. INP There are almost no voltage spikes, with V INP =V REF The LDO remains a closed loop, significantly reducing the ripple of the output voltage Vout. Figure 8 The final output ripple can be determined to be 98uV. As can be seen from the simulation waveform above, adding the transient voltage spike suppression circuit 100 ensures that the voltages at both input terminals of the second operational amplifier 310 are equal throughout the entire cycle in steady state. This ensures that the low-dropout linear regulator circuit operates in a closed-loop state throughout the entire cycle, stabilizing the output voltage and ensuring normal output ripple.

[0041] In summary, the low-dropout linear regulator circuit with the addition of a transient voltage spike suppression circuit 100 in this embodiment can suppress voltage spikes generated by parasitic capacitance from coupling to the non-inverting input of the operational amplifier, ensuring that the voltages at both inputs of the operational amplifier are equal throughout the entire cycle, and ensuring that the low-dropout linear regulator circuit operates in a closed-loop state throughout the entire cycle, thereby stabilizing the output voltage and ensuring normal output ripple.

[0042] Furthermore, the application of the transient voltage spike suppression circuit 100 in buck converters, boost converters, buck-boost converters, and switched-capacitor voltage converters (charge pumps) is the same as its application in the low-dropout linear regulator circuit 300. They all have a voltage feedback node V. FB and switching node voltage V sw V sw The pulse signal will interfere with the voltage feedback node V FB , making V FB Transient voltage spikes are generated, therefore, when the transient voltage spike suppression coupling circuit 100 is applied to Buck converters, Boost converters, Buck-Boost converters, and Charge Pumps, the transient voltage spike suppression coupling circuit 100 is also connected to V. FB This is achieved between the input terminal of the operational amplifier (the input terminal that receives the voltage of the voltage feedback node) and the voltage feedback node V. FB The generated voltage spikes enter the input terminal of the operational amplifier, thereby ensuring the normal operation of the circuit.

[0043] In summary, the voltage conversion circuit with the added transient voltage spike coupling suppression circuit 100 in this embodiment can suppress voltage spikes generated by parasitic capacitance from coupling to the input terminal of the operational amplifier, ensuring stable output voltage and normal output ripple of the voltage conversion circuit.

[0044] The descriptions of the same or corresponding module units in the various embodiments of this disclosure can be referenced in turn.

[0045] In the above description, well-known structural elements and steps have not been described in detail. However, those skilled in the art should understand that the corresponding structural elements and steps can be implemented through various technical means. Furthermore, in order to form the same structural elements, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0046] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims of this invention.

[0047] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0048] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this disclosure may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0049] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A circuit for suppressing transient voltage spike coupling, characterized in that, The circuit for suppressing transient voltage spike coupling includes: a switch isolation circuit and a low-pass filter circuit; The switch isolation circuit is configured to isolate the voltage node that generates the voltage spike from the input terminal that receives the voltage of the voltage node during the occurrence of the voltage spike, wherein the voltage spike is a transient voltage spike caused by parasitic capacitance inside the chip where the transient voltage spike suppression coupling circuit is located and / or outside the chip. The switch isolation circuit is an isolation circuit composed of a switch transistor, which is a switch transistor with a substrate individually biased. The switch isolation circuit includes: a first transistor serving as the switch, and a first operational amplifier; wherein, a first terminal and a second terminal of the first transistor are respectively connected to the low-pass filter circuit and the voltage node generating the voltage spike; the control terminal of the first transistor receives a switch control signal, which is set according to the occurrence time of the voltage spike; the non-inverting input terminal of the first operational amplifier is connected to the first terminal of the first transistor, the non-inverting input terminal of the first operational amplifier is connected to the output terminal of the first operational amplifier, and the output terminal of the first operational amplifier is connected to the substrate terminal of the first transistor; or, The switch isolation circuit includes: a second transistor, a third transistor, and a first capacitor, which serve as the switch; wherein, the second terminal of the second transistor is connected to the first terminal of the third transistor, the substrate terminal of the second transistor is connected to the substrate terminal of the third transistor, the first terminal of the second transistor is connected to the low-pass filter circuit, the second terminal of the third transistor is connected to the node that generates the voltage spike, the control terminals of the second transistor and the third transistor receive the same switch control signal, and the switch control signal is set according to the occurrence time of the voltage spike; one end of the first capacitor is connected to the ground terminal, and the other end of the first capacitor is connected to the node between the second terminal of the second transistor and the first terminal of the third transistor, and the node between the substrate terminal of the second transistor and the substrate terminal of the third transistor, respectively; The low-pass filter circuit is configured to filter out high-frequency voltage spikes generated by the switch isolation circuit during switching.

2. The transient voltage spike suppression circuit according to claim 1, characterized in that, The low-pass filter circuit includes: a first resistor and a second capacitor; Wherein, one end of the first resistor is connected to the switch isolation circuit, the other end of the first resistor is connected to the second capacitor and the input terminal of the voltage receiving node, and the other end of the second capacitor is connected to the ground terminal.

3. The transient voltage spike suppression circuit according to claim 2, characterized in that, The switch control signal is low during the voltage spike and high at other times.

4. The transient voltage spike suppression circuit according to claim 3, characterized in that, Adjust the corresponding parameter values ​​of the first resistor and the second capacitor according to the rise rate of the voltage spike.

5. A voltage conversion circuit, characterized in that, The voltage conversion circuit includes the transient voltage spike coupling suppression circuit described in any one of claims 1 to 4.

6. The voltage conversion circuit according to claim 5, characterized in that, The voltage conversion circuit can be any one of the following: low dropout linear regulator circuit, buck converter circuit, boost converter circuit, buck-boost converter circuit, or switched capacitor voltage converter circuit.

7. The voltage conversion circuit according to claim 6, characterized in that, The transient voltage spike suppression circuit is connected to the voltage feedback node and the input terminal that receives the voltage from the voltage feedback node.

8. The voltage conversion circuit according to claim 7, characterized in that, The voltage spike is a transient voltage spike generated by the voltage feedback node after being interfered with by pulse signal coupling under the condition of parasitic capacitance.

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