A planar back-to-back power combining power amplifier chip circuit

Abstract

The present application relates to the technical fields of microwave integrated circuit, and particularly relates to a kind of flat back-to-back power combining power amplifier chip circuit, including input bonding pressure point RFin_PAD, power distribution microstrip line MSL1, link microstrip MSL2, π type attenuator, back-to-back power amplifier PA1 of layout, back-to-back power amplifier PA2 of layout, power combining microstrip MSL3, high-power isolation resistance R and power output bonding pressure point RFout_PAD;The present application realizes the purpose that the output power of single power amplifier chip is doubled within process rules, and the input and output of two power amplifier chips have high isolation, provides an effective solution for microwave assembly to realize high-power output and miniaturization application.

Description

Technical Field

[0001] This invention relates to the field of microwave integrated circuit technology, and specifically to a planar back-to-back power combining power amplifier chip circuit. Background Technology

[0002] In microwave components, multi-channel power combining is often employed to achieve high power output. Power combining in these components can be achieved in two ways: firstly, by combining multiple chips in a microstrip line planar configuration based on printed circuit board technology; however, this significantly increases the component size, as illustrated in patent application CN201710582086.7. Secondly, a three-dimensional waveguide probe multi-channel combining method can be used, but this increases the complexity of micro-assembly and, due to the use of waveguides, increases the component's volume, as illustrated in patent application CN201920774030.6.

[0003] To meet the application requirements of high power and miniaturization in microwave components, it is of great significance to improve the output power of a single power amplifier chip. Summary of the Invention

[0004] To address the aforementioned problems, this invention provides a planar back-to-back power combining amplifier chip circuit. This circuit solves the problem that once a single power amplifier chip is connected in parallel with multiple channels and its size reaches the upper limit of the manufacturing process, the output power cannot be further increased. Furthermore, by adding a π-type attenuator at the input terminals of the two power amplifier chips, the isolation between their input ports is improved. Additionally, by increasing the power resistor R at the input terminals of the two power combining microstrips, the isolation between the output ports of the two power amplifiers is further enhanced.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] This invention provides a planar back-to-back power combining power amplifier chip circuit, including an input bonding point RFin_PAD, a power distribution microstrip line MSL1, a connecting microstrip MSL2, a π-type attenuator, a back-to-back power amplifier PA1, a back-to-back power amplifier PA2, a power combining microstrip MSL3, a high-power isolation resistor R, and a power output bonding point RFout_PAD.

[0007] The power input bonding point RFin_PAD is connected to the power distribution microstrip MSL1, and then connected to the connection microstrip MSL2;

[0008] The connecting microstrip MSL2 is connected to a π-type attenuator, and then connected to the input matching network IN_MN of the back-to-back power amplifiers PA1 and PA2. The output of the input matching network is connected to the input of the first stage tube cell, the output of the first stage tube cell is connected to the input of the interstage matching network 1, the output of the interstage matching network 1 is connected to the input of the second stage tube cell, the output of the second stage tube cell is connected to the input of the interstage matching network 2, the output of the interstage matching network 2 is connected to the input of the third stage tube cell, the output of the third stage tube cell is connected to the input of the output matching network OUT_MN, and the output of the output matching network OUT_MN is connected to the power combining microstrip MSL3.

[0009] The two power combining microstrips MSL3 are joined together at the power output bonding point RFout_PAD.

[0010] The present invention is further configured such that the two groups of duct cell gate fingers are arranged in parallel and back to back, and the duct cells are connected to the output matching network and then to the power combiner PC to double the output power of a single chip.

[0011] A further feature of this invention is that a ground via for electromagnetic isolation is added between the output matching circuit and the power combiner microstrip MSL3 to reduce the electromagnetic coupling between the microstrips of the output matching circuit and the power combiner circuit.

[0012] A further feature of this invention is that a π-type attenuator is added between the connecting microstrip MSL2 and power amplifiers PA1 and PA2 to improve the isolation between the input ports of power amplifiers PA1 and PA2.

[0013] A further feature of this invention is that a high-power resistor R is connected between the input terminals of the two power combining microstrip lines MSL3 to improve the isolation between the output ports of the two power amplifiers PA1 and PA2.

[0014] Beneficial effects

[0015] Compared with known public technologies, the technical solution provided by this invention has the following beneficial effects:

[0016] This invention solves the problem that the output power cannot be further increased after the parallel arrangement of multiple channels of a single power amplifier chip reaches its limit. It achieves the goal of doubling the output power of a single power amplifier chip within the process specifications, and the input and output of the two power amplifier chips have a high degree of isolation. This provides an effective solution for microwave components to achieve high power output and miniaturization. Attached Figure Description

[0017] Figure 1 This is a block diagram of the circuit principle of a planar back-to-back power combining power amplifier chip according to the present invention.

[0018] Figure 2 This is a schematic diagram of a traditional power combining chip circuit.

[0019] Figure 3 This is a schematic diagram of a planar back-to-back power combining power amplifier chip circuit according to the present invention.

[0020] Figure 4 This is a test diagram of the output power of the 14-18GHz power amplifier MMIC in Example 2. Detailed Implementation

[0021] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0022] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," "outer," "top / bottom," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0023] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installed," "equipped with," "sleeved / connected," "connected," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0024] Example 1:

[0025] like Figure 1This invention provides a planar back-to-back power combining power amplifier chip circuit, including an input bonding point RFin_PAD, a power distribution microstrip line MSL1, a connecting microstrip line MSL2, a π-type attenuator, back-to-back power amplifiers PA1 and PA2, a power combining microstrip line MSL3, a high-power isolation resistor R, and a power output bonding point RFout_PAD. All circuits are integrated on a single substrate using semiconductor technology. The substrate may include, but is not limited to, SiC, GaAs, or Si, and is symmetrically arranged. The power input bonding point RFin_PAD is connected to the power distribution microstrip line MSL1, and then connected to the connecting microstrip line MSL2; the connecting microstrip line MSL2 is connected to the π-type attenuator... The reducer is then connected to the input matching network IN_MN of the back-to-back power amplifiers PA1 and PA2, respectively. The output of the input matching network is connected to the input of the first stage tube cell, the output of the first stage tube cell is connected to the input of the interstage matching network 1, the output of the interstage matching network 1 is connected to the input of the second stage tube cell, the output of the second stage tube cell is connected to the input of the interstage matching network 2, the output of the interstage matching network 2 is connected to the input of the third stage tube cell, the output of the third stage tube cell is connected to the input of the output matching network OUT_MN, and the output of the output matching network OUT_MN is connected to the power combining microstrip MSL3. The two power combining microstrips MSL3 are connected to the power output bonding pressure point RFout_PAD.

[0026] In this embodiment, traditional power amplifiers employ a parallel arrangement of multiple transistor cells, with the power of these cells combined and output via an output matching circuit. When designing traditional power amplifier chips, arranging multiple transistor cells in parallel essentially reaches the upper limit of semiconductor process specifications in terms of the chip's dimensions in the vertical gate finger direction, making it impossible to arrange more transistor cells side-by-side and hindering the achievement of higher power output from a single chip. This invention addresses this by mirror-arranging two identical power amplifiers PA1 and PA2 back-to-back, with the two sets of transistor cells arranged parallel to each other and back-to-back. The transistors are then combined via an output matching network, effectively doubling the output power of a single chip. A π-type attenuator is added between the connecting microstrip MSL2 and the power amplifiers PA1 and PA2 to improve the isolation between the input ports of the two power amplifiers. Furthermore, a large power resistor R is added at the input of the two power combining microstrips MSL3 to further improve the isolation between the output ports of the two power amplifiers PA1 and PA2.

[0027] In this invention, two sets of duct cell gate fingers are arranged in parallel and back to back. The duct cells are connected to the output matching network and then to the power combiner PC to double the output power of a single chip.

[0028] In this invention, in order to reduce the chip area, the output matching microstrip and the power combining microstrip MSL3 are brought close to each other. The closer proximity increases the coupling, resulting in poorer power combining consistency of the cell. A ground via for electromagnetic isolation is added between the output matching circuit and the power combining microstrip MSL3 to reduce the electromagnetic coupling between the microstrips of the output matching circuit and the power combining circuit.

[0029] In this invention, a π-type attenuator is added between the microstrip MSL2 and the power amplifiers PA1 and PA2 to improve the isolation between the input ports of the power amplifiers PA1 and PA2.

[0030] In this invention, a high-power resistor R is connected between the input terminals of the two power combining microstrips MSL3 to improve the isolation between the output ports of the two power amplifiers PA1 and PA2.

[0031] Example 2:

[0032] The traditional method for increasing the output power of a single power amplifier chip is to arrange more transistors in a line, with two groups (16 transistors each) on a horizontal line. Taking a 14-18GHz frequency and an output power of 100W as an example, for instance... Figure 2 As shown, this traditional chip manufacturing method results in a long side dimension of 11.1mm, exceeding the upper limit of the process specifications. Furthermore, the ratio of the long side to the wide side reaches 2.41, making the chip prone to chip breakage and warping, thus affecting chip reliability. The two groups (each with 16 channels) of transistors are close together, causing mutual interference in heat dissipation, leading to increased junction temperature and reduced chip lifespan.

[0033] like Figure 3 As shown, the chip circuit includes an input bonding pad RFin_PAD, a power distribution microstrip line MSL1, a connecting microstrip line MSL2, a π-type attenuator, back-to-back power amplifiers PA1 and PA2, a power combining microstrip line MSL3, a high-power isolation resistor R, and a power output bonding pad RFout_PAD. All of these circuits are integrated onto a single substrate using semiconductor technology and are symmetrically arranged. The operating frequency and output power are... Figure 2 The chips are the same. Chip size: 5.8*6.6mm, chip area: 38.28 square millimeters, significantly smaller than... Figure 2 51.06 square millimeters, and Figure 3 With a long-side to wide-side ratio of only 1.14, the chip is less prone to chip breakage and warping compared to traditional chips, thus improving chip reliability. Two sets (16 channels each) of tube cells are mirrored back-to-back, with the heat-generating areas of the tube cells spaced far apart, which facilitates heat dissipation and reduces tube cell junction temperature, thereby extending chip lifespan.

[0034] Based on the planar back-to-back power combining chip circuit technology of this invention, it is fabricated using GaN HEMT process. Within the 14-18GHz frequency band, under typical gate voltage of -2.0V and drain operating voltage of 28V (period 1ms, duty cycle 10%), the measured output power is ≥100W (50dBm). Test results are shown below. Figure 4 .

[0035] This invention doubles the output power of a single chip by mirroring two identical power amplifiers back to back, arranging two groups of tube cells (16 in each group) with parallel gate finger directions back to back, and passing the tube cells through an output matching network and then through a power combiner (PC).

[0036] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A planar back-to-back power combining power amplifier chip circuit, characterized in that, This includes the power input bonding pad RFin_PAD integrated on the substrate, the power distribution microstrip line MSL1, the bonding microstrip MSL2, the π-type attenuator, the power amplifier PA1, the power amplifier PA2, the power combining microstrip MSL3, the high-power isolation resistor R, and the power output bonding pad RFout_PAD. Power amplifiers PA1 and PA2 are arranged back-to-back on the substrate and symmetrically disposed thereon. The power input bonding point RFin_PAD is connected to the power distribution microstrip line MSL1, and then connected to the connecting microstrip line MSL2. The connecting microstrip line MSL2 is connected to a π-type attenuator, and then connected to the input terminals of the input matching networks IN_MN of power amplifiers PA1 and PA2 respectively. Each power amplifier includes an input matching network IN_MN, a first-stage cell, an inter-stage matching network IMN1, a second-stage cell, an inter-stage matching network IMN2, a third-stage cell, and an output matching network OUT_MN connected in sequence; wherein, the first stage has 4 cells, the second stage has 8 cells, and the third stage has 16 cells; and the gate finger directions of the first, second, and third-stage cells are all the same; the gate finger direction of the cells in power amplifier PA1 is opposite to the gate finger direction of the cells in power amplifier PA2; The output of the matching network OUT_MN is connected to the power combining microstrip MSL3, and the two power combining microstrips MSL3 are connected to the power output bonding pressure point RFout_PAD. A high-power isolation resistor R is connected between the input terminals of the two power combining microstrips MSL3; a ground via for electromagnetic isolation is added between the output matching network OUT_MN and the power combining microstrips MSL3.

2. The power amplifier chip circuit for planar back-to-back power combining according to claim 1, characterized in that, The duct cell gate fingers in power amplifiers PA1 and PA2 are arranged in parallel and back to back. The duct cells are connected to the output matching network OUT_MN and then to the power combiner PC to double the output power of a single chip.

3. The power amplifier chip circuit for planar back-to-back power combining according to claim 1, characterized in that, A ground via for electromagnetic isolation is added between the output matching network OUT_MN and the power combining microstrip MSL3 to reduce the inter-microstrip electromagnetic coupling between the output matching network OUT_MN and the power combining microstrip MSL3.

4. The power amplifier chip circuit for planar back-to-back power combining according to claim 1, characterized in that, A π-type attenuator is added between the connecting microstrip MSL2 and power amplifiers PA1 and PA2 to improve the isolation between the input ports of power amplifiers PA1 and PA2.

5. The power amplifier chip circuit for planar back-to-back power combining according to claim 1, characterized in that, A high-power isolation resistor R is connected between the input terminals of the two power combining microstrip lines MSL3 to improve the isolation between the output ports of power amplifiers PA1 and PA2.

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