operational amplifier

Abstract

The present disclosure provides an operational amplifier, which comprises: an input stage configured to amplify a common-mode input signal received at a corresponding input node and provide a first control signal in response; a first biasing circuit connected to an output of the aforementioned input stage, configured to generate a second control signal opposite to the first control signal according to the first control signal, and control the size of the second control signal by controlling its own circuit state; a second biasing circuit connected to the input stage and the first biasing circuit respectively, configured to control its own circuit state according to the first control signal, and control the size of the first control signal; and an output stage configured to provide an output current according to the first control signal or the second control signal. Thus, the driving capability and stability of the operational amplifier can be improved while ensuring the improvement of the circuit precision, and the operational amplifier also presents low power consumption characteristics.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and specifically to an operational amplifier. Background Technology

[0002] With the widespread application of digital-to-analog converters (DACs) and analog-to-digital converters (ADCs), high-speed operational amplifiers, as their core components, have received increasing attention and research. Speed ​​and accuracy are two important indicators of analog integrated circuits. However, improving speed depends on and is mutually restrictive of the op-amp's unity-gain bandwidth and single-pole characteristics, while accuracy is closely related to the op-amp's DC gain. In practical applications, a trade-off between these two indicators needs to be considered based on the characteristics of the op-amp.

[0003] Fully differential amplifiers generally include two structures: telescopic cascode and folded cascode. However, the telescopic cascode structure has two significant drawbacks: input common-mode limitation and difficulty in shorting the input and output. Therefore, most amplifiers use the folded cascode structure. If the folded cascode is considered as a single-stage amplifier, a traditional folded cascode amplifier requires an additional common-source amplifier stage at the output to increase gain. This circuit is called an operational transconductance amplifier (OTA). However, due to the high output resistance of the input stage and the limitation of the output swing by two saturation voltage drops, the current drive capability of this type of amplifier is very weak. To overcome these two drawbacks and provide sufficient output current in steady-state or transient conditions, a feedforward Class AB push-pull output structure is generally used. This allows for full-swing output at low voltage and ensures high power efficiency with low distortion.

[0004] like Figure 1As shown, a typical Class AB operational amplifier 100 includes: a differential amplifier stage (not shown) as the first part, serving as the input terminal; and a second part, wherein a folded cascode amplifier stage is provided, connected to the differential amplifier stage of the first part, such that the first part and the second part together constitute the first stage of amplification of the operational amplifier. The folded cascode amplifier stage includes: transistors MC1 and MC2 connected via cascode; transistors MC3, MC9, MC7, and MC5 connected in series between the drain of transistor MC1 and ground; transistors MC4, MC11, MC8, and MC6 connected in series between the drain of transistor MC2 and ground; and a first... The first voltage source Vb1 and the second voltage source Vb2 are connected together. The gates of transistors MC3 and MC4 are connected to the first voltage source Vb1, and the gates of transistors MC7 and MC8 are connected to the second voltage source Vb2. A first connection node is formed between transistors MC1 and MC3, and a second connection node is formed between transistors MC2 and MC4. The folded common-source common-gate amplifier stage is connected to the two current signals provided by the differential input stage of the first part through the first node and the second node. The third part is provided with an AB class bias circuit and a push-pull output stage, which are respectively connected to the circuit of the second part, so that the push-pull output stage constitutes the second stage of amplification of the operational amplifier under the control of the AB class bias circuit.

[0005] Figure 1 The AB-type feedforward output is achieved through a direct feedforward path coupled by transistors. Transistors M1 and M2 are output transistors, transistors MC11 and MC12 are floating voltage sources, transistors MC9 and MC10 are floating current sources, transistors MC1 and MC2 also serve as active loads for the differential input pair, transistors MC3 and MC4 are single-transistor cascode amplifiers, and transistors MC9 to MC12 participate in forming a transistor-coupled AB-type control circuit. This AB-type control circuit includes two loops: one is transistor M1-transistor MC11-transistor MC14-transistor MC13, and the other is transistor M2-transistor MC12-transistor MC15-transistor MC16. These two loops control the quiescent current of the output transistors.

[0006] However, when the (differential) operational amplifier circuit is used in combination with a conventional folded cascode amplifier, the amplifier can accommodate input signals that can swing all the way to one of the amplifier's power rails, but this approach still suffers from insufficient current and circuit stability issues. Summary of the Invention

[0007] To address the aforementioned technical problems, this disclosure provides an operational amplifier that can improve the driving capability and stability of the operational amplifier while ensuring improved circuit accuracy and increased voltage output dynamic range, and simultaneously enable the operational amplifier to exhibit low power consumption characteristics.

[0008] This disclosure provides an operational amplifier, including:

[0009] An input stage is configured to amplify the common-mode input signal received at the corresponding input node and provide a first control signal in response.

[0010] The first bias circuit is connected to the output terminal of the aforementioned input stage and is used to generate a second control signal that is inversely related to the first control signal, and to clamp the magnitude of the second control signal by controlling its own circuit state.

[0011] The second bias circuit is connected to the aforementioned input stage and the first bias circuit respectively, and is used to control its own circuit state according to the aforementioned first control signal, so as to clamp the magnitude of the first control signal.

[0012] The output stage has a first terminal for receiving the aforementioned first control signal and a second terminal for receiving the aforementioned second control signal, and is used to provide an output current according to the first control signal or the second control signal.

[0013] Furthermore, the aforementioned input levels include:

[0014] A first current source and a first transistor are connected in series. The first end of the first current source is connected to the positive power supply terminal to receive the positive power supply signal, and the second end is connected to the first end of the first transistor. The second end of the first transistor serves as the output terminal of the aforementioned input stage to provide the aforementioned first control signal. The connection node between the first current source and the first transistor serves as the aforementioned input node to receive the aforementioned common-mode input signal.

[0015] The first voltage source is connected between the positive power supply terminal and the control terminal of the first transistor.

[0016] Furthermore, the aforementioned first bias circuit includes:

[0017] A second transistor and a second current source are connected in series between the positive power supply terminal and the negative power supply terminal;

[0018] A third current source and a third transistor are connected in series between the positive power supply terminal and the negative power supply terminal. The control terminal of the third transistor is connected to the connection node between the aforementioned second transistor and the second current source, and the control terminal of the aforementioned second transistor is connected to the connection node between the aforementioned third current source and the third transistor.

[0019] A fourth transistor and a fourth current source are connected in series between the aforementioned first transistor and the negative power supply terminal. The connection node between the fourth transistor and the fourth current source serves as the output terminal of the aforementioned first bias circuit, used to provide the aforementioned second control signal. The control terminal of the fourth transistor is connected to the control terminal of the aforementioned second transistor.

[0020] Furthermore, the aforementioned second bias circuit includes:

[0021] A fifth transistor and a fifth current source are connected in series between the positive power supply terminal and the negative power supply terminal;

[0022] The sixth transistor has its first terminal connected to the output terminal of the aforementioned input stage, its second terminal connected to the output terminal of the aforementioned first bias circuit, and its control terminal connected to the connection node between the aforementioned fifth transistor and the fifth current source.

[0023] A sixth current source and a seventh transistor are connected in series between the positive power supply terminal and the negative power supply terminal. The control terminal of the seventh transistor is connected to the connection node between the aforementioned fifth transistor and the fifth current source, and the control terminal of the aforementioned fifth transistor is connected to the connection node between the aforementioned sixth current source and the seventh transistor.

[0024] Furthermore, the aforementioned output stage includes:

[0025] An eighth transistor and a ninth transistor are connected in series between the positive power supply terminal and the negative power supply terminal. The control terminal of the eighth transistor is connected to the output terminal of the aforementioned input stage as the aforementioned first terminal and receives the aforementioned first control signal. The control terminal of the ninth transistor is connected to the output terminal of the aforementioned first bias circuit as the aforementioned second terminal and receives the aforementioned second control signal. The connection node of the eighth transistor and the ninth transistor serves as the output terminal of the operational amplifier, providing the aforementioned output current.

[0026] Furthermore, when the aforementioned first control signal is at a low level, the aforementioned fourth transistor is turned off and the aforementioned eighth transistor is turned on. The aforementioned second bias circuit provides the aforementioned output current to the output terminal of the operational amplifier by proportionally mirroring the reference current of the aforementioned fifth current source.

[0027] When the aforementioned first control signal is at a high level, both the aforementioned fourth transistor and the aforementioned ninth transistor are turned on, and the aforementioned second bias circuit provides the aforementioned output current to the output terminal of the operational amplifier by proportionally mirroring the reference current of the aforementioned second current source.

[0028] Furthermore, the aforementioned third transistor and the aforementioned fourth transistor have the same turn-on threshold, and the width-to-length ratio of the aforementioned second transistor is proportional to the width-to-length ratio of the aforementioned ninth transistor. When the aforementioned ninth transistor is turned on, the aforementioned output current is proportional to the reference current provided by the aforementioned second current source.

[0029] Furthermore, the sixth transistor and the seventh transistor have the same turn-on threshold, and the width-to-length ratio of the fifth transistor is proportional to the width-to-length ratio of the eighth transistor. When the eighth transistor is turned on, the output current is proportional to the reference current provided by the fifth current source.

[0030] Furthermore, the aforementioned first transistor, fifth transistor, sixth transistor, seventh transistor, and eighth transistor are each selected from P-type metal-oxide-semiconductor field-effect transistors.

[0031] The aforementioned second transistor, third transistor, fourth transistor, and ninth transistor are each selected from N-type metal-oxide-semiconductor field-effect transistors.

[0032] Furthermore, the aforementioned input stage is connected to a common-mode signal generation circuit via the aforementioned input node. This common-mode signal generation circuit generates the aforementioned common-mode input signal through a differential input signal with a common-mode component.

[0033] The beneficial effects of this disclosure are: the operational amplifier provided by this disclosure can amplify the common-mode input signal received at the corresponding input node using the input stage, and provide a first control signal as a response. By introducing a single-ended common-mode input signal to replace the differential input signal with dual-ended input in the prior art, the influence caused by the fluctuation of the node voltage of the output node when there is a certain difference between the differential input signals is avoided.

[0034] This operational amplifier uses a first bias circuit connected to the input stage output to generate a second control signal inversely to a first control signal, and clamps the magnitude of the second control signal by controlling its own circuit state. It also uses a second bias circuit connected to both the input stage and the first bias circuit to control its own circuit state according to the first control signal, thereby clamping the magnitude of the first control signal. Finally, the output stage provides output current based on either the first or second control signal it receives. By simplifying the operational amplifier's circuit structure, not only is one input current path saved, but the driving capability and stability of the operational amplifier are improved while ensuring increased circuit accuracy and voltage output dynamic range. Simultaneously, the operational amplifier exhibits low power consumption characteristics.

[0035] Meanwhile, the operational amplifier can control the width-to-length ratio of the first bias circuit, the second bias circuit, and the associated transistors in the output stage to be proportional. By adjusting the magnitude of the reference current source on the corresponding circuit, the transistors in the output stage can be made to operate in the saturation region, ensuring the total voltage gain of the operational amplifier across the entire common-mode input voltage range. Attached Figure Description

[0036] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments of this disclosure with reference to the accompanying drawings.

[0037] Figure 1 A circuit diagram of a typical Class AB operational amplifier provided in the prior art is shown;

[0038] Figure 2 A circuit diagram of an operational amplifier provided in an embodiment of this disclosure is shown. Detailed Implementation

[0039] To facilitate understanding of this disclosure, a more complete description will be given below with reference to the accompanying drawings, which illustrate preferred embodiments of the present disclosure. However, this disclosure may be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the contents of this disclosure.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0041] It should be understood that, in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by an electrical or electromagnetic link. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to the other element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0042] In this application, the MOSFET includes a first terminal, a second terminal, and a control terminal. When the MOSFET is in the on state, current flows from the first terminal to the second terminal. The first terminal, the second terminal, and the control terminal of the P-type MOSFET are the source, the drain, and the gate, respectively, and the first terminal, the second terminal, and the control terminal of the N-type MOSFET are the drain, the source, and the gate, respectively.

[0043] Common-mode voltage range refers to the range of voltage signals acceptable at the amplifier input. As explained herein, for an operational amplifier, such as one that can use differential transistor pairs to sense the differential voltage signal at its input, circuitry can be configured to receive a differential input signal with a common-mode component to generate the common-mode input signal required for the operational amplifier's input node, thereby ensuring common-mode operation that accommodates signals having a magnitude substantially the same as at least one signal on the amplifier's power rails.

[0044] The present disclosure will now be described in detail with reference to the accompanying drawings.

[0045] Figure 2 A circuit diagram of an operational amplifier provided in an embodiment of this disclosure is shown.

[0046] refer to Figure 2 This disclosure provides an operational amplifier 200, which includes at least: an input stage 210, a first bias circuit 220, a second bias circuit 230, and an output stage 240.

[0047] The input stage 210 is configured to amplify the common-mode input signal received at the corresponding input node VIN and provide a first control signal V1 in response. The first bias circuit 220 is connected to the output of the input stage 210 and is used to generate a second control signal V2 that is inversely related to the first control signal V1, and to clamp the magnitude of the second control signal V2 by controlling its own circuit state. The second bias circuit 230 is connected to the aforementioned input stage 210 and the first bias circuit 220 respectively, and is used to control its own circuit state according to the first control signal V1 to clamp the magnitude of the first control signal V1. The output stage 240 has a first terminal for receiving the first control signal V1 and a second terminal for receiving the second control signal V2, and is used to provide an output current according to the first control signal V1 or the second control signal V2.

[0048] In this embodiment, the aforementioned input stage 210 includes:

[0049] A first current source I1 and a first transistor M1 are connected in series. The first end of the first current source I1 is connected to the positive power supply terminal VDD to receive the positive power supply signal VDD, and the second end is connected to the first end of the first transistor M1. The second end of the first transistor M1 serves as the output terminal of the aforementioned input stage 210, providing the aforementioned first control signal V1. The connection node between the first current source I1 and the first transistor M1 serves as the aforementioned input node VIN, receiving the aforementioned common-mode input signal.

[0050] A first voltage source is connected between the positive power supply terminal VDD and the control terminal of the first transistor M1 to provide a first bias voltage Vb1 to control the conduction of the first transistor M1.

[0051] In this embodiment, the aforementioned first bias circuit 220 includes:

[0052] The second transistor M2 and the second current source I2 are connected in series between the positive power supply terminal VDD and the negative power supply terminal VSS;

[0053] A third current source I3 and a third transistor M3 are connected in series between the positive power supply terminal VDD and the negative power supply terminal VSS. The control terminal of the third transistor M3 is connected to the connection node of the aforementioned second transistor M2 and the second current source I2, and the control terminal of the aforementioned second transistor M2 is connected to the connection node of the aforementioned third current source I3 and the third transistor M3.

[0054] A fourth transistor M4 and a fourth current source I4 are connected in series between the first transistor M1 and the negative power supply terminal VSS. The connection node of the fourth transistor M4 and the fourth current source I4 serves as the output terminal of the first bias circuit 220, which is used to provide the second control signal V2. The control terminal of the fourth transistor M4 is connected to the control terminal of the second transistor M2.

[0055] In this embodiment, the aforementioned second bias circuit 230 includes:

[0056] The fifth transistor M5 and the fifth current source I5 are connected in series between the positive power supply terminal VDD and the negative power supply terminal VSS.

[0057] The sixth transistor M6 has its first terminal connected to the output terminal of the aforementioned input stage 210, its second terminal connected to the output terminal of the aforementioned first bias circuit 220, and its control terminal connected to the connection node between the aforementioned fifth transistor M5 and the fifth current source I5.

[0058] A sixth current source I6 and a seventh transistor M7 are connected in series between the positive power supply terminal VDD and the negative power supply terminal VSS. The control terminal of the seventh transistor M7 is connected to the connection node of the aforementioned fifth transistor M5 and the fifth current source I5, and the control terminal of the aforementioned fifth transistor M5 is connected to the connection node of the aforementioned sixth current source I6 and the seventh transistor M7.

[0059] In this embodiment, the aforementioned output stage 240 includes:

[0060] The eighth transistor M8 and the ninth transistor M9 are connected in series between the positive power supply terminal VDD and the negative power supply terminal VSSVSS. The control terminal of the eighth transistor M8 is connected as the first terminal to the output terminal of the input stage 210 and connected to the first control signal V1. The control terminal of the ninth transistor M9 is connected as the second terminal to the output terminal of the first bias circuit 220 and connected to the second control signal V2. The connection node of the eighth transistor M8 and the ninth transistor M9 serves as the output terminal VOUT of the operational amplifier, providing the aforementioned output current.

[0061] Furthermore, the aforementioned first transistor M1, fifth transistor M5, sixth transistor M6, seventh transistor M7 and eighth transistor M8 are selected from P-type metal-oxide-semiconductor field-effect transistors (MOSFETs, hereinafter referred to as MOS transistors), and the aforementioned second transistor M2, third transistor M3, fourth transistor M4 and ninth transistor M9 are selected from N-type MOS transistors.

[0062] In this embodiment, the first transistor M1, which is turned on under the control of the first bias voltage Vb1, serves as the first-stage amplifier. It amplifies the input common-mode input signal and outputs the first control signal V1. By introducing a single-ended common-mode input signal to replace the differential input signal with a double-ended input in the prior art, the influence caused by the fluctuation of the node voltage of the output node when there is a certain difference between the differential input signals is avoided.

[0063] contrast Figure 1 There are existing Class AB operational amplifiers in China. Figure 2 The difference in the embodiments shown in this disclosure is that when the aforementioned first control signal V1 is at a low level, the aforementioned fourth transistor M4 is turned off and the aforementioned eighth transistor M8 is turned on, and the aforementioned second bias circuit 230 provides the aforementioned output current to the output terminal of the operational amplifier by proportionally mirroring the reference current of the aforementioned fifth current source I5; when the aforementioned first control signal V1 is at a high level, the aforementioned fourth transistor M4 and the aforementioned ninth transistor M9 are both turned on, and the aforementioned second bias circuit 230 provides the aforementioned output current to the output terminal of the operational amplifier by proportionally mirroring the reference current of the aforementioned second current source I2.

[0064] In this embodiment, the conduction thresholds of the third transistor M3 and the fourth transistor M4 are equal, and the width-to-length ratio of the second transistor M2 is proportional to the width-to-length ratio of the ninth transistor M9. When the ninth transistor M9 is turned on, the output current output is proportional to the reference current provided by the second current source I2. The conduction thresholds of the sixth transistor M6 and the seventh transistor M7 are equal, and the width-to-length ratio of the fifth transistor M5 is proportional to the width-to-length ratio of the eighth transistor M8. When the eighth transistor M8 is turned on, the output current output is proportional to the reference current provided by the fifth current source I5.

[0065] The operational amplifier 200 biases the eighth transistor M8 and the ninth transistor M9, which constitute rail-to-rail output, at a certain quiescent current by connecting the first bias circuit 220 to the ninth transistor M9 of the output stage and the second bias circuit 230 to the eighth transistor M8 of the output stage. This ensures the low power consumption of the operational amplifier 200, while also providing a large output current when needed.

[0066] Specifically, in this embodiment, the first bias circuit 220 is equipped with a third transistor M3 and a fourth transistor M4 that are matched and have a proportional width-to-length ratio, and a second transistor M2 is configured to match the ninth transistor M9 and have a proportional width-to-length ratio. The source current of the second transistor M2 is controlled by the second current source I2. By configuring the second transistor M2, the third transistor M3, and the fourth transistor M4 in the first bias circuit 220 as shown in the figure, when the second control signal V2 is valid, the second control signal V2, i.e., the gate control voltage of the ninth transistor M9, is numerically equal to the sum of the conduction threshold (Vth) of the third transistor M3 and the conduction threshold of the third transistor M3, minus the conduction threshold of the fourth transistor M4. The conduction threshold of the third transistor M3 is set to be equal to that of the fourth transistor M4. Therefore, the conduction threshold of the second transistor M2 is equal to the value of the second control signal V2 connected to the gate of the ninth transistor M9. The second transistor M2 and the ninth transistor M9 are matched and their width-to-length ratio is proportional. Therefore, the output current of the ninth transistor M9 is matched with the source current of the second transistor M2 and they are in a fixed ratio. That is, the drain current of the ninth transistor M9 is a fixed ratio of the reference current provided by the second current source I2. This fixed ratio is equal to the width-to-length ratio of the ninth transistor M9 and the second transistor M2. It does not change with the common-mode input signal and the power supply voltage, thereby improving the driving capability and stability of the operational amplifier 200.

[0067] Similarly, the second bias circuit 230 is equipped with a sixth transistor M6 and a seventh transistor M7 that are matched and have a proportional width-to-length ratio, and a fifth transistor M5 that is matched and has a proportional width-to-length ratio with the eighth transistor M8. The drain current of the fifth transistor M5 is controlled by the fifth current source I5. By setting the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 in the second bias circuit 230 to the connection relationship shown in the figure, when the first control signal V1 is valid, the first control signal V1, i.e., the gate control voltage of the eighth transistor M8, is numerically the sum of the conduction threshold (Vth) of the fifth transistor M5 and the conduction threshold of the seventh transistor M7, minus the conduction threshold of the sixth transistor M6. The conduction threshold of the sixth transistor M6 is set to be equal to that of the seventh transistor M7. Therefore, the conduction threshold of the fifth transistor M5 is equal to the value of the first control signal V1 connected to the gate of the eighth transistor M8. The fifth transistor M5 and the eighth transistor M8 are matched and their width-to-length ratio is proportional. Therefore, the output current of the eighth transistor M8 is matched with the drain current of the fifth transistor M5 and they are in a fixed ratio. That is, the drain current of the eighth transistor M8 is a fixed ratio of the reference current provided by the fifth current source I5. This fixed ratio is equal to the width-to-length ratio of the eighth transistor M8 and the fifth transistor M5. It does not change with the common-mode input signal and the power supply voltage, thereby improving the driving capability and stability of the operational amplifier 200.

[0068] Therefore, the quiescent currents of the eighth transistor M8 and the ninth transistor M9 in the output stage are precisely controlled. By simplifying the circuit structure of the operational amplifier 200, not only is one input current path saved, but the driving capability and stability of the operational amplifier 200 are also improved while ensuring increased circuit accuracy and voltage output dynamic range, and the operational amplifier 200 exhibits low power consumption characteristics.

[0069] The operational amplifier 200 includes two loops: one loop connects the eighth transistor M8, the sixth transistor M6, the seventh transistor M7, and the fifth transistor M5; the other loop connects the ninth transistor M9, the fourth transistor M4, the third transistor M3, and the second transistor M2. These loops control the quiescent current of the output transistors (M8 and M9). The operational amplifier 200 can proportionally control the width-to-length ratio of the associated transistors in the first bias circuit 220, the second bias circuit 230, and the output stage 240. By adjusting the magnitude of the reference current source (I2 or I5) in the corresponding loop, the transistors in the output stage can be made to operate in the saturation region, ensuring the total voltage gain of the operational amplifier across the entire common-mode input voltage range.

[0070] Optionally, in the description of the embodiments of this disclosure, the aforementioned input stage 210 may be connected to a common-mode signal generation circuit (not shown) via the aforementioned input node VIN. The common-mode signal generation circuit can generate the aforementioned common-mode input signal through differential input signals with common-mode components, so as to avoid the influence caused by the fluctuation of the node voltage of the output node when there is a certain difference between the differential input signals in the prior art.

[0071] It should be noted that, in the description of this disclosure, the terms "upper," "lower," "inner," etc., which indicate orientation or positional relationship, are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the components or elements referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0072] Furthermore, throughout this document, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0073] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating this disclosure and are not intended to limit the implementation. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of this disclosure.

Claims

1. An operational amplifier, comprising: An input stage is configured to amplify the common-mode input signal received at the corresponding input node and provide a first control signal in response. A first bias circuit is connected to the output terminal of the input stage and is used to generate a second control signal that is inversely related to the first control signal, and to clamp the magnitude of the second control signal by controlling its own circuit state. The second bias circuit is connected to the input stage and the first bias circuit respectively, and is used to control its own circuit state according to the first control signal in order to clamp the magnitude of the first control signal. The output stage has a first terminal for receiving the first control signal and a second terminal for receiving the second control signal, and is used to provide an output current according to the first control signal or the second control signal. The input stage includes: A first current source and a first transistor are connected in series. The first end of the first current source is connected to the positive power supply terminal to receive the positive power supply signal, and the second end is connected to the first end of the first transistor. The second end of the first transistor serves as the output terminal of the input stage to provide the first control signal, and the connection node between the first current source and the first transistor serves as the input node to receive the common-mode input signal. A first voltage source is connected between the positive power supply terminal and the control terminal of the first transistor.

2. The operational amplifier according to claim 1, wherein, The first bias circuit includes: A second transistor and a second current source are connected in series between the positive power supply terminal and the negative power supply terminal; A third current source and a third transistor are connected in series between the positive power supply terminal and the negative power supply terminal. The control terminal of the third transistor is connected to the connection node of the second transistor and the second current source, and the control terminal of the second transistor is connected to the connection node of the third current source and the third transistor. A fourth transistor and a fourth current source are connected in series between the first transistor and the negative power supply terminal. The connection node of the fourth transistor and the fourth current source serves as the output terminal of the first bias circuit, which is used to provide the second control signal. The control terminal of the fourth transistor is connected to the control terminal of the second transistor.

3. The operational amplifier according to claim 2, wherein, The second bias circuit includes: A fifth transistor and a fifth current source are connected in series between the positive power supply terminal and the negative power supply terminal; The sixth transistor has its first terminal connected to the output terminal of the input stage, its second terminal connected to the output terminal of the first bias circuit, and its control terminal connected to the connection node between the fifth transistor and the fifth current source. A sixth current source and a seventh transistor are connected in series between the positive power supply terminal and the negative power supply terminal. The control terminal of the seventh transistor is connected to the connection node of the fifth transistor and the fifth current source, and the control terminal of the fifth transistor is connected to the connection node of the sixth current source and the seventh transistor.

4. The operational amplifier according to claim 3, wherein, The output stage includes: An eighth transistor and a ninth transistor are connected in series between the positive power supply terminal and the negative power supply terminal. The control terminal of the eighth transistor is connected as the first terminal to the output terminal of the input stage and receives the first control signal. The control terminal of the ninth transistor is connected as the second terminal to the output terminal of the first bias circuit and receives the second control signal. The connection node of the eighth transistor and the ninth transistor serves as the output terminal of the operational amplifier, providing the output current.

5. The operational amplifier according to claim 4, wherein, When the first control signal is at a low level, the fourth transistor is turned off and the eighth transistor is turned on. The second bias circuit provides the output current to the output terminal of the operational amplifier by proportionally mirroring the reference current of the fifth current source. When the first control signal is at a high level, both the fourth transistor and the ninth transistor are turned on, and the second bias circuit provides the output current to the output terminal of the operational amplifier by proportionally mirroring the reference current of the second current source.

6. The operational amplifier according to claim 5, wherein, The third transistor has the same turn-on threshold as the fourth transistor, and the width-to-length ratio of the second transistor is proportional to the width-to-length ratio of the ninth transistor. When the ninth transistor is turned on, the output current is proportional to the reference current provided by the second current source.

7. The operational amplifier according to claim 5, wherein, The sixth transistor has the same turn-on threshold as the seventh transistor, and the width-to-length ratio of the fifth transistor is proportional to the width-to-length ratio of the eighth transistor. When the eighth transistor is turned on, the output current is proportional to the reference current provided by the fifth current source.

8. The operational amplifier according to claim 5, wherein, The first transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are each selected from P-type metal-oxide-semiconductor field-effect transistors. The second transistor, the third transistor, the fourth transistor, and the ninth transistor are each selected from N-type metal-oxide-semiconductor field-effect transistors.

9. The operational amplifier according to claim 1, wherein, The input stage is connected to a common-mode signal generation circuit through the input node. The common-mode signal generation circuit generates the common-mode input signal through a differential input signal with a common-mode component.

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