Frequency multiplication signal generation method and frequency multiplication signal generator

Abstract

This invention provides a method and generator for generating a frequency multiplication signal, relating to the field of multi-sensor signal synchronization technology. The method includes: determining a clock timer frequency based on the microcontroller's main frequency, frequency division sequence, and the target multiplication frequency of the signal to be output; determining a counter maximum value based on the clock timer frequency and the target multiplication frequency; determining a counter comparison value based on the counter maximum value and the duty cycle of the signal to be output; resetting the counter to 0 upon receiving an external interrupt signal, and simultaneously controlling the clock comparator to output a valid level signal for the first cycle of the signal to be output, with the valid edge of the valid level signal aligned with the valid edge of the external interrupt signal; subsequently, when the counter count reaches the counter comparison value or 0, controlling the clock comparator to output a level signal opposite to the previous level signal to generate the frequency multiplication signal. This invention enables the accurate alignment of trigger signals from multiple sensors with the PPS signal at a multiple of each other at low cost.

Description

Technical Field

[0001] This invention relates to the field of multi-sensor signal synchronization technology, and in particular to a method for generating frequency-doubled signals and a frequency-doubled signal generator. Background Technology

[0002] In multi-sensor systems, synchronizing the sampling times of various sensors is a common challenge. Traditional solutions use a clock timer to send sampling signals, synchronizing the time before sending the signals, and then sampling by each sensor at predefined time points. For cost-sensitive applications, this approach struggles to achieve millisecond-level synchronization within cost constraints.

[0003] In autonomous driving systems, synchronizing the sampling signals of various sensors is an even more critical issue. Due to the strict system timing design, it is often necessary not only to synchronize the individual sensors but also to synchronize with the GPS pulses per second (PPS) signal. Sensor trigger signals are typically no more than a hundred times per second, but the PPS signal is fixed at once per second. How to accurately align the sensor trigger signals with the PPS signal in a multiple relationship is a pressing technical problem that needs to be solved. Summary of the Invention

[0004] This invention provides a method for generating frequency harmonic signals and a frequency harmonic signal generator to solve the aforementioned technical problems existing in the prior art.

[0005] This invention provides a method for generating a frequency harmonic signal, comprising:

[0006] The clock timer frequency is determined based on the microcontroller's main frequency, frequency division sequence, and the target multiplier of the multiplier signal to be output.

[0007] The maximum value of the counter is determined based on the clock timer frequency and the target multiplier.

[0008] The counter comparison value is determined based on the maximum value of the counter and the duty cycle of the frequency multiplication signal to be output;

[0009] When an external interrupt signal is received, the counter is reset to 0, and the clock comparator is controlled to output the first cycle of the frequency multiplier signal to be output. The effective edge of the effective level signal is aligned with the effective edge of the external interrupt signal. Then, when the counter count reaches the counter comparison value or 0, the clock comparator is controlled to output a level signal opposite to the previous level signal, thereby generating and outputting the frequency multiplier signal to be output.

[0010] According to the present invention, a method for generating a frequency multiplication signal is provided, which determines the clock timer frequency based on the target frequency multiplication to be output, the microcontroller main frequency, and the frequency division sequence, including:

[0011] The frequency range of the clock timer is determined based on the target multiplication frequency;

[0012] The number of frequency divisions is calculated from the frequency division sequence based on the clock timer frequency range and the microcontroller main frequency.

[0013] The clock timer frequency is calculated based on the frequency division number and the microcontroller's main frequency, using the following formula:

[0014] f t = f c / γ ;

[0015] in, f t Indicates the clock timer frequency. f c Indicates the microcontroller's main frequency. γ This is the frequency division number.

[0016] According to a frequency multiplication signal generation method provided by the present invention, determining a counter maximum value based on the clock timer frequency and the target multiplication frequency includes: calculating the counter maximum value according to the clock timer frequency and the target multiplication frequency using the following formula. RA :

[0017] RA = f t / f out ;

[0018] in, f t Indicates the clock timer frequency. f out Indicates the target frequency multiplication factor.

[0019] According to a method for generating a frequency multiplication signal provided by the present invention, determining a counter comparison value based on the maximum value of the counter and the duty cycle of the frequency multiplication signal to be output includes: determining the counter comparison value according to the following formula. RB :

[0020] RB = α · RA ;

[0021] in, α It is the ratio of the width of the effective level signal in the frequency multiplier signal to the period of the frequency multiplier signal to be output.

[0022] According to the frequency multiplication signal generation method provided by the present invention, the external interrupt signal is the PPS signal of the positioning and navigation system.

[0023] According to the frequency doubling signal generation method provided by the present invention, the positioning and navigation system is a GPS system, a Beidou satellite navigation system, a Galileo satellite navigation system, or a GLONASS satellite navigation system.

[0024] According to a method for generating a frequency-doubled signal provided by the present invention, the frequency-doubled signal to be output is used as a synchronous sampling trigger signal for sensors in an autonomous driving system.

[0025] The present invention also provides a frequency multiplication signal generator, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the frequency multiplication signal generation method as described above.

[0026] The present invention also provides a sensor trigger signal generation system, comprising: a positioning and navigation system, a sensor, and the aforementioned frequency multiplier signal generator, wherein the PPS signal generated by the positioning and navigation system is input to the frequency multiplier signal generator as an external interrupt signal, the frequency multiplier signal generator generates a frequency multiplier signal corresponding to the PPS signal, and inputs the frequency multiplier signal to the sensor as a synchronous sampling trigger signal.

[0027] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the frequency multiplication signal generation method as described above.

[0028] The present invention provides a method and generator for generating frequency multiplication signals. The method involves determining the clock / timer frequency based on the microcontroller's main frequency, frequency division sequence, and the target multiplication frequency of the output frequency multiplication signal; determining the counter's maximum value based on the clock / timer frequency and the target multiplication frequency; determining the counter comparison value based on the counter's maximum value and the duty cycle of the output frequency multiplication signal; and, upon receiving an external interrupt signal, resetting the counter to 0 and simultaneously controlling the clock comparator to output a level signal consistent with the external interrupt signal. Then, when the counter count reaches the counter comparison value or 0, the clock comparator outputs a level signal opposite to the previous level signal, thereby generating the frequency multiplication signal. This invention determines the microcontroller's clock / timer frequency, counter's maximum value, and comparison value by working backward from the target multiplication frequency and duty cycle of the output target frequency multiplication signal. Finally, the clock comparator generates the frequency multiplication signal based on the external interrupt signal and the counter comparison value. This method of generating frequency multiplication signals is low-cost, highly stable, and can quickly achieve sub-millisecond level synchronization accuracy. It can also achieve continuous natural number frequency multiplication, making it suitable for 100Hz-level sensor applications. In multi-sensor systems, it is possible to achieve accurate alignment of trigger signals from multiple sensors with the PPS signal at a multiple ratio at low cost. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0030] Figure 1 This is a flowchart illustrating the frequency multiplication signal generation method provided by the present invention;

[0031] Figure 2 This is an example diagram of the output of a 50Hz frequency-doubled signal in the frequency-doubled signal generation method of the present invention;

[0032] Figure 3 This is a schematic diagram of the frequency multiplication signal generation device provided by the present invention;

[0033] Figure 4 This is a schematic diagram of the sensor trigger signal generation system provided by the present invention. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0035] The frequency harmonic signal generation method of this invention, as described in the embodiments, is as follows: Figure 1 As shown, the method includes:

[0036] Step S110: Determine the clock timer frequency based on the microcontroller's main frequency, frequency division sequence, and the target multiplier frequency of the multiplier signal to be output. In this embodiment, the microcontroller has a timer and pulse width modulation (PWM) output function. The PWM output function is used to adjust the pulse width or duty cycle of the multiplier signal during subsequent multiplier signal generation. The microcontroller can be an industrial-grade microcontroller unit (MCU) with strong IO drive capability, such as an ATMEL MEGA128P or a Cortex 0-level chip. Preferably, the driving frequency of the microcontroller's clock timer should be at least 10 times greater than the target multiplier frequency. 3 This is beneficial for frequency calculation and clock divider settings, reducing errors. The microcontroller's clock counter is best set to a 16-bit or 32-bit counter; an 8-bit counter will have errors.

[0037] Step S120: Determine the maximum value of the counter based on the clock timer frequency and the target frequency multiplication, such that the time it takes for the counter to count from 0 to the maximum value is exactly one cycle of the frequency multiplication signal to be output.

[0038] Step S130: Determine the counter comparison value based on the maximum value of the counter and the duty cycle of the frequency multiplication signal to be output. The comparison value is used to convert the output of the clock comparator after the counter count reaches the comparison value.

[0039] Step S140: Upon receiving an external interrupt signal, reset the counter to 0, and simultaneously control the clock comparator to output a valid level signal for the first cycle of the frequency multiplier signal to be output. The valid edge of this valid level signal is aligned with the valid edge of the external interrupt signal. Then, when the counter count reaches the counter comparison value or 0, control the clock comparator to output a level signal opposite to the previous level signal, thereby generating and outputting the frequency multiplier signal to be output. It should be noted that when the counter count reaches its maximum value, it will restart counting from 0.

[0040] In the frequency multiplication signal generation method of this invention, the clock timer frequency, counter maximum value, and comparison value of the microcontroller are determined by reverse calculation based on the target multiplication frequency and duty cycle of the output frequency multiplication signal. Finally, the clock comparator generates the frequency multiplication signal based on the external interrupt signal and the counter comparison value. This invention provides a low-cost and highly stable method for generating frequency multiplication signals, enabling rapid sub-millisecond level synchronization and continuous natural number frequency multiplication, making it suitable for 100Hz-level sensor applications. In multi-sensor systems, it can cost-effectively align the trigger signals of multiple sensors with the PPS signal in a multiple relationship.

[0041] In this embodiment, step S110 includes:

[0042] The frequency range of the clock timer is determined based on the target multiplier.

[0043] The number of divisions is calculated from the division sequence based on the clock timer frequency range and the microcontroller main frequency.

[0044] The clock timer frequency is calculated based on the frequency division number and the microcontroller's main frequency, using the following formula:

[0045] f t = f c / γ ;

[0046] in, f t Indicates the clock timer frequency. f c Indicates the microcontroller's main frequency. γ The frequency division number, i.e. γ It is the division number of the microcontroller's frequency divider, which is usually set to [1, 2, 4, 8, 16, 32, 64, 128 … ].

[0047] In this embodiment, we will use a 16-bit counter, a 16MHz MCU main frequency, an external interrupt signal (i.e., the GPS PPS signal with a frequency of 1Hz as the input, which is a high-level signal valid on the rising edge), and a target frequency multiplier of 50Hz as the output for illustration. Figure 2 As shown, the goal of this embodiment is to generate a 50Hz frequency multiplier signal, which is a high-level signal, active on the rising edge, and align the 50Hz frequency multiplier signal to a 1Hz PPS reference clock, with their rising edges aligned. The duty cycle TH:TL = 1:1, TH = TL = 10ms, and the period is 20ms. Figure 2 The input is the external interrupt signal, and the output is the frequency multiplier signal to be output. In this example, the input is the GPS PPS signal, and the frequency multiplier signal to be output is a 50Hz frequency multiplier signal.

[0048] The target output frequency multiplier is 50 Hz, with each cycle lasting 20 ms. If a timing error of 1% (±0.2 ms) is required, the clock frequency must be at least 10 times the target frequency multiplier. 3 times, then f t A suitable value range is on the order of 100 kHz, which can achieve an error one order of magnitude higher than the target accuracy, meaning smaller error and higher precision. (Microcontroller main frequency) f c At 16MHz, f t When the frequency division number is in the range of 100 kHz, γ Choosing 128, the clock timer frequency is finally calculated using the formula above. f t It is 125KHz.

[0049] Step S120 includes: calculating the maximum value of the counter according to the clock timer frequency and the target multiplier using the following formula. RA :

[0050] RA = f t / f out ;

[0051] in, f t Indicates the clock timer frequency. f out To represent the target multiplication frequency, using the example above, we can obtain... RA =2500, meaning the counter counts 2500 times within one cycle of the frequency multiplication signal.

[0052] Step S130 includes: determining the counter comparison value according to the following formula. RB :

[0053] RB = α · RA ;

[0054] in, α This is the ratio of the width of the effective level signal to the period of the output frequency multiplier signal. In the example above, since the duty cycle TH:TL of the output frequency multiplier signal is 1:1, the period is 20ms, and the width of the high-level signal (i.e., the pulse width) is 10ms, therefore... α = 0.5, that is RB =1250.

[0055] Continuing the example above, in step S140, when the GPS PPS signal occurs, the counter is set to 0 to synchronize with the PPS signal. At this time, the clock comparator COMP_OUTPUT outputs a high-level signal, with its rising edge aligned with the rising edge of the PPS signal. The counter then continues to accumulate. At 10ms, the counter value reaches 1250, which is the counter comparison value, and the clock comparator COMP_OUTPUT outputs a low level. At 20ms, the counter value reaches its maximum value of 2500, at which point the counter is reset to 0, and the clock comparator COMP_OUTPUT outputs a high level. This process repeats to achieve frequency multiplication and synchronization with the PPS signal.

[0056] In this embodiment, the external interrupt signal is the PPS signal of the positioning and navigation system. The positioning and navigation system is either the GPS system or the BeiDou satellite navigation system.

[0057] In the field of autonomous driving, the frequency-doubled signal can be used as the synchronous sampling trigger signal of sensors in an autonomous driving system, so as to achieve accurate alignment of the trigger signals of multiple sensors with the PPS signal at low cost.

[0058] The frequency doubling signal generation device provided by the present invention is described below. The frequency doubling signal generation device described below can be referred to in correspondence with the frequency doubling signal generation method described above.

[0059] like Figure 3 As shown, the frequency multiplication signal generation device of the present invention is implemented based on a microcontroller with timer and PWM output functions. The device includes:

[0060] The clock timer frequency determination module 310 is used to determine the clock timer frequency based on the microcontroller's main frequency, frequency division sequence, and the target frequency of the multiplier signal to be output.

[0061] The counter maximum value determination module 320 is used to determine the counter maximum value based on the clock timer frequency and the target multiplier.

[0062] The counter comparison value determination module 330 is used to determine the counter comparison value based on the maximum value of the counter and the duty cycle of the frequency multiplication signal to be output.

[0063] The frequency multiplier signal output module 340 is used to reset the counter to 0 when receiving an external interrupt signal, and at the same time control the clock comparator to output the first cycle of the frequency multiplier signal to be output, and the effective edge of the effective level signal is aligned with the effective edge of the external interrupt signal. Then, when the counter count reaches the counter comparison value or 0, the clock comparator is controlled to output a level signal opposite to the previous level signal, thereby generating and outputting the frequency multiplier signal to be output.

[0064] The frequency multiplication signal generation device of this invention determines the clock / timer frequency, counter maximum value, and comparison value of the microcontroller based on the target multiplication frequency and duty cycle of the output multiplication signal. Finally, the clock comparator generates the multiplication signal based on the external interrupt signal and the counter comparison value. This invention provides a low-cost, highly stable method for generating multiplication signals, achieving sub-millisecond level synchronization accuracy quickly, and enabling continuous natural number frequency multiplication, making it suitable for 100Hz-level sensor applications. In multi-sensor systems, it can cost-effectively align the trigger signals of multiple sensors to a multiple of the PPS signal.

[0065] Optionally, the clock timer frequency determination module 310 includes:

[0066] A frequency range determination module is used to determine the frequency range of the clock timer based on the target multiplication frequency.

[0067] The frequency division calculation module is used to calculate the frequency division number from the frequency division number sequence based on the frequency range of the clock timer and the main frequency of the microcontroller.

[0068] The frequency calculation module is used to calculate the clock timer frequency based on the frequency division number and the microcontroller's main frequency. The calculation formula is as follows:

[0069] f t = f c / γ ;

[0070] in, f t Indicates the clock timer frequency. f c Indicates the microcontroller's main frequency. γ This is the frequency division number.

[0071] Optionally, the counter maximum value determination module 320 is specifically used to calculate the counter maximum value according to the clock timer frequency and the target multiplier using the following formula. RA :

[0072] RA = f t / f out ;

[0073] in, f t Indicates the clock timer frequency. f out Indicates the target frequency multiplication factor.

[0074] Optionally, the counter comparison value determination module 330 is specifically used to determine the counter comparison value according to the following formula. RB :

[0075] RB = α · RA ;

[0076] in, α It is the ratio of the width of the effective level signal in the frequency multiplier signal to the period of the frequency multiplier signal to be output.

[0077] Optionally, the external interrupt signal is the PPS signal of the positioning and navigation system.

[0078] Optionally, the positioning and navigation system is a GPS system, a BeiDou satellite navigation system, a Galileo satellite navigation system, or a GLONASS satellite navigation system.

[0079] Optionally, the frequency-doubled signal to be output is used as a synchronous sampling trigger signal for sensors in an autonomous driving system.

[0080] The present invention also provides a frequency multiplier signal generator, which may include: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the frequency multiplier signal generation method, the method comprising:

[0081] The clock timer frequency is determined based on the microcontroller's main frequency, frequency division sequence, and the target multiplier of the multiplier signal to be output.

[0082] The maximum value of the counter is determined based on the clock timer frequency and the target multiplier.

[0083] The counter comparison value is determined based on the maximum value of the counter and the duty cycle of the frequency multiplication signal to be output.

[0084] When an external interrupt signal is received, the counter is reset to 0, and the clock comparator is controlled to output the first cycle of the frequency multiplier signal to be output. The effective edge of the effective level signal is aligned with the effective edge of the external interrupt signal. Then, when the counter count reaches the counter comparison value or 0, the clock comparator is controlled to output a level signal opposite to the previous level signal, thereby generating and outputting the frequency multiplier signal to be output.

[0085] In practical applications, the frequency multiplier signal generator is a microcontroller with timer and pulse width modulation (PWM) output functions. The program to implement the above method is written into the microcontroller's memory in the form of firmware.

[0086] Furthermore, the logical instructions in the aforementioned memory can be implemented as software functional units and sold or used as independent products, and can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0087] The present invention also provides a sensor trigger signal generation system, such as Figure 4 As shown, the system includes a positioning and navigation system 410, a sensor 420, and the aforementioned frequency multiplier signal generator 430. The PPS signal generated by the positioning and navigation system 410 is input to the frequency multiplier signal generator 430 as an external interrupt signal. The frequency multiplier signal generator 430 generates a frequency multiplier signal corresponding to the PPS signal and inputs the frequency multiplier signal as a synchronous sampling trigger signal to the sensor 420. This sensor trigger signal generation system can be used in the field of autonomous driving. In the field of autonomous driving, the positioning and navigation system 410 can be a GPS system, a BeiDou satellite navigation system, a Galileo satellite navigation system, or a GLONASS satellite navigation system. The sensor 420 consists of various sensors in the autonomous driving system, and the frequency multiplier signal generator 430 can be a microcontroller that implements the above method.

[0088] On the other hand, the present invention also provides a computer program product, the computer program product comprising a computer program that can be stored on a non-transitory computer-readable storage medium, wherein when the computer program is executed by a processor, the computer is able to execute the frequency multiplication signal generation method provided by the above methods, the method comprising:

[0089] The clock timer frequency is determined based on the microcontroller's main frequency, frequency division sequence, and the target multiplier of the multiplier signal to be output.

[0090] The maximum value of the counter is determined based on the clock timer frequency and the target multiplier.

[0091] The counter comparison value is determined based on the maximum value of the counter and the duty cycle of the frequency multiplication signal to be output.

[0092] When an external interrupt signal is received, the counter is reset to 0, and the clock comparator is controlled to output the first cycle of the frequency multiplier signal to be output. The effective edge of the effective level signal is aligned with the effective edge of the external interrupt signal. Then, when the counter count reaches the counter comparison value or 0, the clock comparator is controlled to output a level signal opposite to the previous level signal, thereby generating and outputting the frequency multiplier signal to be output.

[0093] In another aspect, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the frequency doubling signal generation method provided by the above methods, the method comprising:

[0094] The clock timer frequency is determined based on the microcontroller's main frequency, frequency division sequence, and the target multiplier of the multiplier signal to be output.

[0095] The maximum value of the counter is determined based on the clock timer frequency and the target multiplier.

[0096] The counter comparison value is determined based on the maximum value of the counter and the duty cycle of the frequency multiplication signal to be output.

[0097] When an external interrupt signal is received, the counter is reset to 0, and the clock comparator is controlled to output the first cycle of the frequency multiplier signal to be output. The effective edge of the effective level signal is aligned with the effective edge of the external interrupt signal. Then, when the counter count reaches the counter comparison value or 0, the clock comparator is controlled to output a level signal opposite to the previous level signal, thereby generating and outputting the frequency multiplier signal to be output.

[0098] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0099] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0100] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for generating a frequency harmonic signal, characterized in that, include: The clock timer frequency is determined based on the microcontroller's main frequency, frequency division sequence, and the target multiplier of the multiplier signal to be output. The maximum value of the counter is determined based on the clock timer frequency and the target multiplier. The counter comparison value is determined based on the maximum value of the counter and the duty cycle of the frequency multiplication signal to be output; When an external interrupt signal is received, the counter is reset to 0, and the clock comparator is controlled to output the first cycle of the frequency multiplier signal to be output. The effective edge of the effective level signal is aligned with the effective edge of the external interrupt signal. Then, when the counter count reaches the counter comparison value or 0, the clock comparator is controlled to output a level signal opposite to the previous level signal, thereby generating and outputting the frequency multiplier signal to be output.

2. The method for generating a frequency harmonic signal according to claim 1, characterized in that, The clock timer frequency is determined based on the microcontroller's main frequency, frequency division sequence, and the target multiplier of the output multiplier signal, including: The frequency range of the clock timer is determined based on the target multiplication frequency; The number of frequency divisions is calculated from the frequency division sequence based on the clock timer frequency range and the microcontroller main frequency. The clock timer frequency is calculated based on the frequency division number and the microcontroller's main frequency, using the following formula: f t = f c / γ ； in, f t Indicates the clock timer frequency. f c Indicates the microcontroller's main frequency. γ This is the frequency division number.

3. The method for generating a frequency harmonic signal according to claim 1, characterized in that, Determining the maximum counter value based on the clock timer frequency and the target multiplier includes: calculating the maximum counter value according to the following formula based on the clock timer frequency and the target multiplier. RA : RA = f t / f out ； in, f t Indicates the clock timer frequency. f out Indicates the target frequency multiplication factor.

4. The method for generating a frequency harmonic signal according to claim 1, characterized in that, Determining the counter comparison value based on the maximum value of the counter and the duty cycle of the frequency multiplication signal to be output includes: determining the counter comparison value according to the following formula. RB : RB = α · RA ； in, α It is the ratio of the width of the effective level signal in the frequency multiplier signal to the period of the frequency multiplier signal to be output.

5. The method for generating a frequency harmonic signal according to any one of claims 1 to 4, characterized in that, The external interrupt signal is the PPS signal of the positioning and navigation system.

6. The method for generating a frequency harmonic signal according to claim 5, characterized in that, The positioning and navigation system is GPS, BeiDou, Galileo, or GLONASS.

7. The method for generating a frequency harmonic signal according to claim 5, characterized in that, The frequency-doubled signal to be output is used as the synchronous sampling trigger signal for sensors in the autonomous driving system.

8. A frequency multiplier signal generator, comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, when the processor executes the program, it implements the frequency multiplication signal generation method as described in any one of claims 1 to 7.

9. A sensor trigger signal generation system, characterized in that, include: The positioning and navigation system, the sensor, and the frequency multiplier signal generator as described in claim 8, wherein the PPS signal generated by the positioning and navigation system is input to the frequency multiplier signal generator as an external interrupt signal, the frequency multiplier signal generator generates a frequency multiplier signal corresponding to the PPS signal, and inputs the frequency multiplier signal as a synchronous sampling trigger signal to the sensor.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the frequency multiplication signal generation method as described in any one of claims 1 to 7.

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