Schmitt trigger with current assist circuit

Abstract

Embodiments of the present disclosure relate to a Schmitt trigger with a current assist circuit. An integrated circuit includes an input pad and a Schmitt trigger coupled to the input pad. The Schmitt trigger includes a main PMOS branch that charges an intermediate node of the Schmitt trigger in response to a voltage transition at the input node. The Schmitt trigger includes a charge assist circuit that facilitates fast charging of the intermediate node of the Schmitt trigger. The charge assist circuit includes a parallel PMOS branch in parallel with the main PMOS branch.

Description

Technical Field

[0001] This disclosure relates to integrated circuits, and more particularly to input / output (I / O) circuits of integrated circuits. Background Technology

[0002] Integrated circuits typically include data input pads. These pads receive signals from external circuitry. These signals can include data signals that switch between low and high values ​​corresponding to data values ​​0 and 1. The data signals arriving at the input pads can have high values ​​significantly lower than the power supply voltage of the integrated circuit. Furthermore, the data signals may exhibit significant noise or other transient characteristics.

[0003] To properly process the data signals arriving at the input pads, integrated circuits typically include a driver circuit coupled to the input pads. The driver circuit receives the voltage at the input pads and outputs a data signal with a value corresponding to the pad data value. The data signal output by the driver circuit can be ground voltage (0) or the high power supply voltage of the integrated circuit (1).

[0004] An example of an input driver circuit is a Schmitt trigger. A Schmitt trigger typically includes two inverters. The first inverter inverts the data signal from the pads. The second inverter inverts the output of the first inverter, thus providing an output corresponding to the data value at the pads, but at the power supply voltage level of the integrated circuit. Schmitt triggers also include circuitry that introduces high and low thresholds to help control the transitions between high and low, and between high and low-high values, of the data signal at the pads. When transitioning from a low data value to a high data value, the output of the Schmitt trigger will not change from 0 to 1 unless the pad voltage exceeds the high threshold. When transitioning from a high data value to a low data value, the output of the Schmitt trigger will not change from 1 to 0 unless the pad voltage is less than the low threshold.

[0005] While Schmitt triggers are a useful input driver, various challenges also exist associated with them. For example, designing a Schmitt trigger with low quiescent current consumption typically results in a correspondingly low switching speed. Increasing the switching speed leads to a significant increase in area consumption. Summary of the Invention

[0006] Embodiments of this disclosure provide Schmitt triggers with low quiescent current consumption and high-frequency operation without high area consumption. The Schmitt trigger includes a charging auxiliary circuit that supplies a high supplemental charging current during transitions between data values, while having virtually no quiescent current consumption between transitions. The charging auxiliary circuit achieves this with very small additional area consumption.

[0007] The high supplemental charging current during the transition period enables the Schmitt trigger to operate very quickly. In other words, when the data value at the input pads of the integrated circuit changes, the output data value of the Schmitt trigger processes this change very quickly with the help of the supplemental charging current supplied by the charging auxiliary circuit. During the time period when the data value at the input pads does not change, the charging auxiliary circuit provides virtually no quiescent current. Therefore, the Schmitt trigger has a very high operating frequency and a very low quiescent current consumption. Attached Figure Description

[0008] Figure 1 This is a block diagram of an integrated circuit including a Schmitt trigger according to some embodiments.

[0009] Figure 2 This is a schematic diagram of an integrated circuit including a Schmitt trigger according to some embodiments.

[0010] Figure 3 According to some embodiments, including and Figure 2 The Schmitt trigger is associated with multiple voltage and current graphs.

[0011] Figure 4 This is a schematic diagram of an integrated circuit including a Schmitt trigger according to some embodiments.

[0012] Figure 5 This is a schematic diagram of a charging auxiliary circuit for a Schmitt trigger according to some embodiments.

[0013] Figure 6 This is a schematic diagram of a charging auxiliary circuit for a Schmitt trigger according to some embodiments.

[0014] Figure 7 This is a flowchart of a method for operating a Schmitt trigger according to some embodiments. Detailed Implementation

[0015] In the following description, certain specific details are set forth in order to provide a thorough understanding of the various disclosed embodiments. However, those skilled in the art will recognize that the embodiments can be practiced without one or more of these specific details or using other methods, components, materials, etc. In other instances, well-known algorithms and facial authentication associated with facial recognition, facial detection, and facial authentication are not shown or described in detail to avoid unnecessarily obscuring the description of the embodiments. Furthermore, well-known components and circuitry associated with memory arrays are not shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

[0016] Unless the context otherwise requires, the word “comprising” and its variations, such as “including” and “comprising of,” shall be interpreted in an open, inclusive sense, meaning “including, but not limited to,” in the following description and claims. Furthermore, unless the context expressly provides otherwise, the terms “first,” “second,” and similar sequence indicators shall be interpreted as interchangeable.

[0017] Throughout this specification, references to "an embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Therefore, the phrases "in an embodiment" or "in one embodiment" appearing in various places throughout the specification do not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0018] As used in this specification and the appended claims, the singular forms “a,” “an,” and “this” include plural indicators unless otherwise expressly provided. It should also be noted that the term “or” is generally used in its broadest sense, meaning “and / or,” unless otherwise expressly provided.

[0019] Figure 1 This is a block diagram of an integrated circuit 100 according to some embodiments. The integrated circuit includes an input pad 102 and a Schmitt trigger 103. The Schmitt trigger 103 serves as an input driver for the input pad 102. As will be described in more detail below, the Schmitt trigger 103 provides high-frequency operation with low quiescent current consumption.

[0020] Integrated circuit 100 may include multiple pads. Each pad corresponds to a terminal of the integrated circuit. Integrated circuit 100 may include a semiconductor die having multiple transistors, dielectric layers, and metal interconnect structures. In some embodiments, each pad may include a conductive pad located on the top or bottom of the integrated circuit die. When integrated circuit 100 is encapsulated in a package, wire bonding, ball bonding, or other types of connectors may be coupled to the pads.

[0021] Input pad 102 is one of the pads of integrated circuit 100. Input pad 102 corresponds to the data input terminal of integrated circuit 100. Input pad receives data signals from external devices. The data signal is a voltage signal. The voltage value of the data signal represents the data value associated with the data signal. A low voltage value corresponds to a data value of 0. A high voltage value corresponds to a data value of 1.

[0022] In some cases, the amplitude of the signal received at input pad 102 may vary significantly. The input signal may have an amplitude lower or higher than the high power supply voltage VDD of integrated circuit 100. In other words, the voltage representing a data value of 1 may be higher or lower than the high power supply voltage VDD of integrated circuit 100. The voltage representing a data value of 0 may be lower or higher than the ground voltage of integrated circuit 100. Furthermore, the data signal received at the input pad may have noise or other transient characteristics.

[0023] Schmitt trigger 103 serves as an input driver coupled to input pad 102. Schmitt trigger 103 receives a data signal at input pad 102 and supplies an output voltage representing a data value at input pad 102 with either a high supply voltage VDD or a ground voltage. When the data signal at input pad 102 corresponds to the data value 1, Schmitt trigger 103 outputs the high supply voltage VDD corresponding to the data value 1 at input pad 102. When the data signal at input pad corresponds to the data value 0, Schmitt trigger 103 outputs the ground voltage corresponding to the actual zero data value at input pad 102.

[0024] The Schmitt trigger 103 includes a first main transistor branch 104 of a first conductivity type, such as a PMOS branch, and a second main transistor branch 106 of a second conductivity type, such as an NMOS branch. The first and second conductivity types are different from each other. The main PMOS branch 104 and the main NMOS branch 106 are coupled together as an inverter. Therefore, the main PMOS branch 104 and the main NMOS branch 106 can correspond to the first inverter 107 of the Schmitt trigger 103. Although this disclosure and the accompanying drawings are primarily directed to an example in which the first main transistor branch 104 is a PMOS transistor branch and the second main transistor branch is an NMOS transistor branch, the first main transistor branch 104 and the second main transistor branch 106 may also have different conductivity types, which does not depart from the scope of this disclosure.

[0025] The main PMOS branch 104 includes one or more PMOS transistors coupled between VDD and the main NMOS branch 106. In a simplified example, the main PMOS branch 104 may include a single PMOS transistor having a source terminal coupled to VDD, a gate terminal coupled to the input pad 102, and a drain terminal coupled to the main PMOS branch 106. In practice, the main PMOS branch 104 may include two or more PMOS transistors connected in series between VDD and the main NMOS branch 106.

[0026] The main NMOS branch 106 includes one or more NMOS transistors coupled between the main PMOS branch 104 and ground. In a simplified example, the main NMOS branch 106 may include a single NMOS transistor having a source terminal coupled to ground, a gate terminal coupled to the input pad 102, and a drain terminal coupled to the drain terminal of the PMOS transistor in the main PMOS branch 104. The drain terminals of the NMOS transistor and the PMOS transistor correspond to the output of the first inverter 107. In practice, the main NMOS branch 106 may include two or more NMOS transistors connected in series and each having a gate terminal coupled to the input pad 102.

[0027] The Schmitt trigger 103 also includes a second inverter 108. The input of the second inverter 108 is coupled to the output of the first inverter 107. The output of the second inverter 108 is the output of the Schmitt trigger 103.

[0028] In operation, a data signal with a data value is received at input pad 102. A first inverter 107 receives the data signal and outputs a signal with a data value opposite to the data value at input pad 102. A second inverter 108 receives the data value from the first inverter 107 and inverts the data value from the first inverter 107. The output of inverter 108 has a data value that matches the data value received at input pad 102.

[0029] although Figure 1 Not shown, the Schmitt trigger 103 also has threshold circuitry that defines an upper and a lower threshold. For the Schmitt trigger 103 to process high-to-low changes at input pad 102, the voltage at input pad 102 must be below the lower threshold. For the Schmitt trigger 103 to process low-to-high changes at input pad 102, the voltage at input pad 102 must exceed the upper threshold.

[0030] In some embodiments, to maintain low power consumption, the main PMOS branch 104 is designed to provide very little quiescent current consumption. Quiescent current consumption corresponds to the current through the main PMOS branch 104, where the trough at the input pad 102 is quiescent. The quiescent current consumption, representing wasted power consumption, occurs when no change is being processed at the input pad 102, within the current through the main PMOS branch 104 or the main NMOS branch 106.

[0031] To ensure low quiescent current consumption, the transistors in the main PMOS branch 104 can be relatively small, supplying only a relatively small current. While a small current helps ensure low quiescent current consumption, it also results in a slower transition when a new data value appears at input pad 102. This is because inverter 108 will not process the change until node 109, which connects the main PMOS branch 104, the main NMOS branch 106, and the input of inverter 108, is charged to the new voltage. Node 109 acts as a capacitor, charging to VDD when input pad 102 transitions from high to low and discharging from VDD to ground when input pad 102 transitions from low to high.

[0032] If input pad 102 is initially at a high voltage representing the data value 1, node 109 is at ground. If input pad 102 transitions from a high voltage to a low voltage representing the data value 0, main PMOS branch 104 turns on, and current flows through main PMOS branch 104, charging node 109 to VDD. If input pad subsequently transitions from a low voltage to a high voltage representing the data value 1, main PMOS branch 104 turns off, and main NMOS branch 106 turns on, and node 109 discharges from VDD to ground through main NMOS branch 106. Therefore, if main PMOS branch 104 can only supply a relatively small current, the charging of node 109 from ground to VDD will occur relatively slowly.

[0033] To provide a fast charging time for node 109, Schmitt trigger 103 includes a charging auxiliary circuit 110. When the main PMOS branch 104 is activated, the charging auxiliary circuit 110 supplies a supplementary charging current to node 109. In addition to the charging current supplied through the main PMOS branch 104, a supplementary charging current is also supplied to node 109. This increase in the supplementary charging current from the charging auxiliary circuit 110 to node 109 results in an extremely fast charging time for node 109. The extremely fast charging time of node 109 corresponds to the ultra-high frequency operation of the Schmitt trigger 103.

[0034] The charging auxiliary circuit 110 provides essentially zero quiescent current consumption between transitions. This is because the charging auxiliary circuit 110 is completely turned off after node 109 is charged to VDD. (Due to...) Figure 2 To make it clearer, the charging auxiliary circuit 110 can be turned off more completely than the transistors in the main PMOS branch 104. Therefore, while the relatively small transistors in the main PMOS branch 104 may not be completely turned off when the voltage on the input pad 102 is high, the charging auxiliary circuit 110 is completely turned off when the voltage on the input pad is high, and the low voltage supplies essentially zero quiescent current.

[0035] This disclosure primarily describes an embodiment of a charging auxiliary circuit that supplies supplemental charging current during a transition from a high voltage value to a low voltage value at input pad 102 (e.g., from 1 to 0 at input pad 102). This is because the main NMOS branch 106 can typically be more reliably turned off completely when the voltage at input pad 102 is low (0), while the main PMOS branch 104 may not be as reliably turned off when the voltage at input pad is high (1). Therefore, the main NMOS branch 106 can be designed to carry a high charging current while maintaining essentially zero quiescent current consumption.

[0036] However, the principles of this disclosure can be extended to a charging auxiliary circuit 110, which accordingly assists the main NMOS branch 106 in discharging node 109 from VDD to ground during the 0-to-1 transition at input pad 102. Therefore, the charging auxiliary circuit 110 according to the principles of this disclosure can be used to assist the main PMOS branch 104, the main NMOS branch 106, or both the main PMOS branch 104 and the main NMOS branch 106, without departing from the scope of this disclosure.

[0037] Figure 2 This is a schematic diagram of an integrated circuit 100 including a Schmitt trigger 103 according to some embodiments. The Schmitt trigger 103 includes a charging auxiliary circuit 110 for improving the switching speed of the Schmitt trigger 103, as will be described in more detail below. Figure 2 The Schmitt trigger 103 is Figure 1 An example of a Schmitt trigger 103.

[0038] The Schmitt trigger 103 includes a main PMOS branch 104 and a main NMOS branch 106 coupled together as an inverter 107. The main PMOS branch 104 includes a first PMOS transistor P1 and a second PMOS transistor P2 connected in series. A third PMOS transistor P3 is coupled between transistor P1 and VDD. The main NMOS branch 106 includes a first NMOS transistor N1 and a second NMOS transistor N2. A third NMOS transistor N3 is coupled between transistor N2 and ground. A fourth NMOS transistor N4 is coupled between the input pad 112 and the gate terminals of transistors P1, P2, N1, and N2.

[0039] The gate terminals of transistors P1, P2, N1, and N2 correspond to the inputs of inverter 107. The gate terminals of transistors P1, P2, N1, and N2 receive the input pad voltage 112 through NMOS transistor N4. The output of inverter 107 corresponds to the drain terminals of transistors P2 and N1, and also to node 109.

[0040] Inverter 108 includes a PMOS transistor P4 and an NMOS transistor N5. The gate terminals of transistors P4 and N5 are coupled to node 109 and receive the output of inverter 107. The source terminal of transistor P4 is coupled to VDD. The source terminal of transistor N5 is coupled to ground. The output of inverter 108 is the drain terminals of transistors P4 and N5.

[0041] Schmitt trigger 103 includes a PMOS transistor P5, the source of which is coupled between the drain of transistor P1 and the source of transistor P2. The drain of transistor P5 is grounded. The gate of transistor P5 is coupled to node 109. Transistor P5 serves to set the upper threshold of Schmitt trigger 103.

[0042] Schmitt trigger 103 includes an NMOS transistor N6, the source terminal of which is coupled to the drain terminal of transistor N2 and the source terminal of transistor N1. The gate terminal of transistor N6 is coupled to node 109. The drain terminal of transistor N6 is coupled to ground. Transistor N6 serves to set the lower threshold of Schmitt trigger 103.

[0043] The Schmitt trigger includes a PMOS transistor P7. The source terminal of transistor P7 is coupled to VDD. The drain terminal of transistor P7 is coupled to node 109. The gate terminal of transistor P7 receives and enables the signal En. When the enable signal is low, PMOS transistor P7 couples node 109 to VDD, thereby forcing the output of Schmitt trigger 103 to ground. This effectively turns off Schmitt trigger 103. When the enable signal is high, transistor P7 is off and Schmitt trigger 103 can operate.

[0044] The charging auxiliary circuit 110 includes a parallel PMOS branch 114, a control reset circuit 116, a transfer transistor 118, and a switching storage element 120.

[0045] When the voltage at input pad 102 transitions from high voltage (1) to low voltage (0), the parallel PMOS branch 114 supplies a supplementary charging current Ics, which helps charge node 109 to VDD. After node 109 is charged to VDD, the parallel PMOS branch 114 supplies essentially zero current. Therefore, the parallel PMOS branch 114 operates in parallel with the main PMOS branch 104 to charge node 109 when input pad 112 transitions from 1 to 0. Although Figure 2 A single parallel PMOS branch 114 is shown, but in practice, there can be multiple parallel PMOS branches 114, each supplying supplementary charging current to node 109 in parallel with the main PMOS branch 104.

[0046] A transfer transistor 118 is coupled between the input pad 102 and the parallel PMOS branch 114. When the transfer transistor 118 transfers a low voltage from the input pad 102 to the parallel PMOS branch 114, the parallel PMOS branch 114 supplies a supplementary charging current Ics. The transfer transistor 118 is also coupled to the switching storage element 120 and the control reset circuit 116.

[0047] Switching storage element 120 is coupled to input pad 102, control reset circuit 116, and transfer transistor 118. Switching storage element 120 stores the pad voltage when the pad voltage is high. When the pad voltage is low, switching storage element 120 stores the high supply voltage VDD. When the voltage at input pad 112 goes low, switching storage element 120 helps to enable transfer transistor 118.

[0048] A control reset circuit 116 is coupled to the switching storage element 120, the transfer transistor 118, and the parallel PMOS branch 114. The control reset circuit 116 includes one or more switches that enable the switching storage element 120 to charge and discharge. The control reset circuit 116 may include one or more switches to pull the gate voltage of the parallel PMOS branch 114 to the supply voltage VDD to prevent any current from flowing out of the parallel PMOS branch 114. The control reset circuit 116 is configured to reset the gate voltage of the transfer transistor 118 when the voltage at the input pad 102 goes low. This ensures that the transfer transistor 118 turns on the next time the voltage at the input pad 102 goes low.

[0049] Reference Figure 2 and Figure 3 To describe Figure 2 The function of the Schmitt trigger 103. Figure 3 Several graphs are shown. Graph 302 corresponds to the voltage at input pad 102 as a function of time. Graph 304 corresponds to the voltage at node 109 as a function of time. Graph 306 corresponds to the output voltage of Schmitt trigger 103 as a function of time. Graph 308 corresponds to the charging current Ic flowing through the main PMOS branch 104 as a function of time. Graph 310 corresponds to the supplementary charging current Ics flowing through the charging auxiliary circuit 110 as a function of time.

[0050] At time T0, the voltage at input pad 112 is low, as shown in curve 302. At time T0, the voltage at node 109 is VDD because inverter 107 inverts the data value at input pad 102, as shown in curve 304. At time T0, the output of Schmitt trigger 103 is ground, indicating a data value of 0 at input pad 102, as shown in curve 306. At time T0, the charging current flowing through PMOS branch 104 is a small non-zero value IL, as shown in curve 308. At time T0, the supplemental charging current is essentially zero, as shown in curve 310.

[0051] At time T1, the value of the data signal at input pad 102 changes from 0 to 1. As the value of the data signal at input pad 102 changes from 0 to 1, the voltage at node 109 transitions from VDD to ground potential, as can be seen in curve 304. Due to the large capacitance of node 109, the transition is not as abrupt as the voltage change at node 102. However, the transition occurs relatively quickly. Shortly after time T1, the output of the Schmitt trigger transitions from ground potential to VDD. This delay in the transition occurs because the transmission of the output signal responds to the transition at node 109. The supplemental charging current remains at values ​​IL and 0 between times T1 and T2, respectively.

[0052] At time T2, the voltage at the input pad transitions from 1 to 0. This causes the charging current to flow from the main PMOS branch 104 to node 109. It also causes the supplemental charging current to flow from the parallel PMOS branch 114 to node 109. The spikes in the charging and supplemental charging currents at time T2 represent charging node 109 from ground to VDD. Once node 109 has reached VDD, the charging and supplemental charging currents return to the leakage level and zero, respectively. Because the supplemental charging current flows at time T2, charging node 109 from 0V to VDD occurs very quickly. Shortly after node 109 transitions from ground to VDD, the output of the Schmitt trigger 103 transitions from 1 (VDD) to 0 (ground). This process repeats itself between times T2 and T4. Although Figure 302 illustrates the voltage at input pad 102 as a square wave, in reality, the voltage at input pad 102 is not a square wave but can transition between low and high values ​​within irregular periods.

[0053] Transistor P3 of the Schmitt trigger 103 helps reduce the quiescent current flowing through the main PMOS branch 104. Transistor P3 is connected as a diode, with its drain and gate terminals coupled together. This results in a voltage drop of approximately 0.7V across transistor P3. Therefore, the voltage at the drain terminal of transistor P1 is VDD - 0.7V. When the voltage at node 109 is 0V, the quiescent current flows through the main PMOS branch 104. The voltage drop across transistor P3 reduces the magnitude of the quiescent current. There may be multiple diode-connected PMOS transistors between the high supply voltage VDD and the main PMOS branch 104.

[0054] Figure 4 This is an illustration of an integrated circuit 100 including a Schmitt trigger 103 according to some embodiments. Figure 2 and Figure 4 The only difference is the charging auxiliary circuit 110. Figure 4 A schematic diagram including the charging auxiliary circuit 110. Figure 4 The charging auxiliary circuit 110 is Figure 1 and Figure 2 An example of the charging auxiliary circuit 110.

[0055] Parallel PMOS branch 114 includes PMOS transistors P7 and P8. Transmission transistor 118 includes NMOS transistor N7. Switching storage element 120 includes resistor R1 and capacitor C1. Control reset circuit 116 includes PMOS transistors P9, P10, P11, and P12. The gate terminals of transistors P7 and P8 are coupled to the drain terminal of transmission transistor N7. The source terminal of transistor P8 is coupled to the high supply voltage VDD. The source terminal of transistor P7 is connected to node 109. The supplementary charging current Ics flows through transistors P8 and P7 to node 109. The gate terminals of transistors P7 and P8 are also coupled to the drain terminal of transistor P10. The gate terminal of transistor P10 receives the signal OUTn, which corresponds to the logical complement of the output OUT of Schmitt trigger 103. The gate of transistor P9 receives ground potential. The gate terminal of transistor P11 receives the output voltage of Schmitt trigger 103. The gate terminal of transistor P12 receives the complementary output signal OUTn.

[0056] Refer again Figure 3The timing and signals shown indicate that at time T0, the voltage on input pad 102 is a low input value, the output voltage OUT is ground potential, and the complementary output OUTn is VDD. Transistor P12 is off while transistor P11 is on. Capacitor C1 charges to VDD. The gate terminal of transistor N7 receives VDD. Transistor P9 is always on. Transistor P10 is off. Transistors P7 and P8 receive the low input voltage from input pad 102 via transfer transistor 102. Since node 109 is already charged to VDD, no current flows through transistors P7 and P8.

[0057] At time T1, the voltage on input pad 102 becomes a high input voltage. Transistors N1 and N2 are enabled, discharging node 109 to ground. The output voltage OUT transitions to VDD. The complementary output voltage OUTn transitions to ground. Transistor P12 turns on, and transistor P11 turns off. Capacitor C1 charges to the high input voltage of input pad 102. Transistors P9 and P10 turn on, thus providing VDD to the gate terminals of transistors P7 and P8 and completely turning them off, so that no supplementary charging current flows. Transistor N7 turns off because both its gate and source terminals are at the high input voltage of input pad 102.

[0058] At time T2, the input pad transitions from a high input voltage to a low input voltage. Since the gate terminal of the transfer transistor N7 is still at a high input voltage due to the charge stored in capacitor C1, this immediately turns on the transfer transistor N7. Because the transfer transistor N7 immediately turns on, the gate terminals of transistors P7 and P8 immediately receive the low input voltage of the input pad 102, instead of the current. Transistors P7 and P8 provide supplementary charging current Ics to node 109 and quickly charge node 109 to VDD. After charging node 109 to VDD, the output OUT transitions to ground. OUTn transitions to VDD. Transistor P12 turns off, and transistor P11 turns on, charging capacitor C1 to VDD. Therefore, the charging auxiliary circuit 110 is reset to the state at time T0.

[0059] The charging auxiliary circuit 110 offers several advantages. The supplemental charging current is activated virtually immediately when the input pad 102 transitions from a high input voltage to a low input voltage. The supplemental charging current Ics rapidly charges node 109 to VDD. When the input pad transitions from a low input voltage to a high input voltage, transistors P7 and P8 are immediately and completely turned off, making the supplemental charging current Ics essentially zero. Therefore, the charging auxiliary circuit 110 enables ultra-high frequency operation of the Schmitt trigger 103 without additional quiescent current consumption and with a very small footprint.

[0060] Figure 5 This is a schematic diagram of a charging auxiliary circuit 110 according to some embodiments. Figure 5The charging auxiliary circuit 110 is Figure 1 and 2 An example of the charging auxiliary circuit 110. Figure 5 The charging auxiliary circuit 110 is shared. Figure 4 Many components of the charging auxiliary circuit 110. Figure 5 Including inverters 124 and 126. Inverter 124 receives the output signal Out and generates a complementary output signal OUTn. The complementary output signal OUTn is applied to the gate terminals of transistors P12 and P10. Inverter 126 receives the complementary output signal OUTn and generates a signal matching the output signal OUT. Charging auxiliary circuit 110 is used in conjunction with... Figure 4 The charging auxiliary circuit 110 operates in basically the same way.

[0061] Figure 6 This is a schematic diagram of a charging auxiliary circuit 110 according to some embodiments. Figure 6 The charging auxiliary circuit 106 is Figure 1 and 2 An example of a charging auxiliary circuit. The charging auxiliary circuit and... Figure 4 The charging auxiliary circuit 106 is basically similar. The main difference is that... Figure 6 In this circuit, the second resistor R2 is coupled between VDD and the source terminal of transistor P8. The presence of resistor R2 helps stabilize the operation of the parallel PMOS branch 114. In particular, the presence of resistor R2 can reduce the effects of variations in the supply voltage VDD. Figure 6 The charging auxiliary circuit 110 is otherwise similar to Figure 4 The charging auxiliary circuit 110 operates in a basically similar manner.

[0062] Figure 7 This is a flowchart of a method 700 for operating a Schmitt trigger according to some embodiments. At 702, method 700 includes supplying an input voltage from the input pads of an integrated circuit to the Schmitt trigger of the integrated circuit. At 704, method 700 includes supplying a charging current from a first main transistor branch of the Schmitt trigger to an intermediate node of the Schmitt trigger in response to a transition of the input voltage from a high input value to a low input value. At 706, method 700 includes supplying a supplementary charging current from a parallel transistor branch of the Schmitt trigger to an intermediate node in response to a transition of the input voltage from a high input value to a low input value.

[0063] In one embodiment, a method includes supplying an input voltage from an input pad of an integrated circuit to a Schmitt trigger of the integrated circuit. The method includes supplying a charging current from the main transistor branch of the Schmitt trigger to an intermediate node of the Schmitt trigger in response to a transition of the input voltage from a high input value to a low input value. The method also includes supplying a supplementary charging current from a parallel transistor branch of the Schmitt trigger to an intermediate node in response to a transition of the input voltage from a high input value to a low input value.

[0064] In one embodiment, the integrated circuit includes an input pad and a Schmitt trigger. The Schmitt trigger includes: an input coupled to the input pad; a first main transistor branch of a first conductivity type coupled between a high supply voltage and an intermediate node; a charging auxiliary circuit including a parallel transistor branch coupled between the supply voltage and the intermediate node; and a second main transistor branch of a second conductivity type opposite to the first conductivity type, coupled between the intermediate node and ground.

[0065] In one embodiment, the integrated circuit includes an input pad and a Schmitt trigger coupled to the input pad. The Schmitt trigger includes a first inverter having a main transistor branch, the main transistor branch including a first transistor of a first conductivity type. The Schmitt trigger includes a second main transistor branch, the second main transistor branch including a second transistor of a second conductivity type coupled to the first PMOS transistor at an intermediate node of the Schmitt trigger. The Schmitt trigger includes a second inverter whose input is coupled to the intermediate node and whose output corresponds to the output of the Schmitt trigger. The Schmitt trigger includes a charging auxiliary circuit coupled to the intermediate node.

[0066] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments based on the detailed description above. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be construed as including all possible embodiments and the full scope of equivalents conferred by these claims. Therefore, the claims are not limited to this disclosure.

Claims

1. An integrated circuit, comprising: Input pads; and Schmitt triggers include: The input is coupled to the input pad; The first main transistor branch is coupled between the high supply voltage and the intermediate node; The charging auxiliary circuit includes: A parallel transistor branch of a first conductivity type coupled between the high power supply voltage and the intermediate node; A transmission transistor coupled between the input pad and the parallel transistor branch; A switching storage element coupled to the gate terminal of the transmission transistor; and A control reset circuit coupled to the switching storage element, the transmission transistor, and the parallel transistor branch; and The second main transistor branch is coupled between the intermediate node and ground.

2. The integrated circuit according to claim 1, wherein, The Schmitt trigger includes a first inverter having an input coupled to the intermediate node and an output corresponding to the output of the Schmitt trigger.

3. The integrated circuit according to claim 1, wherein, The first main transistor branch and the second main transistor branch are second inverters, the input of the second inverter is the input of the Schmitt trigger, and the output of the second inverter is the intermediate node.

4. The integrated circuit according to claim 1, wherein, The first main transistor branch supplies a charging current in response to the input pad transitioning from a high input voltage to a low input voltage, the charging current charging the intermediate node from ground potential to the high supply voltage.

5. The integrated circuit according to claim 4, wherein, The parallel transistor branch supplies supplemental charging current in response to the transition of the input pad from a high input voltage to a low input voltage, and the supplemental charging current helps to charge the intermediate node from ground potential to the high supply voltage.

6. The integrated circuit according to claim 1, wherein, The first main transistor branch is a PMOS transistor branch, and the parallel transistor branch is a parallel PMOS transistor branch.

7. The integrated circuit according to claim 6, wherein, The main transistor branch includes a first PMOS transistor and a second PMOS transistor connected in series.

8. The integrated circuit according to claim 7, wherein, The parallel PMOS branch includes a third PMOS transistor and a fourth PMOS transistor connected in series.

9. A method for operating a Schmitt trigger, comprising: Input voltage is supplied from the input pads of the integrated circuit to the Schmitt trigger of the integrated circuit; In response to the input voltage transition from a high input value to a low input value, a charging current is supplied from the main transistor branch of the Schmitt trigger to the intermediate node of the Schmitt trigger; as well as In response to the input voltage transition from a high input value to a low input value, a supplementary charging current is supplied from the parallel transistor branch of the Schmitt trigger to the intermediate node. The transmission transistor is coupled between the input pad and the parallel transistor branch, the switch storage element is coupled to the gate terminal of the transmission transistor, and the control reset circuit is coupled to the switch storage element, the transmission transistor, and the parallel transistor branch.

10. The method according to claim 9, wherein the main transistor branch is a PMOS transistor branch, and wherein the parallel transistor branch is a parallel PMOS transistor branch.

11. The method of claim 10, further comprising: The intermediate node is charged from ground potential to a high power supply voltage by supplying the charging current and the supplementary charging current.

12. The method according to claim 11, wherein, When the intermediate node is charged to the high power supply voltage, the supplementary charging current is greater than the charging current.

13. The method according to claim 12, wherein, When the input voltage is at the high input value, the supplementary charging current is less than the charging current.

14. The method according to claim 13, wherein, When the input voltage is at the high input value, the supplementary charging current is essentially zero.

15. The method of claim 13, further comprising: The PMOS transistor of the parallel PMOS branch is turned on in response to the switching.

16. The method of claim 10, further comprising: The output of the Schmitt trigger is generated by inverting the voltage of the intermediate node.

17. An integrated circuit, comprising: Input pads; A Schmitt trigger, coupled to the input pad, includes: The first inverter has: The first main transistor branch includes a first transistor of a first conductivity type; and The second main transistor branch includes a second transistor of a second conductivity type opposite to the first conductivity type, and the second transistor is coupled to the first transistor at the intermediate node of the Schmitt trigger. The second inverter has: Input, coupled to the intermediate node; and The output corresponds to the output of the Schmitt trigger; and A charging auxiliary circuit, coupled to the intermediate node, includes: A parallel transistor branch of the first conductivity type coupled between the power supply voltage and the intermediate node; A transmission transistor coupled between the input pad and the parallel transistor branch; A switching storage element coupled to the gate terminal of the transmission transistor; and A control reset circuit coupled to the switch storage element, the transmission transistor, and the parallel transistor branch.

18. The integrated circuit according to claim 17, wherein, The charging auxiliary circuit includes a third transistor of the first conductivity type, which is coupled in parallel with the first transistor to the intermediate node.

19. The integrated circuit according to claim 18, wherein, The first transistor supplies charging current to the intermediate node, and the third transistor supplies supplementary charging current to the intermediate node.

20. The integrated circuit according to claim 17, wherein, The first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.

Images