Asynchronous progress topology in memory devices

Abstract

Devices and methods can relate to generating an asynchronous progress topology in a memory device. The topology can be generated based on results of a number of processes. The processes can be asynchronous as long as the processing resources implementing the processes do not use a clock signal to generate the topology.

Description

Technical Field

[0001] This disclosure generally relates to memory, and more specifically, to apparatus and methods associated with implementing asynchronous process topologies in memory devices. Background Technology

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and includes, in particular, random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM). Non-volatile memory provides persistent data by retaining the stored data when no power is supplied and includes, in particular, NAND flash memory, NOR flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and resistive variable memory (e.g., phase-change random access memory (PCRAM)), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM).

[0003] Memory is also used as a volatile and non-volatile data storage device for a wide range of electronic applications, including (but not limited to) personal computers, portable memory sticks, digital cameras, cellular phones, portable music players (e.g., MP3 players), movie players, and other electronic devices. Memory cells can be arranged in arrays, wherein the arrays are used in memory devices.

[0004] Commands can be provided to the memory using an interface protocol. Commands provided to the memory can be predefined and used to control the functions of the memory. The interface can be used to provide commands to the memory device that cause the memory device to perform operations. Attached Figure Description

[0005] Figure 1 This is a block diagram of a device in the form of a computing system including a memory device, according to several embodiments of the present disclosure.

[0006] Figure 2 This is a block diagram of several processes according to several embodiments of the present disclosure.

[0007] Figure 3 This is a block diagram of an apparatus in the form of a memory device including multiple processing resources, according to several embodiments of the present disclosure.

[0008] Figure 4 This is a block diagram of a device in the form of a memory device comprising multiple storage units, according to several embodiments of the present disclosure.

[0009] Figure 5 This is a block diagram of an apparatus in the form of a memory device including multiple processing resources and comparators, according to several embodiments of the present disclosure.

[0010] Figure 6 This is a block diagram of a device in the form of a memory device including processing resources, according to several embodiments of the present disclosure.

[0011] Figure 7 Example flowcharts illustrating methods for performing operations in a memory according to several embodiments of the present disclosure.

[0012] Figure 8 An example machine is described, within which a set of instructions can be executed to cause the machine to perform the various methodologies discussed herein. Detailed Implementation

[0013] This disclosure includes apparatus and methods related to implementing asynchronous process topologies in a memory device. The memory device may receive and / or generate clock signals. The clock signals can be used to synchronize various operations performed by the memory device. The various operations performed by the memory device may be performed synchronously within the memory device and / or synchronously with devices outside the memory device (e.g., a host device). In various embodiments, the memory device may asynchronously implement processes and / or topologies corresponding to those processes.

[0014] As used herein, "synchronous" refers to the use of a clock signal when performing an operation and / or process. A clock signal includes any timing signal or signal that can be used to track duration, time reference, and / or operational reference. In various instances, the clock signal may be received from the host device. Asynchronous refers to performing an operation and / or process without using a clock signal.

[0015] The memory device may be configured to asynchronously implement processes and / or corresponding topologies when in an incompatible mode. The memory device may not be configurable to asynchronously implement processes and / or corresponding topologies when in a compatible mode.

[0016] Memory devices may conform to interface protocols. An interface protocol is defined as communication between a memory device and a device external to the memory device. If devices communicate as defined by an interface protocol, then they may conform to that protocol. An interface protocol may be defined such that a memory device can receive and process signals from and from multiple devices external to the memory device, where these devices are manufactured by multiple different vendors. An example of an interface protocol is the Double Data Rate (DDR) 5 standard. In various examples, interface protocols may be developed by organizations such as the Joint Electronic Devices Engineering Committee (JEDEC), which enables any device compatible with the interface protocol to communicate with each other without incurring the expense of defining a new interface protocol for multiple devices.

[0017] In each instance, the results of processes implemented in the memory device can be used to select different processes to execute. Processes can be executed asynchronously, and / or the selection of different processes can be performed asynchronously. Asynchronously executing asynchronous processes and / or selecting processes in a synchronous memory device provides the ability to implement processes that would otherwise be impossible to implement in the memory device. For example, asynchronously executing asynchronous processes and / or selecting processes in a synchronous memory device provides the ability to implement a learning process in the memory device. The learning process can include neural networks and other types of learning processes. Although the examples provided herein are given in the context of neural networks, examples can also be implemented using different types of processes.

[0018] The figures in this document follow a numbering convention, where the first digit or the first few digits correspond to the figure number and the remaining digits identify elements or components in the figure. Similar elements or components between different figures can be identified by using similar digits. It should be understood that elements shown in the various embodiments herein may be added, interchanged, and / or eliminated to provide several additional embodiments of this disclosure. Furthermore, the scale and relative dimensions of the elements provided in the figures are intended to illustrate various embodiments of this disclosure and are not intended to be limiting.

[0019] Figure 1 This is a block diagram of a device in the form of a computing system 100 including a memory device 103, according to several embodiments of the present disclosure. As used herein, for example, the memory device 103, memory arrays 110-1, 110-2, 110-3, ..., 110-N and / or host 102 may also be considered as a "device" individually. Memory arrays 110-1, 110-2, 110-3, ..., 110-N may be referred to as memory array 110.

[0020] In this example, system 100 includes a host 102 coupled to memory device 103 via interface 104. The computing system 100 may be a personal laptop, desktop computer, digital camera, mobile phone, memory card reader, or Internet of Things (IoT) enabled device, and other types of systems. Host 102 may include several processing resources (e.g., one or more processors, microprocessors, or some other type of control circuitry) capable of accessing memory 103. System 100 may include a separate integrated circuit, or both host 102 and memory device 103 may be on the same integrated circuit. For example, host 102 may be a system controller for a memory system including multiple memory devices 103, wherein system controller 102 provides access to the respective memory devices 103 through another processing resource (e.g., a central processing unit (CPU)).

[0021] exist Figure 1 In the example shown, host 102 is responsible for executing the operating system (OS) and / or various applications that can be loaded thereto (e.g., loaded thereto from memory device 103 via controller 105). The OS and / or the various applications can be loaded from memory device 103 by providing access commands from host 102 to memory device 103 for accessing data including the OS and / or the various applications. Host 102 can also access data used by the OS and / or the various applications by providing access commands to memory device 103 for retrieving the data used to execute the OS and / or the various applications.

[0022] For clarity, system 100 has been simplified to focus on features particularly relevant to this disclosure. Memory array 110 may be, for example, a DRAM array, SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash array, and / or NOR flash array. Array 110 may include memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as digital lines or data lines).

[0023] Memory device 103 includes an address circuitry 106 for latching address signals provided via interface 104. The interface may include, for example, a physical interface employing a suitable protocol (e.g., a data bus, address bus, and command bus, or a combined data / address / command bus). This protocol may be custom or proprietary, or interface 104 may employ a standardized protocol, such as Peripheral Component Interconnect High Speed ​​(PCIe), Gen-Z Interconnect, Accelerator Cache Coherent Interconnect (CCIX), or the like. Address signals are received and decoded by row decoder 108 and column decoder 112 to access memory array 110. Data can be read from memory array 110 by sensing voltage and / or current changes on sensing lines using sensing circuitry systems 111-1 to 111-N. Sensing circuitry systems 111-1 to 111-N may be referred to as sensing circuitry system 111. Each of the sensing circuit systems 111-1 to 111-N can be coupled to a corresponding memory array from memory arrays 110-1, 110-2, 110-3, ..., 110-N. Each memory array and its corresponding sensing circuit system can constitute the storage bank of memory device 103. Sensing circuit system 111 may include, for example, a sensing amplifier capable of reading and latching a page (e.g., a row) of data from memory array 110. I / O circuit system 107 can be used for bidirectional data communication with host 102 via interface 104. Read / write circuit system 113 is used to write data to or read data from memory array 110. As an example, circuit system 113 may include various drivers, latching circuit systems, etc.

[0024] Control circuitry system 105 decodes signals provided by host 102. These signals may be commands provided by host 102. These signals may include chip enable signals, write enable signals, and address latch signals, used to control operations performed on memory array 110, including data read operations, data write operations, and data erase operations. In various embodiments, control circuitry system 105 is responsible for executing instructions from host 102. Control circuitry system 105 may include a state machine, sequencer, and / or some other type of control circuitry system, which may be implemented in hardware, firmware, or software, or any combination of the three. In some instances, host 102 may be a controller external to memory device 103. For example, host 102 may be a memory controller coupled to the processing resources of a computing device. Data may be provided to and / or from memory array 110 via data line 116.

[0025] In various examples, the functionality of memory device 103 can be controlled by host 102. For instance, host 102 can provide commands to memory device 103 via interface 104 to read from memory array 110 and / or write to memory array 110 and other functionalities of memory array 110. However, the implemented interface protocol may not define commands for controlling the functionality of processing resources implemented in memory device 103 when operating in a compatible mode. The memory device can be configured to receive commands to control the functionality of processing resources when operating in an incompatible mode.

[0026] Processing resources implemented in memory device 103 may be coupled to data line 116, implemented in sensing circuitry system 111, and / or implemented under memory array 110. The execution process of the processing resources can be controlled. As used herein, a process may include one or more operations performed by the processing resources. Operations may include logical operations, such as AND and OR operations, and other types of logical operations. Operations may include addition, subtraction, multiplication, and / or division operations. Operations may also include comparison and selection operations.

[0027] In each instance, the result of the first process can be used to select the next process to execute and / or to provide data to host 102. The process topology can be selected based on the process result. In some instances, the coupling of the processing resources implementing the process can correspond to the process topology and can be based on the process result.

[0028] Figure 2 This is a block diagram of several processes 222-1, 222-2, ..., and 222-M according to several embodiments of the present disclosure. Processes 222-1, 222-2, ..., and 222-M may be referred to as process 222. The processes may be executed by memory device 203. Each of the processes 222 may be executed by one or more processing resources managed by memory device 203.

[0029] Memory device 203 may receive command 220 via its interface. Command 220 may identify process 222-1 to be executed. A first number of processing resources may execute process 222-1 in response to the receipt of the command. Memory device 203 may use the result of process 222-1 to determine whether to execute process 222-2 or whether to provide result 224 (e.g., output / result 224). The determination may be performed by the first number of processing resources, a different number of processing resources, and / or by a comparator and other types of circuitry capable of initiating process 222-2 or providing data. The determination of whether to execute process 222-2 or whether to provide result 224 may be performed asynchronously. For example, the circuitry performing the determination may perform the determination without reference to a clock signal. A certain number of operations for performing the determination may be performed without the use of a clock signal.

[0030] In various instances, process 222-1 and / or portions of process 222-1 can be executed without reference to a clock signal. For example, although a read operation corresponding to process 222-1 can be performed based on a clock signal, different operations corresponding to process 222-1 can be performed without reference to a clock signal.

[0031] The result of process 222-1 can be used to select process 222-2, such as Figure 2 The results of process 222-1 can be used to select process 222-3 (e.g., not shown) and / or different processes in different instances.

[0032] The result of process 222-2 can be used to select process 222-3. The result of process 222-2 can also be used to determine whether to provide the result to the host. In some instances, the result of a process can be used to determine whether to provide the result without selecting the next process. The result of process 222-M can be used to determine that no additional process should be selected and that the result should be provided to the host.

[0033] although Figure 2 The result 224 is presented as being provided by memory device 203 to a device external to memory device 203, but the result 224 may be stored in the memory array of memory device 203. The host may additionally read the result from the memory array. For example, the command for starting process 222-1 may also be associated with a location in the memory array, such that the result corresponding to process 222-1 is stored in a memory cell of the memory array with the address associated with the command.

[0034] Figure 3 This is a block diagram of a device, according to several embodiments of the present disclosure, in the form of a memory device 303 comprising a plurality of processing resources 334-1, 334-2, ..., and 334-M. The processing resources 334-1, 334-2, ..., and 334-M may be referred to as processing resources 334.

[0035] Processing resource 334-1 may be implemented under a memory array (e.g., memory array 110-1). In various instances, sensing amplifiers 332-1, 332-2, ..., and 332-M may also be implemented under a memory array. Sensing amplifiers 332-1, 332-2, ..., and 332-M may be referred to as sensing amplifier 332. In various instances, sensing amplifier 332 may be implemented in parallel with the memory array, rather than under the memory array. Regardless of whether sensing amplifier 332 is implemented under a memory array, sensing amplifier 332 is coupled to processing resource 334. For example, sensing amplifier 332-1 is coupled to processing resource 334-1, sensing amplifier 332-2 is coupled to processing resource 334-2, ..., and sensing amplifier 332-M is coupled to processing resource 334-M.

[0036] The sensing amplifier 332 can be coupled to a sensing line of the memory array. The sensing amplifier 332 can amplify the signal provided from the memory cells of the memory array through the sensing line. The sensing amplifier 332 can provide a signal to the processing resource 334. The processing resource 334 can perform multiple operations on the data provided from the sensing amplifier 332.

[0037] The result of the first process implemented by processing resource 334-1 can be used to provide the result to processing resource 334-2. Processing resource 334-2 can execute a second process using data provided by sensing amplifier 332-2 and / or processing resource 334-2, the second process producing a second result upon implementation. The second result can be used to determine whether to initiate a next process implemented by processing resource 334-3 (not shown). Processing resource 334-M can implement a final process using the result of the previous process and / or data provided by sensing amplifier 332-M. The result of the final process can be provided via multiple I / O lines.

[0038] Although the sensing amplifier is shown as being coupled to a processing resource, multiple processing resources may be coupled to a sensing amplifier and / or multiple sensing amplifiers may be coupled to a processing resource. The coupling of the sensing amplifier 332 to the processing resource 334 can be used to provide data to the processing resource 334.

[0039] In various instances, processing resource 334 may be decoupled from a clock signal, allowing processes implemented by processing resource 334 to execute asynchronously. In various instances, the portion of processing resource 334 used to determine whether to provide data to a processing resource may be performed without using a clock signal, while the remaining portion of processing resource 334 may use a clock signal to perform different operations. The portion of processing resource 334 used to determine which processing resource to provide data to may be performed without using a clock signal, while the remaining portion of processing resource 334 may use a clock signal to perform different operations.

[0040] In various embodiments, memory device 303 may be a three-dimensional (3D) memory device comprising multiple layers stacked together. As an example, the first layer 336 of memory device 303 (e.g., memory array 110-1, such as...) Figure 1 (As explained in the text) Coupled to the second layer 315 of the memory device 303 (e.g., under-array CMOS, such as...) Figure 3 (See description below). Although the first layer 336 is described as being on the second layer 315, the first layer 336 and the second layer 315 may be designed to include several different orientations such that the first layer 336 is coupled to the second layer 315. The examples described herein are not limited to the specific orientation between the first layer 336 and the second layer 315. The first layer 336 of the memory device 303 may comprise an array of memory cells. Although embodiments are not limited thereto, the memory cells of the array may comprise DRAM memory cells.

[0041] The second layer 315 may contain several logical blocks configured to perform various functions, for example, using data values ​​stored in a memory cell array. The logical blocks may contain multiple processing resources 334, which may also be referred to as processing resources 334. In various instances, the second layer may also contain row drivers and / or column drivers. Although in Figure 3 The diagram shows a processing resource of M 334, but the processing resource 334 may contain more or fewer processing resources than shown here.

[0042] The second layer 315 may be one of a plurality of logic blocks contained within memory device 303. Processing resources 334 may be configured to perform artificial intelligence (AI) processing. For example, processing resources 334 may be configured as a network (e.g., a neural network). Each of the processing resources 332 may be a node in the neural network. Each of the processing resources 334 may be coupled to different memory cells of a memory array capable of storing the weights and / or inputs of the network. The processing resources 334 may be interconnected such that the outputs of some processing resources 334 may be received as input by another processing resource 334. The results of the AI ​​processing performed by the processing resources 334 may be stored back into the memory array, latched by a sense amplifier, and / or provided via I / O lines. As used herein, references to networks or learning processes may refer to artificial networks and learning processes.

[0043] Figure 4 This is a block diagram of a device in the form of a memory device 403 comprising a plurality of memory banks 440-1, 440-2, ..., 440-N, according to several embodiments of the present disclosure. Memory banks 440-1, 440-3, ..., 440-N may be referred to as memory banks 440.

[0044] Each of the memory banks may include multiple sense amplifiers and processing resources. For example, memory bank 440-1 includes sense amplifiers 432-1, 432-2, ..., and 432-R and processing resources 434-1, 434-2, ..., and 434-R. Memory bank 440-2 is shown as including sense amplifier 432-R+1 and processing resource 434-R+1. Memory bank 440-N includes sense amplifier 432-R+2 and processing resource 434-R+2. Although each of memory banks 440-2 and 440-N is shown as including a single sense amplifier and a single processing resource, memory banks 440-2 and 440-N may include more than one sense amplifier and one processing resource. Figure 4 More sensing amplifiers and processing resources are shown in the diagram. Sensing amplifiers 432-1, 432-2, ..., 432-R, 432-R+1, and 432-R+2 can be referred to as sensing amplifiers 432. Processing resources 434-1, 434-2, ..., 434-R, 434-R+1, and 434-R+2 can be referred to as processing resources 434.

[0045] Storage bank 440 can be configured to function as a single artificial neural network or as multiple artificial neural networks. For example, processing resources 434-1, 434-2, ..., 434-R of storage bank 440-1 can be configured as a first neural network, processing resources of storage bank 440-2 (including processing resource 434-R+1) can be configured as a second neural network, ..., and processing resources of storage bank 440-N (including processing resource 434-R+2) can be configured as an Nth neural network. In such an example, a process can be defined as the execution of a neural network. A first process can be executed by activating the first neural network. The results of the first neural network can be provided to the second neural network, and so on.

[0046] In several instances, each of the memory banks 440 of the memory device 403 can represent a single layer of a neural network, enabling the implementation of a single neural network comprising N layers. The first layer of the neural network can be represented by a configuration of processing resources 434-1, 434-2, ..., and 434-R. The second layer of the neural network can be represented by a configuration of processing resources in memory bank 440-2, including processing resource 434-R+1. The Nth layer of the neural network can be represented by a configuration of processing resources in memory bank 440-N, including processing resource 434-R+2.

[0047] Each of the processing resources 434 can be coupled to a different sensing amplifier in sensing amplifier 432. Figure 4This demonstrates how the processing resources of one layer are coupled to the processing resources of different layers in a neural network. For example, processing resources 434-1, 434-2, ..., 434-R are coupled to processing resource 434-R+1 of memory bank 440-2. Although not shown, each of processing resources 434-1, 434-2, ..., 434-R can be coupled to each of the processing resources in memory bank 440-2, and each of the processing resources in memory bank 440-2 can be coupled to each of the processing resources in different memory banks, and so on.

[0048] A process may contain layers that allow signals to propagate through a neural network. The result of the first process (including the result of the first layer of the neural network) can be provided to the second process by providing the result to the second layer of the neural network.

[0049] The topology of a neural network can be selected based on the results of processes. The topology describes how data is transferred between processing resources. For example, a first processing resource can be coupled to a second and a third processing resource. Data can be provided from the first processing resource to the second processing resource in response to a first result of a first process executed by the first processing resource. Data can also be provided from the first processing resource to the third processing resource in response to a second result of the first process. Data transfer between the first and second processing resources describes a first topology. Data transfer between the first and third processing resources describes a second topology. The topology also describes the order in which processes executed by processing resources are performed. For example, a first result of a first process can cause a second process executed by the second processing resource to be executed after the first process. A second result of a first process can cause a third process executed by the third processing resource to be executed after the first process. Executing a second process after the first process describes a first topology of the processes, while executing a third process after the first process describes a second topology of the processes.

[0050] The topology between processes in memory bank 440-1 and memory bank 440-2 can be defined based on the results of processing resources 434-1, 434-2, ..., 434-R. Each of processing resources 434-1, 434-2, ..., and 434-R can be selectively coupled to a processing resource in memory bank 440-2 based on the results provided by processing resources 434-1, 434-2, ..., and 434-R. If the result provided by processing resource 434-1 is greater than a threshold, then processing resource 434-1 can be selectively coupled to processing resource 434-R+1. If the result provided by processing resource 434-1 is not greater than a threshold, then processing resource 434-1 can not be coupled to processing resource 434-R+1. As used herein, selective coupling describes the selective provision of data to processing resources based on the results of processes.

[0051] Processing resource 434 can execute a process using inputs and weights stored in a memory array, the process producing a result. Therefore, processing resource 434 can be configured to use different processing resources 434, operate different sensing amplifiers 432, and / or read memory cells coupled to processing resource 434. For example, each of the processing resources 434 can cause memory cells to be read by a corresponding sensing circuit system from sensing circuit system 432, which provides signals to different processing resources 434, and different processing resources 434 receive signals from their corresponding processing resources 434. In various instances, multiple processing resources 434-1, 434-2, ..., 434-R can cause memory cells to be read by sensing circuit system 432-R+1, which provides signals to processing resource 434-R+1, and processing resource 434-R+1 receives signals from processing resources 434-1, 434-2, ..., 434-R.

[0052] Figure 5 This is a block diagram of an apparatus in the form of a memory device 503 comprising a plurality of processing resources 534-1, 534-2, ..., and 534-M and comparators 551-1, 551-2, ..., 551-M, according to several embodiments of the present disclosure. The processing resources 534-1, 534-2, ..., and 534-M may be referred to as processing resources 534, and the comparators 551-1, 551-2, ..., 551-M may be referred to as comparators 551.

[0053] Processing resource 534 can execute several processes. The processing resource can be coupled to comparator 551. For example, processing resource 534-1 is coupled to comparator 551-1, processing resource 534-2 is coupled to comparator 551-2, ..., and processing resource 534-M is coupled to comparator 551-M. Processing resource 534 can provide the results of the processes to comparator 551. Comparator 551 may include circuitry configured to compare the values ​​provided by processing resource 534 with a threshold.

[0054] For example, comparator 551-1 can compare the value provided by processing resource 534-1 with a first threshold. Comparator 551-2 can compare the value provided by processing resource 534-2 with a second threshold. Comparator 551-M can compare the value provided by processing resource 534-M with an Mth threshold. In response to determining that the value provided by processing resource 534 is greater than, equal to, or less than a threshold, comparator 551 can provide a signal to the corresponding processing resource. For example, comparator 551-1 can provide a signal to processing resource 534-2 in response to a value provided by processing resource 534-1 being greater than a threshold.

[0055] Comparator 551 can receive inputs, integrate the inputs, and provide an output (e.g., trigger). For example, comparator 551 can receive multiple inputs, including a first charge and a second charge. The first charge and the second charge can be combined (e.g., integrated) to produce a third charge. The integrated charge can degrade over time (e.g., leak). For example, the charge stored in the capacitor of comparator 551 can degrade over time. Comparator 551 may include resistors and capacitors, as well as other components. The resistors and capacitors may also be referred to as a resistor-capacitor (RC) circuit. The capacitor of comparator 551 can combine charges such that the charge is received at the capacitor. The capacitor can provide the combined charge to a circuit system configured to provide a positive spike.

[0056] Processing resource 534 can be activated multiple times, causing the result of the process to be retained by comparator 551 until a threshold is reached. Determining whether the threshold has been reached involves comparing multiple values. Comparator 551 can provide a signal (e.g., a positive spike) to the corresponding processor. The retained result does not include storage because the value retention is constantly changing, taking into account the degradation of the retained result.

[0057] In some instances, processing resource 534 and / or comparator 551 can operate without reference to a clock signal. For example, processing resource 534 and comparator 551 can operate without reference to a clock signal. Although processing resource 534 and comparator 551 are shown as two separate components, processing resource 534 and the corresponding comparator 551 can form a single component. For example, processing resource 534-1 and comparator 551-1 can form a single device.

[0058] In various examples, comparator 551 may signal different processing resources based on the result of a process executed by one or more processing resources. For example, if the value is less than a first threshold, the comparator may provide a first signal to a first processing resource; if the value is greater than the first threshold but less than a second threshold, a second signal may be provided to a second processing resource; or if the value is greater than a third threshold, a third signal may be provided to a third processing resource, and other possible implementations of the mapping between thresholds and processing resources.

[0059] Figure 6 This is a block diagram of an apparatus in the form of a memory device 603 including processing resources 634, according to several embodiments of the present disclosure. Figure 6 The processing resource 634 is shown as coupled to the data line. Although the processing resource 634 is shown as a single processing resource, it can represent several processing resources, for example... Figure 3 The processing resource is 334. The processing resource 634 represents the combination of the processing resource and the comparator.

[0060] Processing resource 634 may be coupled to command interface 604-1 and command interface 604-3. Although not shown, processing resource 634 may also be coupled to address interface 604-2. Processing resource 634 may receive commands via command interface 604-1. Commands received by processing resource 634 may be used to program processing resource 634 to perform the various functions described herein.

[0061] In addition to activating different processing resources, processing resource 634 can also activate row control unit 608 and / or column control unit 612. Row control unit 608 and column control unit 612 can be activated to provide data values ​​from memory cells of memory array 610 to sense amplifier 611 and from sense amplifier 611 to corresponding processing resources. The memory cells can store weights of an artificial neural network; for example, activating row control unit 608 and / or column control unit 612 can provide weights to corresponding processing resources to execute corresponding processes.

[0062] In various instances, processing resource 634 can receive and / or output data via data interface 604-3. Given that processing resource 634 can output results as the result of executing multiple processes that may be partially asynchronous, processing resource 634 may not be able to provide results synchronously with the host's expected results. To overcome the challenge of providing results via data interface 604-3 when the host expects results, processing resource 634 can hold the results until synchronous delivery of the data is scheduled. Processing resource 634 can provide results after different data has been synchronously provided via data interface 604-3.

[0063] For example, commands to execute multiple asynchronous processes can be received by memory device 603 via command interface 604-1 and / or address interface 604-2. Multiple processes can be executed, and the results can be generated by processing resource 634. Independent of commands to execute multiple processes, memory device 603 can receive commands to execute multiple synchronous operations and / or processes. For example, a read command can be received via command interface 604-1, and the address corresponding to the read command can be received via address interface 604-2. After a read command is received by memory device 603, the memory device can output data read from the memory cell with the address for twenty to twenty-two clock cycles via data interface 604-3. After the read data is provided, processing resource 634 can provide the result via data interface 604-3.

[0064] However, the result of the process provided after data is read from memory array 610 may be incompatible with the standard interface protocol but compatible with a specific interface protocol. Defining different interface protocols can be different from the purpose of simply changing pins using a single interface protocol. For example, an interface protocol may provide "open" pins. An open pin description indicates a pin that can be used to provide signals not defined by the interface protocol. However, when an address is provided via an open pin, providing signals (such as commands) via an open pin does not make the interface protocol incompatible with itself. When different types of signals are provided via open pins, the interface protocol remains compatible with itself because the pin is open. However, redefining each of the pins can lead to different interface protocols being incompatible with each other.

[0065] As used herein, compatibility describes the ability to decode signals received through each of the pins using either the first or second interface protocol without loss of functionality. Compatibility may also include encoding signals using either the first or second interface protocol without degrading the data encoded by the signal. For example, if the host uses the first interface protocol to provide a signal representing a read command to memory device 603 through a specific pin, and the memory device decodes the signal into a write command using the second interface protocol, then the first and second interface protocols are incompatible. Decoding a single signal into anything other than what it was encoded into can result in incompatibility between the interface protocol used to encode the signal and the interface protocol used to decode the signal, except for signals provided via open pins.

[0066] Implementing an incompatible interface protocol also provides the ability to output data at different times compared to outputting data using a compatible interface protocol. When the memory device 603 is in a mode corresponding to the incompatible interface protocol, it can receive commands for performing asynchronous operations. When the memory device 603 is in an incompatible interface protocol mode, it can provide the output of the results of the asynchronous process.

[0067] The host can be configured to receive data in response to a read command being provided to memory device 603 when in a compatible mode. The host can also be configured to receive the results of multiple asynchronous processes when in an incompatible mode. The host can "listen" for unscheduled data after receiving scheduled data. As used herein, scheduled data describes data provided and / or received at an expected time. Unscheduled data describes data provided and / or received at an unexpected time.

[0068] Figure 7Example flowcharts illustrating methods for performing operations in memory according to several embodiments of the present disclosure are provided. At 760, in response to receiving a command from the memory device, a first process can be executed at a first processing resource implemented under the memory array of the memory device, wherein the first process utilizes a first portion of data stored in the memory array to perform the operation. At 762, a determination can be performed asynchronously. The determination can determine whether to provide a signal to a second processing resource based on the result of the first process, wherein the second processing resource is selected based on the result of the first process. At 764, a second process can be executed using a second processing resource implemented under the memory array. The second process can be executed in response to receiving a signal. The second process can be executed using a second portion of data stored in the memory array.

[0069] The method may also include asynchronously performing a determination using logic (e.g., a comparator) configured to compare the result with multiple thresholds. Each of the multiple thresholds may be associated with the selection of different processing resources, including a second processing resource. For example, if the result is less than a first threshold, the comparator may signal a third processing resource; if the result is greater than the first threshold but less than a second threshold, the comparator may signal a fourth processing resource.

[0070] Logic that operates asynchronously to the clock signal of the host device may be coupled to a first processing resource. The first processing resource may provide results to the logic. The logic may be implemented under a memory array. For example, the memory array may be implemented in a first hardware layer of the memory device, and the processing resource and / or logic may be implemented in a second hardware layer of the memory array.

[0071] Logic can couple processing resources, providing a topology between processing resources. For example, a first processing resource can be selectively coupled to multiple processing resources, including a second processing resource, via logic that operates asynchronously with the clock signal of the host device. In various examples, processing resources can be selectively coupled to different processing resources, rather than multiple processing resources, via logic.

[0072] Processing resources can be selectively coupled to multiple processing resources via one or more instances of logic. For example, a processing resource can provide results to multiple instances of logic. Each instance of logic can be configured to couple a processing resource to a different processing resource. For instance, if the result is greater than a first threshold, then the first instance of logic can be configured to couple a first processing resource to a second processing resource. If the result is greater than a second threshold, then the second instance of logic can be configured to couple the first processing resource to a third processing resource, and so on. The first threshold and the second threshold may be equal or different. Implementing different instances of logic provides a topology for selecting processing resources based on process results.

[0073] In each instance, the processing resource providing the result may be selectively coupled to multiple first processing resources. The processing resource receiving the signal may also be selectively coupled to multiple different processing resources providing the signal via multiple instances of logic (comparators). The result of the process executed by the processing resource may be provided to the logic under a memory array. The logic may signal to the processing resource under the memory array in response to the result being greater than or less than a threshold.

[0074] Regardless of whether the first and second processing resources operate asynchronously with the host device's clock signal, the logic can operate asynchronously. For example, when the logic operates asynchronously with the host device's clock signal, the processing resources can operate asynchronously. As used herein, processing resources and / or logic can operate asynchronously with control signals and / or the host device's clock signal. References to synchronization are made in the context of control signals.

[0075] The second processing resource can be configured to execute a second process without the device receiving additional signals. For example, the host can provide a first command that can be used to enable the execution of a first process by the first processing resource. The result of the first process can be used to start a second process executed by the second processing resource. The second process can be started without requiring additional commands and / or signals from the host.

[0076] The memory device can export the results of a first process and the results of a second process on an interface that couples the device to a host during the operation of another command. The operation of the other command may include reading data from the memory array and providing the data to the host. During the process of providing data from the memory device to the host in response to receiving a read command, the memory device can provide the results of the first and second processes. For example, the results can be provided after the data has been read and provided to the host.

[0077] The results of the first and second processes can be provided (e.g., exported) during device operation in non-compatible mode. In compatible mode, the results of the first and / or second processes can be stored in one or more memory arrays coupled to the processing resources executing the first and second processes.

[0078] Figure 8 An example machine illustrating computer system 890 is described, within which a set of instructions is executable to cause the machine to perform the various methodologies discussed herein. In various embodiments, computer system 890 may correspond to a system (e.g., Figure 1 System 100), which includes, is coupled to, or utilizes a memory subsystem (e.g., a memory subsystem). Figure 1 (a memory device 103) or a controller that can be used to execute (e.g., a memory device 103) Figure 1The operation of the controller circuitry system 105). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer-to-peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0079] A machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network device, a server, a network router, a switch, or a bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by said machine. Furthermore, while a single machine is described, the term "machine" should also be considered as any collection of machines that individually or jointly execute one (or more) instructions to perform any or more of the methodologies discussed herein.

[0080] The example computer system 890 includes processing resources 892, main memory 894 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), static memory 898 (e.g., flash memory, static random access memory (SRAM)), and data storage system 899, which communicate with each other via bus 897.

[0081] Processing resource 892 represents one or more general-purpose processing devices, such as microprocessors, central processing units, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or multiple processors implementing combinations of instruction sets. Processing resource 892 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing resource 892 is configured to execute instructions 893 for performing the operations and steps discussed herein. Computer system 890 may further include a network interface device 895 for communication via network 820.

[0082] Data storage system 899 may include machine-readable storage medium 891 (also referred to as computer-readable medium) thereon storing one or more sets of instructions 893 or software embodying any or more of the methodologies or functions described herein. Instructions 893 may also reside wholly or at least partially in main memory 894 and / or processing resources 892 during their execution by computer system 890, which also constitute machine-readable storage medium.

[0083] In one embodiment, instruction 893 includes implementations corresponding to Figure 1 The machine-readable storage medium 891 is shown as a single medium in the exemplary embodiment, but the term "machine-readable storage medium" should be understood to include a single medium or multiple media containing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any or more of the methods of this disclosure. The term "machine-readable storage medium" should be accordingly understood to include (but is not limited to) solid-state memory, optical media, and magnetic media.

[0084] As used herein, "several things" can refer to one or more of such things. For example, "several memory devices" can refer to one or more memory devices. "Multiple things" would prefer to be two or more. Additionally, the designation "N" as used herein (especially with respect to reference element symbols in the figures) indicates that several specific features so indicated may be included in several embodiments of this disclosure.

[0085] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements that achieve the same computational results may be used instead of the specific embodiments shown. This disclosure is intended to cover adaptations or variations of the various embodiments of this disclosure. It should be understood that the foregoing description is illustrative and non-limiting. Those skilled in the art will understand, upon reviewing the foregoing description, combinations of the foregoing embodiments and other embodiments not explicitly described herein. The scope of the various embodiments of this disclosure includes other applications in which the foregoing structures and methods are used. Therefore, the scope of the various embodiments of this disclosure should be determined with reference to the appended claims and the full scope of the equivalents entitled to by such claims.

[0086] In the foregoing detailed embodiments, various features are grouped into a single embodiment for the purpose of simplifying this disclosure. This approach of the disclosure should not be interpreted as reflecting an intention that the disclosed embodiments of the disclosure must use more features than those expressly cited in each claim. Rather, as reflected in the appended claims, the subject matter of the invention lies in fewer than all features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed embodiments, wherein each claim is an independent, separate embodiment.

Claims

1. An apparatus for implementing an asynchronous process topology in a memory device, comprising: The memory array (110-1, 110-2, 110-3, ..., 110-N, 610) is configured to store data and operate synchronously with a clock signal received from the host device (102); Processing resources (334-1, 334-2, ..., 334-M, 434-1, 434-2, ..., 434-R, 434-R+1, 434-R+2, 534-1, 534-2, ..., 534-M, 634), implemented in hardware, coupled to the memory array and multiple sense amplifiers, and configured to: In response to receiving a signal from the device, a first process (222-1, 222-2, ..., 222-M) is executed using the data stored in the memory array and provided by at least one of the plurality of sensing amplifiers, wherein the first process includes a first layer of an artificial neural network; Asynchronously determining that the result of the first process is greater than a threshold without referencing multiple clock signals, including the clock signal of the host device; and In response to the determination that the result of the first process is greater than the threshold, a second process (222-1, 222-2, ..., 222-M) including logical operations is performed on the data, wherein the second process includes a second layer of the artificial neural network; The second process is started without requiring additional commands from the host device.

2. The device of claim 1, wherein the processing resources are configured to execute the first process asynchronously with the clock signal of the host device.

3. The device according to claim 1, wherein the processing resources are further configured to execute the first process and the second process asynchronously with the clock signal of the host device.

4. The device according to any one of claims 1 to 3, wherein the processing resources are further configured to execute a third process (222-1, 222-2, ..., 222-M) in response to determining that the result is greater than different thresholds.

5. The device according to any one of claims 1 to 3, wherein the processing resources are further configured to avoid executing the second process in response to determining that the result is not greater than the threshold.

6. The device according to any one of claims 1 to 3, further comprising an input / output (I / O) circuitry (107) configured to asynchronously provide the result of the second process with respect to the clock signal of the host device.

7. A method for implementing an asynchronous process topology in a memory device, comprising: In response to receiving a command (220) from a memory device (103, 203, 303, 403, 503, 603), a first process (222-1, 222-2, ..., 222-M) is executed at a first processing resource (334-1, 334-2, ..., 334-M, 434-1, 434-2, ..., 434-R, 434-R+1, 434-R+2, 534-1, 534-2, ..., 534-M, 634) under a memory array (110-1, 110-2, 110-3, ..., 110-N, 610) implemented in the memory device, wherein the first process is executed using a first portion of data stored in the memory array, and wherein the first processing resource includes a first layer of an artificial neural network; Asynchronously execute the determination, based on the result of the first process, whether to provide a signal to the second processing resource (334-1, 334-2, ..., 334-M, 434-1, 434-2, ..., 434-R, 434-R+1, 434-R+2, 534-1, 534-2, ..., 534-M, 634), without referring to multiple clock signals including the clock signal of the host device; The second processing resource is selected from multiple processing resources based on the result of the first process; as well as In response to the reception of the signal, a second process (222-1, 222-2, ..., 222-M) is executed using the second processing resource implemented under the memory array, wherein the second process is executed using a second portion of the data stored in the memory array, and wherein the second processing resource includes a second layer of the artificial neural network; The second process is started without requiring additional commands from the host device.

8. The method of claim 7, further comprising asynchronously performing the determination using comparator logic (551-1, 551-2, ..., 551-M) implemented in hardware and configured to compare the result with a plurality of thresholds, wherein each of the plurality of thresholds is associated with the selection of different processing resources (334-1, 334-2, ..., 334-M, 434-1, 434-2, ..., 434-R, 434-R+1, 434-R+2, 534-1, 534-2, ..., 534-M, 634) including the second processing resource.

9. The method of claim 8, wherein the comparator logic, which operates asynchronously, is coupled to the first processing resource, and wherein the method further comprises providing the result of the first process to the comparator logic.

10. The method of claim 8, further comprising providing a signal between the first processing resource and the plurality of processing resources (334-1, 334-2, ..., 334-M, 434-1, 434-2, ..., 434-R, 434-R+1, 434-R+2, 534-1, 534-2, ..., 534-M, 634) including the second processing resource via the comparator logic which operates asynchronously with a clock signal of the host device (102).

11. The method of claim 10, further comprising selectively coupling the first processing resource to the second processing resource via the comparator logic which operates asynchronously with the clock signal of the host device.

12. The method of claim 10, further comprising selectively coupling the first processing resource to the plurality of processing resources via one or more instances of the comparator logic that operates asynchronously with the clock signal of the host device.

13. The method of claim 10, further comprising selectively coupling the second processing resource to the first processing resource and the plurality of processing resources via one or more instances of the comparator logic that operates asynchronously with the clock signal of the host device.

14. The method of claim 10, further comprising operating the comparator logic asynchronously regardless of whether the first processing resource and the second processing resource operate asynchronously with the clock signal of the host device.

15. The method of any one of claims 8 to 14, wherein the comparator logic is implemented under the memory array, and the method further comprises providing the signal to the second processing resource under the memory array.

16. An apparatus for implementing an asynchronous process topology in a memory device, comprising: The first memory array (110-1, 110-2, 110-3, ..., 110-N, 610) is implemented in the first hardware layer of the memory device; The second memory array (110-1, 110-2, 110-3, ..., 110-N, 610) is implemented in the first hardware layer of the memory device; First processing resources (334-1, 334-2, ..., 334-M, 434-1, 434-2, ..., 434-R, 434-R+1, 434-R+2, 534-1, 534-2, ..., 534-M, 634) are implemented in a second hardware layer of the memory device under the first memory array and configured to execute a first process (222-1, 222-2, ..., 222-M) using a first data value from the first memory array; Comparators (551-1, 551-2, ..., 551-M), implemented in the second hardware layer of the memory device and coupled to the first and second processing resources, are configured to provide signals to the second processing resources (334-1, 334-2, ..., 334-M, 434-1, 434-2, ..., 434-R, 434-R+1, 434-R+2, 534-1, 534-2, ..., 534-M, 634) based on the result of the first process; The comparator is configured to provide the signal without referencing a plurality of clock signals, including the clock signal of the host device (102); and The first processing resource and the comparator are implemented in a first memory bank (440-1, 440-2, ..., 440-M) of the memory device, and the first processing resource includes a first artificial neural network; and The second processing resource, implemented in the second hardware layer of the memory device under the second memory array, and configured to execute a second process (222-1, 222-2, ..., 222-M) using a second data value from the second memory array, wherein the second processing resource is configured to execute the second process in response to receiving the signal from the comparator, wherein the second processing resource is implemented in a second memory bank (440-1, 440-2, ..., 440-M) of the memory device including the second memory array, and wherein the second processing resource includes a second artificial neural network; and The second process is started without requiring additional commands from the host device.

17. The apparatus of claim 16, wherein the second processing resource is configured to execute the second process without the memory device receiving additional signals.

18. The device of claim 16, wherein the first memory array, the second memory array, the first processing resource, and the second processing resource operate asynchronously using the clock signal of the host device.

19. The device according to any one of claims 16 to 18, wherein the device is further configured to derive the results of the first process and the results of the second process on an interface (104, 604-1, 604-2, 604-3), the interface coupling the device to a host (102) during the operation of another command.

20. The apparatus of claim 19, wherein the apparatus is configured to export the result of the first process and the result of the second process during operation of the memory device in a non-compatible mode, and is further configured to store the result of the first process and the result of the second process to the first memory array or the second memory array during operation of the memory device in a compatible mode.

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