Method for manufacturing a piezoelectric structure for a radio frequency device and capable of transferring a piezoelectric layer and method for transferring such a piezoelectric layer

Abstract

A method for manufacturing a piezoelectric structure (10, 10') characterized in that it comprises the steps of providing a substrate (20) of piezoelectric material, providing a carrier substrate (100), depositing a dielectric bonding layer (1001) on a single side of the substrate (20) of piezoelectric material at a temperature lower than or equal to 300°C, bonding the substrate (20) of piezoelectric material to the carrier substrate (100) through the dielectric bonding layer (1001) (1'), a thinning step (2') for forming a piezoelectric structure (10, 10') comprising a layer (200) of piezoelectric material bonded to the carrier substrate (100).

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a piezoelectric structure for use in radio frequency devices and capable of transferring a piezoelectric layer, and a method for transferring such a piezoelectric layer. Background Technology

[0002] The known practice is to fabricate radio frequency (RF) devices (e.g., resonators or filters) on a substrate that, from its base to its surface, sequentially comprises a carrier substrate (which is typically made of a material such as silicon or sapphire), an intermediate bonding layer, and a piezoelectric layer.

[0003] Surface acoustic wave (SAW) filters typically consist of a piezoelectric layer and two electrodes in the form of two interleaved metal combs deposited on the surface of the piezoelectric layer. Depending on the operation of the SAW filter, the thickness of the piezoelectric layer can range from tens of nanometers to tens of micrometers. In the latter case, parasitic propagation modes exist extending into the thickness of the piezoelectric layer and are easily reflected at the interface with the underlying carrier substrate. This phenomenon is called "rattle." To avoid these parasitic modes, it is known to roughen the surface of the piezoelectric layer at the interface with the intermediate bonding layer sufficiently so that parasitic waves are reflected in all directions. Considering the expected operating wavelength of the resonator, the roughness of the piezoelectric layer's surface is extremely high, on the order of magnitude of the operating wavelength (several micrometers).

[0004] Piezoelectric layers are typically obtained by transferring a thick substrate of piezoelectric material (e.g., obtained by cutting a casting) onto a carrier substrate. For example, the carrier substrate is a silicon substrate.

[0005] The transfer of the piezoelectric layer requires bonding a thick piezoelectric substrate to a carrier substrate, and then thinning the thick piezoelectric substrate so that only a thin piezoelectric layer of the required thickness for manufacturing the RF device is left on the carrier substrate.

[0006] To achieve good adhesion between the piezoelectric substrate and the carrier substrate, an oxide (e.g., silicon oxide SiO2) layer is typically deposited on each of the two substrates, and the substrates are bonded together by means of the oxide layer.

[0007] On the one hand, because the piezoelectric material and the carrier substrate have very different coefficients of thermal expansion, this annealing process can cause significant deformation of the component.

[0008] On the other hand, depositing an oxide layer on a thick piezoelectric substrate can cause the piezoelectric substrate to bend significantly, which is incompatible with the subsequent steps of the method for designing a flat substrate.

[0009] Finally, as mentioned above, due to the difference in thermal expansion coefficients between the thick piezoelectric substrate and the processed substrate, the heterostructure cannot undergo consolidation annealing. However, without consolidation annealing, the bonding energy between the oxide layers of the two substrates remains very low, resulting in insufficient mechanical strength of the donor dummy substrate. Therefore, fracture may occur at the bonding interface during the step of thinning the thick piezoelectric substrate.

[0010] To ensure good adhesion between the thick piezoelectric substrate and the carrier substrate (especially when the thick piezoelectric substrate has a high roughness), current methods require numerous steps, such as depositing multiple oxide layers and then chemically mechanically polishing (CMP) the oxide layers, which are deposited alternately on both sides of the thick piezoelectric substrate to avoid significant bending (which would prevent bonding). Summary of the Invention

[0011] The present invention aims to overcome these limitations of the prior art by providing a method for manufacturing a piezoelectric structure for radio frequency devices (which can also be used to transfer a piezoelectric layer) and a method for transferring such a piezoelectric layer.

[0012] The present invention relates to a method for manufacturing a piezoelectric structure, the method being characterized by comprising the steps of providing a piezoelectric material substrate, providing a carrier substrate, depositing a dielectric bonding layer on a single surface of the piezoelectric material substrate at a temperature of 300°C or below, bonding the piezoelectric material substrate to the carrier substrate via the dielectric bonding layer, and thinning the piezoelectric structure to form a piezoelectric structure comprising a piezoelectric material layer bonded to the carrier substrate.

[0013] Therefore, as described above, the low stress resulting from depositing the dielectric bonding layer at a low temperature of 300°C or below ensures sufficient mechanical stability, allowing for the thinning steps described in the remainder of the specification and the subsequent assembly steps used in the manufacturing process of the component.

[0014] In some embodiments, the dielectric bonding layer includes a silicon oxide layer deposited on a piezoelectric material substrate by plasma-assisted chemical vapor deposition.

[0015] In an advantageous embodiment, the bonding step includes molecular bonding between the dielectric bonding layer and the carrier substrate, or between the dielectric bonding layer and a dielectric bonding layer formed on the carrier substrate.

[0016] In an advantageous embodiment, there is a bonding interface consolidation annealing at a temperature lower than the deposition temperature of the dielectric bonding layer.

[0017] In an advantageous embodiment, the thinning step is performed at a temperature lower than the deposition temperature of the dielectric bonding layer.

[0018] In an advantageous embodiment, the substrate of the piezoelectric material has a rough surface designed to reflect radio frequency waves.

[0019] In an advantageous embodiment, the thickness of the dielectric bonding layer is between 200 nm and 500 nm.

[0020] In an advantageous embodiment, a dielectric bonding layer is provided on the carrier substrate.

[0021] In an advantageous embodiment, the thinning step includes etching and / or chemical mechanical polishing.

[0022] The present invention also relates to a method for transferring a piezoelectric layer to a final substrate, comprising: providing a piezoelectric structure obtained by performing the aforementioned manufacturing method; forming a weakening region in a piezoelectric material layer to define the piezoelectric layer to be transferred; providing a final substrate; preferably, forming a dielectric bonding layer on the main surface of the final substrate and / or the piezoelectric material layer; bonding the piezoelectric material layer to the final substrate; and breaking and separating the piezoelectric structure along the weakening region at a temperature lower than or equal to the deposition temperature of the dielectric bonding layer.

[0023] In an advantageous implementation, the weakened region is formed by implanting atomic species into the piezoelectric material layer.

[0024] In an advantageous embodiment, the final substrate and the carrier substrate have the same coefficient of thermal expansion. Attached Figure Description

[0025] Other features and advantages of the invention will be better understood by reading the following detailed description with reference to the accompanying drawings, in which:

[0026] Figure 1 A manufacturing method according to one embodiment of the present invention and a substrate according to the embodiment of the present invention are shown;

[0027] Figure 2 A manufacturing method according to another embodiment of the present invention and a substrate according to the other embodiment of the present invention are shown;

[0028] Figure 3 A transfer method according to one embodiment of the present invention is shown;

[0029] Figure 4 A transfer method according to another embodiment of the present invention is shown.

[0030] To improve readability of the accompanying drawings, the layers are not necessarily shown to scale. Detailed Implementation

[0031] Figure 1A carrier substrate 100 (preferably silicon) is shown, to which a piezoelectric material layer 200 (preferably a single-crystal piezoelectric material, or more specifically lithium tantalate or lithium niobate) is transferred. Other materials for the piezoelectric material layer 200 are conceivable. The active layer to be transferred may also include ferroelectric materials, such as LiTaO3, LiNbO3, LiAlO3, BaTiO3, PbZrTiO3, KNbO3, BaZrO3, CaTiO3, PbTiO3, or KTaO3.

[0032] The donor substrate, including the active layer, can be in the form of a standardized circular wafer, for example, with a diameter of 150 mm or 200 mm. However, the invention is not limited in any way to these sizes or forms. The donor substrate can be removed from the ferroelectric material ingot in a manner that gives the donor substrate a predetermined crystal orientation, or the donor substrate can include a ferroelectric material layer bonded to a carrier substrate. The crystal orientation of the active layer of the ferroelectric material to be transferred is selected according to the intended application. Thus, for the material LiTaO3, an orientation between 30° and 60°XY or between 40° and 50°XY is typically chosen, particularly when it is desirable to utilize the thin-layer properties to form a SAW filter. For the material LiNbO3, an orientation of approximately 128°XY is typically chosen. However, the invention is by no means limited to a specific crystal orientation.

[0033] Regardless of the crystal orientation of the ferroelectric material in the donor substrate, the method includes, for example, introducing hydrogen and / or helium species (ions and / or atoms) into the donor substrate. This introduction can, for example, correspond to hydrogen implantation, i.e., bombardment of a flat surface of the donor substrate with hydrogen ions. It is well known that the purpose of the implanted ions is to form a weakened plane that defines a first ferroelectric material layer to be transferred, located on one side of the surface, and forming the remainder of the substrate. The nature and dosage of the implanted species, as well as the type and energy of the implanted ions, are selected based on the thickness of the layer to be transferred and the physicochemical properties of the donor substrate. In the case of a donor substrate made of LiTaO3, it is therefore possible to select an energy between 30 and 300 keV for implantation of 1 × 10⁻⁶ ions. 16 Up to 5×10 17 at / cm 2 The dosage of hydrogen is used to define the first layer, which is approximately 10 to 2000 nm.

[0034] The silicon carrier substrate 100 can also be replaced by a carrier substrate 100 made of sapphire, polycrystalline aluminum nitride (AlN), glass, or any other material having a coefficient of thermal expansion lower than that of the piezoelectric material layer 200 or an inverse coefficient of thermal expansion (in this invention, the coefficient of thermal expansion in a plane parallel to the main surface of the substrate is of interest). Therefore, the carrier substrate 100 acts as a reinforcing element, limiting the expansion of the piezoelectric structure 10 during the temperature changes it undergoes. This allows for a reduction in the thermal frequency coefficient of the piezoelectric material layer 200, that is, the degree to which the frequency of waves propagating through the piezoelectric material layer 200 changes with temperature. Silicon is particularly preferred because it allows for the addition of functionality, enabling electrical isolation for RF applications resulting from the addition of a surface trapping layer.

[0035] The use of silicon not only opens up applications for piezoelectric thin films in large-scale devices up to 300 mm in diameter, but also makes it compatible with the microelectronics industry, which has high requirements for the acceptance of materials other than silicon (especially lithium tantalate or lithium niobate) on the production line. Therefore, it is conceivable to integrate components obtained or manufactured in ferroelectric layers or even piezoelectric layers (e.g., SAW and / or BAW filters) with components obtained or formed in silicon substrates (e.g., transistors, power amplifiers, or even network switches), thereby reducing interconnection losses between different types of components and making such integrated systems more compact.

[0036] Figure 1 The diagram schematically illustrates bonding step 1' for bonding a piezoelectric material substrate 20 to a carrier substrate 100 (preferably silicon). This bonding step 1' for bonding the piezoelectric material substrate 20 to the carrier substrate 100 (preferably silicon) is preferably performed via a molecular adhesion step. The molecular adhesion step includes a bonding step (preferably at room temperature), and the bonding interface can then be solidified and annealed.

[0037] The diagram also schematically illustrates the deposition of the dielectric bonding layer 1001 on a single surface of the piezoelectric substrate 20 prior to bonding step 1', which involves bonding the piezoelectric substrate 20 to the carrier substrate 100 via the dielectric bonding layer 1001. The dielectric bonding layer 1001 is deposited at a temperature below or equal to 300°C. Typically, the deposition temperature of the dielectric bonding layer 1001 is chosen such that the bending caused by the difference in thermal expansion coefficients between the piezoelectric substrate 20 and the dielectric bonding layer 1001 remains compatible with the molecular bonding step, resulting in an assembly consisting of the piezoelectric substrate 20 and the dielectric bonding layer 1001 having a bending of less than or equal to 100 μm. The thickness of the dielectric bonding layer 1001 should be considered. Deposition temperatures below or equal to 300°C show good results within a hypothetical thickness range varying between 200 nm and 500 nm. It has been found that not only does the bending (80 to 90 μm for the 500 nm dielectric bonding layer 1001) remain below the threshold compatible with molecular bonding (approximately 100 μm), but the properties of the dielectric bonding layer 1001 also enhance the binding energy obtained between the dielectric bonding layer 1001 and the carrier substrate 100. The binding energy can therefore reach greater than 1 J / m. 2 These are relatively high values. These energies are high enough to achieve stable mechanical strength during subsequent steps, such as thinning or consolidation annealing.

[0038] The molecular adhesion step is preferably carried out at room temperature (i.e., about 20°C). However, this direct thermal bonding can be performed at temperatures between 20°C and 50°C. Furthermore, the bonding step is advantageously carried out at low pressure, that is, at a pressure less than or equal to 5 mTorr (1 Torr is exactly 101325 / 760 Pascals, i.e., about 133.322 Pa), which allows water to desorb from the surfaces forming the bonding interface. Performing the bonding step under vacuum allows for further improvement in water desorption at the bonding interface.

[0039] In an advantageous embodiment, the piezoelectric substrate 20 has a rough surface designed to reflect radio frequency waves. In this text, a "rough surface" refers to a surface whose roughness is on the same order of magnitude as the wavelength of the RF wave intended to propagate in the piezoelectric layer of a resonator or filter, so as to allow parasitic waves to be reflected in all directions, thereby preventing them from contributing to the output signal of the resonator or filter in question. In the context of this invention, the roughness of such a surface is between 1.0 and 1.8 μm (measured in a peak-to-valley manner). To fill this roughness, the dielectric bonding layer 1001 has a thickness greater than the roughness; flatness is achieved using chemical and / or mechanical etching steps.

[0040] Preferably, the dielectric bonding layer 1001 comprises a silicon oxide layer deposited on the piezoelectric material substrate 20, preferably by plasma-assisted chemical vapor deposition.

[0041] According to another embodiment, the dielectric bonding layer 1001 is a silicon oxide layer or a silicon nitride layer, or a layer comprising a combination of silicon nitride and silicon oxide, or a superposition of at least one layer of silicon oxide and one layer of silicon nitride, preferably obtained by plasma-assisted chemical vapor deposition.

[0042] In an advantageous embodiment, a bonding interface consolidation annealing is performed to enhance the mechanical strength of the piezoelectric structure. This annealing is carried out at a temperature below the deposition temperature of the dielectric bonding layer 1001, thus allowing for an increase in bonding energy without defects at the bonding interface due to the presence of any impurities (e.g., hydrogen) that degas and migrate toward the interface during this annealing process. The consolidation annealing is typically performed at a temperature below or equal to 300°C for durations ranging from several minutes to several hours.

[0043] like Figure 1 As schematically shown, after the piezoelectric material substrate 20 is bonded to the carrier substrate 100, the next step is a thinning step 2' for thinning the piezoelectric material substrate 20. Figure 1 The thinning step 2' is schematically illustrated, which can be achieved, for example, using chemical and / or mechanical etching (polishing, grinding, milling, etc.). This yields a piezoelectric material layer 200. The thinning step may also include the application of smart cutting. TM (SmartCut) TM The method is schematically illustrated in... Figure 3 and Figure 4 The process involves forming a weakened region in the layer to be transferred to define the layer to be transferred from the remaining layers of the substrate selected for transfer, thereby providing a transferable layer to a receiving substrate. The step of bonding the layer to be transferred to the receiving substrate typically utilizes molecular bonding. Then, a detachment step, including breaking and separating along the weakened region, is performed to form a heterostructure comprising the layer to be transferred to the receiving substrate. The thinning step is typically performed at a temperature below the deposition temperature of the dielectric bonding layer 1001, which allows the aforementioned defects at the bonding interface to be avoided due to the presence of any impurities (e.g., hydrogen) and their degassing and migration toward the interface during such thinning step.

[0044] Figure 2 The manufacturing method shown schematically in the diagram is similar to Figure 1The manufacturing method schematically illustrated differs in that a dielectric bonding layer 1002 is formed on the carrier substrate 100 prior to bonding step 1', thus the layer is present in the piezoelectric structure 10' obtained using the manufacturing method according to the invention. Depending on the material selected for the carrier substrate 100, the dielectric bonding layer 1002 is formed in such a way that molecular bonding is allowed between the assembly composed of the piezoelectric substrate 20 and the dielectric bonding layer 1001, and between the assembly 100' composed of the carrier substrate 100 and the dielectric bonding layer 1002. The bending of the assembly 200' is therefore kept less than or equal to 100 μm.

[0045] Preferably, the dielectric bonding layer 1002 comprises a silicon oxide layer. In the case of a carrier substrate 100 made of silicon material, it may be a thermal oxide, but the invention is not limited thereto. In a non-limiting manner, it may also be obtained by plasma-assisted chemical vapor deposition.

[0046] Figure 3 An embodiment of a method for transferring a piezoelectric layer 200' to a final substrate 300' is schematically illustrated, including providing a piezoelectric structure 10' (using... Figure 2 The method illustrated schematically (it should be understood that the invention is not limited to the described embodiment) involves forming a weakened region 0'' in the piezoelectric material layer 200 to define the piezoelectric layer 200' to be transferred from the remaining layer 201 of the piezoelectric material layer 200, providing a final substrate 300', and bonding the piezoelectric material layer 200 to the final substrate 300' in step 2'', which includes a detachment step 2'' of breaking and separating the piezoelectric structure 10' along the weakened region, thereby forming a heterostructure 30' including the piezoelectric layer 200' on the final substrate 300'. The detachment step is preferably performed at a temperature lower than or equal to the deposition temperature of the dielectric bonding layer 1001, preferably at a temperature lower than or equal to 300°C.

[0047] Figure 4 The transfer method illustrated in the diagram is similar to Figure 3 The difference in the transfer method schematically shown is that, prior to the bonding step 1'', a dielectric bonding layer 2001 is formed on the piezoelectric structure 10' and a dielectric bonding layer 2002 is formed on the final substrate 300'; these two dielectric bonding layers 2001 and 2002 are thus present in the heterostructure 30'' obtained using the transfer method according to the invention.

[0048] The thickness of the dielectric layer in the final structure is therefore the sum of the thicknesses of the two dielectric bonding layers. When the thickness of the dielectric layer in the final structure needs to conform to a certain range, a certain degree of flexibility in the fabrication of these layers is achieved on the piezoelectric structure or the final substrate. For example, the final substrate may already include the components described above, and therefore a certain thermal budget cannot be exceeded to avoid damaging these components. Therefore, a thicker dielectric layer can be formed on the piezoelectric structure than on the final substrate.

[0049] The invention is not limited thereto, and only one dielectric bonding layer may be formed on the piezoelectric structure 10' or on the final substrate 300'.

[0050] The bonding step 1'' for bonding the piezoelectric structure 10' to the final substrate 300' (preferably silicon) is preferably performed using a molecular adhesion step. The molecular adhesion step includes a bonding step (preferably at room temperature), and the bonding interface can then be solidified and annealed.

[0051] for Figure 3 and Figure 4 The transfer method schematically illustrated involves forming a weakened region 0'' by implanting atomic species into a piezoelectric material layer 200. Typically, hydrogen ions are used to perform the implantation step 0''. An interesting alternative known to those skilled in the art involves replacing all or part of the hydrogen ions with helium ions.

[0052] For the piezoelectric material layer 200 of lithium tantalate, the hydrogen implantation dose will typically be between 6 × 10⁻⁶. 16 cm -2 Up to 1×10 17 cm -2 The injection energy will typically be between 50 and 170 keV. Therefore, desorption is usually performed at temperatures between 150°C and 300°C. This results in a piezoelectric layer thickness of 200 nm, on the order of 10 nm to 500 nm.

[0053] The final substrate 300' and the carrier substrate 100 can advantageously have the same or at least very similar coefficients of thermal expansion, which allows for better mechanical strength and less deformation during the bonding interface consolidation annealing. Both substrates can have the same properties and are essentially made of silicon, except for the dielectric bonding layer or, if present, a trapping layer. The latter does not have sufficient thickness to significantly affect the benefits of the "sandwich" structure having the final substrate 300' and the carrier substrate 100 of the same material.

[0054] After disengagement, it is advantageous to add additional technical steps to strengthen the bonding interface, restore a good roughness level, or correct any defects generated during the implantation step (e.g., or to prepare the surface for restoration by other methodological steps, such as forming electrodes for SAW-type devices). These steps are, for example, polishing, chemical etching (wet or dry), annealing, and chemical cleaning. These steps can be used alone or in combination, as will be able to be adapted by those skilled in the art.

[0055] In an advantageous embodiment, the carrier substrate 100 and / or the final substrate 300' can be a silicon substrate having a resistivity greater than 1 kΩ·cm. The carrier substrate 100 and / or the final substrate 300' may also include a charge trapping layer disposed on the surface of the silicon substrate intended for bonding. The trapping layer may comprise undoped polycrystalline silicon. In some cases, particularly when the trapping layer has sufficient thickness (e.g., greater than 30 μm), the silicon substrate can have a standard resistivity less than 1 kΩ·cm. Typically, it is an amorphous layer with structural defects such as dislocations, grain boundaries, amorphous regions, gaps, inclusions, pores, etc. These structural defects form traps for charge to easily flow through the material, for example, at the sites of incomplete or dangling chemical bonds. Therefore, conduction is blocked in the trapping layer, thus exhibiting a high resistivity. Advantageously, and for ease of implementation, the trapping layer is formed of a polycrystalline silicon layer. Particularly when it is formed on a resistive silicon substrate, its thickness can be between 0.3 μm and 3 μm. However, thicknesses below or above this range are perfectly acceptable, depending on the expected level of RF performance. To maintain the polycrystalline quality of the layer during the thermal processing that the carrier substrate 100 or the final substrate 300' may undergo, an amorphous layer made of silicon oxide can advantageously be provided on the substrate, for example, prior to the deposition of the charge trapping layer. Alternatively, the trapping layer can be formed by implanting heavy species (e.g., argon) into the surface thickness of the substrate to create structural defects constituting the electric traps. The layer can also be formed by porosifectizing the surface thickness of the substrate.

Claims

1. A method for manufacturing a piezoelectric structure (10, 10') for a radio frequency device, the method comprising providing a piezoelectric material substrate (20), providing a carrier substrate (100), depositing a dielectric bonding layer (1001) onto a single surface of the piezoelectric material substrate (20) at a temperature below or equal to 300°C, bonding the piezoelectric material substrate (20) to the carrier substrate (100) via the dielectric bonding layer (1001) (1'), a thinning step (2') comprising thinning the substrate of the piezoelectric material layer (200) bonded to the carrier substrate (100), and a bonding interface consolidation annealing at a temperature below the deposition temperature of the dielectric bonding layer (1001).

2. The method according to the preceding claim, wherein, The dielectric bonding layer (1001) includes a silicon oxide layer deposited on a piezoelectric material substrate (20) by plasma-assisted chemical vapor deposition.

3. The method according to any one of the preceding claims, wherein, The bonding step (1') includes molecular bonding between the dielectric bonding layer (1001) and the carrier substrate (100) or between the dielectric bonding layer (1001) and the dielectric bonding layer (1002) formed on the carrier substrate (100).

4. The method according to claim 1, wherein, The thinning step (2') is performed at a temperature lower than the deposition temperature of the dielectric bonding layer (1001).

5. The method according to claim 1, wherein, The substrate (20) of the piezoelectric material has a rough surface designed to reflect radio frequency waves.

6. The method according to claim 1, wherein, The thickness of the dielectric bonding layer (1001) is between 200 nm and 500 nm.

7. The method of claim 1, further comprising providing a dielectric bonding layer (1002) on a carrier substrate (100).

8. The method according to claim 1, wherein, The thinning step (2') includes etching and / or chemical mechanical polishing.

9. A method for transferring a piezoelectric layer (200') to a final substrate (300'), comprising: The method provides a piezoelectric structure (10, 10') obtained by implementing any of the preceding claims for manufacturing a piezoelectric structure, forming a weakened region (0'') in a piezoelectric material layer (200) to define the piezoelectric layer (200') to be transferred, providing a final substrate (300'), and a step (1'') of bonding the piezoelectric material layer (200) and the final substrate (300') together, including a detachment step (2'') of breaking and separating the piezoelectric structure (10, 10') along the weakened region at a temperature below or equal to the deposition temperature of the dielectric bonding layer (1001).

10. The method of claim 9, further comprising: Dielectric bonding layers (2001, 2002) are formed on the main surface of the final substrate (300') and / or the piezoelectric material layer (200).

11. The method according to claim 9, wherein, Weakened regions are formed by injecting atomic species into the piezoelectric material layer (200).

12. The method according to claim 9, wherein, The final substrate (300') and the carrier substrate (100) have the same coefficient of thermal expansion.

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