Wafer level package structure, manufacturing method thereof and sensor

Abstract

The application provides a wafer-level packaging structure, a manufacturing method thereof and a sensor, relates to the packaging technology field of integrated circuits, and can improve the signal transmission accuracy of a wafer-level sensor. The wafer-level packaging structure comprises a device wafer, a plurality of reference devices and a cushion wafer. The reference devices are arranged on the device wafer and are configured to set the reference devices. The cushion wafer is arranged on the device wafer and comprises a first subpart and a second subpart connected to each other; the first subpart is arranged around the reference devices; one reference device region is arranged in an area surrounded by the first subpart; the second subpart covers the reference device region in the orthographic projection on the device wafer; and in the direction away from the device wafer, the surface of the second subpart away from the first subpart is inclined towards the side close to the first subpart. The application is used for transmitting sensing signals.

Description

Technical Field

[0001] This application relates to the field of integrated circuit packaging technology, and in particular to a wafer-level packaging structure and its fabrication method, and a sensor. Background Technology

[0002] Micro-Electro-Mechanical Systems (MEMS) are miniature integrated systems that utilize integrated circuit manufacturing technology and micromachining technology to fabricate microsensors and microactuators on a single chip. Among them, MEMS sensors have advantages such as small size, light weight, low power consumption, high reliability, high sensitivity, and ease of integration, and are gradually replacing traditional mechanical sensors.

[0003] Wafer-level packaging (WLP) is a structure that first encapsulates multiple MEMS sensors into a single package, and then dices the wafer-level package to form multiple independent MEMS sensor packages. The MEMS sensor package includes the MEMS sensor itself. MEMS sensors are susceptible to changes in their resistance due to external environmental factors, which causes deviations in the output electrical signal from the actual situation, affecting the performance of the MEMS sensor. Typically, adjusting the MEMS sensor package structure improves its performance, and since the packaging cost accounts for approximately 50%-80% of the total cost, how to design the MEMS sensor package structure is a key research direction for those skilled in the art. Summary of the Invention

[0004] Embodiments of this application provide a wafer-level packaging structure and its fabrication method, as well as a sensor, which can improve the signal transmission accuracy of wafer-level sensors.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, a wafer-level packaging structure is provided. The wafer-level packaging structure includes a device wafer, a plurality of reference device regions, and a padding wafer. The plurality of reference device regions are disposed on the device wafer and configured to house reference devices. The padding wafer is disposed on the device wafer; the padding wafer includes a plurality of padding regions, each padding region including a first sub-region and a second sub-region, the second sub-region being connected to the first sub-region. A reference device region is disposed within the area enclosed by the first sub-region; the orthographic projection of the second sub-region onto the device wafer covers the reference device region; and, along a direction away from the device wafer, the surface of the second sub-region away from the first sub-region is inclined toward the side closer to the first sub-region.

[0007] The reference device is configured to output a signal for reference, enabling the wafer-level package (WLP) structure to accurately correct or determine the actual output signal based on the reference signal, thereby improving the performance of the individual structures after dicing. The second sub-section's orthogonal projection onto the device wafer covers the reference device. This reduces the influence of external electromagnetic waves on the value of the reference signal output by the reference device, improving the accuracy of the reference signal. Simultaneously, along the direction away from the device wafer, the surface of the second sub-section away from the first sub-section tilts towards the side closer to the first sub-section; that is, the thickness of the second sub-section decreases along the direction away from the first sub-section. This reduces the blocking effect of the second sub-section on other electronic devices located on the side of the reference device away from the first sub-section, thus improving the reception of external electromagnetic waves by other electronic devices and enhancing the performance of the wafer-level package structure.

[0008] In some examples, the wafer-level packaging structure also includes multiple functional device regions; the functional device regions are disposed in the area enclosed by the first sub-part, configured to house functional devices and output sensing signals; along a direction perpendicular to the device wafer, the two ends of the second sub-part are respectively flush with the two ends of the first sub-part; and the orthographic projection of the second sub-part on the device wafer does not overlap with the functional device regions.

[0009] In some examples, the padding region has vias. The vias are located further away from the openings of the functional devices and are larger than the vias located closer to the openings of the functional devices. The boundary of the orthographic projection of the vias onto the device wafer surrounds the functional device region.

[0010] In some examples, the padding region further includes at least one barrier layer. The at least one barrier layer is disposed on the side of the second sub-section adjacent to the reference device region and is connected to the second sub-section. The orthogonal projection of the barrier layer onto the device wafer covers the reference device region and is configured to block electromagnetic waves from irradiating the reference device.

[0011] In some examples, the padding region also includes at least one getter. The orthographic projection of the at least one getter on the device wafer does not overlap with the orthographic projection of the functional device region on the device wafer; and / or, the barrier layer includes a getter.

[0012] In some examples, the wafer-level packaging structure also includes a cap wafer. The cap wafer is disposed on the side of the pad wafer away from the device wafer. The cap wafer, multiple pad regions, and the device wafer enclose multiple hermetically sealed cavities. A reference device region and a functional device region are grouped together; at least one group of functional device regions and reference device regions is located within a cavity.

[0013] In some examples, the region within the cavity enclosed by the edge of the functional device region extending in a direction perpendicular to the device wafer is spaced apart from the surface of the second sub-part away from the first sub-part.

[0014] In a second aspect, a sensor is provided. The sensor includes a device layer, a reference device, and a pad layer. The reference device is disposed on the device layer. The pad layer is disposed on the device layer and includes a first sub-part and a second sub-part connected together. Along a direction away from the device wafer, the surface of the second sub-part is inclined toward the side closer to the first sub-part away from the surface of the first sub-part; wherein, a reference device is disposed within the area enclosed by the first sub-part; the orthographic projection of the second sub-part onto the device wafer covers the reference device.

[0015] The sensor provided in the embodiments of this application is formed by cutting the wafer-level packaging structure provided in the first aspect, and therefore has all the beneficial effects of the wafer-level packaging structure described above, which will not be repeated here.

[0016] In some examples, the second sub-part is located near the surface of the device layer, connected to the surface of the first sub-part near the device layer, and lies on the same plane.

[0017] In some examples, the sensor also includes a functional device disposed within the area enclosed by the first sub-part and configured to output a sense signal. The orthographic projection of the second sub-part onto the device layer does not overlap with the functional device; along a direction perpendicular to the device wafer, the two ends of the second sub-part are flush with the two ends of the first sub-part; and external electromagnetic waves irradiate the functional device along the inclined surface of the second sub-part away from the first sub-part.

[0018] In some examples, the padding layer has vias. The vias are located further away from the openings of the functional devices and are larger than the vias located closer to the openings of the functional devices. The boundary of the orthographic projection of the vias onto the device wafer surrounds the functional device region.

[0019] In some examples, the sensor also includes a blocking layer disposed on the side of the second sub-section near the reference device and connected to the second sub-section; the orthographic projection of the blocking layer on the device layer covers the reference device and is configured to block electromagnetic waves from illuminating the reference device.

[0020] In some examples, the sensor also includes a getter. The orthographic projection of the getter onto the device layer does not overlap with the orthographic projection of the functional device onto the device layer; and / or, the barrier layer includes a getter.

[0021] In some examples, the sensor also includes a capping layer. The capping layer is disposed on the side of the padding layer away from the device wafer. The capping layer, padding layer, and device layer enclose a sealed cavity in which the functional device and reference device are located.

[0022] In some examples, the region within the cavity enclosed by the edge of the functional device extending in a direction perpendicular to the device wafer is spaced apart from the surface of the second sub-part away from the first sub-part.

[0023] Thirdly, a method for fabricating a wafer-level packaging structure is provided. This method is used to fabricate a wafer-level packaging structure as provided in any example of the first aspect above. The method includes: fabricating a device wafer having multiple reference device regions; and providing reference devices within the reference device regions.

[0024] A padding wafer is fabricated, comprising multiple padding regions. Each padding region includes a connected first sub-region and a second sub-region. Along a direction away from the device wafer, the second sub-region is inclined towards the side closest to the first sub-region, away from its surface. The padding wafer is aligned and bonded to the surface of a device wafer that serves as a reference device. A reference device region is located within the area enclosed by the first sub-region, and the orthographic projection of the second sub-region onto the device wafer covers the reference device region.

[0025] In some examples, forming the padding wafer includes: forming a second seal and a third seal on two opposing surfaces of the padding wafer; forming a barrier layer on the surface of the padding wafer where the third seal is located; and the third seal surrounding the barrier layer. The padding wafer is etched to form vias; the via walls are the surfaces of the second sub-parts away from the first sub-parts.

[0026] In some examples, fabricating a device wafer further includes: setting multiple functional device regions on the device wafer, with functional devices disposed within the functional device regions; and external electromagnetic waves irradiating the functional devices along an inclined surface of the second sub-part away from the first sub-part.

[0027] There is a gap between the functional device area and the reference device area; and the functional device is located within the boundary of the orthogonal projection of the via on the device wafer. A fourth seal is formed on the device wafer, surrounding the reference device area and the functional device area. The fourth seal is solder-bonded to the third seal on the padding wafer, and the orthogonal projection of the barrier layer on the device wafer covers the reference device area.

[0028] In some examples, the fabrication method further includes: preparing a capping wafer, the preparation of which includes a first seal and a getter formed on the capping wafer. The device wafer, the padding wafer, and the capping wafer form a wafer-level package structure. The first seal is bonded to a second seal on the padding wafer via solder; the orthographic projection of the getter on the device wafer does not overlap with the orthographic projection of the functional device on the device wafer.

[0029] The method for fabricating a wafer-level packaging structure provided in the embodiments of this application is used to fabricate a wafer-level packaging structure as provided in the first aspect, and therefore has all the beneficial effects of the above-described wafer-level packaging structure, which will not be repeated here. Attached Figure Description

[0030] Figure 1A schematic diagram of a wafer-level packaging structure provided for an embodiment of this application;

[0031] Figure 2 for Figure 1 A schematic diagram of a structure along section line AA;

[0032] Figure 3 for Figure 2 A schematic diagram of the local structure of G;

[0033] Figure 4 A schematic diagram of a sensor structure provided for an embodiment of this application;

[0034] Figure 5 for Figure 4 A structural schematic diagram along section line BB;

[0035] Figure 6 for Figure 4 Another structural schematic diagram along section line BB;

[0036] Figure 7 for Figure 4 Another structural schematic diagram along section line BB;

[0037] Figure 8 for Figure 4 Another structural schematic diagram along section line BB;

[0038] Figure 9 for Figure 4 Another structural schematic diagram along section line BB;

[0039] Figure 10 for Figure 4 Another structural schematic diagram along section line BB;

[0040] Figure 11 for Figure 4 Another structural schematic diagram along section line BB;

[0041] Figure 12 for Figure 4 Another structural schematic diagram along section line BB;

[0042] Figure 13 This is a schematic diagram illustrating one fabrication step of a wafer-level packaging structure provided in an embodiment of this application.

[0043] Figure 14 This is a schematic diagram illustrating another fabrication step of the wafer-level packaging structure provided in an embodiment of this application. Detailed Implementation

[0044] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments.

[0045] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." Words such as "exemplarily" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplarily" or "for example" in this application should not be construed as preferred or advantageous over other embodiments or designs. Specifically, the use of words such as "exemplarily" or "for example" is intended to present the relevant concepts in a concrete manner.

[0046] In describing some embodiments, the term "electrical connection" may be used to indicate that two or more components have direct physical or electrical contact. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0047] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0048] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0049] Wafer-level packaging (WLP) enables the packaging and testing of MEMS sensors on a wafer and is a widely used packaging technology for mass-producing MEMS devices. WLP employs a pre-packaging followed by dicing technique, avoiding contamination and microstructure damage that can occur during dicing. WLP allows for unified and simultaneous design of MEMS sensors and packaging, improving design efficiency and reducing costs. Furthermore, WLP significantly reduces intermediate steps and shortens the cycle time from MEMS sensor manufacturing and packaging to final product completion, thus lowering costs. Therefore, designing WLP structures to improve packaging effectiveness and MEMS sensor performance is a key research focus for those skilled in the art.

[0050] Therefore, this application provides a wafer-level packaging structure. For example... Figure 1 and Figure 2As shown, the wafer-level packaging structure 1000 encapsulates multiple MEMS sensors on a large-sized wafer substrate, and then dices them to divide them into multiple individual wafer-level packaging structures 1001 (i.e., sensors, which will be described below as an example of sensor 1001).

[0051] like Figure 2 As shown, the wafer-level packaging structure 1000 includes a device wafer 10, multiple reference device regions 20, and a padding wafer 30.

[0052] Device wafer 10 is a substrate supporting the MEMS sensor. For example, the material of device wafer 10 includes one or more of silicon, quartz, sapphire, and ceramic. For instance, the material of device wafer 10 includes silicon. For example, the shape of device wafer 10 can be a circular, rectangular, or polygonal substrate. For example, the shape of device wafer 10 is rectangular. This can be configured according to actual needs.

[0053] like Figure 3 As shown, a padding wafer 30 is disposed on the device wafer 10, and the padding wafer 30 includes a plurality of padding regions 301. Figure 4 As shown, the padding region 301 includes a first sub-region 31 and a second sub-region 32; the second sub-region 32 is connected to the first sub-region 31. A reference device region 20 is disposed within the region enclosed by the first sub-region 31; the orthographic projection of the second sub-region 32 onto the device wafer 10 covers the reference device region 20; and, along a direction away from the device wafer 10, the surface of the second sub-region 32, away from the first sub-region 31, is inclined towards the side closer to the first sub-region 31.

[0054] It should be noted that the second sub-section 32 of the padding region 301 is connected to the first sub-section 31, that is, the connection surface of the first sub-section 31 and the second sub-section 32 is the interface between the two. Therefore, along the direction perpendicular to the device wafer 10, the two ends of the second sub-section 32 are flush with the two ends of the first sub-section 31. Here, the thickness of the interface between the two is not limited along the direction parallel to the device wafer 10.

[0055] like Figure 3 As shown, reference device region 20 is disposed on device wafer 10 and configured to house reference device 21. It can be understood that reference device 21 is configured to output a reference signal so that the wafer-level package structure 1000 can use the reference signal as a basis to determine or correct the accuracy of the actual output signal, thereby improving the performance of the sensor 1001 formed after dicing of the wafer-level package structure 1000. The second sub-section 32 of the pad region 301, with its orthographic projection on the device wafer 10, covers reference device region 20, reducing the influence of external electromagnetic waves on the value of the reference signal output by reference device 21 and improving the accuracy of the output signal of reference device region 20.

[0056] In some examples, the padding wafer 30 can be a substrate of the same specifications (shape and size) as the device wafer 10. For example, the shape of the padding wafer 30 is substantially the same as that of the device wafer 10, and can be rectangular. For example, the side length or diameter of the padding wafer 30 is substantially the same as that of the device wafer 10, and can be 8-inch or 12-inch, etc. For example, the thickness of the padding wafer 30 ranges from 5μm to 5mm. The thickness of the padding wafer 30 can be selected according to the specifications of the packaged MEMS sensor. For example, the thickness of the padding wafer 30 can be 5μm, 20μm, 100μm, 1mm, and 5mm.

[0057] In some examples, such as Figure 3 As shown, the wafer-level packaging structure 1000 also includes multiple functional device regions 40, which are disposed within the area enclosed by the first sub-part 31. The functional device regions 40 are configured to house functional devices 41 and output sensing signals. Exemplarily, the functional device 41 is a MEMS device, which may include one or more MEMS devices such as a gyroscope, accelerometer, pressure gauge, and infrared focal plane array. For example, the functional device 41 may include an infrared focal plane array.

[0058] The orthographic projection of the second sub-section 32 on the device wafer 10 does not overlap with the functional device region 40; and external electromagnetic waves irradiate the functional device 41 along the inclined surface of the second sub-section 32 away from the first sub-section 31. The degree of inclination of the surface of the second sub-section 32 away from the first sub-section 31 can be set as needed to improve the placement of electromagnetic waves on the functional device 41 and improve the sensing effect of the functional device 41.

[0059] For example, the degree of inclination of the surface of the second sub-part 32 away from the first sub-part 31 can be set according to the distance and relative position relationship between the functional device 41 and the second sub-part 32. This application does not impose any limitations on this. For example, the orthographic projection of the second sub-part 32 on the device wafer 10 can exactly cover the reference device area 20. The cross-section of the second sub-part 32 is a right-angled triangle, and the cross-sectional area decreases along the direction away from the first sub-part 31, so that external electromagnetic waves can irradiate the functional device 41 along the smooth inclined surface of the second sub-part 32 away from the first sub-part 31.

[0060] It should be noted that, considering the fabrication process of the second sub-section 32, the orthographic projection of the second sub-section 32 on the device wafer 10 can exactly cover the reference device region 20. Alternatively, the second sub-section 32 can be arranged around the reference device region 20 (for example, the orthographic projection of the second sub-section 32 on the device wafer 10 can be a closed ring or an open ring), and a portion of the orthographic projection of the second sub-section 32 on the device wafer 10 can cover the reference device region 20. This application does not limit the specific structure of the second sub-section 32, as long as the orthographic projection of the second sub-section 32 on the device wafer 10 at least covers the reference device region 20.

[0061] In some examples, such as Figure 3 As shown, the padding region 301 has a via 33. The opening of the via 33 away from the functional device region 40 is larger than the opening of the via 33 near the functional device region 40. Furthermore, the boundary of the orthographic projection of the via 33 on the device wafer 10 surrounds the functional device region 40.

[0062] In this way, the boundary of the smallest opening of the via 33 projected onto the device wafer 10 surrounds the functional device region 40, thus exposing the functional device region 40. This is beneficial for improving the electromagnetic wave reception effect of the functional device 41 and enhancing its sensing effect. Furthermore, the opening of the padding region 301 on the side away from the functional device region 40 is larger. Since the electromagnetic waves do not strike the functional device region 40 perpendicularly, more electromagnetic waves will pass through the opening of the via 33 away from the device wafer 10 to strike the functional device 41, thereby improving the sensing effect of the functional device 41.

[0063] The shape enclosed by the orthographic projection of the via 33 onto the device wafer 10 can be any one or more of a rectangle, circle, and polygon, and can be selected according to the shape of the functional device 40. The via 33 can be etched into the pad layer region 301 using reactive ion etching to form a via. The etching process can be wet etching, in which the pad layer wafer 30 to be etched is placed in an etching solution with a defined chemical composition and a fixed temperature. The etching solution has different etching rates on different crystal planes of the pad layer wafer 30, thus creating the required via 33 on the pad layer wafer 30.

[0064] In some examples, such as Figure 3 As shown, the padding region 301 further includes at least one blocking layer 50, which is disposed on the side of the second sub-section 32 of the padding region 301 near the reference device region 20 and connected to the second sub-section 32. The orthogonal projection of the blocking layer 50 on the device wafer 10 covers the reference device region 20 and is configured to block electromagnetic waves from irradiating the reference device 21.

[0065] For example, one or two blocking layers 50 can be arranged side by side on the side of the second sub-section 32 near the reference device area 20 to increase the shielding area. Alternatively, one or two blocking layers 50 can be stacked on the side of the second sub-section 32 near the reference device area 20 to improve the blocking effect, further reduce the influence of external electromagnetic waves on the magnitude of the reference signal output by the reference device 21, and improve the accuracy of the actual output signal of the wafer-level package structure 1000.

[0066] The material of the aforementioned blocking layer 50 includes metals or other materials capable of effectively blocking electromagnetic waves. For example, the material of the blocking layer 50 includes one or more of titanium, zirconium alloys, titanium alloys, gold, platinum, chromium, and nickel. For instance, the material of the blocking layer 50 includes a titanium alloy.

[0067] In some examples, such as Figure 3 As shown, the wafer-level packaging structure 1000 also includes a capping wafer 60. The capping wafer 60 is disposed on the side of the padding wafer 30 away from the device wafer 10. For example, the capping wafer 60 is one or more substrate materials such as silicon, germanium, and glass. For instance, the capping wafer 60 is a silicon wafer.

[0068] Please continue reading. Figure 3 The capping wafer 60, multiple padding regions 301, and device wafer 10 form multiple sealed cavities. A reference device region 20 and a functional device region 40 are grouped together; at least one group of functional device regions 40 and reference device regions 20 are located in a cavity.

[0069] In some examples, the region within the cavity enclosed by the edge of the functional device region 40 extending in a direction perpendicular to the device wafer 10 is spaced apart from the surface of the second sub-part 32 away from the first sub-part 31. Thus, while ensuring that electromagnetic waves incident in a direction perpendicular to the device wafer 10 irradiate the functional device region 40, at least a portion of the electromagnetic waves within the cavity are not blocked by the second sub-part 32 and irradiate the functional device region 40, improving the effectiveness of the functional device region 40 in sensing electromagnetic waves.

[0070] In some embodiments, such as Figure 3 As shown, the padding region 301 also includes at least one getter 90. The getter 90 is located within the cavity. Thus, the getter 90 can absorb residual gas in the cavity and exhaust gases generated during MEMS device operation, improving the quality of the vacuum environment within the cavity and thus extending the lifespan of the MEMS devices. For example, the getter 90 can be a non-evaporable getter, such as one or more of titanium, zirconium alloys, or titanium alloys. For instance, the getter 90 may comprise a titanium alloy.

[0071] The orthographic projection of getter 90 on device wafer 10 does not overlap with the orthographic projection of functional device region 40 on device wafer 10; and / or, if pad region 301 includes barrier layer 50, barrier layer 50 includes getter 90.

[0072] For example, the orthographic projection of the getter 90 on the device wafer 10 may at least partially overlap with the orthographic projection of the barrier layer 50 on the device wafer 10, but may not overlap with the orthographic projection of the functional device region 40 on the device wafer 10.

[0073] Alternatively, since the getter 90 is made of a metal element or alloy, which can block electromagnetic waves, the material of the barrier layer 50 can be the same as that of the getter 90, or the barrier layer 50 can include the getter 90. In this way, the barrier layer 50 can be made of the same material and the same manufacturing process as the getter 90, reducing the number of process steps in the entire manufacturing process of the wafer-level packaging structure 1000.

[0074] This application also provides a sensor 1001. For example... Figure 4 As shown, the sensor 1001 is formed by cutting the wafer-level packaging structure 1000 provided in the above embodiment.

[0075] like Figure 5 As shown, the sensor 1001 includes a device layer 11, a reference device 21, and a pad layer 310. The pad layer 310 is obtained by cutting the pad region 301 of the divided pad wafer 30.

[0076] Device layer 11 is the substrate supporting the MEMS sensor. For example, the material of device layer 11 includes one or more of silicon, quartz, sapphire, and ceramic. For instance, the material of device layer 11 includes silicon. For example, the shape of device layer 11 can be a circular, rectangular, or polygonal substrate. For example, the shape of device layer 11 is rectangular. This can be configured according to actual needs.

[0077] Reference device 21 is disposed on device layer 11 and configured to output a reference signal.

[0078] A pad 310 is disposed on the device wafer 10. The pad 310 includes a first sub-part 31 and a second sub-part 32 connected together. The first sub-part 31 is disposed around a reference device 21. Along a direction away from the device wafer 10, the second sub-part 32 is inclined toward the side closer to the first sub-part 31, away from the surface of the first sub-part 31. A reference device 21 is disposed within the area enclosed by the first sub-part 31. The orthographic projection of the second sub-part 32 onto the device wafer 10 covers the reference device 21.

[0079] It should be noted that the second sub-section 32 of the padding region 301 is connected to the first sub-section 31, that is, the connection surface of the first sub-section 31 and the second sub-section 32 is the interface between the two. Therefore, along the direction perpendicular to the device wafer 10, the two ends of the second sub-section 32 are flush with the two ends of the first sub-section 31. Here, the thickness of the interface between the two is not limited along the direction parallel to the device wafer 10.

[0080] Reference device 21 is configured to output a reference signal so that sensor 1001 can accurately determine or correct the actual output signal based on the reference signal, thereby improving the performance of sensor 1001. The orthographic projection of the second sub-part 32 onto device layer 11 covers reference device 21. This reduces the influence of external electromagnetic waves on the value of the reference signal output by reference device 21, improving the accuracy of the reference signal. Simultaneously, along a direction perpendicular to device layer 11, the two ends of the second sub-part 32 are flush with the two ends of the first sub-part 31, and along a direction away from device layer 11, the surface of the second sub-part 32 away from the first sub-part 31 tilts towards the side closer to the first sub-part 31. That is, along a direction away from the first sub-part 31, the thickness of the second sub-part 32 decreases, reducing the blocking effect of the second sub-part 32 on other electronic devices located on the side of reference device 21 away from the first sub-part 31, thus improving the performance of sensor 1001.

[0081] It should be explained that, along the direction perpendicular to the device layer 11, the two ends of the second sub-part 32 are flush with the two ends of the first sub-part 31. This is because the second sub-part 32 and the first sub-part 31 are an integral structure, and the surface shape and size of the second sub-part 32 connected to the first sub-part 31 are the same. Therefore, the two ends of the second sub-part 32 are flush with the two ends of the first sub-part 31. This application divides the pad layer 310 according to the function of the first sub-part 31 and the second sub-part 32, but does not limit the pad layer 310 to include only these two parts, nor does it limit the overall size relationship of the first sub-part 31 and the second sub-part 32.

[0082] In some examples, the pad 310 can be a substrate of the same specifications (shape and size) as the device layer 11. For example, the shape of the pad 310 is substantially the same as that of the device layer 11, and can be rectangular. For example, the side length or diameter of the pad 310 is substantially the same as that of the device layer 11, and can be 8 inches or 12 inches, etc. For example, the thickness of the pad 310 ranges from 5 μm to 5 mm. The thickness of the pad 310 can be selected according to the specifications of the packaged MEMS sensor. For example, the thickness of the pad 310 can be 5 μm, 20 μm, 100 μm, 1 mm, and 5 mm.

[0083] like Figures 5-12 As shown, the cross-sectional area of ​​the second sub-part 32 decreases along the direction away from the first sub-part 31. The cross-section of the second sub-part 32 is perpendicular to the device layer 11 and to the connection surface between the first sub-part 31 and the second sub-part 32. This reduces the blocking effect of the second sub-part 32 on the electromagnetic waves received by other electronic devices located on the side of the reference device 21 away from the first sub-part 31, thereby improving the performance of the wafer-level package structure 1000.

[0084] It should be noted that, considering the manufacturing process of the second sub-part 32, the orthographic projection of the second sub-part 32 on the device layer 11 can exactly cover the reference device 21. Alternatively, the second sub-part 32 can be arranged around the reference device 21 (for example, the orthographic projection of the second sub-part 32 on the device layer 11 can be a closed ring or an open ring), and a portion of the orthographic projection of the second sub-part 32 on the device layer 11 can cover the reference device 21. This application does not limit the specific structure of the second sub-part 32, as long as the orthographic projection of the second sub-part 32 on the device layer 11 at least covers the reference device 21.

[0085] For example, the orthographic projection of the second sub-part 32 onto the device layer 11 can exactly cover the reference device 21. For example... Figure 5 As shown, the surface of the second sub-part 32 is away from the surface of the first sub-part 31 and is inclined toward the side closer to the first sub-part 31. The cross-section of the second sub-part 32 is a right-angled triangle, and the cross-sectional area decreases along the direction away from the first sub-part 31, so that external electromagnetic waves can irradiate the functional device 41 along the smooth inclined surface of the second sub-part 32 away from the first sub-part 31.

[0086] For example, the orthographic projection of the second sub-part 32 onto the device layer 11 can exactly cover the reference device 21. For example... Figure 6 As shown, the surface of the second sub-part 32 away from the first sub-part 31 is inclined toward the side closer to the first sub-part 31, and the surface of the second sub-part 32 away from the first sub-part 31 is concave toward the direction closer to the first sub-part 31. Here, the cross-sectional area of ​​the second sub-part 32 away from the functional device 41 is smaller, which helps to ensure that more electromagnetic waves irradiate the functional device 41.

[0087] For example, the orthographic projection of the second sub-part 32 onto the device layer 11 can exactly cover the reference device 21. For example... Figure 7 As shown, the cross-section of the second sub-section 32 is a right trapezoid, and the cross-sectional area decreases along the direction away from the first sub-section 31. In this way, while ensuring the shielding effect on the reference device 21, external electromagnetic waves can be irradiated onto the functional device 41 along the smooth inclined surface of the second sub-section 32 away from the first sub-section 31.

[0088] For example, the orthographic projection of the second sub-part 32 onto the device layer 11 can exactly cover the reference device 21. For example... Figure 8 As shown, along a direction parallel to the plane of the pad 310, the surface of the second sub-part 32 away from the device layer 11 has a certain size, and the size of the surface of the second sub-part 32 away from the device layer 11 is smaller than the size of the surface of the second sub-part 32 close to the device layer 11. The surface of the second sub-part 32 away from the first sub-part 31 is concave inward in the direction close to the first sub-part 31. The cross-sectional area of ​​the second sub-part 32 decreases along the direction away from the first sub-part 31.

[0089] In addition, such as Figure 9 As shown, the orthographic projection of the second sub-part 32 onto the device layer 11 can exactly cover the reference device 21. The cross-section of the second sub-part 32 is an acute-angled triangle, with the cross-sectional area decreasing along the direction away from the first sub-part 31. It can be understood that, if the pad layer 310 is thick, or due to limitations in the etching process, the pad layer 310 can be etched twice, i.e., etched from the two opposite surfaces of the pad layer 310, resulting in the second sub-part 32 having an acute-angled triangular cross-section.

[0090] In some examples, such as Figures 5-8 and Figures 10-12 As shown, the second sub-part 32 is close to the surface of the device layer 11 and is connected to the surface of the first sub-part 31 close to the device layer 11, and is located on the same plane. In this way, the surface of the second sub-part 32 close to the device layer 11 is closer to the reference device 21, which is beneficial to improving the blocking effect on electromagnetic waves incident along the direction close to the device layer 11 that irradiate the reference device 21.

[0091] The angle and connection method between the plane on which the surface of the second sub-part 32 is far from the surface of the first sub-part 31 and the plane on which the surface of the second sub-part 32 is close to the device layer 11 can be selected and set according to actual needs and process requirements. This application does not impose any restrictions on this.

[0092] For example, such as Figure 7 As shown, the portion where the second sub-part 32 overlaps with the reference device 21 on the device layer 11 is thicker, which helps to improve the blocking effect of the second sub-part 32 on electromagnetic waves incident along the direction close to the device wafer that irradiate the reference device 21.

[0093] In some examples, such as Figure 10 and Figure 11 As shown, the second sub-part 32 is a ring structure and is arranged around the reference device 21. The orthographic projection of part of the second sub-part 32 on the device layer 11 covers the reference device 21.

[0094] For example, the second sub-section 32 includes two parts: one part is the shielding portion 321 that covers the reference device 21 by orthographic projection on the device layer 11, and the other part is the non-shielding portion 322. The cross-sectional shape of the shielding portion 321 and the cross-sectional shape of the non-shielding portion 322 may be the same or different. It can be set according to specific requirements and processes.

[0095] For example, the orthographic projection of the second sub-part 32 onto the device layer 11 is a closed ring, and the cross-sectional shape of the shielding portion 321 of the second sub-part 32 is the same as the cross-sectional shape of the non-shielding portion 322. Figure 10As shown, the second sub-part 32 is close to the surface of the device layer 11 and is connected to the surface of the first sub-part 31 close to the device layer 11, and is located on the same plane. The cross-sectional shape of the shielding part 321 and the cross-sectional shape of the non-shielding part 322 of the second sub-part 32 are both right-angled triangles.

[0096] For example, the orthographic projection of the second sub-part 32 onto the device layer 11 is a closed ring, and the cross-sectional shape of the shielding portion 321 of the second sub-part 32 is different from the cross-sectional shape of the non-shielding portion 322. Figure 11 As shown, the second sub-part 32 is close to the surface of the device layer 11 and is connected to the surface of the first sub-part 31 close to the device layer 11, and they are located on the same plane. The cross-sectional shape of the shielding part 321 is a right triangle; the cross-sectional shape of the non-shielding part 322 is a right trapezoid.

[0097] In some examples, such as Figures 4 to 11 As shown, the sensor 1001 also includes a functional device 41, which is disposed within the area enclosed by the first sub-part 31 and configured to output a sensing signal. That is, the first sub-part 31 surrounds the reference device 21 and the functional device 41 within the same area. The orthographic projection of the second sub-part 32 onto the device layer 11 covers the reference device 21, and the orthographic projection of the second sub-part 32 onto the device layer 11 does not overlap with the functional device 41; and external electromagnetic waves irradiate the functional device 41 along the inclined surface of the second sub-part 32 away from the first sub-part 31. The degree of inclination of the surface of the second sub-part 32 away from the first sub-part 31 can be set as needed to improve the detection of electromagnetic waves on the functional device 41 and enhance the sensing effect of the functional device 41. For example, the degree of inclination of the surface of the second sub-part 32 away from the first sub-part 31 can be set according to the distance and relative positional relationship between the functional device 41 and the second sub-part 32. This application does not impose any limitations on this.

[0098] Please continue reading. Figures 4 to 11 The padding layer 310 has a via 33. The wall of the via 33 is the surface of the second sub-part 32 away from the first sub-part 31, and the cross-sectional shape of the via 33 is related to the cross-sectional shape of the second sub-part 32. The shape enclosed by the boundary of the orthographic projection of the via 33 on the device layer 11 can be any one or more of rectangles, circles, and polygons, and can be set according to the position, shape, and size of the reference device 21 and the functional device 41, ensuring that the via 33 only exposes the functional device 40.

[0099] The via wall of via 33 is the surface of the second sub-part 32 away from the first sub-part 31, i.e., the boundary of the orthographic projection of via 33 onto the device layer 11, surrounding the functional device 41. Thus, via 33 exposes only the functional device 41, allowing the functional device 41 to acquire electromagnetic waves passing through it and output an induced signal. The reference device 21, shielded by the second sub-part 32, can output a reference signal unaffected by external electromagnetic waves. This facilitates comparison of the induced signal and the reference signal during subsequent signal determination, eliminating the influence of the functional device 41's own resistance on the output signal magnitude. Furthermore, the opening of via 33 away from the functional device region 40 is larger than the opening of via 33 near the functional device region 40. This results in a larger opening on the side of the pad layer 310 away from the functional device 41. Since the electromagnetic waves do not strike the functional device 41 perpendicularly, more electromagnetic waves will pass through the opening of via 33 away from the device wafer 10 to strike the functional device 41, improving the sensing effect of the functional device 41.

[0100] For example, the functional device 41 is a MEMS sensor, which may include one or more MEMS devices such as a gyroscope, accelerometer, pressure gauge, and infrared focal plane array. For instance, the functional device 41 includes an infrared focal plane array.

[0101] In some examples, such as Figure 4 As shown, the wafer-level package structure 1000 also includes a barrier layer 50, which is disposed on the side of the second sub-section 32 near the reference device 21 and connected to the second sub-section 32. The orthogonal projection of the barrier layer 50 onto the device layer 11 covers the reference device 21 and is configured to block electromagnetic waves from illuminating the reference device 21. The barrier layer 50 can further reduce the influence of external electromagnetic waves on the magnitude of the reference signal output by the reference device 21, thereby improving the accuracy of the actual output signal of the wafer-level package structure 1000.

[0102] For example, the material of the blocking layer 50 includes metal or other materials capable of effectively blocking electromagnetic waves. For instance, the material of the blocking layer 50 includes one or more of titanium, zirconium alloy, titanium alloy, gold, platinum, chromium, and nickel. For example, the material of the blocking layer 50 includes a titanium alloy.

[0103] In some examples, such as Figures 4 to 11 As shown, the sensor 1001 also includes a capping layer 61, a first seal 71, a second seal 72, a third seal 73, and a fourth seal 74.

[0104] A capping layer 61 is disposed on the side of the pad layer 310 away from the device layer 11. For example, the capping layer 61 is one or more substrates made of materials such as silicon, germanium, and glass. For instance, the capping layer 61 is a silicon wafer. It should be noted that in the embodiments of this application, the portion of the pad layer 310 used to support the device wafer and the capping layer 61 is designated as the first sub-part 31, and the remaining portion of the first sub-part 31 near the reference device 21 is designated as the second sub-part 32, to facilitate the description of the shape and function of each part of the pad layer 310. However, the embodiments of this application do not limit the shape and size of other parts of the pad layer 310. Vias 33 are etched through the pad layer 310. The pad layer 310, the capping layer 61, and the device layer 11 together form a sealed cavity for the MEMS sensor (functional device 41 and reference device 21). The height of the sealed cavity is mainly determined by the thickness of the pad layer 310. The thickness of the pad 310 is related to the specifications of the MEMS sensor in order to reduce the impact of particulate impurities in the sealed cavity on the performance of the MEMS sensor and improve the isolation tolerance of the sensor 1001.

[0105] For example, an infrared antireflection film is provided on the surface of the capping layer 61 away from or near the device layer 11. The material of the infrared antireflection film includes one or more of zinc sulfide, germanium, and zinc selenide. The infrared antireflection film is configured to increase the infrared transmittance, thereby increasing the amount of infrared light irradiating the functional device 41 and improving the sensing effect of the functional device 41.

[0106] The first sealing element 71 is disposed on the side of the cap layer 61 near the device layer 11 and is connected to the cap layer 61.

[0107] The second seal 72 is disposed on the side of the pad 310 near the cap layer 61 and is connected to the pad 310.

[0108] The third sealing element 73 is disposed on the side of the pad 310 away from the cap layer 61 and is connected to the pad 310.

[0109] The fourth seal 74 is disposed on the side of the device layer 11 near the cap layer 61 and is connected to the device layer 11.

[0110] The first seal 71 and the second seal 72 are connected by solder 80; the third seal 73 and the fourth seal 74 are connected by solder 80.

[0111] For example, the materials used for the first seal 71, the second seal 72, the third seal 73, and the fourth seal 74 include composite materials such as Cr / Au, Cr / Ni / Au, or Ti / Pt / Au. The materials used for the first seal 71, the second seal 72, the third seal 73, and the fourth seal 74 may be the same or different.

[0112] For example, the first seal 71, the second seal 72, the third seal 73, and the fourth seal 74 are all made of the same material, a three-layer composite material of Cr / Ni / Au. These seals include a bottom layer, an intermediate layer, and a top layer. The top layer is a wetting layer for contact with the solder, made of Au, to facilitate eutectic brazing with the solder; the bottom layer is an adhesion layer for contact with the substrate (device layer 11, pad layer 310, and cap layer 61), made of Cr, to facilitate adhesion with the intermediate layer; the intermediate layer is a barrier layer made of Ni to prevent the top layer metal from diffusing into the substrate.

[0113] For example, solder 80 can be a variety of alloy solders, such as Sn-based solders, Sn-In, Sn-Ag, Sn-Au, Sn-Ag-Cu, etc., which can be selected according to the material of the composite seal.

[0114] In some examples, the region within the cavity enclosed by the edge of the functional device 41 extending in a direction perpendicular to the device wafer 10 is spaced apart from the surface of the second sub-part 32 away from the first sub-part 31. Thus, while ensuring that electromagnetic waves incident in a direction perpendicular to the device wafer 10 irradiate the functional device 41, at least a portion of the electromagnetic waves within the cavity are not blocked by the second sub-part 32, thereby improving the effectiveness of the functional device 41 in sensing electromagnetic waves.

[0115] In some examples, such as Figure 12 As shown, the cross-section of the second sub-section 32 is a right-angled trapezoid. Furthermore, the portion of the second seal 72 on the surface of the second sub-section 32 away from the device layer 11 is larger, which helps improve the stability of the bonding between the pad layer 310 and the capping layer 61. Simultaneously, due to the large number of film layers between the capping layer 61 and the reference device 21, electromagnetic waves incident from the capping layer 61 will pass through the second seal 72, the second sub-section 32, and the barrier layer to reach the reference device 21. This further reduces the impact of the incident electromagnetic waves on the accuracy of the reference signal output by the reference device 21, thus improving the performance of the wafer-level package structure 1000.

[0116] In some examples, such as Figures 4 to 12 As shown, sensor 1001 also includes a getter 90. Thus, in the sealed cavity of the MEMS sensor (functional device 41 and reference device 21) formed by the pad layer 310, the cap layer 61, and the device layer 11, the getter 90 can absorb residual gas and exhaust gas generated during MEMS sensor operation, improving the quality of the vacuum environment within the sealed cavity and thus extending the lifespan of the MEMS sensor. For example, the getter 90 can be a non-evaporable getter, such as titanium, zirconium alloy, or one or more titanium alloys. For instance, the getter 90 may be a titanium alloy.

[0117] The orthographic projection of getter 90 on device layer 11 does not overlap with the orthographic projection of functional device 41 on device layer 11; and / or, barrier layer 50 includes getter 90.

[0118] For example, the orthographic projection of the getter 90 on the device layer 11 may at least partially overlap with the orthographic projection of the barrier layer 50 on the device layer 11, but may not overlap with the orthographic projection of the functional device 41 on the device layer 11.

[0119] Alternatively, since the material used for the getter 90 includes a metallic element or alloy, which can achieve the effect of blocking electromagnetic waves, based on the function of the blocking layer 50, the material of the blocking layer 50 can be the same as that of the getter 90, or the blocking layer 50 can include the getter 90. In this way, the blocking layer 50 can be made with the same material and the same manufacturing process as the getter 90, reducing the process steps in the entire manufacturing process of the sensor 1001.

[0120] It is understandable that, such as Figures 4 to 12 As shown, sensor 1001 also includes multiple wire bonding windows 100. The wire bonding windows 100 are disposed on device layer 11. Furthermore, each sensor 1001 has multiple wire bonding windows 100, which are disposed on the side of the first sub-part 31 away from the via 33 and electrically connected to reference device 21 and functional device 41. These windows are configured to transmit the reference signal output by reference device 21 and the sensing signal output by functional device 41 to a circuit electrically connected to each sensor 1001.

[0121] This application also provides a method for fabricating a wafer-level packaging structure. For example... Figure 4 , Figure 13 and Figure 14 As shown, the fabrication method of the wafer-level packaging structure 1000 includes: S10 to S50.

[0122] S10: Fabricate device wafer 10, which has multiple reference device regions 20; reference devices 21 are provided in the reference device regions 20.

[0123] For example, multiple reference device areas 20 are arranged in an array, with one reference device in each reference device area 20.

[0124] The fabrication of device wafer 10 includes S11 to S14.

[0125] S11: A reference device 21 is disposed on the device wafer 10. The reference device 21 is configured to output a reference signal.

[0126] S12: Multiple functional device regions 40 are provided on the device wafer 10, and functional devices 41 are provided in the functional device regions 40. The functional devices 41 are configured to output sensing signals. And external electromagnetic waves irradiate the functional devices 41 along the inclined surface of the second sub-section 32 away from the first sub-section 31.

[0127] Furthermore, there is a gap between the functional device region 40 and the reference device region 20. The functional device region 40 is located within the boundary of the orthogonal projection of the via onto the device wafer 10.

[0128] Typically, the reference device 21 is smaller than the functional device 41, as long as it can output a valid reference signal. The reference device 21 can be located on either side of the functional device 41; this application does not impose specific limitations on the specifications of the reference device 21. For example, the functional device 41 includes an infrared focal plane array. The reference device 21 operates on the same principle as the functional device 41 and outputs the same type of electrical signal.

[0129] S13: A fourth sealing element 74 is formed on the device wafer 10. A reference device region 20 and a functional device region 40 are grouped together, and the fourth sealing element 74 surrounds the group of reference device regions 20 and functional device regions 40. The fourth sealing element 74 is a three-layer composite structure including a bottom layer, an intermediate layer, and a top layer. The top layer is a wetting layer for contact with solder, made of Au material, to facilitate eutectic brazing with solder; the bottom layer is an adhesion layer for contact with the substrate (device wafer 10, pad wafer 30, and cap wafer 60), made of Cr material, to facilitate adhesion with the intermediate layer; the intermediate layer is a barrier layer made of Ni material to prevent the top layer metal from diffusing into the substrate. Thus, materials Cr, Ni, and Au are sequentially deposited on the device wafer, and then patterned using photolithography to form the fourth sealing element 74.

[0130] It should be noted that in subsequent processes, the first sealing element 71, the second sealing element 72, and the third sealing element 73 can be formed using the same materials and processes as the fourth sealing element 74. Further details will not be provided in subsequent embodiments of this application. Deposition processes include thermal evaporation and sputtering, and can be configured according to actual needs.

[0131] S14: A wire bonding window 100 is formed on the device wafer 10. The wire bonding window 100 is electrically connected to the reference device 21 and the functional device 41, and is configured to transmit the reference signal output by the reference device 21 and the sensing signal output by the functional device 41 to a circuit electrically connected to each sensor 1001. The wire bonding window is located on the side of the fourth seal 74 away from the reference device 21. The wire bonding window 100 includes a plurality of pads, the number of which can be set according to the actual number of signal lines.

[0132] S20: Fabricate a padding wafer 30, which includes multiple padding regions 301. Each padding region 301 includes a connected first sub-region 31 and a second sub-region 32. Along a direction away from the device wafer 10, the second sub-region 32 is inclined towards the side closer to the first sub-region 31, away from its surface. Along a direction perpendicular to the device wafer 10, both ends of the second sub-region 32 are flush with both ends of the first sub-region 31.

[0133] S20 includes: S21 to S23.

[0134] S21: A second seal 72 and a third seal 73 are formed on two opposite surfaces of the pad wafer 30.

[0135] S22: A barrier layer 50 is formed on the surface where the third seal 73 is located; the third seal 73 surrounds the barrier layer 50.

[0136] Material for the barrier layer 50 is deposited on the surface of the pad wafer 30 that forms the third seal 73, and then photoresist is coated and photolithography is performed to form the barrier layer 50.

[0137] The material of the blocking layer 50 includes metals or other materials capable of effectively blocking electromagnetic waves. For example, the material of the blocking layer 50 includes one or more of titanium, zirconium alloys, titanium alloys, gold, platinum, chromium, and nickel. For instance, the material of the blocking layer 50 includes a titanium alloy.

[0138] In addition, the barrier layer 50 can also be formed simultaneously with the third seal 73. For example, the pattern of the barrier layer 50 can be etched while the three-layer material stack of the third seal 73 is patterned.

[0139] S23: Etch the pad wafer 30 to form a via 33; the wall of the via 33 is the surface of the second sub-part 32 away from the first sub-part 31.

[0140] The shape enclosed by the boundary of the orthographic projection of the via 33 onto the device wafer 10 can be any one or more of a rectangle, circle, and polygon, and can be selected according to the shape of the functional device 41. The pad wafer 30 can be etched using either dry etching or wet etching processes to form the via 33. For example, the etching process can be wet etching, in which the pad wafer 30 to be etched is placed in an etching solution with a defined chemical composition and a fixed temperature. The etching solution has different etching rates on different crystal planes of the pad wafer 30, allowing the creation of the required shielding structure (i.e., the shielding portion 321 of the second sub-part 32) on the pad wafer 30.

[0141] S30: The pad wafer 30 and the device wafer 10 are aligned and bonded to the surface of the reference device 21, wherein the fourth seal 74 and the third seal 73 of the pad wafer 30 are bonded together by solder 80. For example, the solder 80 is formed on the fourth seal 74 by evaporation, electroplating, or screen printing, and the pad wafer 30 and the first substrate are bonded together using vacuum bonding equipment (e.g., a wafer bonding machine).

[0142] For example, after the pad wafer 30 is aligned with the device wafer 10, the orthographic projection of the second sub-part 32 on the device wafer 10 covers the reference device 21, and the orthographic projection of the barrier layer 50 on the device wafer 10 also covers the reference device 21. Furthermore, the functional device 41 is located within the boundary of the orthographic projection of the via 33 on the device wafer 10. In this way, the barrier layer 50 can reduce the impact of electromagnetic waves incident within the wafer-level packaging structure 1000 on the reference device 21, and the structure of each part of the pad wafer 30 does not affect the electromagnetic wave induction effect of the functional device 41. Specifically, the orthographic projection of the via 33 on the surface of the pad wafer 30 away from the device wafer 10 covers the orthographic projection of the via 33 on the surface of the pad wafer 30 close to the device wafer 10.

[0143] S40: Prepare capped wafer 60.

[0144] S40 includes: S41 to S43.

[0145] S41: An infrared antireflection film is formed on the capped wafer 60. An infrared antireflection film is grown by coating one or more materials, such as zinc sulfide, germanium, and zinc selenide, onto at least one surface of the capped wafer 60 using an evaporation process. The infrared antireflection film is configured to increase infrared transmittance, thereby increasing the amount of infrared light reaching the functional device 41 and improving the sensing effect of the functional device 41.

[0146] S42: A first seal 71 is formed on the capping wafer 60. The manufacturing process and materials of the first seal 71 are the same as those of the fourth seal 74, and will not be described again here.

[0147] S43: Form getter 90 on capped wafer 60.

[0148] For example, the getter 90 can be a non-evaporable getter, such as titanium, zirconium alloy, or one or more titanium alloys. For example, the getter 90 includes a titanium alloy. The titanium alloy material is sputtered on the capping wafer 60 using a deposition process, and the patterned getter 90 is formed by a photolithography process; the getter 90 can also be formed simultaneously with the first seal 71 using the same material.

[0149] S50: Based on the wafer-level packaging structure 1000 formed by assembling device wafer 10, pad wafer 30 and cap wafer 60, activate getter 90.

[0150] The first seal 71 is bonded to the second seal 72 of the pad wafer 30 by solder 80. For example, the solder 80 is formed on the second seal 72 by evaporation, electroplating or screen printing process, and the assembled device wafer 10 and pad wafer 30 are bonded to the cap wafer 60 by vacuum bonding equipment (e.g., wafer bonding machine).

[0151] The orthographic projection of getter 90 on device wafer 10 does not overlap with the orthographic projection of functional device 41 on device wafer 10. The activation temperature of getter 90 can be determined based on the material of getter 90 and the actual application of the device; for example, the activation temperature is approximately 400°C. In the sealed cavity formed by device wafer 10, pad wafer 30, and cap wafer 60, the activated getter 90 can absorb residual gas and exhaust gas generated by the operation of the MEMS sensor, improving the quality of the vacuum environment in the sealed cavity and thus extending the service life of the MEMS sensor.

[0152] It is understandable that the process sequence for assembling the aforementioned device wafer 10, pad wafer 30, and cap wafer 60 to form the wafer-level package structure 1000, based on the structure of the already fabricated pad wafer 30, can be as follows: device wafer 10 and pad wafer 30 can be assembled and aligned first, and then assembled and aligned with the cap wafer 60; or the cap wafer 60 and pad wafer 30 can be assembled and aligned first, and then assembled and aligned with the device wafer 10; or device wafer 10, pad wafer 30, and cap wafer 60 can be placed in the same mounting space and aligned and assembled simultaneously. This application does not limit the bonding order of assembling device wafer 10, pad wafer 30, and cap wafer 60, and can be set according to the actual assembly scenario.

[0153] Furthermore, the wafer-level packaging structure 1000 formed by the above process steps can be cut into multiple individual packaging structures 1001 (i.e., sensors 1001) using a dicing machine when dicing is required, for application in various electronic devices.

[0154] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0155] Although this application has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made thereto without departing from the spirit and scope of this application. Accordingly, this specification and drawings are merely exemplary illustrations of this application as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from the spirit and scope of this application. Thus, if such modifications and modifications of this application fall within the scope of the claims of this application and their equivalents, this application is also intended to include such modifications and modifications.

Claims

1. A wafer-level packaging structure, characterized in that, include: Device wafers; Multiple reference device regions are disposed on the device wafer and configured to house reference devices; A padding wafer is disposed on the device wafer; the padding wafer includes a plurality of padding regions, each padding region including a first sub-region and a second sub-region connected together; wherein, a reference device region is disposed within the region enclosed by the first sub-region; the orthographic projection of the second sub-region on the device wafer covers the reference device region; and, along a direction away from the device wafer, the surface of the second sub-region away from the first sub-region is inclined toward the side closer to the first sub-region; A capping wafer is disposed on the side of the padding wafer away from the device wafer; the capping wafer, the plurality of padding regions, and the device wafer form a plurality of sealed cavities; the reference device region is located within the cavity; Multiple functional device areas are disposed within the area enclosed by the first sub-part, and are configured to house functional devices and output sensing signals.

2. The wafer-level packaging structure according to claim 1, characterized in that, Along a direction perpendicular to the device wafer, the two ends of the second sub-part are flush with the two ends of the first sub-part; the orthogonal projection of the second sub-part on the device wafer does not overlap with the functional device area.

3. The wafer-level packaging structure according to claim 2, characterized in that, The padding area has a via; the via is farther from the opening of the functional device and larger than the via is closer to the opening of the functional device; The boundary of the via's orthogonal projection on the device wafer surrounds the functional device area.

4. The wafer-level packaging structure according to claim 3, characterized in that, The cushion layer area also includes: At least one blocking layer is disposed on the side of the second sub-part near the reference device region and connected to the second sub-part; the orthogonal projection of the blocking layer on the device wafer covers the reference device region and is configured to block electromagnetic waves from irradiating the reference device.

5. The wafer-level packaging structure according to claim 4, characterized in that, The cushion layer area also includes at least one getter; The orthographic projection of the at least one getter on the device wafer does not overlap with the orthographic projection of the functional device region on the device wafer; and / or, The barrier layer includes the getter.

6. The wafer-level packaging structure according to claim 2, characterized in that, A reference device region and a functional device region are grouped together; at least one group of the functional device regions and the reference device region are located within a cavity.

7. The wafer-level packaging structure according to claim 6, characterized in that, The region within the cavity, enclosed by the edge of the functional device region extending in a direction perpendicular to the device wafer, is spaced apart from the surface of the second sub-part away from the first sub-part.

8. A sensor, characterized in that, include: Device layer; A reference device is disposed on the device layer; A pad layer, disposed on the device layer, includes a first sub-part and a second sub-part connected together; along a direction away from the device layer, the surface of the second sub-part away from the first sub-part is inclined toward the side close to the first sub-part; wherein, a reference device is disposed in the area enclosed by the first sub-part; the orthographic projection of the second sub-part on the device layer covers the reference device; A functional device, disposed within the area enclosed by the first sub-part, is configured to output a sensing signal; A capping layer is disposed on the side of the padding layer away from the device layer; the capping layer, the padding layer, and the device layer form a sealed cavity; the functional device and the reference device are located within the cavity.

9. The sensor according to claim 8, characterized in that, The cross-sectional shape of the second sub-part is a right triangle or a right trapezoid; the cross-section is perpendicular to the device layer and perpendicular to the connection surface between the first sub-part and the second sub-part.

10. The sensor according to claim 9, characterized in that, Along a direction perpendicular to the device layer, the two ends of the second sub-part are flush with the two ends of the first sub-part; and the orthographic projection of the second sub-part on the device layer does not overlap with the functional device.

11. The sensor according to claim 10, characterized in that, The pad layer has vias; the boundary of the orthographic projection of the vias onto the device layer surrounds the functional device. The via is farther from the opening of the functional device than the via is closer to the opening of the functional device.

12. The sensor according to claim 10, characterized in that, The sensor also includes: A blocking layer is disposed on the side of the second sub-part closer to the reference device and connected to the second sub-part; the orthographic projection of the blocking layer on the device layer covers the reference device and is configured to block electromagnetic waves from irradiating the reference device.

13. The sensor according to claim 12, characterized in that, The sensor also includes a getter; The orthographic projection of the getter onto the device layer does not overlap with the orthographic projection of the functional device onto the device layer; and / or The barrier layer includes the getter.

14. The sensor according to claim 8, characterized in that, The region within the cavity enclosed by the edge of the functional device extending in a direction perpendicular to the device layer is spaced apart from the surface of the second sub-part away from the first sub-part.

15. A method for fabricating a wafer-level packaging structure, characterized in that, Used to fabricate a wafer-level packaging structure as described in any one of claims 1 to 7; the fabrication method includes: A device wafer is fabricated, the device wafer having multiple reference device regions; reference devices are disposed within the reference device regions. A padding wafer is fabricated, the padding wafer comprising a plurality of padding regions; each padding region comprising a connected first sub-section and a second sub-section; along a direction away from the device wafer, the surface of the second sub-section is away from the surface of the first sub-section and is inclined toward the side closer to the first sub-section. The pad wafer and the device wafer are aligned and bonded to the surface of the reference device; one of the reference device regions is located in the area enclosed by the first sub-part, and the orthographic projection of the second sub-part on the device wafer covers the reference device region; A capping wafer is fabricated, wherein the capping wafer is disposed on the side of the padding wafer away from the device wafer; the capping wafer, the plurality of padding regions, and the device wafer form a plurality of sealed cavities; the reference device region is located within the cavities; The fabrication of the device wafer includes: setting multiple functional device regions on the device wafer, wherein functional devices are provided in the functional device regions; and external electromagnetic waves irradiate the functional devices along the inclined surface of the second sub-part away from the first sub-part.

16. The method for fabricating a wafer-level packaging structure according to claim 15, characterized in that, The preparation of the padding wafer includes: A second seal and a third seal are formed on two opposite surfaces of the padding wafer; a barrier layer is formed on the surface of the padding wafer where the third seal is located; the third seal surrounds the barrier layer. The padding wafer is etched to form vias; the via wall is the surface of the second sub-part away from the first sub-part.

17. The method for fabricating a wafer-level packaging structure according to claim 16, characterized in that, The fabrication device wafer also includes: There is a gap between the functional device area and the reference device area; and the functional device area is located within the boundary of the orthogonal projection of the via on the device wafer; A fourth seal is formed on the device wafer, the fourth seal surrounding the reference device region and the functional device region; The fourth seal is bonded to the third seal of the padding wafer by solder, and the orthogonal projection of the barrier layer on the device wafer covers the reference device area.

18. The method for fabricating a wafer-level packaging structure according to claim 17, characterized in that, The capping wafer includes a first seal and a getter formed on the surface of the capping wafer; The device wafer, the padding wafer, and the capping wafer form the wafer-level packaging structure; wherein the first seal and the second seal of the padding wafer are bonded by solder; the orthographic projection of the getter on the device wafer does not overlap with the orthographic projection of the functional device region on the device wafer.

Images