Leakage detection circuit and leakage detection method for memory

Abstract

The present disclosure provides a leakage detection circuit of a memory, a memory, an electronic device and a leakage detection method. The memory comprises a charge pump module comprising a charge pump and a comparator, the comparator comparing a reference voltage and a feedback voltage proportional to an output voltage of the charge pump and generating a feedback signal, wherein the leakage detection circuit comprises a duty cycle detection circuit for determining whether the memory has a leakage according to a duty cycle of the feedback signal. The leakage detection circuit of the memory can accurately and quickly detect whether the memory has a leakage according to the duty cycle of the feedback signal of the memory.

Description

Technical Field

[0001] This disclosure relates to the field of leakage current detection technology, and more specifically, to a leakage current detection circuit, a memory, an electronic device, and a leakage current detection method. Background Technology

[0002] When erasing data in a memory, a high negative voltage is applied to the word lines and the substrate to erase the data using the tunneling effect. After multiple erase operations, the memory will exhibit various leakage mechanisms, such as leakage between word lines and between word lines and the substrate.

[0003] The memory in the related technology does not employ a leakage current detection mechanism. After multiple erase operations, the leakage current in the memory will affect the erasure effect.

[0004] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] This disclosure provides a leakage current detection circuit, a memory, an electronic device, and a leakage current detection method for a memory, which can accurately and quickly detect whether the memory is leaking current based on the duty cycle of the memory's feedback signal.

[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0007] This disclosure provides a leakage current detection circuit for a memory, comprising: the memory including a charge pump module, the charge pump module including a charge pump and a comparator, the comparator comparing a reference voltage and a feedback voltage proportional to the output voltage of the charge pump and generating a feedback signal, wherein the leakage current detection circuit includes: a duty cycle detection circuit, used to determine whether there is leakage current in the memory based on the duty cycle of the feedback signal.

[0008] In some exemplary embodiments of this disclosure, the duty cycle detection circuit includes: a capacitor, a first terminal of which has an initial voltage and a second terminal of which is grounded; a charging path; and a discharging path; wherein, during the detection period, when the feedback signal is at a first level, the capacitor discharges through the discharging path, and when the feedback signal is at a second level, the charging path charges the capacitor; if the voltage value at the first terminal of the capacitor decreases to a first voltage threshold, it is determined that the duty cycle of the feedback signal is greater than the duty cycle threshold, and the memory has leakage current.

[0009] In some exemplary embodiments of this disclosure, the duty cycle detection circuit includes: a capacitor, a first terminal of which has an initial voltage, and a second terminal of which is connected to a ground terminal; a charging path; and a discharging path; wherein, during the detection time period, when the feedback signal is at a first level, the charging path charges the capacitor, and when the feedback signal is at a second level, the capacitor discharges through the discharging path; if the voltage at the first terminal of the capacitor rises to a second voltage threshold, it is determined that the duty cycle of the feedback signal is greater than the duty cycle threshold, and whether the memory has leakage current is determined.

[0010] In some exemplary embodiments of this disclosure, the charging path includes a first current source and a first switch connected in series between the power supply terminal and a first terminal of the capacitor.

[0011] In some exemplary embodiments of this disclosure, the discharge path includes a second current source and a second switch connected in series between a first terminal of the capacitor and a ground terminal.

[0012] In some exemplary embodiments of this disclosure, the leakage current detection circuit further includes: a third switch connected between a first terminal of the capacitor and a power supply terminal; wherein, outside the detection time period, the third switch is turned on; and during the detection time period, the third switch is turned off.

[0013] In some exemplary embodiments of this disclosure, the discharge amount of the capacitor when the feedback signal is at a first level is greater than the charging amount of the capacitor when the feedback signal is at a second level.

[0014] In some exemplary embodiments of this disclosure, the amount of charge of the capacitor when the feedback signal is at a first level is greater than the amount of discharge of the capacitor when the feedback signal is at a second level.

[0015] In some exemplary embodiments of this disclosure, the charge pump module further includes an oscillator that provides a clock signal to the charge pump when the feedback signal is at a first level, and that stops providing the clock signal to the charge pump when the feedback signal is at a second level.

[0016] In some exemplary embodiments of this disclosure, the leakage current detection circuit further includes an inverter, wherein the input terminal of the inverter is connected to the first terminal of the capacitor.

[0017] This disclosure provides a memory including any of the leakage current detection circuits described above.

[0018] This disclosure provides an electronic device including the memory described above.

[0019] This disclosure provides a leakage current detection method for a memory, the memory including a charge pump module and a leakage current detection circuit, the charge pump module including a charge pump and a comparator, the comparator comparing a reference voltage and a feedback voltage proportional to the output voltage of the charge pump and generating a feedback signal, wherein the leakage current detection method includes: determining whether there is leakage current in the memory based on the duty cycle of the feedback signal.

[0020] In some exemplary embodiments of this disclosure, the leakage detection circuit includes a capacitor, a charging path, and a discharging path; wherein determining whether the memory has leakage based on the duty cycle of the feedback signal includes: during the detection period, when the feedback signal is at a first level, discharging the capacitor through the discharging path; when the feedback signal is at a second level, charging the capacitor through the charging path; determining that the memory has leakage in response to the voltage at the first terminal of the capacitor decreasing to a first voltage threshold; or; during the detection period, when the feedback signal is at a first level, charging the capacitor through the charging path; when the feedback signal is at a second level, discharging the capacitor through the discharging path; determining that the memory has leakage in response to the voltage at the first terminal of the capacitor increasing to a second voltage threshold.

[0021] The leakage detection circuit for a memory provided in this disclosure can accurately and quickly detect whether the memory is leaking current based on the duty cycle of the memory's feedback signal. The controller marks blocks with leakage as bad blocks based on the detection results and records them in a bad block list. Furthermore, the leakage detection circuit provided in this disclosure can detect the memory while it is operating (e.g., during programming or erasing operations on the memory cell array), enabling timely detection of the memory cell array's condition.

[0022] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this disclosure. Attached Figure Description

[0023] The above and other objects, features and advantages of this disclosure will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0024] Figure 1 This is a schematic diagram of a memory according to an exemplary embodiment.

[0025] Figure 2 This is a schematic diagram of a block in a storage cell array according to an exemplary embodiment.

[0026] Figure 3 This is a schematic diagram of a charge pump module according to an exemplary embodiment.

[0027] Figure 4 This is a schematic diagram of a duty cycle detection circuit in a memory leakage detection circuit according to an exemplary embodiment.

[0028] Figure 5 This is a schematic diagram of a leakage detection circuit for a memory according to an exemplary embodiment.

[0029] Figure 6 This is a schematic diagram of a leakage detection circuit for a memory according to an exemplary embodiment.

[0030] Figure 7 It is based on Figure 5 The waveforms of the feedback signal, enable signal, voltage at the first terminal of the capacitor, and output signal of the inverter in the leakage current detection circuit are shown. Detailed Implementation

[0031] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0032] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known structures, methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0033] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0034] Figure 1 This is a schematic diagram of a memory according to an exemplary embodiment.

[0035] like Figure 1As shown, the memory 10 provided in this embodiment may include a memory cell array 100, a controller 102, a word line decoder 104, a bit line decoder 106, a charge pump module 108, and a leakage current detection circuit 110.

[0036] The memory 10 can be either volatile or non-volatile. Volatile memory requires power to maintain data and can be, for example, random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM). Non-volatile memory can maintain stored data even when power is off and can be, for example, NAND flash memory, NOR flash memory, electrically erasable programmable ROM (EEPROM), phase-change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM).

[0037] This disclosure provides an electronic device including the aforementioned memory 10. The memory 10 can be electrically connected to the electronic device and can be a built-in or external storage device of the electronic device. The electronic device can store and manage data, and can be a personal computer, laptop computer, mobile terminal, personal digital assistant, or camera, etc., without limitation in this disclosure.

[0038] The storage cell array 100 may include multiple blocks. Figure 2 This is a schematic diagram of a block in a memory cell array. (Reference) Figure 2 The present invention will use NOR flash memory as an example for the description of memory 10, but is not limited thereto. The memory cell array 100 includes multiple memory cells addressed via word lines WL and bit lines BL. A memory cell may be, for example, a transistor with a floating gate. The transistor also includes a substrate, a source, a drain, and a control gate, wherein the control gate is connected to the corresponding word line WL, and the drain is connected to the corresponding bit line BL. A word line decoder 104 is used to select the word line WL. A bit line decoder 106 is used to select the bit line BL. The controller 102 can communicate with the host of an electronic device via a bus, such as a Serial Advanced Technology Attachment (SATA) standard, a Universal Serial Bus (USB) standard, or a Serial Peripheral Interface (SPI) standard bus. The controller 102 controls various operations of the memory cell array according to instructions from the host, such as programming operations, erasing operations (also known as write operations), reading operations, and verification operations. A charge pump module 108 is used to provide various operating voltages for the memory 10. Operating voltages include, for example, the erase voltage applied to the substrate during an erase operation, and the programming voltage applied to the word line during a programming operation.

[0039] A common defect in memory 10 is word line leakage, such as leakage between two word lines or leakage from a word line to the substrate. The leakage detection circuit provided in this disclosure embodiment can detect whether leakage exists in memory 10. Specifically, the leakage detection circuit can perform leakage detection when memory 10 performs programming or erasing operations.

[0040] Figure 3 This is a schematic diagram of a charge pump module according to an exemplary embodiment. The output voltage of the charge pump module 108 is the operating voltage of the memory. The charge pump module may include a charge pump 1081, an oscillator 1082, a comparator 1083, voltage divider resistors R1 and R2.

[0041] The charge pump 1081 provides an output voltage VOUT greater than the input voltage to the load. The charge pump 1081 can be, for example, a Dickson charge pump or a charge pump of other structures. The load can be, for example, a word line or a substrate. The oscillator 1082 provides a clock signal CLK to the charge pump 1081. Voltage divider resistors R1 and R2 are connected between the output terminal of the charge pump 1081 and ground. The node between voltage divider resistors R1 and R2 is connected to one of the input terminals of comparator 1083. Voltage divider resistors R1 and R2 provide a feedback voltage VFB proportional to the output voltage of the charge pump 1081. Comparator 1083 compares the reference voltage VREF and the feedback voltage VFB and generates a feedback signal PUMP_EN. The reference voltage VREF can be provided by a bandgap reference circuit. The feedback signal PUMP_EN can be a first level or a second level.

[0042] For example, when the output voltage VOUT of the charge pump 1081 is lower than the target value, the feedback voltage VFB, which is proportional to the output voltage VOUT, is lower than the reference voltage VREF. The feedback signal PUMP_EN output by the comparator 1083 is at the first level (e.g., high level). The oscillator 1082 provides the clock signal CLK to the charge pump 1081, and the charge pump 1081 performs a boost operation to increase the output voltage VOUT.

[0043] When the output voltage VOUT is higher than or equal to the target value, the feedback voltage VFB, which is proportional to the output voltage VOUT, is higher than or equal to the reference voltage VREF. The feedback signal PUMP_EN output by comparator 1083 is at the second level (e.g., low level). The oscillator stops providing a clock signal to charge pump 1081, and charge pump 1081 stops boost operation.

[0044] The target values ​​and reference voltages mentioned above can be set according to actual conditions, and this disclosure does not impose any restrictions on them.

[0045] Continue to refer to Figure 3 The feedback signal PUMP_EN output by comparator 1083 can be used as the input signal of leakage current detection circuit 110.

[0046] This disclosure provides a leakage detection circuit 110 for a memory 10. The leakage detection circuit 110 can determine whether there is leakage in the memory 10 by detecting whether the duty cycle of the feedback signal PUMP_EN is greater than a duty cycle threshold. When there is leakage in the memory 10 (e.g., leakage between word lines, leakage from a word line to the substrate), the output voltage VOUT of the charge pump 1081 decreases rapidly, and the second level (low level) duration of the feedback signal PUMP_EN is short. When the duty cycle of the feedback signal PUMP_EN is greater than the duty cycle threshold, it is determined that there is leakage in the memory 10. The high level duration of the feedback signal PUMP_EN is t1, and the low level duration of the feedback signal PUMP_EN is t2. Then, the duty cycle of the feedback signal PUMP_EN can be t1 / (t1+t2). The duty cycle threshold can be determined according to the specific situation of the charge pump module, memory cell, and word line.

[0047] Figure 4 This is a schematic diagram of a duty cycle detection circuit in a memory leakage detection circuit according to an exemplary embodiment. (Reference) Figure 4 The duty cycle detection circuit of the leakage current detection circuit of the memory may include a capacitor C1, a charging path and a discharging path.

[0048] The first terminal of capacitor C1 has an initial voltage, and the second terminal of capacitor C1 is connected to ground. The initial voltage of the first terminal of capacitor C1 can be the power supply voltage VDD, or it can be 0V, or it can be any other value between 0V and the power supply voltage VDD. When the initial voltage of the first terminal of capacitor C1 is the power supply voltage VDD, during the detection period, when the feedback signal PUMP_EN is at the first level, capacitor C1 can discharge through the discharge path, and when the feedback signal PUMP_EN is at the second level, the charging path charges capacitor C1. If the voltage value of the first terminal of the capacitor drops to a first voltage threshold during the detection period, it is determined that there is leakage in memory 10.

[0049] With the initial voltage at the first terminal of capacitor C1 at 0V, during the detection period, when the feedback signal PUMP_EN is at the first level, the charging path charges capacitor C1; when the feedback signal PUMP_EN is at the second level, capacitor C1 can discharge through the discharge path. If the voltage at the first terminal of the capacitor rises to the second voltage threshold during the detection period, leakage is determined in memory 10.

[0050] In an exemplary embodiment, the charging path may include a first current source IS1 and a first switch S1, which are connected in series between the power supply terminal and the first terminal of the capacitor C1. The first current source IS1 is used to provide a first current I1, which may be a fixed charging current.

[0051] In an exemplary embodiment, the discharge path may include a second current source IS2 and a second switch S2, which are electrically connected between the first end of capacitor C1 and ground terminal GND. The second current source IS2 is used to provide a second current I2, which may be a discharge current of a fixed magnitude.

[0052] In an exemplary embodiment, when the first switch S1 is open and the second switch S2 is open, capacitor C1 discharges through the discharge path; when the first switch S1 is open and the second switch S2 is open, the charging path charges capacitor C1.

[0053] When the initial voltage at the first terminal of capacitor C1 is the power supply voltage VDD, the feedback signal is at the first level for a period of time t1. After capacitor C1 discharges through the discharge path for t1, the charge Q on capacitor C1... C1 The voltage VDET at the first terminal of capacitor C1 is (VDD*C1-I2*t1) / C1. Then, the feedback signal is at the second level for a period of time t2. After capacitor C1 is charged for t2, the charge Q on capacitor C1 is... C1 The voltage VDET at the first terminal of capacitor C1 is (VDD*C1-I2*t1+I1*t2), meaning it is related to the duty cycle of the feedback signal. The voltage at the first terminal of capacitor C1 can be used to determine if there is leakage in memory 10. When memory 10 has leakage, the discharge amount of capacitor C1 is greater than the charge amount. When the voltage at the first terminal of capacitor C1 drops below the first voltage threshold during the detection period, it can be determined that memory 10 has leakage.

[0054] With the initial voltage at the first terminal of capacitor C1 being 0, the feedback signal is at the first level for a period of time t1. After capacitor C1 is charged for t1, the charge Q on capacitor C1... C1 The voltage VDET at the first terminal of capacitor C1 is (I1*t1) / C1; the feedback signal is at the second level for a period of time t2; after capacitor C1 discharges through the discharge path for t2, the charge Q on capacitor C1 is... C1The input voltage is I1*t1 - I2*t2, and the voltage VDET at the first terminal of capacitor C1 is (I1*t1 - I2*t2) / C1. This means the voltage at the first terminal of capacitor C1 is related to the duty cycle of the feedback signal. The magnitude of the voltage at the first terminal of capacitor C1 can be used to determine if there is leakage in memory 10. When memory 10 has leakage, the charge on capacitor C1 is greater than the discharge. When the voltage at the first terminal of capacitor C1 rises above the second voltage threshold during the detection period, it can be determined that memory 10 has leakage.

[0055] In some embodiments, the magnitude of the first current I1 is equal to the magnitude of the second current I2.

[0056] It should be noted that the time when the feedback signal is at the first level and the time when the feedback signal is at the second level can be interspersed in segments. t1 can represent the total length of time during the detection period when the feedback signal is at the first level, and t2 can represent the total length of time during the detection period when the feedback signal is at the second level.

[0057] The leakage detection circuit for a memory provided in this disclosure can accurately and quickly detect whether the memory is leaking current based on the duty cycle of the memory's feedback signal. The controller marks blocks with leakage as bad blocks based on the detection results and records them in a bad block list. Furthermore, the leakage detection circuit provided in this disclosure can detect the memory while it is operating (e.g., during programming or erasing operations on the memory cell array), enabling timely detection of the memory cell array's condition.

[0058] Figure 5 This is a schematic diagram of a leakage detection circuit for a memory according to an exemplary embodiment. Figure 5 The leakage current detection circuit shown may also include a third switch S3 and an inverter INV1. The third switch S3 can be connected between the first terminal of capacitor C1 and the power supply terminal. Outside the detection period, the third switch S3 is on, setting the voltage at the first terminal of capacitor C1 to the power supply voltage VDD. During the detection period, the third switch S3 is off. When the voltage at the first terminal of capacitor C1 drops to a first voltage threshold, the output signal of inverter INV1 changes from 0 to 1.

[0059] Figure 6 This is a schematic diagram of a leakage detection circuit for a memory according to an exemplary embodiment. Figure 6The leakage current detection circuit shown may also include a third switch S3 and an inverter INV1. The third switch S3 can be connected between the first terminal of capacitor C1 and the ground terminal. Outside the detection period, the third switch S3 is on, setting the voltage at the first terminal of capacitor C1 to 0V. During the detection period, the third switch S3 is off. When the voltage at the first terminal of capacitor C1 rises to a second voltage threshold, the output signal of inverter INV1 changes from 1 to 0. The period outside the detection period can include before the detection start time and after the detection end time, while the period within the detection period can be between the detection start time and the detection end time. For example, when the enable signal VDET_EN is low, it is outside the detection period, and the third switch S3 is closed; when the enable signal VDET_EN is high, it is during the detection period, and the third switch S3 is off.

[0060] refer to Figure 5 Before the detection start time, the third switch closes, allowing the power supply to charge capacitor C1, setting the initial voltage at the first terminal of capacitor C1 to VDD. That is, an initial voltage difference is set for capacitor C1. Then, by detecting whether the voltage VDET at the first terminal of capacitor C1 drops to a first voltage threshold within a predetermined detection time, it is determined whether the memory 10 has malfunctioned. The first voltage threshold can be the critical value that causes the output of inverter INV1 to change from low to high. The first voltage threshold and inverter INV1 can be matched by adjusting capacitor C1, the first current source IS1, and the second current source IS2.

[0061] During the detection period, the third switch is open, and the duty cycle detection circuit in the leakage current detection circuit starts working. For the specific working process and principle of the duty cycle detection circuit in the leakage current detection circuit, please refer to [link / reference]. Figure 4 The embodiments shown and the above textual descriptions will not be repeated here.

[0062] After the detection ends, the third switch closes, allowing the power supply to recharge capacitor C1, restoring the voltage at the first terminal of capacitor C1 to VDD.

[0063] Figure 7 It is based on Figure 5 The waveforms of the feedback signal, enable signal, voltage at the first terminal of the capacitor, and output signal of the inverter in the leakage current detection circuit are shown.

[0064] refer to Figure 7Taking the case of leakage in memory 10 as an example, the duty cycle of the feedback signal PUMP_EN is relatively large. The enable signal VDET_EN of the leakage detection circuit can change from low to high level after the charge pump stabilizes, and the leakage detection circuit starts working. After the enable signal VDET_EN of the leakage detection circuit is high, during the period when the feedback signal PUMP_EN is high, capacitor C1 discharges through the discharge path, and the voltage VDET at the first terminal of capacitor C1 decreases. During the period when the feedback signal PUMP_EN is low, the charging path charges capacitor C1, and the voltage VDET at the first terminal of capacitor C1 increases. Because there is leakage in memory 10, the duration of the high level is longer than the duration of the low level, and the amount of discharge is greater than the amount of charging. When the voltage VDET at the first terminal of capacitor C1 drops to the toggling point of inverter INV1, the output signal VDETH of the inverter changes from low to high.

[0065] In this embodiment of the present disclosure, when the output signal VDETH of the inverter changes from low level to high level, it can be determined that there is leakage in the memory 10, and the address of the block of the memory 10 with leakage is recorded, and the bad block list is updated.

[0066] refer to Figure 6 Before the detection start time, the third switch is closed, and the initial voltage at the first terminal of capacitor C1 is 0, as is the voltage at the second terminal of capacitor C2. That is, the initial voltage difference of capacitor C1 is set to 0, and then the memory 10 is judged to have malfunctioned by detecting whether the voltage VDET at the first terminal of capacitor C1 rises to the second voltage threshold within a predetermined detection time. The predetermined value can be the critical value that causes the output of inverter INV1 to change from high to low. The second voltage threshold and inverter INV1 can be matched by adjusting capacitor C1, the first current source IS1, and the second current source IS2.

[0067] During the detection period, the third switch is open, and the duty cycle detection circuit in the leakage current detection circuit starts working. For the specific working process and principle of the duty cycle detection circuit in the leakage current detection circuit, please refer to [link / reference]. Figure 4 The embodiments shown and the above textual descriptions will not be repeated here.

[0068] After the detection ends, the third switch closes, restoring the voltage at the first terminal of capacitor C1 to 0.

[0069] The memory leakage detection circuit provided in this embodiment can accurately and quickly detect whether the memory is leaking current based on the flipping of the output signal of the inverter.

[0070] This disclosure provides a leakage current detection method for a memory. The memory includes a charge pump module and a leakage current detection circuit. The charge pump module includes a charge pump and a comparator. The comparator compares a reference voltage and a feedback voltage proportional to the output voltage of the charge pump and generates a feedback signal. The leakage current detection method includes determining whether there is leakage current in the memory based on the duty cycle of the feedback signal. Specifically, if the duty cycle of the feedback signal is greater than a duty cycle threshold, it is determined that there is leakage current in the memory.

[0071] In an exemplary embodiment, the leakage detection circuit includes a capacitor, a charging path, and a discharging path.

[0072] The method of determining whether the memory has leakage based on the duty cycle of the feedback signal includes: during the detection time, when the feedback signal is at a first level, discharging the capacitor through the discharge path; when the feedback signal is at a second level, charging the capacitor through the charging path; and determining that the duty cycle of the feedback signal is greater than the duty cycle threshold in response to the voltage at the first terminal of the capacitor dropping to a first voltage threshold, indicating that the memory has leakage.

[0073] Determining whether the memory has leakage based on the duty cycle of the feedback signal includes: during the detection time, when the feedback signal is at a first level, charging the capacitor through the charging path; when the feedback signal is at a second level, discharging the capacitor through the discharge path; and determining that the duty cycle of the feedback signal is greater than the duty cycle threshold in response to the voltage at the first terminal of the capacitor rising to a second voltage threshold, indicating that the memory has leakage.

[0074] For details not disclosed in the embodiments of the method disclosed herein, please refer to the above embodiments of the present disclosure, and these will not be repeated here.

[0075] Exemplary embodiments of this disclosure have been specifically illustrated and described above. It should be understood that this disclosure is not limited to the detailed structures, arrangements, or implementation methods described herein; rather, this disclosure is intended to cover various modifications and equivalent arrangements contained within the spirit and scope of the appended claims.

Claims

1. A leakage current detection circuit for a memory, the memory including a charge pump module, the charge pump module including a charge pump and a comparator, the comparator comparing a reference voltage and a feedback voltage proportional to the output voltage of the charge pump and generating a feedback signal, characterized in that, The leakage current detection circuit is used to detect leakage current when the memory performs programming or erasing operations, including: A duty cycle detection circuit is used to determine whether the memory has leakage current based on the duty cycle of the feedback signal; The duty cycle detection circuit includes: A capacitor, wherein a first terminal of the capacitor has an initial voltage and a second terminal of the capacitor is connected to a ground terminal; The charging path includes a first current source and a first switch connected in series between the power supply terminal and the first terminal of the capacitor; and The discharge path includes a second current source and a second switch connected in series between the first terminal of the capacitor and the ground terminal. A third switch is connected between the first terminal of the capacitor and the ground terminal, wherein the third switch is turned on outside the detection time and turned off during the detection time; During the detection period, when the feedback signal is at the first level, the charging path charges the capacitor; when the feedback signal is at the second level, the capacitor discharges through the discharge path. If the voltage at the first terminal of the capacitor rises to the second voltage threshold, it is determined that the duty cycle of the feedback signal is greater than the duty cycle threshold, and the memory has leakage.

2. The leakage current detection circuit according to claim 1, characterized in that, During the detection period, when the feedback signal is at the first level, the capacitor discharges through the discharge path; when the feedback signal is at the second level, the charging path charges the capacitor. If the voltage at the first terminal of the capacitor drops to the first voltage threshold, it is determined that the duty cycle of the feedback signal is greater than the duty cycle threshold, and the memory has leakage.

3. The leakage current detection circuit according to claim 2, characterized in that, Also includes: A third switch is connected between the first terminal of the capacitor and the power supply terminal; wherein, outside the detection time period, the third switch is turned on; During the detection period, the third switch is turned off.

4. The leakage current detection circuit according to claim 2, characterized in that, When the feedback signal is at the first level, the discharge amount of the capacitor is greater than the charging amount of the capacitor when the feedback signal is at the second level.

5. The leakage current detection circuit according to claim 1, characterized in that, When the feedback signal is at the first level, the amount of charge on the capacitor is greater than the amount of discharge on the capacitor when the feedback signal is at the second level.

6. The leakage current detection circuit according to claim 1 or 2, characterized in that, The charge pump module also includes an oscillator that provides a clock signal to the charge pump when the feedback signal is at a first level, and stops providing a clock signal to the charge pump when the feedback signal is at a second level.

7. The leakage current detection circuit according to claim 1 or 2, characterized in that, Also includes: An inverter, wherein the input terminal of the inverter is connected to the first terminal of the capacitor.

8. A memory comprising a leakage current detection circuit as described in any one of claims 1-7.

9. An electronic device comprising the memory as claimed in claim 8.

10. A method for detecting leakage current in a memory, the memory comprising a charge pump module and a leakage current detection circuit, the charge pump module comprising a charge pump and a comparator, the comparator comparing a reference voltage and a feedback voltage proportional to the output voltage of the charge pump and generating a feedback signal, characterized in that, The leakage current detection method includes: The presence of leakage current in the memory is determined based on the duty cycle of the feedback signal; The leakage current detection circuit is used to detect leakage current when the memory performs programming or erasing operations. The leakage current detection circuit includes a capacitor, a charging path, a discharging path, and a third switch. The third switch is connected between the first terminal of the capacitor and the ground terminal. Outside the detection time, the third switch is turned on, and during the detection time, the third switch is turned off. Determining whether the memory has leakage current based on the duty cycle of the feedback signal includes: During the detection period, when the feedback signal is at a first level, the capacitor is charged through the charging path; when the feedback signal is at a second level, the capacitor is discharged through the discharging path; in response to the voltage at the first terminal of the capacitor rising to a second voltage threshold, it is determined that the memory has leakage.

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